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| 12 00 mhz to 36 00 mhz rx mixer with integrated fractional - n pll and vco data sheet ADRF6604 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog d evices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2010C 2014 analog devices, inc. all rig hts reserved. technical support www.analog.com features rx m ixer with integrated f ractional - n pll rf input f requency range : 1200 mhz to 3600 mhz internal lo frequency r ange: 2500 mhz to 2900 mhz input p1db: 14 . 5 db m input ip3: 27.5 db m i i p3 o ptimization via e xternal p in ssb n oise f igure ip3set pin op en: 1 4.3 db ip3se t pin at 3.3 v: 1 5 .5 db voltage c onversion g ain: 6 .8 db matched 200 ? if o utput i mpedance if 3 db b andwidth: 500 mhz programmable via 3 - wire spi i nterface 40- lead , 6 mm 6 mm lfcsp applications cellular b ase s tations general description the ADRF6604 is a hi gh dynamic range active mixer with integrated phase - locked loop (pll) and voltage controlled oscillator (vco). the pll/synthesizer uses a fractional - n pll to generate a f lo input to the mixer. the reference input can be divided or multiplied and then app lied to the pll phase frequency detector (pfd). the pll can support input reference frequencies from 12 mhz to 160 mhz. the pfd output controls a charge pump whose output drives an off - chip loop filter. the loop filter output is then applied to an integ rated vco. the vco output at 2 f lo is applied to a n lo divider , as well as to a programmable pll divider. the programmable pll divider is controlled by a sigma - delta ( - ) modulator (sdm). the modulus of the sdm can be programmed from 1 to 2047. the acti ve mixer converts the single - ended , 50 rf input to a differential, 200 ? if output. the if output can operate up to 500 mhz. the ADRF6604 is fabricated using an advanced silicon - germanium b icmos process. it is available in a 40 - lead, rohs - compliant , 6 mm 6 mm lfcsp with an exposed paddle . performance is specified over the ?40c to +85c temperature range. table 1. part no. internal lo range 3 db rf in balun range 1 db rf in balun range adrf6601 750 mhz 300 mhz 450 mhz 1160 mhz 2500 mhz 1600 mhz adrf6602 1550 mhz 1000 mhz 1350 mhz 2150 mhz 3100 mhz 2750 mhz adrf6603 2100 mhz 1100 mhz 1450 mhz 2600 mhz 3200 mhz 2850 mhz ADRF6604 2500 mhz 1200 mhz 1600 mhz 290 0 mhz 3600 mhz 3200 mhz functional block dia gram mux r set cp vtune lodrv_en lon lop ip3set vcc1 2:1 mux vco core rf in temp sensor declvco decl2p5 decl3p3 ifp buffer buffer ifn vcc2 vcc_lo vcc_mix vcc_v2i vcc_lo nc ? + charge pump 250a, 500a (default), 750a, 1000a prescaler 2 le clk spi interface data muxout nc 3.3v ldo 2.5v ldo vco ldo div by 2, 1 pll_en ref_in gnd ADRF6604 internal lo range 2500mhz to 2900mhz 34 19 18 39 3 5 4 8 6 14 13 12 16 38 37 36 7 11 15 20 21 23 24 25 28 30 31 35 32 33 2 9 40 26 29 27 17 10 1 22 phase frequency detector third-order fractional interpolator fraction reg modulus integer reg n counter 21 to 123 2 2 4 08553-001 figure 1 .
ADRF6604 data sheet rev. b | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision hist ory ............................................................................... 2 specifications ..................................................................................... 3 rf specifications .......................................................................... 3 synthesizer/pll speci fications ................................................... 4 logic input and power specifications ....................................... 4 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 9 rf frequency sweep .................................................................... 9 if frequency sweep ................................................................... 10 spurious performance ................................................................ 15 register structure ........................................................................... 16 register 0 integer divide cont rol (default: 0x0001c0) ..... 16 register 1 modulus divide control (default: 0x003001) ........ 16 register 2 fractional divide control (defaul t: 0x001802) ...... 17 register 3 - modulator dither control (default: 0x10000b) ................................................................... 17 register 4 pll charge pump, pfd, and reference p ath control (default: 0x0aa7e4) ................................................... 18 register 5 pll enable and lo path control (default: 0x0000e5) ................................................................... 19 register 6 vco control and vco enable (default: 0x1e2106) ................................................................... 19 register 7 mixer bias enable and external vco enable (default: 0x000007) .................................................................... 19 theory of operati on ...................................................................... 20 programming the ADRF6604 ................................................... 20 initialization sequence .............................................................. 20 lo selection logic ..................................................................... 21 applications information .............................................................. 22 basic connections for operation ............................................. 22 ac test fixture ............................................................................... 23 evaluation board ............................................................................ 24 evaluation board control software ......................................... 24 schematic and artwork ............................................................. 26 evaluation board configuration options ............................... 28 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 29 revision history 1/14 rev. a to rev. b change to product title ................................................................... 1 updated outline dimensions (lead - to - pad dimension) ......... 29 5 /11 rev. 0 to rev. a changes to features and general description sections .............. 1 changes to table 2 ............................................................................ 3 changes to synthesizer specifications parameter and to phase noise parameter, table 3 ............................................................. 4 changes to power supplies parameter, table 4 ............................ 4 replaced typical performance characteristics section; renumbered sequentially ........................................................... 9 added spurious performance section ......................................... 15 change to figure 41 ....................................................................... 17 changes to figure 42 ...................................................................... 18 changes to theory of operation section .................................... 20 changes to figure 46 ...................................................................... 22 added ac test fixture section and figure 47 ........................... 23 changes to evaluation board con trol software section and figure 48 ...................................................................................... 24 changes to figure 49 ...................................................................... 25 6/10 revision 0: initial version data sheet ADRF6604 rev. b | page 3 of 32 specifications rf specifications v s = 5 v , ambient temperature (t a ) = 25c , f ref = 153.6 mhz , f pfd = 38.4 mhz , high - side lo injection , f if = 140 mhz , iip3 optimized using c dac = 0xc and ip3set = 3.3 v, unless otherwise noted. table 2. parameter test conditions /comments min typ max unit internal lo frequency range 2500 2900 mhz rf input frequency range 3 db rf input ran ge 1200 3600 mhz rf input at 2360 mhz input return l oss relative to 50 ? (can be improved with external match) ? 16.2 db input p1db 14.6 dbm second - order intercept (iip2) ? 5 dbm each tone (10 mhz spacing between tones) 54.5 dbm third - order intercept (iip3) ? 5 dbm each tone (10 mhz spacing between tones) 28 dbm sin gle - sideb and noise figure ip3set = 3.3 v 14.8 db ip3set = open 13.9 db lo -to -i f leakage at 1 lo f requency, 50 ? t ermination at the rf p ort ? 43 dbm rf input at 2560 mhz input return loss relative to 50 ? (can be improved with external match ) ? 21 db input p1db 14.5 dbm second - order intercept (iip2) ? 5 dbm each tone (10 mhz spacing between tones) 58.2 dbm third - order intercept (iip3) ? 5 dbm each tone (10 mhz spacing between tones) 27.6 dbm single - sideb and noise figure ip3set = 3.3 v 14.9 db ip3set = open 14. 2 db lo -to - if leakage at 1 lo frequency, 50 ? termination at the rf port ? 42 dbm rf input at 2760 mhz input return loss relative to 50 ? (can be improved with external match) ? 20 db input p1db 14.4 dbm se cond - order intercept (iip2) ? 5 dbm each tone (10 mhz spacing between tones) 64.4 dbm third - order intercept (iip3) ? 5 dbm each tone (10 mhz spacing between tones) 27 dbm single - sideb and noise figure ip3set = 3.3 v 15.5 db ip3set = open 14.6 db lo -to - if leakage at 1 lo frequency, 50 ? termination at the rf port ? 44 dbm if output voltage conversion gain differential 200 ? load 6. 8 db if bandwidth small signal 3 db bandwidth 500 mhz output common - mode voltage external pull - up balun or inductors required 5 v gain flatness over frequency range, any 5 mhz/50 mhz 0.2/ 0.5 db gain variation over full temperature range 1.3 db output swing differential 200 ? load 2 v p -p output return loss relative to 200 ? ? 1 5 db lo input/out put (lop, lon) externally applied 1 lo input, internal pll disabled frequency range 250 6000 mhz output level (lo as output) 1 lo into a 50 ? load, lo output buffer enabled ? 9 dbm input level (lo as input) ? 6 0 +6 dbm input impedance 50 ? ADRF6604 data sheet rev. b | page 4 of 32 synthesizer/pll spec ifications v s = 5 v , ambient temperature (t a ) = 25c , f ref = 153.6 mhz , f ref power = 4 dbm , f pfd = 38.4 mhz , high - side lo injection , f if = 140 mhz , iip3 optimized using c dac = 0xc and ip3set = 3.3 v, unless otherwise noted. table 3. parameter test conditions /comments min typ max unit synthesizer specifications synthesizer s pecifications r eferenced to 1 lo frequency range internally g enerated lo 2500 2900 mhz figure of merit 1 p ref _in = 0 dbm ? 221.4 dbc/hz /hz reference spurs f pfd = 38.4 mhz f pfd /4 ? 107 dbc f pfd ? 82 dbc > f pfd ? 80 dbc phase noise f lo = 2500 mhz to 2900 mhz, f pfd = 38.4 mhz 1 khz to 10 khz offset ? 87.7 dbc/hz 100 khz offset ? 96 dbc/hz 500 khz offs et ? 117 dbc/hz 1 mhz offset ? 126 dbc/hz 5 mhz offset ? 142 dbc/hz 10 mhz offset ? 148 dbc/hz 20 mhz offset ? 150 dbc/hz integrated phase noise 1 k hz to 4 0 mhz integration bandwidth 0.69 rms pfd frequency 20 40 mhz reference character istics ref_in, muxout pins ref_in input frequency 12 160 mhz ref_in input capacitance 4 pf muxout output level v ol (lock detect output selected) 0.25 v v oh (lock detect output selected) 2.7 v muxout duty cycle 50 % charge pump pump current programmable to 250 a, 500 a, 750 a, 1 m a 500 a output compliance range 1 2.8 v 1 the figure of merit (fom) is computed as phase noise (dbc/hz) C 10 l og 10(f p f d ) C 20 l og 10(f lo /f p f d ). the fom was measured across th e full lo range, with f ref = 80 mhz, and f ref power = 10 dbm (500 v/s slew rate) with a 40 mhz f pfd . the fom was computed at 50 khz offset. logic input and powe r specifications v s = 5 v , ambient temperature (t a ) = 25c , f ref = 153.6 mhz , f pfd = 38.4 mhz , high - side lo injection , f if = 140 mh z , iip3 optimized using c dac = 0x c and ip3set = 3.3 v, unless otherwise noted. table 4. parameter test conditions /comments min typ max unit logic inputs clk, data, le input high voltage , v inh 1.4 3.3 v input low voltage , v inl 0 0.7 v input current , i inh /i inl 0.1 a input capacitance , c in 5 pf power supplies vcc 1, vcc2, vcc_lo , vcc_mix, and vcc_v2i pins voltage range 4.75 5 5.25 v supply current pll only 96 ma external lo mode (internal pll disabled, ip 3set pin = 3.3 v , lo o utput buffer off ) 164 ma internal lo mode (internal pll enabled , ip3set pin = 3.3 v , lo output buffer on ) 2 74 ma internal lo mode (internal pll enabled, ip3set pin = 3.3 v , lo output buffer off ) 260 ma power - down mode 30 ma data sheet ADRF6604 rev. b | page 5 of 32 timing characteristi cs v cc2 = 5 v 5 %. table 5. parameter limit unit description t 1 20 ns min le setup time t 2 10 ns min data -to - cl k setup time t 3 10 ns min data -to - clk hold time t 4 25 ns min clk h igh duration t 5 25 ns min clk l ow d uration t 6 10 ns min clk - to - le s etup t ime t 7 20 ns min le p ulse w idth timing diagram c l k da t a l e d b 23 (ms b ) d b 2 2 d b 2 d b 1 ( c o n t r o l b i t c 2 ) ( c o n t r o l b i t c 3) d b 0 ( l s b ) ( c o n t r o l b i t c 1 ) t 1 t 2 t 3 t 7 t 6 t 4 t 5 08553-002 figure 2 . timing diagram ADRF6604 data sheet rev. b | page 6 of 32 absolute maximum rat ings table 6. parameter rating supply voltage , vcc 1 , vc c 2, vcc_lo, vcc_mix, vcc_v2i ? 0.5 v to +5.5 v digital i/o , clk, data, le , lodrv_en, pll_en ? 0.3 v to + 3.6 v vtune 0 v to 3.3 v ifp, ifn ? 0.3 v to vcc _v2i + 0.3 v rf in 16 dbm lop, lon , ref_in 13 dbm ja (exposed paddle soldered down) 35c/w maximum junction temperature 150c operating temperature range ? 40c to +85c storage temperature range ? 65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution data sheet ADRF6604 rev. b | page 7 of 32 pin configurati on and function desc riptions pin 1 indicator notes 1. nc = no connect. do not connect to this pin. 2. the exposed paddle should be soldered to a low impedance ground plane. 1 vcc1 2 decl3p3 3 cp 4 gnd 5 r set 6 ref_ in 7 gnd 8 muxout 9 decl2p5 10 vcc2 23 gnd 24 gnd 25 gnd 26 rf in 27 vcc_v2i 28 gnd 29 ip3set 30 gnd 22 vcc_mix 21 gnd 11 gnd 12 data 13 clk 15 gnd 17 vcc_lo 16 pll_en 18 ifp 19 ifn 20 gnd 14 le 33 nc 34 vcc_lo 35 gnd 36 lodrv_en 37 lon 38 lop 39 vtune 40 declvco 32 nc 31 gnd top view (not to scale) ADRF6604 08553-003 figure 3 . pin configuration table 7 . pin function descriptions pin no. mnemonic description 1 vcc 1 power supply for the 3.3 v ldo . power supply voltage range is 4.75 v to 5. 25 v. each power supply pin should be decoupled with a 100 p f capacitor and a 0.1 f capacitor located close to the pin. 2 decl3p3 decoupling node for 3.3 v ldo . connect a 0.1 f capacitor between this pin and ground. 3 cp charge p ump output pin. connect to vtune through the loop filter . 4 , 7 , 11, 15, 20 , 21, 23, 24, 25, 28, 30, 31, 35 gnd ground . connect these pins to a low impedance ground plane. 5 r set charge pump current . the nominal charge pump current can be set to 250 a, 500 a , 750 a, or 1 ma using bit db1 1 and bit db1 0 in register 4 and by setting bit db18 in register 4 to 0 (i nternal reference c urrent). in this mode, no external r set is required. if bit db18 is set to 1, the four nominal charge pump currents (i nominal ) can be externally adjus ted according to the following equation: 37.8 4 . 217 ? ? ? ? ? ? ? ? ? = nominal cp set i i r 6 ref _in reference input . nominal input level is 1 v p - p. input range is 12 mhz to 160 mhz. this pin is internally dc - biased and should be ac - coupled. 8 muxout multiplexer output . this ou tput can be programmed to provide the reference o utput signal or the l ock d etect signal. the output is selected by programming the appropriate register . 9 decl2p5 decoupling node for 2.5 v ldo . connect a 0.1 f capacitor between this pin and ground. 10 v cc2 power supply for the 2.5 v ldo . power supply voltage range is 4.75 v to 5.25 v. each power supply pin should be decoupled with a 100 pf capacitor and a 0.1 f capacitor located close to the pin. 12 data serial data input . the serial data input is load ed msb first ; the three lsbs are the control bits. 13 clk serial clock input . th e serial clock input is used to clock in the serial data to the registers. the data is latched into the 24 - bit shift register on the clk rising edge. the m aximum clock frequen cy is 20 mhz. 14 le load enable . when the le input pin goes high, the data stored in the shift register is loaded into one of the eight registers. t he relevant latch is selected by the three control bits of the 24 - bit word. 16 pll_en pll enable . switch b etween i nternal pll and external lo i nput. when this pin is logic high , the mixer lo is automatically switched to the internal pll and the internal pll is powered up. when this pin is logic low , the internal pll is powered down and the external lo input is routed to the mixer lo inputs. the spi can also be used to switch modes. 17, 34 vcc_lo power supply. power supply voltage range is 4.75 v to 5.25 v. each power supply pin should be decoupled with a 100 pf capacitor and a 0.1 f capacitor located close to the pin. 18, 19 ifp , ifn mixer if outputs . these outputs s hould be pulled to vcc _mix with rf c hokes . ADRF6604 data sheet rev. b | page 8 of 32 pin no. mnemonic description 22 vcc _mix power supply. power supply voltage range is 4.75 v to 5.25 v. each power supply pin should be decoupled with a 100 pf capacitor and a 0.1 f capacitor located close to the pin. 26 r f in rf input . single - ended , 50 ? . 27 vcc_v2i power supply. power supply voltage range is 4.75 v to 5.25 v. each power supply pin should be decoupled with a 100 pf capacitor and a 0.1 f capacitor located close to the pin. 29 ip3set connec t a resistor from this pin to a 5 v supply to adjust i i p3. no rm ally leave open . 32, 33 nc nc = no connect. do not connect to this pin. 36 lodrv_en lo driver enable . together with pin 16 (pll_en), this digital input pin determines whether the lop and lon pin s operate as inputs or outputs . lop and lon become inputs if the pll_en pin is low or if the pll_en pin is set high with the plen bit (db6 in register 5 ) set to 0. lop and lon become outputs if either the lodrv_en pin or the ldrv bit ( db3 in register 5 ) is set to 1 whi le the pll_en pin is set h igh. the e xternal lo drive frequency must be 1 lo . this pin has an internal 100 k? pull - down resistor . 37, 38 lon, lop local oscillator input/output . the internally generated 1 lo is available on these pins. when internal lo generation is disabled, an e xternal 1 lo can be applied to these pins. 39 vtune vco control voltage input . this pin is driven by the output of the loop filter. the n ominal input voltage range on this pin is 1.5 v to 2.5 v . 40 declvco decoupling node for vco ldo . connect a 100 pf c apacitor and a 10 f capacitor between this pin and ground. ep ad exposed paddle. the exposed paddle should be soldered to a low impedance ground plane. data sheet ADRF6604 rev. b | page 9 of 32 typical performance characteristics rf frequency sweep cdac = 0xc, internally generated high-side lo, rf in = ?5 dbm, f if = 140 mhz, unless otherwise noted. 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 2360 2410 2460 2510 2560 2610 2660 2710 2760 rf frequency (mhz) gain (db) 08553-104 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 4. gain vs. rf frequency 90 80 70 60 50 40 30 2360 2410 2460 2510 2560 2610 2660 2710 2760 rf frequency (mhz) input ip2 (dbm) 08553-105 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 5. input ip2 vs. rf frequency 20 18 16 14 12 10 8 6 4 2 0 2360 2410 2460 2510 2560 2610 2660 2710 2760 rf frequency (mhz) noise figure (db) 08553-106 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 6. noise figure vs. rf frequency 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 2360 2410 2460 2510 2560 2610 2660 2710 2760 rf frequency (mhz) input ip3 (dbm) 08553-107 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 7. input ip3 vs. rf frequency 18 17 16 15 14 13 12 11 10 9 8 2360 2410 2460 2510 2560 2610 2660 2710 2760 rf frequency (mhz) input p1db (dbm) 08553-108 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 8. input p1db vs. rf frequency ADRF6604 data sheet rev. b | page 10 of 32 if frequency sweep cdac = 0xc, internally generated swept low-side lo, f rf = 2490 mhz, rf in = ?5 dbm, unless otherwise noted. 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 if frequency (mhz) gain (db) 08553-109 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 9. gain vs. if frequency 90 80 70 60 50 40 30 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 if frequency (mhz) input ip2 (dbm) 08553-110 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 10. input ip2 vs. if frequency, rf in = ?5 dbm 20 18 16 14 12 10 8 6 4 2 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 if frequency (mhz) noise figure (db) 08553-111 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 11. noise figu re vs. if frequency 45 40 35 30 25 20 15 10 5 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 if frequency (mhz) input ip3 (dbm) 08553-112 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 12. input ip3 vs. if frequency, rf in = ?5 dbm 20 18 16 14 12 10 8 6 4 2 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 if frequency (mhz) input p1db (dbm) 08553-113 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 13. input p1db vs. if frequency data sheet ADRF6604 rev. b | page 11 of 32 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 ?45 ?50 ?55 ?60 2500 2550 2600 2650 2700 2750 2800 2850 2900 lo frequency (mhz) lo-to-if feedthrough (dbm) 08553-114 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 14. lo-to-if feedthrough vs. lo frequency, lo output turned off, cdac = 0xc ? 20 ?25 ?30 ?35 ?40 ?45 ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 2500 2550 2600 2650 2700 2750 2800 2850 2900 lo frequency (mhz) lo-to-rf leakage (dbm) 08553-115 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 15. lo-to-rf leakage vs. lo frequency, lo output turned off 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 ?45 ?50 2300 2400 2500 2600 2700 2800 2900 3000 3100 rf frequency (mhz) return loss (db) 08553-116 figure 16. rf input return loss vs. rf frequency 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 ?10 ?11 ?12 ?13 ?14 ?15 2300 2400 2500 2600 2700 2800 2900 3000 3100 lo frequency (mhz) return loss (db) 08553-117 figure 17. lo input return loss vs. lo frequency (including tc1-1-13 balun) 350 300 250 200 150 100 50 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 50 100 150 200 250 300 350 400 450 500 if frequency (mhz) resistance ( ? ) capacitance (pf) 08553-118 resistance capacitance figure 18. if differential output impedance (r parallel, c equivalent) 35 30 25 20 15 10 ?60 ?50 ?40 ?30 ?20 ?10 0 cw blocker level (dbm) noise figure (db) 08553-119 ip3set = open ip3set = 3.3v figure 19. ssb noise figure vs. 5 mhz offset cw blocker level, lo frequency = 2500 mhz, rf frequency = 2358 mhz ADRF6604 data sheet rev. b | page 12 of 32 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 ?45 ?50 ?55 ?60 2160 2260 2360 2460 2560 2660 2760 2860 2960 rf frequency (mhz) rf-to-if isolation (dbc) 08553-120 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 20. rf-to-if isolation vs. rf frequency, high-side lo, if = 140 mhz, lo output turned off 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 ?10 ?11 ?12 ?13 ?14 ?15 2500 2550 2600 2650 2700 2750 2800 2850 2900 lo frequency (mhz) lo output amplitude (dbm) 08553-121 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 21. lo output amplitude vs. lo frequency 25 20 15 10 5 0 ?5 ?10 ?15 ?20 ?25 0 50 100 150 200 250 time (s) frequency deviation from 2500mhz (mhz) 08553-122 figure 22. frequency deviation from 2500 mhz vs. time (demonstrates lo frequency settling time from 2490 mhz to 2500 mhz) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2500 2550 2600 2650 2700 2750 2800 2850 2900 lo frequency (mhz) v tune voltage (v) 08553-123 t a = +85c t a = +25c t a = ?40c figure 23. vtune vs. lo frequency 350 300 250 200 150 100 2500 2550 2600 2650 2700 2750 2800 2850 2900 lo frequency (mhz) supply current (ma) 08553-124 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 24. supply current vs. lo frequency 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 ?55 ?35 ?15 5 25 45 65 85 105 temperature (c) vptat voltage (v) 08553-125 ip3set = open ip3set = 3.3v figure 25. vptat voltage vs. temper ature (ip3set = optimized, open) data sheet ADRF6604 rev. b | page 13 of 32 complementary cumulative distribution function (ccdf), f rf = 2360 mhz, f if = 140 mhz. 100 90 80 70 60 50 40 30 20 10 0 ?0.5 0 0.5 1.0 1.5 2.0 gain (db) distribution percentage (%) 08553-126 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 26. gain 100 90 80 70 60 50 40 30 20 10 0 45 50 55 60 65 70 75 input ip2 (dbm) distribution percentage (%) 08553-127 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 27. input ip2 100 90 80 70 60 50 40 30 20 10 0 10 11 12 13 14 15 16 17 18 19 20 noise figure (db) distribution percentage (%) 08553-128 ip3set = open t a = +85c t a = +25c t a = ?40c figure 28. noise figure 100 90 80 70 60 50 40 30 20 10 0 22 23 24 25 26 27 28 29 30 input ip3 (dbm) distribution percentage (%) 08553-129 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 29. input ip3 100 90 80 70 60 50 40 30 20 10 0 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 input p1db (dbm) distribution percentage (%) 08553-130 ip3set = open ip3set = 3.3v t a = +85c t a = +25c t a = ?40c figure 30. input p1db 100 90 80 70 60 50 40 30 20 10 0 ?50 ?48 ?46 ?44 ?42 ?40 ?38 ?36 lo feedthrough to if (dbm) distribution percentage (%) 08553-131 t a = +85c t a = +25c t a = ?40c ip3set = open ip3set = 3.3v figure 31. lo feedthrough to if, lo output turned off ADRF6604 data sheet rev. b | page 14 of 32 measured at if output, cdac = 0xc, ip3set = open, internally generated high-side lo, f ref = 153.6 mhz, f pfd = 38.4 mhz, rf in = ?5 dbm, f if = 140 mhz, unless otherwise noted. phase noise measur ements made at lo output, unless otherwise noted. ? 70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 1k 1m 10m 100m 1g offset frequency (hz) phase noise (dbc/hz) 08553-132 lo frequency = 2883.2mhz lo frequency = 2537.6mhz t a = +85c t a = +25c t a = ?40c figure 32. phase noise vs. offset frequency ? 70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 ?110 2500 2550 2600 2650 2700 2750 2800 2850 2900 lo frequency (mhz) spurs level (dbc) 08553-133 offset at 2 pfd offset at 4 pfd t a = +85c t a = +25c t a = ?40c figure 33. pll reference spurs vs. lo frequency (2 pfd and 4 pfd) ? 70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 ?110 2500 2550 2600 2650 2700 2750 2800 2850 2900 lo frequency (mhz) spurs level (dbc) 08553-134 offset at 3 pfd offset at 1 pfd t a = +85c t a = +25c t a = ?40c offset at 0.25 pfd figure 34. pll reference spurs vs. lo frequency (0.25 pfd, 1 pfd, and 3 pfd) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2500 2550 2600 2650 2700 2750 2800 2850 2900 lo frequency (mhz) integrated phase noise ( rms) 08553-135 t a = +85c t a = +25c t a = ?40c figure 35. integrated phase noise vs. lo frequency ? 80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 2500 2550 2600 2650 2700 2750 2800 2850 2900 lo frequency (mhz) phase noise (dbc/hz) 08553-136 offset = 1khz offset = 100khz offset = 5mhz t a = +85c t a = +25c t a = ?40c figure 36. phase noise vs. lo frequency (1 khz, 100 khz, and 5 mhz steps) ? 80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 ?125 ?130 2500 2550 2600 2650 2700 2750 2800 2850 2900 lo frequency (mhz) phase noise (dbc/hz) 08553-137 offset = 10khz offset = 1mhz t a = +85c t a = +25c t a = ?40c figure 37. phase noise vs. lo frequency (10 khz, 1 mhz steps) data sheet ADRF6604 rev. b | page 15 of 32 spurious performance (n f rf ) ? (m f lo ) spur measurements w ere m ade using the standard evaluation board (see the evaluation board section ) . mixer spurious products were measured in decibels relative to the c arrier (dbc) from the if output power level. all spurious components greater than ? 125 dbc are shown . lo = 2 500 mhz, rf = 2 36 0 mhz (horizontal axis is m , vertical axis is n ), and rf in power = 0 dbm. m n 0 1 2 3 4 0 -115.19 ? 43.0184 ? 33.3455 1 ? 23.6708 0.0 ? 67.1671 ? 47.1921 2 ? 63.4281 ? 65.1191 ? 61.1065 ? 79.8957 ? 80.0324 3 ? 83.6746 ? 86.8944 ? 58.5001 ? 105.514 4 ? 108.708 ? 104.041 ? 108.518 5 ? 110.825 ? 113.19 6 ? 108.548 7 lo = 2 700 mhz, rf = 2 56 0 mhz (horizontal axis is m , vertical axis is n ), and rf in power = 0 dbm. m n 0 1 2 3 4 0 ? 114.804 ? 42.7987 ? 31.9174 1 ? 22.6289 0.0 ? 65.0063 ? 48.5279 2 ? 61.2522 ? 66.5602 ? 57.5224 ? 77.0905 ? 76.8305 3 ? 84.4436 ? 82.5056 ? 56.9437 ? 98.8811 4 ? 108.087 ? 98.5103 ? 99.2295 5 ? 110.572 ? 113.601 6 ? 109.829 7 lo = 2 90 0 mhz, rf = 276 0 mhz (horizontal axis is m , vertical axis is n ), and rf in power = 0 dbm. m n 0 1 2 3 4 0 ? 114.956 ? 44.0336 ? 31.2423 1 ? 22.092 0.0 ? 62.6978 ? 48.9358 2 ? 60.2824 ? 69.8043 ? 56.7826 ? 73.218 3 ? 85.957 ? 80.7407 ? 56.7503 ? 105.061 4 ? 108.949 ? 100.938 ? 100.159 5 ? 110.193 ? 111.146 6 ? 111.428 7 ADRF6604 data sheet rev. b | page 16 of 32 r egister s tructure this section provides the register m aps for the ADRF6604 . the three lsbs determine the register that is programmed . register 0 i nteger divide contro l ( default : 0 x 0001c0) divide mode db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 0 0 0 0 dm id6 id5 id4 id3 id2 id1 id0 c3(0) c2(0) c1(0) dm 0 1 id6 id5 id4 id3 id2 id1 id0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 1 0 0 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 ... ... 119 120 (integer mode only) integer divide ratio 21 (integer mode only) 22 (integer mode only) 23 (integer mode only) 24 ... ... 56 (default) integer integer divide ratio control bits divide mode fractional (default) 121 (integer mode only) 122 (integer mode only) 123 (integer mode only) reserved 08553-004 figure 38 . register 0 integer divide control register map register 1 m odulus divid e control (default: 0 x003001) modulus value db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 0 md10 md9 md8 md7 md6 md5 md4 md3 md2 md1 md0 c3(0) c2(0) c1(1) md10 md9 md8 md7 md6 md5 md4 md3 md2 md1 md0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 0 0 0 0 0 0 0 0 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 1 1 1 modulus value ... ... 2047 control bits 1 1536 (default) 2 ... ... reserved 08553-005 figure 39 . register 1 modulus divide control register map data sheet ADRF6604 rev. b | page 17 of 32 r egister 2 f ractional d ivide c ontrol ( default : 0x001802) fd10 fd9 fd8 fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 0 0 0 0 0 0 0 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... fractional value must be less than modulus fractional value 0 1 ... ... 768 (default) ... ... data sheet ADRF6604 rev. b | page 19 of 32 register 5 pll enable and lo path control (def ault: 0 x 0000e5) reserved lo div1 pll en lo div1 lo ext lo drv db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 ldv2 db6 db5 db4 db3 db2 db1 db0 cd3 cd2 cd1 cd0 plen ldv1 lxl ldrv c3(1) c2(0) c1(1) ldrv 0 1 lxl 0 1 ldv1 0 1 divide by 1 divide by 2 (default) lo output driver enable driver off (default) driver on plen 0 1 disable enable (default) pll enable external lo drive enable (pin 37, pin 38) internal lo output (default) external lo input divide-by-2 in lo chain enable cap dac control bits cd3 cd2 cd1 cd0 0 0 0 0 ... ... ... ... min ... capacitor dac control for iip3 optimization 1 1 1 1 max 0 0 0 0 0 0 0 0 0 0 0 0 08553-009 ldv2 0 1 divide by 1 divide by 2 (default) divide-by-2 or 1 figure 43 . register 5 pll enable and lo path control register map regis ter 6 vco control and vco enable ( default : 0x1e2106) charge pump enable 3.3v ldo enable vco enable vco switch vco bw sw ctrl vco en vco ldo enable vco amplitude reserved vco band select from spi vbs[5:0] vco band select from spi 0x00 default charge pump enable 0x01 ?. ?. 0x00 0 ?. ?. 0x18 24 (default) ?. ?. 0x2b 43 ?. ?. 0x3f 63 (recommended) 0x20 0x3f vco sw 0 1 vco switch control from spi regular (default) band cal vco enable disable enable (default) db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 control bits db23 cpen l3en vco en vco sw vc5 vc4 vc3 vc2 vc1 vc0 vbsrc vbs5 vbs4 vbs3 vbs2 vbs1 vbs0 c3(1) c2(1) c1(0) lven vc[5:0] vco amplitude vbsrc 0 1 vco bw cal and sw source control band cal (default) spi 0 1 lven vco ldo enable disable enable (default) 0 1 l3en 3.3v ldo enable disable enable (default) 0 1 cpen disable enable (default) 0 1 0 0 0 08553-010 figure 44 . register 6 vco control and vco enable register map r egister 7 mixer bias enable and exte rnal vco enable ( default : 0x 000007) db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 xvco xvco res mbe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c3(1) c2(1) c1(1) mixer b_en reserved control bits mbe 0 1 xvco 0 1 internal vco (default) external vco mixer bias enable enable (default) disable external vco 08553-011 figure 45 . re gister 7 mixer bias enable and external vco enable register map ADRF6604 data sheet rev. b | page 20 of 32 theory of operat i on the ADRF6604 integrates a h igh performance down converting mixer with a state - of - the - art fractional - n pll. the pll also integrates a low noise vco. the spi port allows the user to control the fractional - n pll functions and the m ixe r optimization functions , as well as allowing for an externally applied lo or vco. the mixer core within the ADRF6604 is the next generation of an industry - leading family of m ixe rs from analog devices , inc . the rf input i s converted to a current and then mixed down to i f using high performance npn transistors. the mixer output currents are transformed to a differential output . the high performance active mixer core results in an exceptional iip3 and i p1db with a very low output noise floor for excellent dynamic range. over the specified frequency range , the ADRF6604 typically provide s if in put p1db of 1 4. 5 db m and iip3 of 27.5 db m. improved performance at specific frequencies can be achieved with the use of the internal capacitor dac (cdac) , which is programm able via the spi port, and by using a resi stor to a 5 v supply from the ip3set pin (p in 29). adjust ment of the capacitor dac allows increments in phase shift at internal nodes in the ADRF6604 , thus allowing cancellation of third - order distortion with no change in supply current. connecting a resistor to a 5 v supply from the ip3set pin increases the internal m ixe r core current, th ereby improving overall i i p2 and i ip3, as well as i p1db. using t he ip3set pin for this purpose increase s the overall supply current. the fractional divide function of the pll allows the frequency multipl ication value from ref _ in to lo o ut put to be a fractional value rather than to be restricted to an integer value as i n tradi - tional plls. in operation, this multiplication value is int + ( frac / mod ) where: int is the integer value. frac is the fractional value . mod is the modulus value . the int, frac, and mod values are all programmable via the spi port. in other frac tio nal - n pll designs, fractional multi - plication is achieved by periodically changing the fractional value in a deterministic way. the disadvantage of this approach is that there are often spurious components close to the fundamental signal. in the ADRF6604 , a - modulator is used to distribute the fractional value randomly, thus significantly reducing the spurious content due to the fr actional function. programming the ADRF6604 the ADRF6604 is programmed via a 3 - pin spi port. the timing requirements for the spi port are shown in figure 2 . e ight pro - grammable regist ers, each with 24 bits, con trol the operation of the device. the register functions are listed in table 8 . table 8. ADRF6604 register functions register function regi ster 0 integer divide control for the pll register 1 modulus divide control for the pll register 2 fractional divide control for the pll register 3 - modulator dither control register 4 pll charge pump, pfd, reference path control register 5 pll en able and lo path control register 6 vco control and vco enable register 7 mixer bias enable and e xternal vco enable note that internal calibration for the pll must be run when the ADRF6604 is initialized at a given frequency. this calibration is run automatically whenever r egister 0, register 1, or register 2 is programmed. because the other registers affect pll performance, register 0, register 1, and register 2 should always be programmed last and in the following order: register 0, register 1, register 2 . to program the frequency of the ADRF6604 , the user typically programs only r egister 0 , register 1, and register 2 . howeve r, if registers other than these are programmed first, a short delay should be inserted before programming r egister 0. this delay e nsure s that the vco band calibration has sufficient time to complete before the final band calibration for r egister 0 is ini tiated. software is available on the ADRF6604 product page under the evaluation boards & kits section that allows easy programming from a pc running windows ? xp or vista. initia l ization seque nce to ensure proper power - up of the ADRF6604 , it is important to reset the pll circuitry after the vcc supply rail settles to 5 v 0.25 v. resetting the pll ensures that the internal bias c ells are properly configured, even under poor supply start - up conditions. to ensure that the pll is reset after power - up, use the following procedure: 1. disable the pll by setting the plen bit to 0 (register 5, bit db6). 2. after a delay of >100 ms, set the pl en bit to 1 (register 5, bit db6) . after this procedure is completed , the other registers should be programmed in the following order: register 7, register 6, register 4, register 3, register 2, register 1. then, after a delay of >100 ms, register 0 shoul d be programmed. data sheet ADRF6604 rev. b | page 21 of 32 lo selection logic the down converting mixer in the ADRF6604 can be used without the internal pll by applying an external differential lo to pin 37 (lon) and pin 38 ( lop ). in addition, when using an lo generated by the internal pll, the lo signal can be accessed directly at these pins. this function can be used for debugging purposes , or the internally generated lo can be used as the lo for a separate mixer. the operation of th e lo generation and whether lop and lon are input s or output s are determined by the logic levels applied at pin 16 (pll_en) and p in 36 (lodrv_en) , as well as b it db 3 (ldrv) and bit db 6 (plen) in r egister 5. the combination of externally applied logic and i nternal bits required for particular lo functions is given in table 9 . table 9 . lo selection logic pins 1 register 5 bits 1 outputs pin 16 (pll_en) pin 36 (lodrv_en) bit db6 (plen) bit db3 (ldrv) output buffer lo 0 x 0 x disabled external 0 x 1 x disabled external 1 x 0 x disabled external 1 0 1 0 disabled internal 1 x 1 1 enabled internal 1 1 1 x enabled internal 1 x = dont care. ADRF6604 data sheet rev. b | page 22 of 32 applications informa tion basic co nnections for operat ion figure 46 shows the basic connections for the ADRF6604 evalu - ation board. the six power supply pins should be individually de coupled using 100 pf and 0.1 f capacitors located as close as possible to the device. in addition, the internal decoupling nodes (decl 3p3, decl2p5, and declvco ) should be decoupled with the capacitor values shown in figure 46. the rf input is i nternally ac - coupled and needs no external bias. the if outputs are open collector , and a bias inductor is required from these outputs to vcc. a peak - to - peak differential swing on rf i n of 1 v (0.353 v rms for a sine wave inpu t) results in an if output power of 4.7 dbm. the reference frequency for the pll should be from 12 mhz to 160 mhz and should be applied to the ref _ in pin , which should be ac - coupled and terminated with a 50 ? resistor as shown in figure 46 . the reference signal , or a divided - down version of the r eference signal , can be brought back off chip at the mu ltiplexer output pin (muxout). a lock detect signal and a voltage proportional to the ambient temperature can also b e selected on the multiplexer output pin . the loop filter is connected between the cp and vtune pins. when connected in this way , the internal vco is operational. for information about th e loop filter compon ents , see the evaluatio n board configuration options section. operation with an external vco is also possible. in this case, the loop filter components should be referred to ground. the output of the loop filter is connected to the input voltage pin of the external vco . the out put of the vco is brought back into the device on the lop and lon pins , using a balun if necessary . 08553-024 r28 0? (0402) rfin mux r set cp vtune lodrv_en lon lop 2:1 mux vco core temp sensor decl2p5 decl3p3 declvco buffer buffer ifn ifp 2 1 4 5 3 ip3set rf in ? + charge pump 250a, 500a (default), 750a, 1000a prescaler 2 muxout ref_in ADRF6604 19 5 8 36 11 7 4 20 15 23 21 25 24 30 28 35 31 26 phase frequency detector third-order fractional interpolator fraction reg modulus integer reg n counter 21 to 123 2 2 4 divider 2 spi interface c43 10f (0603) c14 22pf (0603) cp test point (orange) c13 6.8pf (0603) c40 22pf (0603) c7 0.1f (0402) vcc red +5v vcc vtune c15 2.7nf (1206) c2 open (0402) c1 100pf (0402) r1 0? (0402) r38 0? (0402) r37 0? (0402) r2 open (0402) c42 10 f (0603) c17 0.1 f (0402) r63 open (0402) r65 10k? (0402) r9 1 0k? (0402) r12 0? (0402) r10 3k? (0603) r62 0? (0402) r11 open (0402) rfout c16 100p f (0402) r18 0? (0402) c41 open (0603) c11 0.1 f (0402) c27 0.1 f (0402) c29 0.1 f (0402) c12 100p f (0402) r8 0? (0402) r16 0? (0402) c31 1nf (0402) c6 1nf (0402) r55 open (0402) vcc1 red s1 open r56 0? (0402) c5 1nf (0402) r70 49.9? (0402) 4 lo in/out ref_in refout 3 5 1 t8 tc1-1-13+ r20 0? (0402) r54 10k ? (0402) r19 0? (0402) s2 r53 10k ? (0402) r35 0? (0402) r30 0? (0402) r50 open (0402) r57 0? (0402) r36 0? (0402) p1 9-pin dsub vcc_lo vcc2 vcc1 pll_en clk data le 27 13 12 c8 100pf (0402) r6 0? (0402) c25 0.1f (0402) c24 100pf (0402) r26 0? (0402) c23 0.1f (0402) c22 100pf (0402) r25 0? (0402) c20 0.1f (0402) c21 100pf (0402) r24 0? (0402) c19 0.1f (0402) c18 100pf (0402) r17 0? (0402) c9 0.1f (0402) c10 100pf (0402) r7 0? (0402) 2 4 6 1 3 5 7 c32 open (0402) r51 open (0402) c33 open (0402) r52 open (0402) c34 open (0402) 14 div by 2, 1 vcc_mix vcc_v2i vcc_lo r27 0? (0402) r43 0? (0402) vcc +5v r59 0? (0402) 16 2 9 29 18 40 39 3 6 38 37 34 22 17 10 1 8 9 figure 46 . basic connections for operation of the ADRF6604 data sheet ADRF6604 rev. b | page 23 of 32 ac test fixture characterization data for the ADRF6604 was taken under very strict test conditions. all possible techniques we re used to achieve optimum a ccuracy and to remove degrading effe cts of the signal generation and measurement equipment. figure 47 shows the typical ac test set up used in the characterization of the ADRF6604 . rohde & schwarz fsea30 if_out agilent 34401a set to idc (set for supply current) rf1 agilent n5181a rf2 agilent n5181a ref_in agilent n5181a hp 11636a power divider agilent 34980a with three 34921 modules and one 34950 module ADRF6604 characterization rack diagram. all instruments are controlled by a lab computer via a usb to gpib controller, daisy chained to each individual instrument. ref_in rf in 5v dc via 10-pin dc header 5v dc measured for supply current agilent e3631a 25v set to 3.3v, 6v set to 5v. returns are jumpered together ADRF6604 evaluation board gnd via 10-pin dc header 3.3v dc via 10-pin dc header 9-pin controller d-sub and 10-pin dc header 08553-027 figure 47 . ADRF6604 ac test setu p ADRF6604 data sheet rev. b | page 24 of 32 evaluation board figure 50 shows the schematic of the r o hs - compliant evalu a tion board fo r the ADRF6604 . this board has four layers and was designed using ro gers 4350 hybrid m aterial to minimize high frequency losses. fr4 material is also adequate if the design can accept the sli ghtly higher trace loss of this material. the evaluation board is designed to operate using the internal vco of the device ( the default configuration) or using an external vco. to use an external vco, r62 and r12 should be removed. place 0 ? resistors in r 63 and r11. the input of the external vco should be connected to the vtune sma connector , and the external vco output should be connected to the lo in/out sma connector. in addition to these hardware changes, internal register settings must be changed to e nable operation with an external vco (see the register 6 vco control and vco enable (default: 0 x 1e2106) section) . additional configuration options for the evaluation board are described in table 10. evaluation b oard control s oftware software to program the ADRF6604 is available for download from the ADRF6604 product page under the evaluation boards & kits section . to install the software 1. d ownload and extract the zip file : adrf6x0x_ customer_6p0p0 _ install. zip file . 2. follow the instructions in the read me file. the evaluation board can be connected to the pc using a pc parallel port or a usb port. these options are selectable from the opening menu of the software interface (see figure 48 ). the evaluation board is shipped with a 25 - pin parallel port cable for connection to the pc parallel port. to connect the evaluation board to a usb port , a usb adapter board ( e va l - adf4xxxz - usb ) must be p urchased from analog d evices . this board connects to the pc using a standard usb cable with a usb mini - connector at one end. an additional 25 - pin male to 9 - pin female adapter is required to mate the e va l - adf4xxxz - usb board to the 9 - pin d - s ub connector on the ADRF6604 evaluation board. 08553-028 figure 48 . control software opening menu figure 49 shows the main window of the control software with the default settings displayed. data sheet ADRF6604 rev. b | page 25 of 32 08553-029 figure 49 . main window of the ADRF6604 evaluation board software ADRF6604 data sheet rev. b | page 26 of 32 schematic and artwor k 08553-023 a g n d a g n d a g n d a g n d a g n d n c a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d a g n d e - p a d a g n d a g n d a g n d a g n d a g n d a g n d a g n d 1 v c c 1 v cc 2 1 v cc 5 1 v cc _ l o 1 1 v cc _ bb 1 1 v cc _ r f 1 v cc 1 1 v cc _ l o 1 v cc 4 1 v c o _ l d o 1 c p 1 d a t a 1 i p 3 se t 1 l e 1 cl k 1 2 p 5 v 1 o s c _ 3 p 3 v 1 3 p 3 v 1 r 1 0 3 k r 6 3 100 k r 3 7 0 d n i r 1 1 r 1 2 0 0 r 6 2 10 k r 6 5 r 9 10 k 22 p f c 4 0 c 1 4 22 p f c 1 3 6 . 8 p f c 1 5 2 . 7 n f l 2 t b d l 1 t b d c 3 6 d n i c 3 5 d n i 0 r 6 6 r 6 7 0 r 6 8 0 d n i c 4 1 10 u f 0 . 1 u f c 9 10 u f c 4 2 10 u f c 4 3 p 1 - 6 p 1 - 1 1 2 3 4 5 6 7 8 9 p1 a m p 745781 - 4 t b d r 2 7 i p 3 se t c 3 4 100 p f d n i 100 p f d n i c 3 3 c 3 2 100 p f d n i 1 k d n i r 5 2 r 5 1 1 k d n i 1 k d n i r 5 0 c 2 8 10 u f r 4 7 0 0 r 4 8 v c c v c c 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 5 1 6 1 8 2 0 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 2 1 1 3 1 4 1 7 1 9 p a d z 1 v cc _ b b r 6 0 t b d r 4 4 d n i v c c 4 6 1 3 2 t 3 t c 4 - 1 w r 5 9 0 0 r 4 3 0 . 1 u f c 2 9 c 2 5 0 . 1 u f d n i r 5 8 1 di g _ g n d r 3 6 0 0 r 5 7 1 2 3 s 2 r 5 3 10 k 10 k r 5 4 r 5 6 10 k v c c c 3 1 1000 p f r 4 9 d n i 1 n f c 6 c 5 1 n f l o _ e x t e r n 0 r 3 3 10 k r 5 5 v c c 3 2 1 s 1 o u tp u t _ e n 0 r 3 0 r 1 9 0 100 p f c 1 0 r 1 8 0 d n i r 2 c 1 2 100 p f 0 r 2 5 r 2 6 0 0 r 3 8 r 8 0 0 r 3 5 1 g n d 0 r 2 9 v c c 1 j 1 y 1 r 1 0 v cc _ se n s e s n s 1 s n s v c o _ l d o l o _ e x t e r n 2 p 5 v _ l d o 3 p 3 v _ l d o ag n d v cc _ se n s e ag n d v c c 1 0 j 1 8 j 1 r 2 0 0 v cc _ b b v cc _ l o v cc _ r f v cc _ b b v cc _ l o v cc _ l o 0 r 2 8 r 1 4 d n i r 1 5 0 c 3 10 p f c 4 22000 p f 0 . 1 u f c 7 0 r 6 c 2 0 . 1 u f c 1 100 p f 100 p f c 8 0 r 7 c 1 1 0 . 1 u f r e f i n r e f o u t r 1 6 0 0 . 1 u f c 1 9 100 p f c 1 8 c 1 7 0 . 1 u f c 1 6 100 p f 0 r 1 7 o u t c 2 1 100 p f r 2 4 0 c 2 0 0 . 1 u f 0 . 1 u f c 2 3 100 p f c 2 2 c 2 4 100 p f 0 . 1 u f c 2 7 r f i n v c c 0 r 3 1 r 3 2 0 0 r 3 4 2 j 1 3 j 1 4 j 1 5 j 1 6 j 1 7 j 1 9 j 1 1 g n d 1 1 g n d 2 v cc _ r f i f n i f p o s c _ 3 p 3 v v c c p 4 - t 7 p 4 - t 7 p 3 - t 7 p 3 - t 7 p 1 - t 7 p 1 - t 7 p 1 - t 7 l o 0 r 6 9 1 1 a 2 2 a 3 3 a 4 4 a 5 5 a 6 6 a t 7 1 5 3 4 2 t 8 p 3 - t 7 p 4 - t 7 o u tp u t _ e n i p 3 se t r 7 0 49 . 9 3 p 3 v _ l d o v c o _ l d o 2 p 5 v _ l d o v t u n e p 1 - 6 r 7 2 0 p 1 - 1 r 7 1 t b d vcc1 decl3p3 cp gnd r set ref_ in gnd muxout decl2p5 vcc2 gnd gnd gnd rf in vcc_v2i gnd ip3set gnd vcc_mix gnd nc vcc_lo gnd lodrv_en lon lop vtune declvco nc gnd gnd data clk gnd vcc_lo pll_en ifp ifn gnd le figure 5 0 . evaluation boar d schematic data sheet ADRF6604 rev. b | page 27 of 32 08553-013 figure 51 . evaluation board layout (bottom) 08553-012 figure 52 . evaluation board layout (top) ADRF6604 data sheet rev. b | page 28 of 32 evaluation board c onfiguration options table 10. component descriptio n default condition/ option settings s1, r55, r56, r33 lo select. switch and resistors to ground the lodrv_en pin. the lodrv_en pin setting , in combination with internal register settings, determines whether the lo p and lon pins function as inputs or outp uts (see the lo selection logic section for more information) . s1 = r55 = open (not installed) , r56 = r33 = 0 ? , lodrv_en = 0 v lo in/out sma connector lo input/o utput . an external 1 lo or 2 lo can be applied to this single - ended input connector . lo input refin sma connector reference i nput . the input reference frequency for the pll is applied to this conn ector. input impedance is 5 0 ?. refout sma connector multiplexer output. the refout connector connects directly to the muxout pin. the on- board multiplexer can be programmed to b ring out the following signals: refin, 2 refin, refin/2, and refin/4 ; t em perature sensor o utput v oltage ; and l ock d etect indicator . lock detect cp test point charge p ump t est p oint . the unfiltered charge pump signal can be probed at this test point. note that th e cp pin should not be probed during critical measurements , such a s phase noise. r37, c14, r9, r10, c15, c13, r65, c40 loop filter . loop filter components . r11, r12 loop f ilter r eturn . when the internal vco is used, the loop filter co mponents should be returned to the declvco pin ( pin 40 ) by installing a 0 ? resistor in r12. when an external vco is used, the loop filter components can be returned to ground by installing a 0 ? resistor in r11 . r12 = 0 ? (0402) , r11 = open (0402) r62, r63, vtune sma connector internal vs. e xternal vco . when the internal vco is enabled, the loop filter components are connect ed directly to the vtune pin (pin 39) by installing a 0 ? resistor in r62. to use an external vco, r62 should be left open. a 0 ? resistor should be installed in r63 , and the voltage input of the vco shoul d be connected to the vtune sma connector. the output of the vco is brought back into the pll via the lo in/out sma connector. r62 = 0 ? (0402) , r63 = open (0402) r2 r set p in . this pin is unused and should be left open . r2 = open (0402) rfin sma connecto r rf i nput . the rf i nput signal should be applied to the rfin sma connector. the rf input of the ADRF6604 is ac - coupled ; therefore, no bias is necessary. r3 = r23 = open (0402) t3 if o utput . the differential if o utput s ignal s from the ADRF6604 (ifp and ifn) are converted to a single - ended signal by t3. data sheet ADRF6604 rev. b | page 29 of 32 outline dimensions 1 40 10 1 1 31 30 21 20 compliant t o jedec s t andards mo-220-vjjd-2 06-01-2012-d 0.50 bsc pin 1 indic a t or 4.50 ref 0.20 min 0.50 0.40 0.30 t o p view 12 max 0.80 max 0.65 ty p sea ting plane coplanarit y 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 4.25 4.10 sq 3.95 0.60 max 0.60 max pin 1 indic a t or 6.10 6.00 sq 5.90 5.85 5.75 sq 5.65 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. exposed pad (bottom view) figure 53 . 40- l ead l ead fr ame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad ( cp - 40 - 1 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADRF6604 acpz -r7 ? 40c to +85 c 40- lead lead frame chip scale package [ lfcsp_vq] cp -40-1 ADRF6604 - evalz evaluation board 1 z = rohs compliant part. ADRF6604 data sheet rev. b | page 30 of 32 notes data sheet ADRF6604 rev. b | page 31 of 32 notes ADRF6604 data sheet rev. b | page 32 of 32 notes ? 2010 C 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owner s. d08553 - 0- 1/14(b) |
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