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nxp semiconductors data sheet: technical data document number: imx6ullcec rev. 1.2, 11/2017 ordering information see table 1 on page 3 mcimx6y0dvm05aa mcimx6y0dvm05ab mcimx6y1dvm05aa mcimx6y1dvm05ab mcimx6y1dvk05aa mcimx6y1dvk05ab mcimx6y2dvm05aa mcimx6y2dvm05ab MCIMX6Y2DVM09AA mcimx6y2dvm09ab mcimx6y7dvm09aa mcimx6y7dvm09ab mcimx6y7dvk05aa mcimx6y7dvk05ab mcimx6y2dvk09ab package information plastic package mapbga 14 x 14 mm, 0.8 mm pitch mapbga 9 x 9 mm, 0.5 mm pitch ? 2016-2017 nxp b.v. 1 i.mx 6ull introduction the i.mx 6ull processors represent nxp?s latest achievement in integrated multimedia-focused products offering high performance proc essing with a high degree of functional integration, ta rgeted towards the growing market of connected devices. the i.mx 6ull is a high performance, ultra efficient processor family with featuring nxp?s advanced implementation of the single arm cortex ? -a7 core, which operates at speeds of up to 900 mhz. i.mx 6ull includes integrated power management module that reduces the complexity of external power supply and simplifies the power sequencin g. each processor in this family provides various memory interfaces, including lpddr2, ddr3, ddr3l, raw and managed nand flash, nor flash, emmc, quad spi, and a wide range of other interfaces for connecti ng peripherals, such as wlan, bluetooth?, gps, displays, and camera sensors. i.mx 6ull applications processors for consumer products 1. i.mx 6ull introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. ordering information . . . . . . . . . . . . . . . . . . . . . . . 3 1.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3. modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1. special signal considerations . . . . . . . . . . . . . . . 18 3.2. recommended connections for unused analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1. chip-level conditions . . . . . . . . . . . . . . . . . . . . . 21 4.2. power supplies requirements and restrictions . 31 4.3. integrated ldo voltage regulator parameters . . 32 4.4. pll?s electrical characteristics . . . . . . . . . . . . . . . 34 4.5. on-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . 35 4.6. i/o dc parameters . . . . . . . . . . . . . . . . . . . . . . . . 36 4.7. i/o ac parameters . . . . . . . . . . . . . . . . . . . . . . . . 40 4.8. output buffer impedance parameters . . . . . . . . . 43 4.9. system modules timing . . . . . . . . . . . . . . . . . . . . 45 4.10. multi-mode ddr controller (mmdc) . . . . . . . . . . 57 4.11. general-purpose media interface (gpmi) timing 58 4.12. external peripheral interface parameters . . . . . . . 66 4.13. a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5. boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . 103 5.1. boot mode configuration pins . . . . . . . . . . . . . . 103 5.2. boot device interface allocation . . . . . . . . . . . . . 104 6. package information and contact assignments . . . . . 111 6.1. 14 x 14 mm package information . . . . . . . . . . . . 111 6.2. 9 x 9 mm package information . . . . . . . . . . . . . . 124 7. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
i.mx 6ull applications processors for consumer products, rev. 1.2, 11/2017 2 nxp semiconductors i.mx 6ull introduction the i.mx 6ull processors are specifically useful fo r applications such as: ? telematics ? audio playback ? connected devices ? iot gateway ? access control panels ? human machine interfaces (hmi) ? portable medical and health care ? ip phones ? smart appliances ?ereaders the features of the i.mx 6ull processors include: ? single-core arm cortex -a7?the single core a7 provides a cost-effective and power-efficient solution. ? multilevel memory system?the multilevel memo ry system of processor is based on the l1 instruction and data caches, l2 cache, and intern al and external memory. the processor supports many types of external memory devices, in cluding ddr3, low voltage ddr3, lpddr2, nor flash, nand flash (mlc and slc), onenand ?, quad spi, and managed nand, including emmc up to rev 4.4/4.41/4.5. ? smart speed technology?power management implemented throughout the ic that enables multimedia features and peripherals to consum e minimum power in both active and various low power modes. ? dynamic voltage and frequency sc aling?the power efficiency of devices by scaling the voltage and frequency to optimize performance. ? multimedia powerhouse?the multimedia performance of proces sor is enhanced by a multilevel cache system, neon? mpe (media processor engine) co-processor, a programmable smart dma (sdma) controller, an asynchronous audio sample rate converter, an electrophoretic display (epd) controller, and a pixel processing pipe line (pxp) to support 2d image processing, including color-space conversion, scaling, alpha-blending, and rotation. ? 2x ethernet interfaces?2x 10/100 mbps ethernet controllers. ? human-machine interface?each processor suppor ts one digital parallel display interface. ? interface flexibility?each processor supports connections to a variet y of interfaces: two high-speed usb on-the-go with phy, multiple e xpansion card ports (high-speed mmc/sdio host and other), two 12-bit adc modules with up to 10 total input channels and two can ports. ? advanced security?the processors deliver hardware -enabled security featur es that enable secure e-commerce, digital rights mana gement (drm), information encryption, secure boot, aes-128 encryption, sha-1, sha-256 hw acc eleration engine, and secure software downloads. the security features are discussed in the i.mx 6ull security reference manual (imx6ullsrm). i.mx 6ull introduction i.mx 6ull applications processors for consumer products, rev. 1.2, 11/2017 nxp semiconductors 3 ? integrated power management?the processors integrate linear regul ators and internally generate voltage levels for different domains. this si gnificantly simplifies system power management structure. for a comprehensive list of the i.mx 6ull features, see section 1.2, ?features " ? . 1.1 ordering information table 1 provides examples of or derable part numbers cove red by this data sheet. table 1. ordering information part number feature package junction temperature t j ( ? c) mcimx6y0dvm05aa mcimx6y0dvm05ab features supports: ? 528 mhz, commercial grade for general purpose ? no security ? no lcd/csi ?no can ? ethernet x1 ? usb otg x1 ? adc x1 ?uart x4 ?sai x1 ? no esai ?timer x2 ?pwm x4 ?i2c x2 ?spi x2 14 x 14 mm, 0.8 pitch mapbga 0 to +95 mcimx6y1dvm05aa mcimx6y1dvm05ab features supports: ? 528 mhz, commercial grade for general purpose ? basic security ? no lcd/csi ?can x1 ? ethernet x1 ? usb otg x2 ? adc x1 ?uart x8 ?sai x3 ?esai x1 ?timer x4 ?pwm x8 ?i2c x4 ?spi x4 14 x 14 mm, 0.8 pitch mapbga 0 to +95 i.mx 6ull applications processors for consumer products, rev. 1.2, 11/2017 4 nxp semiconductors i.mx 6ull introduction mcimx6y2dvm05aa mcimx6y2dvm05ab features supports: ? 528 mhz, commercial grade for general purpose ? basic security ? with lcd/csi ?can x2 ? ethernet x2 ? usb otg x2 ? adc x2 ?uart x8 ?sai x3 ?esai x1 ?timer x4 ?pwm x8 ?i2c x4 ?spi x4 14 x 14 mm, 0.8 pitch mapbga 0 to +95 mcimx6y1dvk05aa mcimx6y1dvk05ab features supports: ? 528 mhz, commercial grade for general purpose ? basic security ? no lcd/csi ?can x1 ? ethernet x1 ? usb otg x2 ? adc x1 ?uart x8 ?sai x3 ?esai x1 ?timer x4 ?pwm x8 ?i2c x4 ?spi x4 9 x 9 mm, 0.5 pitch mapbga 0 to +95 mcimx6y7dvk05aa mcimx6y7dvk05ab features supports: ? 528 mhz, commercial grade for general purpose ? basic security ? with lcd/csi ?epdc ?no can ? ethernet x1 ? usb otg x2 ? adc x2 ?uart x4 ?sai x3 ?esai x1 ?timer x4 ?pwm x4 ?i2c x4 ?spi x4 9 x 9 mm, 0.5 pitch mapbga 0 to +95 table 1. ordering information part number feature package junction temperature t j ( ? c) i.mx 6ull introduction i.mx 6ull applications processors for consumer products, rev. 1.2, 11/2017 nxp semiconductors 5 figure 1 describes the part number nomencl ature so that the users can identify the characteristics of the specific part number they have (for example, cores, frequency, temp erature grade, fuse options, and silicon mcimx6y2dvk09ab features supports: ? 900 mhz, commercial grade for general purpose ? basic security ? with lcd/csi ?can x2 ? ethernet x2 ? usb otg x2 ? adc x2 ?uart x8 ?sai x3 ?esai x1 ?timer x4 ?pwm x8 ?i2c x4 ?spi x4 9 x 9 mm, 0.5 pitch mapbga 0 to +95 mcimx6y2dvm09ab mcimx6y2dvm09ab features supports: ? 900 mhz, commercial grade for general purpose ? basic security ? with lcd/csi ?can x2 ? ethernet x2 ? usb otg x2 ? adc x2 ?uart x8 ?sai x3 ?esai x1 ?timer x4 ?pwm x8 ?i2c x4 ?spi x4 14 x 14mm, 0.8 pitch mapbga 0 to +95 mcimx6y7dvm09aa mcimx6y7dvm09ab features supports: ? 900 mhz, commercial grade for general purpose ? basic security ? with lcd/csi ?epdc ?no can ? ethernet x1 ? usb otg x2 ? adc x2 ?uart x4 ?sai x3 ?esai x1 ?timer x4 ?pwm x4 ?i2c x4 ?spi x4 14 x 14mm, 0.8 pitch mapbga 0 to +95 table 1. ordering information part number feature package junction temperature t j ( ? c) i.mx 6ull applications processors for consumer products, rev. 1.2, 11/2017 6 nxp semiconductors i.mx 6ull introduction revision). the primary characteristic which describes which data sheet a pplies to a specific part is the temperature grade (junction) field. ? the i.mx 6ull applications processors for consumer pr oducts data sheet (imx6ullcec) covers parts listed with a ?d (commercial temp)? ensure to have the proper data sheet for specific pa rt by verifying the temperat ure grade (junction) field and matching it to the proper data sheet. if th ere will be any questions, visit the web page nxp.com/imx6series or contact a nxp representative for details. figure 1. part number nomenclature?i.mx 6ull 1.2 features the i.mx 6ull processors are based on arm cortex-a7 mpcore? pl atform, which has the following features: ? supports single arm cortex-a7 mp core (with trustzone) with: ? 32 kb l1 instruction cache ? 32 kb l1 data cache ? private timer and watchdog part differentiator @ with epdc 7 reserved 6 5 4 3 general purpose 2 (full feature) 2 general purpose 1 (reduced feature) 1 baseline 0 junction temperature (tj) + consumer: 0 to + 95 c d industrial: -40 to +105 c c arm cortex-a7 frequency $$ 528 mhz 05 792 mhz 08 900 mhz 09 package type rohs mapbga 14 x 14 mm, 0.8 pitch vm mapbga 9 x 9 mm, 0.5 pitch vk qualification level mc prototype samples pc mass production mc special sc i.mx 6 family x i.mx 6ull y silicon rev a rev 1.0 (mask number: 0n70s) a rev 1.1 (mask number: 1n70s) b fuse option % reserved a mc imx6 x @ + vv $$ % a i.mx 6ull introduction i.mx 6ull applications processors for consumer products, rev. 1.2, 11/2017 nxp semiconductors 7 ? cortex-a7 neon media processing engine (mpe) co-processor ? general interrupt controller (gic) with 128 interrupts support ? global timer ? snoop control unit (scu) ? 128 kb unified i/d l2 cache ? single master axi bus interface output of l2 cache ? frequency of the core (includi ng neon and l1 cache), as per table 10, "operating ranges," on page 24 . ? neon mpe coprocessor ? simd media processing architecture ? neon register file with 32x64- bit general-purpose registers ? neon integer execute pipe line (alu, shift, mac) ? neon dual, single-precision floating poi nt execute pipeli ne (fadd, fmul) ? neon load/store and permute pipeline ? 32 double-precision vfpv3 floating point registers the soc-level memory system consists of the following a dditional components: ? boot rom, including hab (96 kb) ? internal multimedia/shared, fa st access ram (ocram, 128 kb) ? external memory interfaces: the i.mx 6ull proces sors support latest, high volume, cost effective handheld dram, nor, and nan d flash memory standards. ? 16-bit lp-ddr2-800, 16-bit ddr3-800 and ddr3l-800 ? 8-bit nand-flash, including support for raw ml c/slc, 2 kb, 4 kb, and 8 kb page size, ba-nand, pba-nand, lba-n and, onenand? and others. bch ecc up to 40 bits. ? 16/8-bit nor flash. all eimv2 pins are muxed on other interfaces. each i.mx 6ull processor enables th e following interfaces to external devices (some of them are muxed and not available simultaneously): ?displays: ? one parallel display port, support max 85 mhz display clock and up to wxga (1366 x 768) at 60 hz ? support 24-bit, 18-bit, 16-bit, and 8-bit parallel display ? electrophoretic display contro ller support direct-d river for e-ink epd panel, with up to 2048x1536 resolution at 106 hz ? camera sensors: ? one parallel camera port, up to 24 bit and 133.3 mhz pixel clock ? support 24-bit, 16-bit, 10-bit, and 8-bit input ? support bt.656 interface ? expansion cards: ? two mmc/sd/sdio card ports all supporting: i.mx 6ull applications processors for consumer products, rev. 1.2, 11/2017 8 nxp semiconductors i.mx 6ull introduction ? 1-bit or 4-bit transfer mode specifications for sd and sd io cards up to uhs-i sdr-104 mode (104 mb/s max) ? 1-bit, 4-bit, or 8-bit transfer mode specific ations for mmc cards up to 52 mhz in both sdr and ddr modes (104 mb/s max) ? 4-bit or 8-bit transfer m ode specifications for emmc ch ips up to 200 mhz in hs200 mode (200 mb/s max) ?usb : ? two high speed (hs) usb 2.0 otg (up to 480 mbps), with integrated hs usb phy ? miscellaneous ips and interfaces: ? three i2s/sai/ac97, up to 1.4 mbps each ?esai ? sony philips digital interface format (spdif), rx and tx ? eight uarts, up to 5.0 mbps each: ? providing rs232 interface ? supporting 9-bit rs485 multidrop mode ? support rts/cts for hardware flow control ? four ecspi (enhanced cspi), up to 52 mbps each ? four i 2 c, supports 400 kbps ? two 10/100 ethernet controller (ieee1588 compliant) ? eight pulse width modulators (pwm) ? system jtag controller (sjc) ? gpio with interrupt capabilities ? 8x8 key pad port (kpp) ? one quad spi to connect to serial nor flash ? two flexible controller area network (flexcan) ? three watchdog timers (wdog) ? 8-bit/10-bit/12-bit/16- bit camera interface ? two 12-bit analog to digital converters (adc ) with up to 10 input channels in total the i.mx 6ull processors in tegrate advanced power mana gement unit and controllers: ? provide pmu, including ldo su pplies, for on-chip resources ? use temperature sensor for monitoring the die temperature ? use voltage sensor for monitoring the die voltage ? support dvfs techniques for low power modes ? use sw state retention and power gating for arm and neon ? support various levels of system power modes ? use flexible clock gating control scheme i.mx 6ull introduction i.mx 6ull applications processors for consumer products, rev. 1.2, 11/2017 nxp semiconductors 9 the i.mx 6ull processors use dedicated hardware accelerators to meet the targeted multimedia performance. the use of hardware a ccelerators is a key factor in obtai ning high performanc e at low power consumption numbers, while having the cpu core relatively free for performing other tasks. the i.mx 6ull processors incorporat e the following hardware accelerators: ? pxp?pixel processing pipeline for image resize, rotation, overlay and csc. off loading key pixel processing operations are required to support the lcd disp lay applications. ? asrc?asynchronous sample rate converter security functions are enabled and accelerated by the following hardware: ? arm trustzone including the tz architecture (s eparation of interrupts, memory mapping, etc.) ? sjc?system jtag controller. protecting jt ag from debug port attacks by regulating or blocking the access to th e system debug features. ? snvs?secure non-volatile storage, including se cure real time clock, both active tamper and passive tamper detection logic has up to 10 tamper inputs. voltage monitor, temperature monitor, and clock frequency monitor prot ects the secure key storage. ? csu?central security unit. enhancement for the ic identification module (iim). will be configured during boot and by efus es and will determine the secu rity level operation mode as well as the tz policy. ? a-hab?advanced high assurance boot?hab v4 with the new embedded enhancements: aes-128 encryption, sha-1, and sha-256 hw accel eration engine, 2048-bi t rsa key, version control mechanism, warm boot, csu, and tz initialization. note the actual feature set depends on th e part numbers as described in table 1. functions, such as display and camer a interfaces, connectivity interfaces. i.mx 6ull applications processors for consumer products, rev. 1.2, 11/2017 10 nxp semiconductors architectural overview 2 architectural overview the following subsections provide an architectural overview of th e i.mx 6ull processor system. 2.1 block diagram figure 2 shows the functional modules in the i.mx 6ull processor system. . figure 2. i.mx 6ull system block diagram ' h e x j ' $ 3 7 3 , 8 & |