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integrated circuit systems, inc. ics9250-29 third party brands and names are the property of their respective owners. block diagram 9250-29 rev a 02/01/01 recommended application: solano type chipset. output features: ? 2 cpu (2.5v) (up to 133mhz achievable through i 2 c) 13 sdram (3.3v) (up to 133mhz achievable through i 2 c) 5 pci (3.3 v) @33.3mhz 1 ioapic (2.5v) @ 33.3 mhz 3 hublink clocks (3.3 v) @ 66.6 mhz 2 (3.3v) @ 48 mhz (non spread spectrum) 1 ref (3.3v) @ 14.318 mhz features: supports spread spectrum modulation, 0 to -0.5% down spread. i 2 c support for power management efficient power management scheme through pd# uses external 14.138 mhz crystal alternate frequency selections available through i 2 c control. functionality pin configuration 56-pin 300mil ssop * this input has a 50k w pull-down to gnd. ** this input has a 50k w pull-up to vdd ioapic vddl gndl *fs1/ref vddr x1 x2 gndr vdd3 3v66-0 3v66-1 3v66-2 gnd3 pciclk0 pciclk1 pciclk2 vdd2 gnd2 pciclk3 pciclk4 fs0 gnda vdda sclk s data gndf vddf 48mhz_0 gndl vddl cpuclk0 cpuclk1 gnd1 sdram0 sdram1 vdd1 gnd1 sdram2 sdram3 sdram4 sdram5 vdd1 gnd1 sdram6 sdram7 sdram8 sdram9 vdd1 gnd1 sdram10 sdram11 vdd1 gnd1 sdram12 tristate#/pd#** 48mhz_1 ics9250-29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 frequency generator & integrated buffers for celeron & p ii / iii ? ref cpu66/100/133 [1:0] vddl 3v66 [2:0] sdram [12:0] pciclk [4:0] ioapic vddl pll2 48mhz [1:0] x1 x2 xtal osc control logic config reg fs(1:0) pd# tristate# 2 2 3 13 5 /2 /2 /3 /2 pll1 spread spectrum sdata sclk # e t a t s i r t0 s f1 s f u p c z h m m a r d s z h m 00x e t a t s i r te t a t s i r t 01xt s e tt s e t 100 z h m 6 6z h m 0 0 1 110 z h m 0 0 1z h m 0 0 1 101 z h m 3 3 1z h m 3 3 1 111 z h m 3 3 1z h m 0 0 1 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. power groups vdda, gnda = cpu, pll (analog) vddf, gndf = fixed pll, 48m (analog/digital) vddr, gndr = ref, x1, x2 (analog/digital) vdd3, gnd3 = 3v66 (digital) vdd2, gnd2 = pci (digital) vdd1, gnd1 = sdram (digital) vddl, gndl = ioapic, cpu (digital)
2 ics9250-29 the ics9250-29 is a single chip clock solution for solano type chipset. it provides all necessary clock signals for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces emi by 8db to 10 db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9250-29 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. general description pin configuration r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 1c i p a o it u o. z h m 3 . 3 3 t a g n i n n u r t u p t u o k c o l c v 5 . 2 5 5 , 2l d d vr w pc i p a o i & u p c r o f y l p p u s r e w o p v 5 . 2 6 5 , 3l d n gr w pc i p a o i & u p c r o f y l p p u s r e w o p v 5 . 2 r o f d n u o r g 4 1 s fn iy t i l a n o i t c n u f t u p t u o l l a , y c n e u q e r f u p c s e n i m r e t e d . n i p t c e l e s n o i t c n u f f e rt u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3 , 7 2 , 3 2 , 7 1 , 9 , 5 9 4 , 3 4 , 7 3 , 3 3 x d d vr w py l p p u s r e w o p v 3 . 3 61 xn i k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 72 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 3 3 ( p a c , 6 2 , 2 2 , 8 1 , 3 1 , 8 2 5 , 8 4 , 2 4 , 6 3 , 2 3 x d n gr w py l p p u s v 3 . 3 r o f s n i p d n u o r g 0 1 , 1 1 , 2 1) 0 : 2 ( 6 6 v 3t u ob u h r o f s t u p t u o k c o l c z h m 6 6 d e x i f v 3 . 3 1 20 s fn i. y t i l a n o i t c n u f t u p t u o l l a , y c n e u q e r f u p c s e n i m r e t e d . n i p t c e l e s n o i t c n u f 4 1 , 5 1 , 6 1 , 9 1 , 0 2) 0 : 4 ( k l c i c pt u os t u p t u o k c o l c i c p v 3 . 3 0 3 # e t a t s i r tn i # e t a t s i r t e h t o t s t l u a f e d n i p # d p / # e t a t s i r t e h t p u r e w o p t a d e r a h s e e s ( . s e d o m t s e t d n a # e t a t s i r t e h t e l b a n e o t n o i t c n u f t u p n i . ) n o i t p i r c s e d l l u f r o f n o i t a r e p o n i p # d pn i o t n i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a d n a o c v e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i e h t . e t a t s r e w o p w o l a e b t o n l l i w n w o d r e w o p e h t f o y c n e t a l e h t . d e p p o t s e r a l a t s y r c e h t . s m 3 n a h t r e t a e r g 4 2k l c sn ii f o t u p n i k c o l c 2 t u p n i c 5 2a t a d sn ii r o f t u p n i a t a d 2 . t u p n i l a i r e s c 8 2 , 9 2) 0 : 1 ( z h m 8 4t u o. s t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 , 8 3 , 5 3 , 4 3 , 1 3 , 4 4 , 1 4 , 0 4 , 9 3 1 5 , 0 5 , 7 4 , 6 4 , 5 4 m a r d s ] 0 : 2 1 [ t u o n a c s t u p t u o m a r d s l l a . z h m 3 3 1 d n a z h m 0 0 1 g n i n n u r t u p t u o v 3 . 3 i h g u o r h t f f o d e n r u t e b 2 c 4 5 , 3 5) 0 : 1 ( k l c u p ct u o g n i d n e p e d z h m 3 3 1 r o z h m 0 0 1 , z h m 6 6 . t u p t u o k c o l c s u b t s o h v 5 . 2 . s n i p s f n o
3 ics9250-29 power down waveform note 1. after pd# is sampled active (low) for 2 consective rising edges of cpuclks, all the output clocks are driven low on their next high to low tranistiion. 2 . power-up latency <3ms. 3. waveform shown for 100mhz maximum allowed current clock enable configuration # d pk l c u p cm a r d sc i p a o i6 6 v 3k l c i c p , f e r z h m 8 4 c s os o c v 0w o lw o lw o lw o lw o lw o lf f of f o 1n on on on on on on on o o n a l o s n o i t i d n o c n o i t p m u s n o c y l p p u s v 5 . 2 x a m , s d a o l p a c e t e r c s i d x a m v 5 2 6 . 2 = 2 q d d v d n g r o 3 q d d v = s t u p n i c i t a t s l l a n o i t p m u s n o c y l p p u s v 3 . 3 x a m , s d a o l p a c e t e r c s i d x a m v 5 6 4 . 3 = 3 q d d v d n g r o 3 q d d v = s t u p n i c i t a t s l l a e d o m n w o d r e w o p ) 0 = # n w d r w p ( a m 2a m 2 z h m 6 6 e v i t c a l l u f 0 0 = ) 0 : 1 ( s f a m 5 3a m 0 4 4 z h m 0 0 1 e v i t c a l l u f 1 0 = ) 0 : 1 ( s f a m 0 5a m 0 3 4 z h m 3 3 1 e v i t c a l l u f 1 1 = ) 0 : 1 ( s f a m 0 6a m 0 4 4 z h m 3 3 1 e v i t c a l l u f 0 1 = ) 0 : 1 ( s f a m 0 6a m 0 0 5
4 ics9250-29 1. the ics clock generator is a slave/receiver, i 2 c (smb) component. it is only a "write" mode smb device, no readback on this part. read-back will lock up the piix-4 due to the byte count of 00 h . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit notes: controller (host) ics (slave/receiver) start bit address d2 (h) a ck dummy command code a ck dummy byte count a ck byte 0 a ck byte 1 ack byte 2 a ck byte 3 a ck byte 4 a ck byte 5 a ck stop bit how to write: note: this clock does not support read back. doing a read back will lock up the piix-4 system.
5 ics9250-29 e t a t s i r t0 s f1 s fu p cm a r d s6 6 v 3i c pz h m 8 4f e rc i p a o i 00x e t a t s i r te t a t s i r te t a t s i r te t a t s i r te t a t s i r te t a t s i r te t a t s i r t 01x 2 / k l c t2 / k l c t3 / k l c t6 / k l c t2 / k l c tk l c t6 / k l c t 100 z h m 6 . 6 6z h m 0 0 1z h m 6 . 6 6z h m 3 . 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 3 . 3 3 110 z h m 0 0 1z h m 0 0 1z h m 6 . 6 6z h m 3 . 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 3 . 3 3 101 z h m 3 3 1z h m 3 3 1z h m 6 . 6 6z h m 3 . 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 3 . 3 3 111 z h m 3 3 1z h m 0 0 1z h m 6 . 6 6z h m 3 . 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 3 . 3 3 truth table byte 0: control register (1 = enable, 0 = disable) byte 1: control register (1 = enable, 0 = disable) t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b- ) d i d e v r e s e r (0) e v i t c a n i / e v i t c a ( 6 t i b- ) d i d e v r e s e r (0) e v i t c a n i / e v i t c a ( 5 t i b- ) d i d e v r e s e r (0) e v i t c a n i / e v i t c a ( 4 t i b- ) d i d e v r e s e r (1) e v i t c a n i / e v i t c a ( 3 t i b- m u r t c e p s d a e r p s0) f f o = 0 / n o = 1 ( 2 t i b9 21 _ z h m 8 41) e v i t c a n i / e v i t c a ( 1 t i b8 20 _ z h m 8 41) e v i t c a n i / e v i t c a ( 0 t i b- ) d i d e v r e s e r (0) e v i t c a n i / e v i t c a ( t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b0 47 m a r d s1) e v i t c a n i / e v i t c a ( 6 t i b1 46 m a r d s1) e v i t c a n i / e v i t c a ( 5 t i b4 45 m a r d s1) e v i t c a n i / e v i t c a ( 4 t i b5 44 m a r d s1) e v i t c a n i / e v i t c a ( 3 t i b6 43 m a r d s1) e v i t c a n i / e v i t c a ( 2 t i b7 42 m a r d s1) e v i t c a n i / e v i t c a ( 1 t i b0 51 m a r d s1) e v i t c a n i / e v i t c a ( 0 t i b1 50 m a r d s1) e v i t c a n i / e v i t c a ( note: reserved id bits must be written with "0"
6 ics9250-29 byte 2: control register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. pwd = power on default 3. undefined bits can be written with either "1" or "0" t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b2 1) p g a ( 2 _ 6 6 v 31) e v i t c a n i / e v i t c a ( 6 t i b1 32 1 m a r d s1) e v i t c a n i / e v i t c a ( 5 t i b4 31 1 m a r d s1) e v i t c a n i / e v i t c a ( 4 t i b5 30 1 m a r d s1) e v i t c a n i / e v i t c a ( 3 t i b8 39 m a r d s1) e v i t c a n i / e v i t c a ( 2 t i b9 38 m a r d s1) e v i t c a n i / e v i t c a ( 1 t i b5 11 k l c i c p1) e v i t c a n i / e v i t c a ( 0 t i b- t i b d e n i f e d n u0 ) e v i t c a n i / e v i t c a ( byte 3: ics reserved functionality and frequency select register (default as noted in pwd) note 1: for system operation, the bsel lines of the cpu will program fs0, fs1 for the appropriate cpu speed, always with sdram = 100mhz. after bios verifies the sdram is pc133 speed, then bit 0 can be written from the default 0 to 1 to change the sdram output frequency from 100mhz to 133mhz. this will only change if the cpu is at the 133mhz fsb speed as shown in this table. the cpu, 3v66, pci and ioapic clocks will be glitch free during this transition, and only sdram will change. note 2: must be written with "0" note 3: undefined bits can be written with either "1" or "0" t i bn o i t p i r c s e dd w p 7 t i b) 2 e t o n ( t i b d e v r e s e r s c i 0 6 t i b) 2 e t o n ( t i b d e v r e s e r s c i 0 5 t i b) 2 e t o n ( t i b d e v r e s e r s c i 0 4 t i b) 2 e t o n ( t i b d e v r e s e r s c i 0 3 t i b) l a m r o n = 0 / % 5 = 1 ( e d o m k c o l c r e v o % 5 0 2 t i b) 3 e t o n ( t i b d e n i f e d n u 1 1 t i bn o i t p i r c s e d n i p e e s ) # e t a t s i r t = 0 / # n d r w p = 1 ( # n d r w p / # e t a t s i r t 1 0 t i b 0 t i b1 s f0 s f k l c u p c z h m m a r d s z h m 6 6 v 3 z h m k l c i c p z h m c i p a o i z h m 0 1 e t o n 000 6 6 . 6 60 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 001 0 . 0 0 10 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 010 2 3 . 3 3 12 3 . 3 3 16 6 . 6 63 3 . 3 33 3 . 3 3 011 2 3 . 3 3 10 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 100 6 6 . 6 60 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 10 1 0 . 0 0 10 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 110 2 3 . 3 3 12 3 . 3 3 16 6 . 6 63 3 . 3 33 3 . 3 3 111 2 3 . 3 3 12 3 . 3 3 16 6 . 6 63 3 . 3 33 3 . 3 3
7 ics9250-29 byte 4: reserved register (1 = enable, 0 = disable) byte 5: reserved register (1 = enable, 0 = disable) t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b- ) d e v r e s e r (0) e v i t c a n i / e v i t c a ( 6 t i b- ) d e v r e s e r (0) e v i t c a n i / e v i t c a ( 5 t i b- ) d e v r e s e r (0) e v i t c a n i / e v i t c a ( 4 t i b- ) d e v r e s e r (0) e v i t c a n i / e v i t c a ( 3 t i b- ) d e v r e s e r (0) e v i t c a n i / e v i t c a ( 2 t i b0 24 k l c i c p1) e v i t c a n i / e v i t c a ( 1 t i b9 13 k l c i c p1) e v i t c a n i / e v i t c a ( 0 t i b6 12 k l c i c p1) e v i t c a n i / e v i t c a ( t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b- ) d e v r e s e r (0) e v i t c a n i / e v i t c a ( 6 t i b- ) d e v r e s e r (0) e v i t c a n i / e v i t c a ( 5 t i b- ) d e v r e s e r (0) e v i t c a n i / e v i t c a ( 4 t i b- ) d e v r e s e r (0) e v i t c a n i / e v i t c a ( 3 t i b- ) d e v r e s e r (0) e v i t c a n i / e v i t c a ( 2 t i b- ) d e v r e s e r (0) e v i t c a n i / e v i t c a ( 1 t i b- ) d e v r e s e r (0) e v i t c a n i / e v i t c a ( 0 t i b- ) d e v r e s e r (0) e v i t c a n i / e v i t c a ( notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. pwd = power on default
8 ics9250-29 absolute maximum ratings core supply voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.6 v i/o supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ? 0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . . 0 c to +70 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . ? 65 c to +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operation al sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v + 5%, vddl=2.5 v+ 5%(unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd -5 5 a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 a operating i dd3.3op c l = 0 pf; select @ 66m 100 ma supply current power down i dd3.3pd c l = 0 pf; with input address to vdd or gnd 600 a supply current input frequency f i v dd = 3.3 v; 14.318 mhz pin inductance 1 l pin 7nh c in logic inputs 5 pf c out out put pin capacitance 6 pf c inx x1 & x2 pins 13.5 22.5 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms t pzh ,t pzh output enable delay (all outputs) 1 10 ms t plz ,t pzh output disable delay (all outputs) 1 10 ms 1 guarenteed by design, not 100% tested in production. delay 1 input capacitance 1 group timing relationship table 1 p u o r gz h m 6 6 u p c z h m 0 0 1 m a r d s z h m 0 0 1 u p c z h m 0 0 1 m a r d s z h m 3 3 1 u p c z h m 0 0 1 m a r d s z h m 3 3 1 u p c z h m 3 3 1 m a r d s t e s f f oe c n a r e l o tt e s f f oe c n a r e l o tt e s f f oe c n a r e l o tt e s f f oe c n a r e l o t m a r d s o t u p cs n 5 . 2 -s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5s n 5 7 . 3s p 0 0 5 6 6 v 3 o t u p cs n 5 . 7s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5 6 6 v 3 o t m a r d ss n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s n 5 7 . 3 -s p 0 0 5 i c p o t 6 6 v 3s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5 c i p a o i o t i c ps n 0 . 0s n 1s n 0 . 0s n 1s n 0 . 0s n 1s n 0 . 0s n 1 t o d & b s uh c n y s aa / nh c n y s aa / nh c n y s aa / nh c n y s aa / n
9 ics9250-29 electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; v ddl = 2.5 v +/-5%;c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output impedance r dsn1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.4 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.13 5 v -33 -33 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.46 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.47 2 ns duty cycle d t1 1 v t = 1.5 v 45 50.2 55 % skew t sk1 1 v t = 1.5 v 175 ps jitter t jcyc-cyc 1 v t = 1.5 v 500 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70c, v dd =3,3v +/-5%, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 45 ? output impedance r dsn2 b 1 v o = v dd *(0.5) 13.5 45 ? output high voltage v oh2 b i oh = -1 ma 2 v output low voltage v ol2 b i ol = 1 ma 0.4 v output high current i oh2 b v oh @min = 1.0v , v oh@ max = 2.375v -27 -27 ma output low current i ol2 b v ol @min = 1.2v , v ol@ max = 0.3v 27 30 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.10 1.6 ns fall time t f2b 1 v oh = 2.0 v, v ol = 0.4 v 0.4 1.26 1.6 ns duty cycle d t2b 1 v t = 1.25 v 45 53.6 55 % skew t sk2b 1 v t = 1.25 v 175 ps jitter t jcyc-cyc 1 v t = 1.25 v 250 ps 1 guarenteed by design, not 100% tested in production.
10 ics9250-29 electrical characteristics - ioapic t a = 0 - 70c;v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp4b 1 v o = v dd *(0.5) 9 30 ? output impedance r dsn4 b 1 v o = v dd *(0.5) 9 30 ? output high voltage v oh4 b i oh = -1 ma 2 v output low voltage v ol4 b i ol = 1 ma 0.4 v output high current i oh4 b v oh@ mi n = 1.0 v, v oh@ max = 2.375 v -27 -27 ma output low current i ol4 b v ol@ min = 1.2 v, v ol@ max= 0.3v 27 30 ma rise time t r4b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.09 1.6 ns fall time t f4b 1 v oh = 2.0 v, v ol = 0.4 v 0.4 1.22 1.6 ns duty cycle d t4b 1 v t = 1.25 v 45 50.2 55 % jitter t jcyc-cyc 1 v t = 1.25 v 500 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - sdram t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%, c l = 20 - 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp3 1 v o = v dd *(0.5) 10 24 ? output impedance r dsn3 1 v o = v dd *(0.5) 10 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 v output high current i oh3 v oh @min = 2.0 v, v oh@ max =3.135 v -54 -46 ma output low current i ol3 v ol@ min = 1.0 v, v ol@ max =0.4 v 49 53 ma rise time t r3 1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.19 1.6 ns fall time t f3 1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.43 1.6 ns duty cycle d t3 1 v t = 1.5 v 45 54.9 55 % skew t sk3 1 v t = 1.5 v 250 ps jitter t j cyc-cyc 1 v t = 1.5 v 250 ps 1 guarenteed by design, not 100% tested in production.
11 ics9250-29 electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output impedance r dsn1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.4 v output high current i oh1 v oh@ min = 1.0 v, v oh@ max = 3.135 v -33 -33 ma output low current i ol1 v ol@ min = 1.95 v, v ol@ max = 0.4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.43 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.63 2 ns duty cycle d t1 1 v t = 1.5 v 45 51.9 55 % skew t sk1 1 v t = 1.5 v 500 ps jitter t jcyc-cyc 1 v t = 1.5 v 500 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - ref, 48mhz_0 t a = 0 - 70c; v dd = 3.3 v +/-5%, vddl = 2.5 v +/-5%, c l = 10 -20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp5 1 v o = v dd *(0.5) 20 60 ? output impedance r dsn5 1 v o = v dd *(0.5) 20 60 ? output high voltage v oh5 i oh = 1 ma 2.4 v output low voltage v ol5 i ol = -1 ma 0.4 v output high current i oh5 v oh @min =1 v, v oh@max = 3.135 v -29 -23 ma output low current i ol5 v ol@min =1.95 v, v ol@min =0.4 v 29 27 ma rise time t r5 1 v ol = 0.4 v, v oh = 2.4 v 1 1.53 4 ns fall time t f5 1 v oh = 2.4 v, v ol = 0.4 v 1 1.76 4 ns duty cycle d t5 1 v t = 1.5 v 45 53.6 55 % t jcyc-cyc 1 v t = 1.5 v; fixed clocks 500 ps t jcyc-cyc 1 v t = 1.5 v; ref clocks 1000 ps 1 guarenteed by design, not 100% tested in production. jitter
12 ics9250-29 electrical characteristics - 48mhz_1 t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 10 - 15 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp3 1 v o = v dd *(0.5) 10 24 ? output impedance r dsn3 1 v o = v dd *(0.5) 10 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 v output high current i oh3 v oh @min = 2.0 v, v oh@ max =3.135 v -33 -33 ma output low current i ol3 v ol@ min = 1.0 v, v ol@ max =0.4 v 30 38 ma rise time t r3 1 v ol = 0.4 v, v oh = 2.4 v 0.5 0.81 2.0 ns fall time t f3 1 v oh = 2.4 v, v ol = 0.4 v 0.5 0.95 2.0 ns duty cycle d t3 1 v t = 1.5 v 45 53.1 55 % jitter t j cyc-cyc 1 v t = 1.5 v 500 ps 1 guarenteed by design, not 100% tested in production.
13 ics9250-29 group offset waveforms cycle repeats 0ns cpu 66mhz cpu 100mhz cpu 133mhz sdram 133mhz sdram 100mhz 3.3v 66mhz pci 33mhz ioapic 33mhz ref 14.318mhz usb 48mhz 10ns 20ns 30ns 40ns
14 ics9250-29 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics9250-29 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5- bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k tristate#/pd# pin description: the tristate#/pd# pin provides the capability of invoking tristate mode during board level testing. at power up the tristate#/pd# pin defaults to the tristate# input function to enable the trestate# and test modes. approximately 1.5ms to 3ms after power on, the tristate#/ pd# changes to the pd# input function and the tristate# functionality is disabled (if tristate# is not active).
15 ics9250-29 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ordering information ics9250 y f-29-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp - t min max min max a 2.413 2.794 .095 .110 a1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c 0.127 0.254 .005 .010 d e 10.033 10.668 .395 .420 e1 7.391 7.595 .291 .299 e 0.635 basic 0.025 basic h 0.381 0.635 .015 .025 l 0.508 1.016 .020 .040 n 0 8 0 8 variations min max min max 56 18.288 18.542 .720 .730 jedec mo-118 doc# 10-0034 6/1/00 rev b n d mm. d (inch) see variations symbol see variations see variations in millimeters common dimensions in inches common dimensions see variations

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