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integrated circuit systems, inc. ics9250-26 third party brands and names are the property of their respective owners. block diagram 9250-26 rev b 01/19/01 recommended application: 810/810e type chipset. provides three cpu speeds (66.6, 100, 133mhz) with sdram = 133.3mhz. output features: ? 3 cpu (2.5v) 66.6/133.3mhz (up to 150mhz achievable through i 2 c) 9 sdram (3.3v) @ 133.3mhz (up to 150mhz achievable through i 2 c) 8 pci (3.3 v) @33.3mhz 2 ioapic (2.5v) @ 33.3 mhz 2 hublink clocks (3.3 v) @ 66.6 mhz 2 usb (3.3v) @ 48 mhz ( non spread spectrum) 1 ref (3.3v) @ 14.318 mhz features: supports spread spectrum modulation , down spread 0 to -0.5% and 0.25% center spread. i 2 c support for power management efficient power management scheme through pd# uses external 14.138 mhz crystal alternate frequency selections available through i 2 c control. functionality pin configuration 56-pin 300mil ssop * this input has a 120k ? pull-down to gnd. *fs2//ref0 vdd0 x1 x2 gnd0 gnd1 3v66-0 3v66-1 vdd1 vdd2 pciclk0 pciclk1 pciclk2 gnd2 pciclk3 pciclk4 gnd2 pciclk5 pciclk6 pciclk7 vdd2 vdd3 gnd3 gnd4 48mhz_0 48mhz_1 vdd4 fs0 gndl1 ioapic0 ioapic1 vddl1 cpuclk0 vddl0 cpuclk1 cpuclk2 gndl0 gnd5 sdram0 sdram1 vdd5 sdram2 sdram3 gnd5 sdram4 sdram5 vdd5 sdram6 sdram7 gnd5 sdram_f vdd5 pd# sclk s data fs1 ics9250-26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 frequency generator & integrated buffers for celeron & p ii / iii ? 2 s f1 s f0 s fn o i t c n u f x0 0 e t a t s i r t x0 1t s e t 010 z h m 6 6 = u p c e v i t c a z h m 0 0 1 = m a r d s 011 z h m 0 0 1 = u p c e v i t c a z h m 0 0 1 = m a r d s 111 z h m 3 3 1 = u p c e v i t c a z h m 0 0 1 = m a r d s 110 ) n o i t i d n o c l a i c e p s ( z h m 3 3 1 = u p c e v i t c a z h m 3 3 1 = m a r d s ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9250-26 the ics9250-26 is a single chip clock solution for 810/810e type chipset. it provides all necessary clock signals for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces emi by 8db to 10 db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9250-26 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. general description pin configuration r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 1 2 s ft u o t u p t u o l l a , y c n e u q e r f u p c s e n i m r e t e d . n i p t c e l e s n o i t c n u f 0 5 h t i w ( y t i l a n o i t c n u f ? ) 0 f e rt u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3 31 xt u o k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 42 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 3 3 ( p a c , 3 2 , 4 2 , 5 3 , 1 4 , 7 4 5 , 6 , 4 1 , 7 1 ) 0 : 5 ( d n gr w py l p p u s v 3 . 3 r o f s n i p d n u o r g 7 , 8] 0 : 1 [ 6 6 v 3t u ob u h r o f s t u p t u o k c o l c z h m 6 6 d e x i f v 3 . 3 , 2 2 , 7 2 , 3 3 , 8 3 , 4 4 2 , 9 , 0 1 , 0 1 , 1 2 ) 0 : 5 ( d d vr w py l p p u s r e w o p v 3 . 3 , 6 1 , 8 1 , 9 1 , 0 2 1 1 , 2 1 , 3 1 , 5 1 ) 0 : 7 ( k l c i c pt u os k l c u p c s u o n o r h c n y s h t i w , s t u p t u o k c o l c i c p v 3 . 3 5 2 , 6 2) 0 : 1 ( z h m 8 4t u ob s u r o f s t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 8 2 , 9 2) 0 : 1 ( s ft u o t u p t u o l l a , y c n e u q e r f u p c s e n i m r e t e d . s n i p t c e l e s n o i t c n u f . 3 e g a p n o e l b a t y t i l a n o i t c n u f o t r e f e r e s a e l p . y t i l a n o i t c n u f 0 3a t a d sn ii r o f t u p n i a t a d 2 . t u p n i l a i r e s c 1 3k l c sn ii f o t u p n i k c o l c 2 t u p n i c 2 3# d pn i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i e h t . e t a t s r e w o p w o l a o t n i n w o d r e w o p e h t f o y c n e t a l e h t . d e p p o t s e r a l a t s y r c e h t d n a o c v . s m 3 n a h t r e t a e r g e b t o n l l i w , 2 4 , 0 4 , 9 3 , 7 3 , 6 3 6 4 , 5 4 , 3 4 ) 0 : 7 ( m a r d st u o d e n r u t e b n a c s t u p t u o m a r d s l l a . z h m 0 0 1 g n i n n u r t u p t u o v 3 . 3 i h g u o r h t f f o 2 c 4 3f _ m a r d st u oi y b d e t c e f f a t o n m a r d s z h m 0 0 1 g n i n n u r e e r f v 3 . 3 2 c 8 4 , 6 5) 0 : 1 ( l d n gr w pc i p a & u p c r o f y l p p u s r e w o p v 5 . 2 r o f d n u o r g 9 4 , 0 5 , 2 5) 0 : 2 ( k l c u p ct u o z h m 3 3 1 z h m 0 0 1 r o z h m 6 6 . t u p t u o k c o l c s u b t s o h v 5 . 2 s n i p s f n o g n i d n e p e d 3 5 , 1 5) 0 : 1 ( l d d vr w pc i p a o i & u p c r o f y l p p y u s r e w o p v 5 . 2 5 5 , 4 5) 0 : 1 ( c i p a o it u o. z h m 3 . 3 3 t a g n i n n u r s t u p t u o k c o l c v 5 . 2
3 ics9250-26 maximum allowed current e 0 1 8 n o i t i d n o c n o i t p m u s n o c y l p p u s v 5 . 2 x a m , s d a o l p a c e t e r c s i d x a m v 5 2 6 . 2 = 2 q d d v d n g r o 3 q d d v = s t u p n i c i t a t s l l a n o i t p m u s n o c y l p p u s v 5 . 2 x a m , s d a o l p a c e t e r c s i d x a m v 5 6 4 . 3 = 2 q d d v d n g r o 3 q d d v = s t u p n i c i t a t s l l a e d o m n w o d r e w o p 0 = # n w d r w p ( a m 0 1a m 0 1 z h m 6 6 e v i t c a l l u f 0 1 = 0 , 1 l e s a m 0 7a m 0 8 2 z h m 0 0 1 e v i t c a l l u f 1 1 = 0 , 1 l e s a m 0 0 1a m 0 8 2 clock enable configuration # d pk l c u p cm a r d sc i p a o iz h m 6 6k l c i c p , f e r z h m 8 4 c s os o c v 0w o lw o lw o lw o lw o lw o lf f of f o 1n on on on on on on on o power groups* vdd0, gnd0 = ref & crystal vdd1, gnd1 = 3v66 vdd2, gnd2 = pciclk vdd3, gnd3 = pll core vdd4, gnd4 = 48mhz vdd5, gnd5 = sdram_f, sdram vddl0, gndl0 = cpuclk vddl1, gndl1 = ioapic * to ensure the processor will power up to the desired frequency, the 3.3v supply to the ics9250-26 needs to reach a stable condition before the 2.5v supply does. in most systems, the power up ramp of the 2.5v is slower than the 3.3v ramp. for those instances, no special requirements are necessary.
4 ics9250-26 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending first byte (byte 0) through byte 5 ? ics clock will acknowledge each byte one at a time . ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends first byte (byte 0) through byte 5 ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) a ck byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) a ck dummy command code a ck dummy byte count a ck byte 0 a ck byte 1 ack byte 2 a ck byte 3 a ck byte 4 a ck byte 5 a ck stop bit how to write:
5 ics9250-26 t i bn o i t p i t c s e dd w p 7 t i b ) l a m r o n e t a r e p o o t k c o l c 0 e b o t s d e e n ( t i b d e v r e s e r s c i0 6 t i b ) l a m r o n e t a r e p o o t k c o l c 0 e b o t s d e e n ( t i b d e v r e s e r s c i0 5 t i b ) l a m r o n e t a r e p o o t k c o l c 0 e b o t s d e e n ( t i b d e v r e s e r s c i0 t i b ) 0 , 3 ( ) 0 , 3 ( t i b k l c u p c z h m m a r d s z h m 6 6 v 3 z h m k l c i c p z h m x x x x 1 e t o n 2 s f ) w h ( 0 s f ) w h ( 1 l e s ) 3 t i b ( 0 l e s ) 0 t i b ( 0000 7 6 . 6 60 0 . 0 0 10 6 . 6 60 3 . 3 3 0001 0 0 . 0 70 0 . 5 0 10 0 . 0 70 0 . 5 3 0010 7 6 . 2 70 0 . 9 0 17 6 . 2 73 3 . 6 3 0011 7 6 . 4 70 0 . 2 1 16 6 . 4 73 3 . 7 3 0100 0 0 . 0 0 10 0 . 0 0 10 6 . 6 60 3 . 3 3 0101 0 0 . 5 0 10 0 . 5 0 10 0 . 0 70 0 . 5 3 0110 0 0 . 9 0 10 0 . 9 0 17 6 . 2 73 3 . 6 3 0111 1 0 . 2 1 10 0 . 2 1 16 6 . 4 73 3 . 7 3 1000 4 3 . 3 3 14 3 . 3 3 16 6 . 8 83 3 . 4 4 100 1 0 0 . 0 4 10 0 . 5 0 10 0 . 0 70 0 . 5 3 10 10 0 0 . 0 2 10 0 . 0 90 0 . 0 60 0 . 0 3 10 11 0 0 . 4 2 10 0 . 4 2 16 6 . 2 83 3 . 1 4 1100 4 3 . 3 3 10 0 . 0 0 10 6 . 6 60 3 . 3 3 1101 0 0 . 0 5 10 0 . 0 5 10 0 . 5 70 5 . 7 3 1110 0 0 . 0 4 10 0 . 0 4 10 0 . 0 70 0 . 5 3 1111 9 9 . 2 3 19 9 . 2 3 10 6 . 6 60 3 . 3 3 4 t i b % 5 . - o t 0 m u r t c e p s d a e r p s d a e r p s n w o d = 0 % 5 2 . m u r t c e p s d a e r p s d a e r p s r e t n e c = 1 0 2 t i b) n o i t a r e p o k c o l c l a m r o n r o f 1 e b o t s d e e n ( d e s u t o n 1 1 t i b) n o i t a r e p o k c o l c l a m r o n r o f 1 e b o t s d e e n ( d e s u t o n 1 byte 5: ics reserved functionality and frequency select register (default as noted in pwd) note1: default at power-up will be for bit 3 and bit 0 to be 00, with external hardware selection of fs0, fs2 defining specific frequency.
6 ics9250-26 byte 0: control register (1 = enable, 0 = disable) byte 1: control register (1 = enable, 0 = disable) byte 2: control register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. pwd = power on default t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i bd i d e v r e s e r0) e v i t c a n i / e v i t c a ( 6 t i bd i d e v r e s e r0) e v i t c a n i / e v i t c a ( 5 t i bd i d e v r e s e r0) e v i t c a n i / e v i t c a ( 4 t i bd i d e v r e s e r1) e v i t c a n i / e v i t c a ( 3 t i b m u r t c e p s d a e r p s ) f f o = 0 / n o = 1 ( 1) e v i t c a n i / e v i t c a ( 2 t i b6 21 z h m 8 41) e v i t c a n i / e v i t c a ( 1 t i b5 20 z h m 8 41) e v i t c a n i / e v i t c a ( 0 t i b9 42 k l c u p c0) e v i t c a n i / e v i t c a ( t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b6 37 m a r d s1) e v i t c a n i / e v i t c a ( 6 t i b7 36 m a r d s1) e v i t c a n i / e v i t c a ( 5 t i b9 35 m a r d s1) e v i t c a n i / e v i t c a ( 4 t i b0 44 m a r d s1) e v i t c a n i / e v i t c a ( 3 t i b2 43 m a r d s1) e v i t c a n i / e v i t c a ( 2 t i b3 42 m a r d s1) e v i t c a n i / e v i t c a ( 1 t i b5 41 m a r d s1) e v i t c a n i / e v i t c a ( 0 t i b6 40 m a r d s1) e v i t c a n i / e v i t c a ( note: do not write in id bits, these bits are for ics internal use only. t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b0 27 k l c i c p1) e v i t c a n i / e v i t c a ( 6 t i b9 16 k l c i c p1) e v i t c a n i / e v i t c a ( 5 t i b8 15 k l c i c p1) e v i t c a n i / e v i t c a ( 4 t i b6 14 k l c i c p1) e v i t c a n i / e v i t c a ( 3 t i b5 13 k l c i c p1) e v i t c a n i / e v i t c a ( 2 t i b3 12 k l c i c p1) e v i t c a n i / e v i t c a ( 1 t i b2 11 k l c i c p1) e v i t c a n i / e v i t c a ( 0 t i b- d e v r e s e r1) e v i t c a n i / e v i t c a ( must write a '1' in bit 0 after read back.
7 ics9250-26 byte 3: reserved register (1 = enable, 0 = disable) byte 4: reserved register (1 = enable, 0 = disable) t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 6 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 5 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 4 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 3 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 2 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 1 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 0 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 6 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 5 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 4 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 3 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 2 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 1 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 0 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. pwd = power on default
8 ics9250-26 electrical characteristics - input/supply/common output paramete t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd -5 5 a i il1 v in = 0 v; inputs with no pull-up resistors -5 2 i il2 v in = 0 v; inputs with pull-up resistors -200 -100 c l = 0 pf; select @ 66 mhz 97 110 c l = 0 pf; select @ 100 mhz 91 105 c l = 0 pf; select @ 133 mhz 100 130 c l = max loads; select @ 66 mhz 275 310 c l = max loads; select @ 100 mhz 267 300 c l = max loads; select @ 133 mhz 278 350 c l = 0 pf; select @ 66 mhz 8 10 c l = 0 pf; select @ 100 mhz 11 15 c l = 0 pf; select @ 133 mhz 13 20 c l = max loads; select @ 66 mhz 22 70 c l = max loads; select @ 100 mhz 31 100 c l = max loads; select @ 133 mhz 37 130 i dd3.3pd c l = max loads 220 400 i dd.25pd input address vdd or gnd <1 10 input frequency f i v dd = 3.3 v 12 14.318 16 m hz pin inductance l pin 7nh c in logic inputs 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target frequency 5 ms settling time 1 t s from 1st crossing to 1% target frequency 5 ms clk stab ilizatio n 1 t stab from v dd = 3.3 v to 1% target frequency 5 ms t pzh ,t pzl output enable delay (all outputs) 1 10 ns t phz ,t plz output disable delay (all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. delay 1 ma ma input capacitance 1 i dd2.5op a powerdown current operating supply current input low current a ma ma i dd3.3op absolute maximum ratings core supply voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 v i/o supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
9 ics9250-26 electrical characteristics - cpu t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 16 45 ? output impedance r dsn2b 1 v o = v dd *(0.5) 13.5 21 45 ? output high voltage v oh2b i oh = -1 ma 2 v output low voltage v ol2b i ol = 1 ma 0.4 v v oh @ min = 1.0 v -27 -68 v oh @ max = 2.375 v -9 -27 v ol @ min = 1.2 v 27 54 v ol @ max = 0.3 v 11 30 rise time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 0.4 1.1 1.6 ns fall time 1 t f2b v oh = 2.0 v, v ol = 0.4 v 0.4 1.1 1.6 ns v t = 1.25 v, 66, 100 mhz 45 49 55 v t = 1.25 v, 133 mhz 40 48 55 skew window 1 t sk2b v t = 1.25 v 65 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc2b v t = 1.25 v 90 250 ps 1 guaranteed by design, not 100% tested in production. % d t2b duty cycle 1 ma ma output high current output low current i oh2b i ol2b electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp1b 1 v o = v dd *(0.5) 12 14 55 ? output impedance r dsn1b 1 v o = v dd *(0.5) 12 14.5 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 -108 v oh @ max = 3.135 v -9 -33 v ol @ min = 1.95 v 30 95 v ol @ max = 0.4 v 29 38 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.2 1.6 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.2 1.6 ns duty cycle 1 d t1 v t = 1.5 v 45 49 55 % skew window 1 t sk1 v t = 1.5 v 65 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 120 500 ps 1 guaranteed by design, not 100% tested in production. output high current output low current ma ma i oh1 i ol1
10 ics9250-26 electrical characteristics - ioapic t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp4b 1 v o = v dd *(0.5) 9 16 30 ? output impedance r dsn4 b 1 v o = v dd *(0.5) 9 20 30 ? output high voltage v oh4b i oh = -1 ma 2 v output low voltage v ol4b i ol = 1 ma 0.4 v v oh @ min = 1.0 v -27 -68 v oh @ max = 2.375 v -9 -27 v ol @ min = 1.2 v 27 54 v ol @ max = 0.3 v 11 30 ris e time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 0.4 1.1 1.6 ns fall time 1 t f4 b v oh = 2.0 v, v ol = 0.4 v 0.4 1.1 1.6 ns duty cycle 1 d t4b v t = 1.25 v 45 49 55 % skew window 1 t sk4b v t = 1.25 v 25 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc4b v t = 1.25 v 150 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh4b ma output low current i ol4b ma electrical characteristics - sdram t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp3b 1 v o = v dd *(0.5) 10 12 24 ? output impedance r dsn3b 1 v o = v dd *(0.5) 10 15 24 ? v oh @ min = 2.0 v -54 -92 v oh @ max = 3.135 v -16 -46 v ol @ min = 1.0 v 54 68 v ol @ max = 0.4 v 29 53 rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 0.4 1 1.6 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 0.4 1.5 1.6 ns duty cycle 1 d t3 v t = 1.5 v 45 52 55 % skew window 1 t sk3 v t = 1.5 v 85 250 ps v t = 1.5 v, 66, 100 mhz 120 250 v t = 1.5 v, 133 mhz 150 300 1 guaranteed by design, not 100% tested in production. jitter, cycle-to-cycle 1 t jcyc-cyc3 ps ma ma output high current output low current i oh3 i ol3
11 ics9250-26 electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp1b 1 v o = v dd *(0.5) 12 15 55 ? output impedance r dsn1b 1 v o = v dd *(0.5) 12 15 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 -106 v oh @ max = 3.135 v -14 -33 v ol @ min = 1.95 v 30 94 v ol @ max = 0.4 v 29 38 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.3 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.4 2 ns duty cycle 1 d t1 v t = 1.5 v 45 51 55 % skew window 1 t sk1 v t = 1.5 v 250 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 150 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh1 ma output low current i ol1 ma electrical characteristics - ref, 48mhz_0 (pin 25) t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp5b 1 v o = v dd *(0.5) 20 29 60 ? output impedance r dsn5 b 1 v o = v dd *(0.5) 20 27 60 ? output high voltage v oh15 i oh = -1 ma 2.4 v output low voltage v ol5 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -29 -54 v oh @ max = 3.135 v -11 -23 v ol @ min = 1.95 v 29 54 v ol @ max = 0.4 v 16 27 ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 0.4 1.1 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 0.4 1.6 4 ns duty cycle 1 d t5 v t = 1.5 v 45 53 55 % jitter, cycle-to-cycle 1 t jcyc-cyc5 v t = 1.5 v, fixed clocks 130 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc5 v t = 1.5 v, ref clocks 650 1000 ps 1 guaranteed by design, not 100% tested in production. output high current i oh5 ma output low current i ol5 ma
12 ics9250-26 electrical characteristics - 48mhz_1 (pin 26) t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp3b 1 v o = v dd *(0.5) 10 15 24 ? output impedance r dsn3b 1 v o = v dd *(0.5) 10 15 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.55 v v oh @ min = 2.0 v -54 -82 v oh @ max = 3.135 v -20 -46 v ol @ min = 1.0 v 54 95 v ol @ max = 0.4 v 28 53 rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 0.4 1.1 1.6 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 0.4 1.3 1.6 ns duty cycle 1 d t3 v t = 1.5 v 45 53 55 % jitter, cycle-to-cycle 1 t jcyc-cyc3b v t = 1.5 v 130 250 ps 1 guaranteed by design, not 100% tested in production. output high current i oh3 ma output low current i ol3 ma group skews (cpu = 66 mhz) t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% cpu & ioapic load (lumped) = 20 pf; pci, sdram, 3v66 load (lumped) = 30 pf refer to group offset waveform diagram for definition of transition edges. parameter symbol conditions min typ max units cpu to sdram skew 1 t sk1 cpu-sdram -3 -2.6 -2 ns skew window 1 t w1 cpu-sdram 0 150 500 ps cpu to 3v66 skew 1 t sk1 cpu-3v66 77.28ns skew window 1 t w1 cpu-3v66 0 130 500 ps sdram to 3v66 skew 1 t sk1 sdram-3v66 -500 100 500 ps skew window 1 t w1 sdram-3v66 0 155 500 ps 3v66 to pci skew 1 t sk1 3v66-pci 1.5 2.4 3.5 ns skew window 1 t w1 3v66-pci 0 275 500 ps ioapic to pci skew 1 t sk1 ioapic-pci -1 -0.4 1 ns skew window 1 t w1 ioapic-pci 00.251 ns 1 guaranteed by design, not 100% tested in production. cpu @ 1.25 v, sdram @ 1.5 v cpu @ 1.25 v, 3v66 @ 1.5 v sdram, 3v66 @ 1.5 v 3v66, pci @ 1.5 v ioapic @ 1.25 v, pci @ 1.5 v
13 ics9250-26 group skews (cpu = 100 mhz) t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% cpu & ioapic load (lumped) = 20 pf; pci, sdram, 3v66 load (lumped) = 30 pf refer to group offset waveform diagram for definition of transition edges. parameter symbol conditions min typ max units cpu to sdram skew 1 t sk2 cpu-sdram 4.5 4.9 5.5 ns skew window 1 t w2 cpu-sdram 0 140 500 ps cpu to 3v66 skew 1 t sk2 cpu-3v66 4.5 4.8 5.5 ns skew window 1 t w2 cpu-3v66 0 150 500 ps sdram to 3v66 skew 1 t sk2 sdram-3v66 -500 100 500 ps skew window 1 t w2 sdram-3v66 0 155 500 ps 3v66 to pci skew 1 t sk2 3v66-pci 1.5 2.4 3.5 ns skew window 1 t w2 3v66-pci 0 275 500 ps ioapic to pci skew 1 t sk2 ioapic-pci -1 -0.4 1 ns skew window 1 t w2 ioapic-pci 00.251 ns 1 guaranteed by design, not 100% tested in production. 1 guaranteed by design, not 100% tested in production. cpu @ 1.25 v, sdram @ 1.5 v cpu @ 1.25 v, 3v66 @ 1.5 v sdram, 3v66 @ 1.5 v 3v66, pci @ 1.5 v ioapic @ 1.25 v, pci @ 1.5 v group skews (cpu = 133 mhz) t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% cpu & ioapic load (lumped) = 20 pf; pci, sdram, 3v66 load (lumped) = 30 pf refer to group offset waveform diagram for definition of transition edges. parameter symbol conditions min typ max units cpu to sdram skew 1 t sk3 cpu-sdram -500 70 500 ps skew window 1 t w3 cpu-sdram 0 125 500 ps cpu to 3v66 skew 1 t sk3 cpu-3v66 -500 -145 500 ps skew window 1 t w3 cpu-3v66 0 220 500 ps sdram to 3v66 skew 1 t sk3 sdram-3v66 -500 100 500 ps skew window 1 t w3 sdram-3v66 0 155 500 ps 3v66 to pci skew 1 t sk3 3v66-pci 1.5 2.4 3.5 ns skew window 1 t w3 3v66-pci 0 275 500 ps ioapic to pci skew 1 t sk3 ioapic-pci -1 -0.4 1 ns skew window 1 t w3 ioapic-pci 00.251 ns 1 guaranteed by design, not 100% tested in production. 3v66, pci @ 1.5 v ioapic @ 1.25 v, pci @ 1.5 v sdram, 3v66 @ 1.5 v cpu @ 1.25 v, sdram @ 1.5 v cpu @ 1.25 v, 3v66 @ 1.5 v
14 ics9250-26 group offset waveforms power down waveform note 1. after pd# is sampled active (low) for 2 consective rising edges of cpuclks, all the output clocks are driven low on their next high to low tranistiion. 2 . power-up latency <3ms. 3. waveform shown for 100mhz
15 ics9250-26 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ordering information ics9250 y f-26-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp - t min max min max a 2.413 2.794 .095 .110 a1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c 0.127 0.254 .005 .010 d e 10.033 10.668 .395 .420 e1 7.391 7.595 .291 .299 e 0.635 basic 0.025 basic h 0.381 0.635 .015 .025 l 0.508 1.016 .020 .040 n 0 8 0 8 variations min max min max 56 18.288 18.542 .720 .730 jedec mo-118 doc# 10-0034 6/1/00 rev b n d mm. d (inch) see variations symbol see variations see variations in millimeters common dimensions in inches common dimensions see variations

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