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  integrated circuit systems, inc. ics9250-25 third party brands and names are the property of their respective owners. block diagram 9250-25 rev a 10/03/00 pin configuration recommended application:  
    
? 2 - cpus @ 2.5v, up to 153.33mhz.  13 - sdram @ 3.3v, up to 153.33mhz.  3 - 3v66 @ 3.3v, 2x pci mhz.  8 - pci @3.3v.  1 - 48mhz, @3.3v fixed.  1 - 24mhz @ 3.3v  1 - ref @3.3v, 14.318mhz. features:  up to 153.33mhz frequency support  support power management through pd#.  spread spectrum for emi control ( 0.25%) center spread.  uses external 14.318mhz crystal  fs pins for frequency select key specifications:  cpu output jitter: <250ps  ioapic output jitter: <500ps  48mhz, 3v66, pci output jitter: <500ps  ref output jitter. <1000ps  cpu output skew: <175ps  pci output skew: <500ps  3v66 output skew <175ps  for group skew timing, please refer to the group timing relationship table. frequency generator & integrated buffers for celeron & p ii / iii ? 56-pin 300 mil ssop         ! "! #$$    !  s data sclk pll2 pll1 spread spectrum 48mhz 24mhz cpuclk [1:0] 2 12 8 3 sdram [11:0] ioapic pciclk [7:0] sdram_f 3v66 [2:0] x1 x2 xtal osc cpu divder sdram divder ioapic divder pci divder 3v66 divder fs[4:0] pd# control logic config. reg. / 2 ref0 vddref x1 x2 gndref gnd3v66 3v66-1 3v66-2 vdd3v66 vddpci *fs0/pciclk0 *fs1/pciclk1 pciclk2 gndpci pciclk3 pciclk4 pciclk5 vddpci pciclk6 pciclk7 gndpci pd# sclk s data vddsdr sdram11 sdram10 gndsdr 3v66-0 1 1 ref0/fs4* vddlapic ioapic vddlcpu cpuclk0 cpuclk1 gndlcpu gndsdr sdram0 sdram1 sdram2 vddsdr sdram3 sdram4 sdram5 gndsdr sdram6 sdram7 sdram_f vddsdr gnd48 24mhz/fs2* 48mhz/fs3* vdd48 vddsdr sdram8 sdram9 gndsdr 1 1 ics9250-25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 preliminary product preview product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice.
 ics9250-25 preliminary product preview third party brands and names are the property of their respective owners. general description pin configuration n i p r e b m u n e m a n n i pe p y tn o i t p i r c s e d , 5 2 , 8 1 , 0 1 , 9 , 1 5 4 , 7 3 , 3 3 , 2 3 d d vr w py l p p u s r e w o p v 3 . 3 21 xn i k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 32 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 3 3 ( p a c , 1 2 , 4 1 , 5 , 4 , 6 3 , 9 2 , 8 2 9 4 , 1 4 d n gr w py l p p u s v 3 . 3 r o f s n i p d n u o r g 6 , 7 , 8] 0 : 2 [ 6 6 v 3t u ob u h r o f s t u p t u o k c o l c z h m 6 6 d e x i f v 3 . 3 1 1 0 k l c i c p 1 t u os k l c u p c s u o n o r h c n y s h t i w , s t u p t u o k c o l c i c p v 3 . 3 0 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 2 1 1 k l c i c p 1 n is k l c u p c s u o n o r h c n y s h t i w , s t u p t u o k c o l c i c p v 3 . 3 1 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l , 6 1 , 7 1 , 9 1 , 0 2 3 1 , 5 1 ] 2 : 7 [ k l c i c pt u os k l c u p c s u o n o r h c n y s h t i w , s t u p t u o k c o l c i c p v 3 . 3 2 2# d pn i o t n i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a d n a o c v e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i e h t . e t a t s r e w o p w o l a e b t o n l l i w n w o d r e w o p e h t f o y c n e t a l e h t . d e p p o t s e r a l a t s y r c e h t . s m 3 n a h t r e t a e r g 3 2k l c sn ii f o t u p n i k c o l c 2 t u p n i c 4 2a t a d sn ii r o f t u p n i a t a d 2 . t u p n i l a i r e s c 4 3 z h m 8 4t u ob s u r o f t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 3 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 5 3 2 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l z h m 4 2t u ot u p t u o z h m 4 2 d e x i f v 3 . 3 8 3f _ m a r d st u oi y b d e t c e f f a t o n m a r d s z h m 0 0 1 g n i n n u r e e r f v 3 . 3 2 c , 3 4 , 4 4 , 7 4 , 8 4 , 1 3 , 9 3 , 0 4 , 2 4 6 2 , 7 2 , 0 3 , 0 3 ] 0 : 1 1 [ m a r d st u o f f o d e n r u t e b n a c s t u p t u o m a r d s l l a . z h m 0 0 1 g n i n n u r t u p t u o v 3 . 3 i h g u o r h t 2 c 0 5l d n gr w pc i p a & u p c r o f y l p p u s r e w o p v 5 . 2 r o f d n u o r g 2 5 , 1 5] 0 : 1 [ k l c u p ct u o. s n i p s f m o r f d e v i r e d y c n e u q e r f t u p t u o . t u p t u o k c o l c s u b t s o h v 5 . 2 5 5 , 3 5l d d vr w pc i p a o i , u p c r o f y l p p y u s r e w o p v 5 . 2 4 5c i p a o it u o. z h m 7 6 . 6 1 t a g n i n n u r s t u p t u o k c o l c v 5 . 2 6 5 4 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 0 f e r 1 t u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3     % !  &  %  !  
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     !          &     &!       &          (               &  &          2 !  ( !  2 !         &  2       &&   !  (   electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v + 5%, vddl=2.5 v+ 5%(unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd -5 5 a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 a operating i dd3 .3 op c l = 0 pf; select @ 66m 100 ma supply current power down i dd3 .3 pd c l = 0 pf; with input address to vdd or gnd 600 a supply current input frequency f i v dd = 3.3 v; 14.318 mhz pin inductance l p in 7nh input capacitance 1 c in logic inputs 5 pf c out out put pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms delay t pzh ,t pzh output enable delay (all outputs) 1 10 ns t plz ,t pzh output disable delay (all outputs) 1 10 ns 1 guarenteed by design, not 100% tested in production. ) 
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 ics9250-25 preliminary product preview third party brands and names are the property of their respective owners. electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output impedance r dsn1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.135 v -33 -33 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.6 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.6 ns duty cycle d t1 1 v t = 1.5 v 45 55 % skew t sk1 1 v t = 1.5 v 175 ps jitter t jcyc-cyc v t = 1.5 v 500 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70c, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 45 ? output impedance r dsn2 b 1 v o = v dd *(0.5) 13.5 45 ? output high voltage v oh2 b i oh = -1 ma 2 v output low voltage v ol2 b i ol = 1 ma 0.4 v output high current i oh2 b v oh @min = 1.0v , v oh@ max = 2.375v -27 -27 ma output low current i ol2 b v ol @min = 1.2v , v ol@ max = 0.3v 27 30 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time t f2b 1 v oh = 0.4 v, v ol = 2.0 v 0.4 1.6 ns duty cycle d t2b 1 v t = 1.25 v 455055ns skew t sk2b 1 v t = 1.25 v 175 ps t jcyc-cyc 1 v t = 1.25 v 250 ps jitter 1 guarenteed by design, not 100% tested in production.
 ics9250-25 preliminary product preview third party brands and names are the property of their respective owners. electrical characteristics - ioapic t a = 0 - 70c;v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp4b 1 v o = v dd *(0.5) 9 30 ? output impedance r dsn4 b 1 v o = v dd *(0.5) 9 30 ? output high voltage v oh4 \ b i oh = -5.5 ma 2 v output low voltage v ol4 b i ol = 9.0 ma 0.4 v output high current i oh4 b v oh@ mi n = 1.4 v, v oh@ max = 2.5 v -36 -21 ma output low current i ol4 b v ol@ min = 1.0 v, v ol@ max= 0.2 36 31 ma rise time t r4b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time t f4b 1 v oh = 2.0 v, v ol = 0.4 v 0.4 1.6 ns duty cycle d t4b 1 v t = 1.25 v 45 55 % jitter t jcyc-cyc v t = 1.25 v 500 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - sdram t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 - 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp3 1 v o = v dd *(0.5) 10 24 ? output impedance r dsn3 1 v o = v dd *(0.5) 10 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 v output high current i oh3 v oh @min = 2.0 v, v oh@ max =3.135 v -54 -46 ma output low current i ol3 v ol@ min = 1.0 v, v ol@ max =0.4 v 54 53 ma rise time t r3 1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.6 ns fall time t f3 1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.6 ns duty cycle d t3 1 v t = 1.5 v 45 55 % skew t sk3 1 v t = 1.5 v 250 ps jitter t j cyc-cyc v t = 1.5 v 250 ps 1 guarenteed by design, not 100% tested in production.
 ics9250-25 preliminary product preview third party brands and names are the property of their respective owners. electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output impedance r dsn1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.135 v -33 -33 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns duty cycle d t1 1 v t = 1.5 v 45 55 % skew t sk1 1 v t = 1.5 v 500 ps jitter t jcyc-cyc v t = 1.5 v 500 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - 48m, ref t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 -20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp5 1 v o = v dd *(0.5) 20 60 ? output impedance r dsn5 1 v o = v dd *(0.5) 20 60 ? output high voltage v oh5 i oh = 1 ma 2.4 v output low voltage v ol5 i ol = -1 ma 0.4 v output high current i oh5 v oh @min =1 v, v oh@max = 3.135 v -29 -23 ma output low current i ol5 v ol@min =1.95 v, v ol@min =0.4 v 29 27 ma rise time t r5 1 v ol = 0.4 v, v oh = 2.4 v 1.8 4 ns fall time t f5 1 v oh = 2.4 v, v ol = 0.4 v 1.7 4 ns duty cycle d t5 1 v t = 1.5 v 45 55 % jitter t jcyc-cyc 1 v t = 1.5 v; fixed clocks 500 ps t jcyc-cyc 1 v t = 1.5 v; ref clocks 1000 ps 1 guarenteed by design, not 100% tested in production.

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     "   controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ack byte 2 ac k byte 3 ac k byte 4 ac k byte 5 ac k stop bit how to write:
ics9250-25 preliminary product preview third party brands and names are the property of their respective owners. fig. 1 shared pin operation - input/output pins $  %& "   
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 ics9250-25 preliminary product preview third party brands and names are the property of their respective owners. power down waveform  #5 <& 3$c    ?/ @&     &)3d)/.   ! !  % /   2 e /      3 "!  f7  (5 1&   & *eg
 ics9250-25 preliminary product preview third party brands and names are the property of their respective owners. group offset waveforms cycle repeats 0ns cpu 66mhz cpu 100mhz cpu 133mhz sdram 133mhz sdram 100mhz 3.5v 66mhz pci 33mhz apic 33mhz ref 14.318mhz usb 48mhz 10ns 20ns 30ns 40ns
 ics9250-25 preliminary product preview third party brands and names are the property of their respective owners. product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice. ordering information ics9250 y f-25-t               
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   2  h ics xxxx y f - ppp - t min max min max a 2.413 2.794 .095 .110 a1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c 0.127 0.254 .005 .010 d e 10.033 10.668 .395 .420 e1 7.391 7.595 .291 .299 e 0.635 basic 0.025 basic h 0.381 0.635 .015 .025 l 0.508 1.016 .020 .040 n 0 8 0 8 variations min max min max 56 18.288 18.542 .720 .730 jedec mo-118 doc# 10-0034 6/1/00 rev b n d mm. d (inch) see variations symbol see variations see variations in millimeters common dimensions in inches common dimensions see variations


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