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integrated circuit systems, inc. ics9250-23 third party brands and names are the property of their respective owners. block diagram 9250-23 rev a 4/3/01 pin configuration recommended application: 810/810e type chipset output features: ? 2 - cpus @ 2.5v, up to 166mhz. 13 - sdram @ 3.3v, up to 166mhz. 2 - 3v66 @ 3.3v, 2x pci mhz. 8 - pci @3.3v. 1 - 48mhz, @3.3v fixed. 1 - 24mhz @ 3.3v 2 - ref @3.3v, 14.318mhz. features: up to 166mhz frequency support support power management through pd#. spread spectrum for emi control ( 0.25%) center spread. uses external 14.318mhz crystal fs pins for frequency select key specifications: cpu output jitter: <250ps ioapic output jitter: <500ps 48mhz, 3v66, pci output jitter: <500ps ref output jitter. <1000ps cpu output skew: <175ps pci output skew: <500ps 3v66 output skew <175ps for group skew timing, please refer to the group timing relationship table. frequency generator & integrated buffers for celeron & p ii / iii ? 56-pin 300 mil ssop 1. these pins will have 2x drive strength. * 120k ohm pull-up to vdd on indicated inputs. power groups gndref, vddref = ref, crystal gnd3v66, vdd3v66 = 3v66 gndpci, vddpci = pciclks gndcor, vddcor = pllcore gnd48, vdd48 = 48 gndsdr, vddsdr = sdram gndlcpu, vddlcpu = cpuclk gndlpci, vddlapic = ioapic ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9250-23 third party brands and names are the property of their respective owners. general description pin configuration n i p r e b m u n e m a n n i pe p y tn o i t p i r c s e d 11 f e rt u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3 , 5 2 , 8 1 , 0 1 , 9 , 2 5 4 , 7 3 , 3 3 , 2 3 d d vr w p. y l p p u s r e w o p v 3 . 3 31 xn i k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c . 2 x m o r f r o t s i s e r 42 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 3 3 ( p a c , 1 2 , 4 1 , 6 , 5 , 6 3 , 9 2 , 8 2 9 4 , 1 4 d n gr w p. y l p p u s v 3 . 3 r o f s n i p d n u o r g 7 , 8] 0 : 1 [ 6 6 v 3t u o. b u h r o f s t u p t u o k c o l c z h m 6 6 d e x i f v 3 . 3 1 1 0 k l c i c p 1 t u o. s k l c u p c s u o n o r h c n y s h t i w , s t u p t u o k c o l c i c p v 3 . 3 0 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 2 1 1 k l c i c p 1 t u o. s k l c u p c s u o n o r h c n y s h t i w , s t u p t u o k c o l c i c p v 3 . 3 1 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l , 6 1 , 7 1 , 9 1 , 0 2 3 1 , 5 1 ] 2 : 7 [ k l c i c pt u o. s k l c u p c s u o n o r h c n y s h t i w , s t u p t u o k c o l c i c p v 3 . 3 2 2# d pn i o t n i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a d n a o c v e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i e h t . e t a t s r e w o p w o l a e b t o n l l i w n w o d r e w o p e h t f o y c n e t a l e h t . d e p p o t s e r a l a t s y r c e h t . s m 3 n a h t r e t a e r g 3 2k l c sn ii f o t u p n i k c o l c 2 . t u p n i c 4 2a t a d so / ii r o f n i p a t a d 2 . t n a r e l o t v 5 y r t i u c r i c c 4 3 z h m 8 4t u o. b s u r o f t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 3 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 5 3 2 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l z h m 4 2t u o. t u p t u o z h m 4 2 d e x i f v 3 . 3 8 3f _ m a r d st u oi y b d e t c e f f a t o n m a r d s z h m 0 0 1 g n i n n u r e e r f v 3 . 3 2 . c , 1 3 , 0 3 , 7 2 , 6 2 , 3 4 , 2 4 , 0 4 , 9 3 8 4 , 7 4 , 6 4 , 4 4 ] 0 : 1 1 [ m a r d st u o f f o d e n r u t e b n a c s t u p t u o m a r d s l l a . z h m 0 0 1 g n i n n u r t u p t u o v 3 . 3 i h g u o r h t 2 . c 0 5l d n gr w p. c i p a & u p c r o f y l p p u s r e w o p v 5 . 2 r o f d n u o r g 2 5 , 1 5] 0 : 1 [ k l c u p ct u o. s n i p s f m o r f d e v i r e d y c n e u q e r f t u p t u o . t u p t u o k c o l c s u b t s o h v 5 . 2 5 5 , 3 5l d d vr w p. c i p a o i , u p c r o f y l p p y u s r e w o p v 5 . 2 4 5c i p a o it u o. z h m 7 6 . 6 1 t a g n i n n u r s t u p t u o k c o l c v 5 . 2 6 5 4 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 0 f e r 1 t u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3 the ics9250-23 is a single chip clock solution for desktop designs using the 810/810e style chipset. it provides all necessary clock signals for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9250-23 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. serial programming i 2 c interface allows changing functions, stop clock programming and frequency selection.
3 ics9250-23 third party brands and names are the property of their respective owners. frequency selection clock enable configuration 4 s f3 s f2 s f1 s f0 s f u p c z h m m a r d s z h m z h m 6 6 v 3 i c p z h m z h m c i p a o i 00000 0 0 . 9 60 5 . 3 0 10 0 . 9 60 5 . 4 35 2 . 7 1 0000 1 0 0 . 0 70 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 1 000 10 0 0 . 1 70 5 . 6 0 10 0 . 1 70 5 . 5 35 7 . 7 1 000 11 0 9 . 6 65 3 . 0 0 10 9 . 6 65 4 . 3 33 7 . 6 1 00100 0 0 . 2 70 0 . 8 0 10 0 . 2 70 0 . 6 30 0 . 8 1 0010 1 0 0 . 5 70 5 . 2 1 10 0 . 5 70 5 . 7 35 7 . 8 1 00110 0 6 . 6 70 9 . 4 1 10 6 . 6 70 4 . 8 30 2 . 9 1 00111 0 0 . 5 80 5 . 7 2 10 0 . 5 80 5 . 2 45 2 . 1 2 01000 0 0 . 8 60 0 . 2 0 10 0 . 8 60 0 . 4 30 0 . 7 1 01001 0 0 . 4 70 0 . 1 1 10 0 . 4 70 0 . 7 30 5 . 8 1 01010 0 0 . 0 4 10 0 . 0 4 10 0 . 0 70 0 . 5 30 5 . 7 1 01011 3 3 . 3 3 13 3 . 3 3 17 6 . 6 63 3 . 3 37 6 . 6 1 01100 0 0 . 0 5 10 0 . 0 5 10 0 . 5 70 5 . 7 35 7 . 8 1 01101 0 0 . 5 5 10 0 . 5 5 10 5 . 7 75 7 . 8 38 3 . 9 1 01110 0 0 . 6 6 10 0 . 6 6 10 0 . 3 80 5 . 1 45 7 . 2 2 01111 0 0 . 6 6 10 0 . 6 6 10 0 . 1 1 10 8 . 5 50 9 . 7 2 10000 7 7 . 1 1 17 7 . 1 1 12 5 . 4 76 2 . 7 33 6 . 8 1 100 0 1 8 7 . 4 0 18 7 . 4 0 16 8 . 9 63 9 . 4 36 4 . 7 1 100 10 1 5 . 9 0 11 5 . 9 0 11 0 . 3 70 5 . 6 35 2 . 8 1 100 1 1 0 9 . 0 0 10 9 . 0 0 17 2 . 7 63 6 . 3 32 8 . 6 1 10 10 0 0 0 . 7 1 10 0 . 7 1 10 5 . 8 75 2 . 9 33 6 . 9 1 10 10 1 5 7 . 3 2 15 7 . 3 2 10 5 . 2 85 2 . 1 42 6 . 0 2 10 1 10 3 3 . 3 3 13 3 . 3 3 19 8 . 8 84 4 . 4 42 2 . 2 2 10111 0 5 . 2 4 10 5 . 2 4 10 0 . 5 90 5 . 7 45 7 . 3 2 11000 0 0 . 6 3 15 2 . 2 0 10 5 . 8 65 2 . 4 33 1 . 7 1 1100 1 0 0 . 0 4 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 1 110 10 0 0 . 3 4 10 5 . 7 0 10 0 . 2 70 0 . 6 30 0 . 8 1 110 11 0 9 . 3 3 18 6 . 0 0 15 4 . 7 63 7 . 3 36 8 . 6 1 11100 7 6 . 6 4 10 0 . 0 1 13 3 . 3 77 6 . 6 33 3 . 8 1 1110 1 3 3 . 9 4 10 0 . 2 1 17 6 . 4 73 3 . 7 37 6 . 8 1 11110 0 3 . 3 5 19 2 . 5 1 14 2 . 7 72 6 . 8 30 3 . 9 1 11111 7 6 . 6 6 12 3 . 5 2 14 3 . 3 87 6 . 1 43 8 . 0 2 # d pk l c u p cm a r d sc i p a o iz h m 6 6k l c i c p , f e r z h m 8 4 c s os o c v 0w o lw o lw o lw o lw o lw o lf f of f o 1n on on on on on on on o
4 ics9250-23 third party brands and names are the property of their respective owners. power down waveform note 1. after pd# is sampled active (low) for 2 consective rising edges of cpuclks, all the output clocks are driven low on their next high to low tranistiion. 2 . power-up latency <3ms. 3. waveform shown for 100mhz
5 ics9250-23 third party brands and names are the property of their respective owners. fig. 1 via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used both to provide the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figure 1 shows a means of implementing this function when a switch or 2 pin header is used. when no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, then only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
6 ics9250-23 third party brands and names are the property of their respective owners. 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 5 controller (host) will need to acknowledge each byte controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) a ck byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) a ck dummy command code a ck dummy byte count a ck byte 0 a ck byte 1 ack byte 2 a ck byte 3 a ck byte 4 a ck byte 5 a ck stop bit how to write:
7 ics9250-23 third party brands and names are the property of their respective owners. byte 0: functionality and frequency select register (default=0) (1 = enable, 0 = disable) notes: 1. default at power-up will be for latched logic inputs to define frequency, as diplayed by bit 3. t i b n o i t p i r c s e d d w p t i b ) 4 : 7 , 2 ( ) 4 : 7 , 2 ( t i b k l c u p c z h m m a r d s z h m 6 6 v 3 z h m k l c i c p c i p a o i z h m 0 0 1 0 0 1 e t o n 00000 0 0 . 9 60 5 . 3 0 10 0 . 9 60 5 . 4 35 2 . 7 1 00001 0 0 . 0 70 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 1 00010 0 0 . 1 70 5 . 6 0 10 0 . 1 70 5 . 5 35 7 . 7 1 00011 0 9 . 6 65 3 . 0 0 10 9 . 6 65 4 . 3 33 7 . 6 1 00100 0 0 . 2 70 0 . 8 0 10 0 . 2 70 0 . 6 30 0 . 8 1 00101 0 0 . 5 70 5 . 2 1 10 0 . 5 70 5 . 7 35 7 . 8 1 00110 0 6 . 6 70 9 . 4 1 10 6 . 6 70 4 . 8 30 2 . 9 1 00111 0 0 . 5 80 5 . 7 2 10 0 . 5 80 5 . 2 45 2 . 1 2 01000 0 0 . 8 60 0 . 2 0 10 0 . 8 60 0 . 4 30 0 . 7 1 01001 0 0 . 4 70 0 . 1 1 10 0 . 4 70 0 . 7 30 5 . 8 1 01010 0 0 . 0 4 10 0 . 0 4 10 0 . 0 70 0 . 5 30 5 . 7 1 01011 3 3 . 3 3 13 3 . 3 3 17 6 . 6 63 3 . 3 37 6 . 6 1 01100 0 0 . 0 5 10 0 . 0 5 10 0 . 5 70 5 . 7 35 7 . 8 1 01101 0 0 . 5 5 10 0 . 5 5 10 5 . 7 75 7 . 8 38 3 . 9 1 01110 0 0 . 6 6 10 0 . 6 6 10 0 . 3 80 5 . 1 45 7 . 2 2 01111 0 0 . 6 6 10 0 . 6 6 10 0 . 1 1 10 8 . 5 50 9 . 7 2 10000 7 7 . 1 1 17 7 . 1 1 12 5 . 4 76 2 . 7 33 6 . 8 1 1000 1 8 7 . 4 0 18 7 . 4 0 16 8 . 9 63 9 . 4 36 4 . 7 1 100 10 1 5 . 9 0 11 5 . 9 0 11 0 . 3 70 5 . 6 35 2 . 8 1 100 11 0 9 . 0 0 10 9 . 0 0 17 2 . 7 63 6 . 3 32 8 . 6 1 10 100 0 0 . 7 1 10 0 . 7 1 10 5 . 8 75 2 . 9 33 6 . 9 1 10 10 1 5 7 . 3 2 15 7 . 3 2 10 5 . 2 85 2 . 1 42 6 . 0 2 10 110 3 3 . 3 3 13 3 . 3 3 19 8 . 8 84 4 . 4 42 2 . 2 2 10 111 0 5 . 2 4 10 5 . 2 4 10 0 . 5 90 5 . 7 45 7 . 3 2 11000 0 0 . 6 3 15 2 . 2 0 10 5 . 8 65 2 . 4 33 1 . 7 1 11001 0 0 . 0 4 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 1 11010 0 0 . 3 4 10 5 . 7 0 10 0 . 2 70 0 . 6 30 0 . 8 1 11011 0 9 . 3 3 18 6 . 0 0 15 4 . 7 63 7 . 3 36 8 . 6 1 11100 7 6 . 6 4 10 0 . 0 1 13 3 . 3 77 6 . 6 33 3 . 8 1 11101 3 3 . 9 4 10 0 . 2 1 17 6 . 4 73 3 . 7 37 6 . 8 1 11110 0 3 . 3 5 19 2 . 5 1 14 2 . 7 72 6 . 8 30 3 . 9 1 11111 7 6 . 6 6 12 3 . 5 2 14 3 . 3 87 6 . 1 43 8 . 0 2 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 6 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 d a e r p s r e t n e c % 5 2 . 0 e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0
8 ics9250-23 third party brands and names are the property of their respective owners. byte 1: control register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. pwd = power on default t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 # 3 s f 6 t i b-0 # 0 s f 5 t i b-0 # 2 s f 4 t i b5 31 z h m 4 2 3 t i b-1 ) d e v r e s e r ( 2 t i b4 31 z h m 8 4 1 t i b-1 ) d e v r e s e r ( 0 t i b8 31 f _ m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b0 21 7 k l c i c p 6 t i b9 11 6 k l c i c p 5 t i b7 11 5 k l c i c p 4 t i b6 11 4 k l c i c p 3 t i b5 11 3 k l c i c p 2 t i b3 1 1 2 k l c i c p 1 t i b2 11 1 k l c i c p 0 t i b1 11 0 k l c i c p byte 3: control register (1 = enable, 0 = disable) byte 2: control register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b9 31 7 m a r d s 6 t i b0 41 6 m a r d s 5 t i b2 41 5 m a r d s 4 t i b3 41 4 m a r d s 3 t i b4 41 3 m a r d s 2 t i b6 4 1 2 m a r d s 1 t i b7 41 1 m a r d s 0 t i b8 41 0 m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b71 0 _ 6 6 v 3 5 t i b81 1 _ 6 6 v 3 4 t i b-0 # 4 s f 3 t i b4 51 c i p a o i 2 t i b-0 # 1 s f 1 t i b1 51 1 k l c u p c 0 t i b2 51 0 k l c u p c byte 4: control register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b6 21 1 1 m a r d s 2 t i b7 21 0 1 m a r d s 1 t i b0 31 9 m a r d s 0 t i b1 31 8 m a r d s byte 5: control register (1 = enable, 0 = disable)
9 ics9250-23 third party brands and names are the property of their respective owners. absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. group timing relationship table core supply voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 v i/o supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115c p u o r g z h m 6 6 u p cz h m 0 0 1 u p cz h m 3 3 1 u p c t e s f f oe c n a r e l o tt e s f f oe c n a r e l o tt e s f f oe c n a r e l o t m a r d s o t u p cs n 5 . 2s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5 6 6 v 3 o t u p cs n 5 . 7s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5 6 6 v 3 o t m a r d ss n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5 i c p o t 6 6 v 3s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5 t o d & b s uh c n y s aa / nh c n y s aa / nh c n y s aa / n electrical characteristics - input/supply/common output parameters t a = 0 - 70o c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter s ymb o l co nditi o n s min typ max unit s input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd -5 5 25 power down current i dd3.3vpd cl = 0 pf; with input to vdd or gnd 600 a input frequency f i v dd = 3.3 v 14.318 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 1 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms t pzh,tpzl output enable delay(all outputs) 1 10 ns t phz, t plz output disable delay(all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. ma delay 1
10 ics9250-23 third party brands and names are the property of their respective owners. electrical characteristics - cpuclk t a = 0 - 7 0 o c ; v dd = 3 . 3 v + / - 5% , v ddl = 2 . 5 v + / - 5% ; c l = 20 pf ( un l es s parameter s ymb o l co nditi o n s output high voltage v oh2b i oh = -1 ma output low voltage v ol2b i ol = 1 ma voh @min = 1 v v oh@max = 2.375v vol @min = 1.2 v v ol@max =0.3v rise time t r2b 1 v ol = 1 v, v oh = 2.0 v fall time t f2b 1 v oh = 2.0 v, v ol = 0.4 v duty cycle d t2b 1 v t = 1.25 v skew t sk2b 1 v t = 1.25 v jitter , cycle-to-cycle t jcyc-cyc2b 1 v t = 1.25 v (cpu 133, sdram 10 0 jitter , cycle-to-cycle t jcyc-cyc 1 v t = 1.25 v (all other select b) 1 guaranteed by design, not 100% tested in production. output high current i oh2b output low current i ol2b electrical characteristics - ioapic t a = 0 - 7 0 o c ; v dd = 3 . 3 v + / - 5% , v ddl = 2 . 5 v + / - 5% ; c l = 20 pf ( un l ess ot h erw i se state d) parameter symbol conditions min typ max units output high voltage v oh4b i oh = -18 ma 2.4 2.9 v output low voltage v ol4b i ol = 9 ma 0.25 0.4 v output high current i oh4b voh = 2.0 v -58 -22 ma vol @min = 1.0 v 31 34.1 v ol@max =0.2v 7.85 31 rise time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 0.4 1.28 2 ns fall time 1 t f4b v oh = 2.0 v, v ol = 0.4 v 0.4 1.2 1.6 ns duty cycle 1 d t4b v t = 1.25 v 45 49.6 55 % jitter, cycle-to-cycle t jcyc-cyc4b 1 v t = 1.25 v 432 750 ps 1 guaranteed by design, not 100% tested in production. ma output low current i ol4b
11 ics9250-23 third party brands and names are the property of their respective owners. electrical characteristics - pciclk t a = 0 - 7 0 o c ; v dd = 3 . 3 v + / - 5% , v ddl = 2 . 5 v + / - 5% ; c l = 60 pf f or p c i 0 & p c i 1 , c l = 30 pf f or ot h er p c is parameter symbol conditions min typ max units output high voltage v oh1 i oh = -1 ma 2.4 3.25 v output low voltage v ol1 i ol = 1 ma 0.03 0.55 v voh @ min = 1 v -71 -33 v oh@max = 3.135v -33 -10 vol @min = 1.95 v 38 74 v ol@max =0.4v 22 30 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.65 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.53 2 ns duty cycle 1 d t1 v t = 1.5 v 45 51.1 55 % skew 1 t sk1 v t = 1.5 v 331 500 ps jitter , cycle-to-cycle t jcyc-cyc1 v t = 1.5 v 185 500 ps 1 guaranteed by design, not 100% tested in production. ma ma output high current i oh1 output low current i ol1 electrical characteristics - 3v66 t a = 0 - 7 0 o c ; v dd = 3 . 3 v + / - 5% , v ddl = 2 . 5 v + / - 5% ; c l = 10 - 30 pf parameter symbol conditions output high voltage v oh1 i oh = -1 ma output low voltage v ol1 i ol = 1 ma voh @ min = 1 v v oh@max = 3.135v vol @min = 1.95 v v ol@max =0.4v fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v duty cycle 1 d t1 v t = 1.5 v skew 1 t sk1 v t = 1.5 v jitter 1 ,cycle-to-cycle t jcyc-cyc1 v t = 1.5 v 1 guaranteed by design, not 100% tested in production. v ol = 0.4 v, v oh = 2.4 v rise time 1 t r1 i oh1 i ol1 output high current output low current
12 ics9250-23 third party brands and names are the property of their respective owners. electrical characteristics - 24mhz t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unl e parameter symbol conditions output high voltage v oh5 i oh = -1 ma output low voltage v ol5 i ol = 1 ma voh @min = 1 v v oh@max = 3.135v vol @min = 1.95 v v ol@max =0.4v ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v duty cycle 1 d t5 v t = 1.5 v jitter 1 ,cy cl e-t o-cy cl e t jcyc-cyc5 v t = 1.5 v, 24mhz 1 guaranteed by design, not 100% tested in production. output high current i oh5 output low current i ol5 electrical characteristics - 48mhz, ref t a = 0 - 7 0 o c ; v dd = 3 . 3 v + / - 5% , v ddl = 2 . 5 v + / - 5% ; c l = 20 pf ( un l es s parameter symbol conditions output high voltage v oh5 i oh = -1 ma output low voltage v ol5 i ol = 1 ma voh @ min = 1 v v oh@max = 3.135v vol @min = 1.95 v v ol@max =0.4v rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v duty cycle 1 d t5 v t = 1.5 v jitter 1 , cycle-to-cycle t j c y c-c y c5 v t = 1.5 v, 24mhz jitter 1 , cycle-to-cycle t j c y c-c y c5 v t = 1.5 v, 48mhz jitter 1 , cycle-to-cycle t jcyc-cyc5 v t = 1.5 v, ref 1 guaranteed by design, not 100% tested in production. output high current output low current i oh5 i ol5
13 ics9250-23 third party brands and names are the property of their respective owners. electrical characteristics - sdram t a = 0 - 7 0 o c ; v dd = 3 . 3 v + / - 5% , v ddl = 2 . 5 v + / - 5% ; c l = 30 pf parameter symbol conditions min typ max units output high voltage v oh1 i oh = -1 ma 2.4 3.28 v output low voltage v ol1 i ol = 1 ma 0.03 0.4 v voh @ min = 2 v -85 -54 v oh@max = 3.135v -46 -12 vol @min = 1 v 54 63 v ol@max =0.4v 27 53 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.25 1.6 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.53 1.6 ns duty cycle 1 d t1 v t = 1.5 v 45 53.2 55 % skew t sk1 v t = 1.5 v 267 380 ps jitter 1 , cycle-to-cycle t jcyc-cyc1 v t = 1.5 v 176 250 ps 1 guaranteed by design, not 100% tested in production. ma ma output high current i oh1 output low current i ol1 (n o sk ew wi n d ow i s nee d e d f or g roup sk ew spec. ) t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% 24mhz, 48mhz, ref, cpu & ioapic load = 20 pf; pci, sdram & 3v66 load = 30 pf. refer to group offset waveform diagram for definition of transition edges. group skews (cpu = 66 mhz; sdram = 100mhz) parameter symbol conditions min typ max units cpu to sdram skew 1 t sk1 cpu-sdram cpu @ 1.25 v, sdram @ 1.5 v 2.0 3.0 ns cpu to 3v66 skew 1 t sk1 cpu-3v66 cpu @ 1.25 v, 3v66 @ 1.5 v 7 8 ns sdram to 3v66 skew 1 t sk1 sdram-3v66 sdram @1.5v, 3v66 @ 1.5 v -500 394 500 ps 3v66 to pci skew 1 t sk1 3v66-pci 3v66 @1.5v, pci @ 1.5 v 1.5 2.58 3.5 ns group skews (cpu = 100 mhz; sdram = 100mhz) parameter symbol conditions min typ max units cpu to sdram skew 1 t sk1 cpu-sdram cpu @ 1.25 v, sdram @ 1.5 v 4.5 5.5 ns cpu to 3v66 skew 1 t sk1 cpu-3v66 cpu @ 1.25 v, 3v66 @ 1.5 v 4.5 4.63 5.5 ns sdram to 3v66 skew 1 t sk1 sdram-3v66 sdram @1.5v, 3v66 @ 1.5 v -500 396 500 ps 3v66 to pci skew 1 t sk1 3v66-pci 3v66 @1.5v, pci @ 1.5 v 1.5 2.58 3.5 ns group skews (cpu = 133 mhz; sdram = 100mhz) parameter symbol conditions min typ max units cpu to sdram skew 1 t sk1 cpu-sdram cpu @ 1.25 v, sdram @ 1.5 v -500 -322 500 ps cpu to 3v66 skew 1 t sk1 cpu-3v66 cpu @ 1.25 v, 3v66 @ 1.5 v -500 -284 500 ps sdram to 3v66 skew 1 t sk1 sdram-3v66 sdram @1.5v, 3v66 @ 1.5 v -500 389 500 ps 3v66 to pci skew 1 t sk1 3v66-pci 3v66 @1.5v, pci @ 1.5 v 1.5 2.61 3.5 ns
14 ics9250-23 third party brands and names are the property of their respective owners. group offset waveforms cpu/itp/hclk [66mhz (2.5v)] cpu/itp/hclk [100mhz (2.5v)] sdram [11:0, f] & dclkwr [100mhz (3.3v)] 3v66 link (ich / mgch) [66mhz (3.3v)] pci [7:0] lpc/sio [33mhz (3.3v)] ref clock [14.318mhz (3.3v)] usb [48mhz (3.3v)] apic (cpu/mch) [16.67mhz (2.5v)] 0ns cpu 66 period cpu 100 period sdram 100 period 3v66-pci 25ns 50ns 75ns
15 ics9250-23 third party brands and names are the property of their respective owners. ordering information ics9250 y f-23 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator device type prefix ics, av = standard device example: ics xxxx y f - ppp ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2 . 41 2 . 80 . 09 5. 110 a1 0 . 20 0 . 40 . 008 . 016 b 0 . 20 0 . 34 . 008 . 0135 c 0 . 13 0 . 25 . 005 . 010 d e 10 . 03 10 . 68 . 395 . 420 e1 7 . 40 7 . 60 . 291 . 299 e h 0 . 38 0 . 64 . 015 . 025 l 0 . 50 1 . 02 . 020 . 040 n

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