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integrated circuit systems, inc. ics9250-16 third party brands and names are the property of their respective owners. block diagram 9250-16 rev h 9/5/00 recommended application:

output features: ? 3 cpu (2.5v) 66.6/133.3mhz (up to 150mhz achievable through i 2 c) 9 sdram (3.3v) @ 133.3mhz (up to 150mhz achievable through i 2 c) 8 pci (3.3 v) @33.3mhz 2 ioapic (2.5v) @ 33.3mhz 2 hublink clocks (3.3 v) @ 66.6mhz 2 usb (3.3v) @ 48mhz ( non spread spectrum) 1 ref (3.3v) @ 14.318mhz features: supports spread spectrum modulation, down spread 0 to -0.5% and 0.25% center spread. i 2 c support for power management efficient power management scheme through pd# uses external 14.138mhz crystal alternate frequency selections available through i 2 c control. functionality pin configuration 56-pin 300mil ssop *fs2//ref0 vdd0 x1 x2 gnd0 gnd1 3v66-0 3v66-1 vdd1 vdd2 pciclk0 pciclk1 pciclk2 gnd2 pciclk3 pciclk4 gnd2 pciclk5 pciclk6 pciclk7 vdd2 vdd3 gnd3 gnd4 48mhz_0 48mhz_1 vdd4 fs0 gndl1 ioapic0 ioapic1 vddl1 cpuclk0 vddl0 cpuclk1 cpuclk2 gndl0 gnd5 sdram0 sdram1 vdd5 sdram2 sdram3 gnd5 sdram4 sdram5 vdd5 sdram6 sdram7 gnd5 sdram_f vdd5 pd# sclk s data fs1 ics9250-16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ref0 cpu66/100/133 [2:0] vddl 3v66 [1:0] sdram [7:0] pciclk [7:0] ioapic [1:0] vddl sdram_f pll2 48mhz [1:0] x1 x2 xtal osc control logic config reg fs(2:0) pd# 2 3 2 8 1 8 2 /2 /2 /3 /2 pll1 spread spectrum sdata sclk frequency generator & integrated buffers for celeron & p ii / iii ? 2 s f1 s f0 s fn o i t c n u f x0 0 e t a t s i r t x0 1t s e t 010 z h m 6 6 = u p c e v i t c a z h m 0 0 1 = m a r d s 011 z h m 0 0 1 = u p c e v i t c a z h m 0 0 1 = m a r d s 111 z h m 3 3 1 = u p c e v i t c a z h m 0 0 1 = m a r d s 110 ) n o i t i d n o c l a i c e p s ( z h m 3 3 1 = u p c e v i t c a z h m 3 3 1 = m a r d s ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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' electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd -5 5 a i il1 v in = 0 v; inputs with no pull-up resistors -5 2 i il2 v in = 0 v; inputs with pull-up res is tors -200 -100 c l = 0 pf; select @ 66 mhz 97 110 c l = 0 pf; select @ 100 mhz 91 105 c l = 0 pf; select @ 133 mhz 100 130 c l = max loads; select @ 66 mhz 275 310 c l = max loads; select @ 100 mhz 267 300 c l = max loads; select @ 133 mhz 278 350 c l = 0 pf; select @ 66 mhz 8 10 c l = 0 pf; select @ 100 mhz 11 15 c l = 0 pf; select @ 133 mhz 13 20 c l = max loads; select @ 66 mhz 22 70 c l = max loads; select @ 100 mhz 31 100 c l = max loads; select @ 133 mhz 37 130 i dd3.3pd c l = max loads 220 400 i dd.25pd input address vdd or gnd <1 10 input frequency f i v dd = 3.3 v 12 14.318 16 mhz pin inductance l pin 7nh c in lo g ic in p u t s 5 p f c out output pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target frequency 5 ms settling time 1 t s from 1st crossing to 1% target frequency 5 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target frequency 5 ms t pzh ,t pzl output enable delay (all outputs) 1 10 ns t phz ,t plz output disable delay (all outputs) 1 10 ns 1 guaranteed by des ign, not 100% tes ted in production. input low current a ma ma i dd3 .3 op delay 1 ma ma input capacitance 1 i dd2 .5 op a powerdown current operating supply current
ics9250-16 electrical characteristics - cpu t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 16 45 ? output impedance r dsn2b 1 v o = v dd *(0.5) 13.5 21 45 ? output high voltage v oh2b i oh = -1 ma 2 v output low voltage v ol2b i ol = 1 ma 0.4 v v oh @ min = 1.0 v -27 -68 v oh @ max = 2.375 v -9 -27 v ol @ min = 1.2 v 27 54 v ol @ max = 0.3 v 11 30 rise time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 0.4 1.1 1.6 ns fall time 1 t f2b v oh = 2.0 v, v ol = 0.4 v 0.4 1.1 1.6 ns v t = 1.25 v, 66, 100 mhz 45 49 55 v t = 1.25 v, 133 mhz 40 48 55 skew window 1 t sk2b v t = 1.25 v 65 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc2b v t = 1.25 v 90 250 ps 1 guaranteed by design, not 100% tested in production. % d t2b duty cycle 1 ma ma output high current output low current i oh2b i ol2b electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp1b 1 v o = v dd *(0.5) 12 14 55 ? output impedance r dsn1b 1 v o = v dd *(0.5) 12 14.5 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 -108 v oh @ max = 3.135 v -9 -33 v ol @ min = 1.95 v 30 95 v ol @ max = 0.4 v 29 38 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.2 1.6 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.2 1.6 ns duty cycle 1 d t1 v t = 1.5 v 45 49 55 % skew window 1 t sk1 v t = 1.5 v 65 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 120 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh1 ma output low current i ol1 ma

ics9250-16 electrical characteristics - ioapic t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp4b 1 v o = v dd *(0.5) 9 16 30 ? output impedance r dsn4b 1 v o = v dd *(0.5) 9 20 30 ? output high voltage v oh4b i oh = -1 ma 2 v output low voltage v ol4b i ol = 1 ma 0.4 v v oh @ min = 1.0 v -27 -68 v oh @ max = 2.375 v -9 -27 v ol @ min = 1.2 v 27 54 v ol @ max = 0.3 v 11 30 rise time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 0.4 1.1 1.6 ns fall time 1 t f4b v oh = 2.0 v, v ol = 0.4 v 0.4 1.1 1.6 ns duty cycle 1 d t4b v t = 1.25 v 45 49 55 % skew window 1 t sk4b v t = 1.25 v 81 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc4b v t = 1.25 v 150 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh4b ma output low current i ol4b ma electrical characteristics - sdram t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp3b 1 v o = v dd *(0.5) 10 12 24 ? output impedance r dsn3b 1 v o = v dd *(0.5) 10 15 24 ? v oh @ min = 2.0 v -54 -92 v oh @ max = 3.135 v -16 -46 v ol @ min = 1.0 v 54 68 v ol @ max = 0.4 v 29 53 rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 0.4 1 1.6 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 0.4 1.5 1.6 ns duty cycle 1 d t3 v t = 1.5 v 45 52 55 % skew window 1 t sk3 v t = 1.5 v 85 250 ps v t = 1.5 v, 66, 100 mhz 120 250 v t = 1.5 v, 133 mhz 150 300 1 guaranteed by design, not 100% tested in production. jitter, cycle-to-cycle 1 t jcyc-cyc3 ps ma ma output high current output low current i oh3 i ol3
ics9250-16 electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp1b 1 v o = v dd *(0.5) 12 15 55 ? output impedance r dsn1b 1 v o = v dd *(0.5) 12 15 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 -106 v oh @ max = 3.135 v -14 -33 v ol @ min = 1.95 v 30 94 v ol @ max = 0.4 v 29 38 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.3 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.4 2 ns duty cycle 1 d t1 v t = 1.5 v 45 51 55 % skew window 1 t sk1 v t = 1.5 v 250 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 150 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh1 ma output low current i ol1 ma electrical characteristics - ref, 48mhz_0 (pin 25) t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp5b 1 v o = v dd *(0.5) 20 29 60 ? output impedance r dsn5b 1 v o = v dd *(0.5) 20 27 60 ? output high voltage v oh15 i oh = -1 ma 2.4 v output low voltage v ol5 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -29 -54 v oh @ max = 3.135 v -11 -23 v ol @ min = 1.95 v 29 54 v ol @ max = 0.4 v 16 27 rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 0.4 1.3 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 0.4 1.6 4 ns duty cycle 1 d t5 v t = 1.5 v 45 53 55 % jitter, cycle-to-cycle 1 t j c y c-c y c5 v t = 1.5 v, fixed clocks 130 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc5 v t = 1.5 v, ref clocks 465 1000 ps 1 guaranteed by design, not 100% tested in production. output high current i oh5 ma output low current i ol5 ma
ics9250-16 electrical characteristics - 48mhz_1 (pin 26) t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp3b 1 v o = v dd *(0.5) 10 15 24 ? output impedance r dsn3b 1 v o = v dd *(0.5) 10 15 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.55 v v oh @ min = 2.0 v -54 -82 v oh @ max = 3.135 v -20 -46 v ol @ min = 1.0 v 54 95 v ol @ max = 0.4 v 28 53 rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 0.4 1.1 1.6 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 0.4 1.3 1.6 ns duty cycle 1 d t3 v t = 1.5 v 45 53 55 % jitter, cycle-to-cycle 1 t jcyc-cyc3b v t = 1.5 v 130 250 ps 1 guaranteed by design, not 100% tested in production. output high current i oh3 ma output low current i ol3 ma
ics9250-16 group offset waveforms 0ns 10ns 20ns 30ns 40ns 0ns 10ns 20ns 30ns 40ns 0ns 10ns 20ns 30ns 40ns 0ns 10ns 20ns 30ns 40ns cycle repeats cycle repeats cycle repeats cycle repeats cpu 100mhz cpu 66mhz cpu 133mhz sdram 100mhz sdram 100mhz sdram 100mhz 3.3v 66mhz 3.3v 66mhz 3.3v 66mhz 3.3v 66mhz pci 33mhz 7.5ns 5.0ns 6.0ns 2.5ns 0.0ns 0.0ns 0.0ns 0.0ns 0.0ns 1.5-3.5ns
ics9250-16 group skews (cpu = 66 mhz) t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% cpu & ioapic load (lumped) = 20 pf; pci, sdram, 3v66 load (lumped) = 30 pf refer to group offset waveform dia g ram for definition of transition ed g es. parameter symbol conditions min typ max units cpu to sdram skew 1 t sk1 cpu-sdram -3 -2.6 -2 ns skew window 1 t w1 cpu-sdram 0 150 500 ps cpu to 3v66 skew 1 t sk1 cpu-3v66 77.28ns skew window 1 t w1 cpu-3v66 0 130 500 ps sdram to 3v66 skew 1 t sk1 sdram-3v66 -500 100 500 ps skew window 1 t w1 sdram-3v66 0 155 500 ps 3v66 to pci skew 1 t sk1 3v66-pci 1.5 2.4 3.5 ns skew window 1 t w1 3v66-pci 0 275 500 ps ioapic to pci skew 1 t sk1 ioapic-pci -1 -0.4 1 ns skew window 1 t w1 ioapic-pci 00.251 ns 1 guaranteed by design, not 100% tested in production. cpu @ 1.25 v, sdram @ 1.5 v cpu @ 1.25 v, 3v66 @ 1.5 v sdram, 3v66 @ 1.5 v 3v66, pci @ 1.5 v ioapic @ 1.25 v, pci @ 1.5 v group skews (cpu = 100 mhz) t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% cpu & ioapic load (lumped) = 20 pf; pci, sdram, 3v66 load (lumped) = 30 pf refer to group offset waveform dia g ram for definition of transition ed g es. parameter symbol conditions min typ max units cpu to sdram skew 1 t sk2 cpu-sdram 4.5 4.9 5.5 ns skew window 1 t w2 cpu-sdram 0 140 500 ps cpu to 3v66 skew 1 t sk2 cpu-3v66 4.5 4.8 5.5 ns skew window 1 t w2 cpu-3v66 0 150 500 ps sdram to 3v66 skew 1 t sk2 sdram-3v66 -500 100 500 ps skew window 1 t w2 sdram-3v66 0 155 500 ps 3v66 to pci skew 1 t sk2 3v66-pci 1.5 2.4 3.5 ns skew window 1 t w2 3v66-pci 0 275 500 ps ioapic to pci skew 1 t sk2 ioapic-pci -1 -0.4 1 ns skew window 1 t w2 ioapic-pci 00.251 ns 1 guaranteed by design, not 100% tested in production. 1 guaranteed by design, not 100% tested in production. cpu @ 1.25 v, sdram @ 1.5 v cpu @ 1.25 v, 3v66 @ 1.5 v sdram, 3v66 @ 1.5 v 3v66, pci @ 1.5 v ioapic @ 1.25 v, pci @ 1.5 v
ics9250-16 group skews (cpu = 133 mhz) t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% cpu & ioapic load (lumped) = 20 pf; pci, sdram, 3v66 load (lumped) = 30 pf refer to group offset waveform dia g ram for definition of transition ed g es. parameter symbol conditions min typ max units cpu to sdram skew 1 t sk3 cpu-sdram -500 70 500 ps skew window 1 t w3 cpu-sdram 0 125 500 ps cpu to 3v66 skew 1 t sk3 cpu-3v66 -500 -145 500 ps skew window 1 t w3 cpu-3v66 0 220 500 ps sdram to 3v66 skew 1 t sk3 sdram-3v66 -500 100 500 ps skew window 1 t w3 sdram-3v66 0 155 500 ps 3v66 to pci skew 1 t sk3 3v66-pci 1.5 2.4 3.5 ns skew window 1 t w3 3v66-pci 0 275 500 ps ioapic to pci skew 1 t sk3 ioapic-pci -1 -0.4 1 ns skew window 1 t w3 ioapic-pci 00.251 ns 1 guaranteed by design, not 100% tested in production. 3v66, pci @ 1.5 v ioapic @ 1.25 v, pci @ 1.5 v sdram, 3v66 @ 1.5 v cpu @ 1.25 v, sdram @ 1.5 v cpu @ 1.25 v, 3v66 @ 1.5 v
ics9250-16 3,,% c3 1 clock load c1 c1 2 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 ferrite bead vdd c2 22f/20v tantalum ferrite bead vdd c2 22f/20v tantalum 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 = routed power = ground connection key (component side copper) = ground plane connection = power route connection = solder pads = clock load 3.3v power route 3.3v power route 2.5v power route 45$% 8a
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ics9250-16 ordering information ics9250 y f-16-t

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7 ics xxxx y f - ppp - t ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. min ma x min ma x a 2.413 2.794 .095 .110 a1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c 0.127 0.254 .005 .010 d e 10.033 10.668 .395 .420 e1 7.391 7.595 .291 .299 e 0.635 ba sic 0.025 ba sic h 0.381 0.635 .015 .025 l 0.508 1.016 .020 .040 n 0 8 0 8 v a ria tions min ma x min ma x 28 9.398 9.652 .370 .380 34 11.303 11.557 .445 .455 48 15.748 16.002 .620 .630 56 18.288 18.542 .720 .730 64 20.828 21.082 .820 .830 j e d e c m o- 118 doc# 10-0034 6/1/00 rev b sy mbol see variations see variations in millimeters common dimensions in inc he s common dimensions see variations n d mm. d (inch) see variations

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