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_______________ge ne ra l de sc ript ion the max456 is the first monolithic cmos 8 x 8 video crosspoint switch that significantly reduces compon ent count, board space, and cost. the crosspoint switc h contains a digitally controlled matrix of 64 t-swit ches that connect eight video input signals to any, or a ll, out- put channels. each matrix output connects to eight internal, high-speed (250v/s), unity-gain-stable b uffers capable of driving 400 and 20pf to 1.3v. for appli- cations requiring increased drive capability, the max456 outputs can be connected directly to two max470 quad, gain-of-two video buffers, which are capable of driving 75 loads. three-state output capability and internal, program ma- ble active loads make it feasible to parallel multi ple max456s and form larger switch matrices. in the 40-pin dip package, crosstalk (70db at 5mhz) is minimized, and board area and complexity are simpli - fied by using a straight-through pinout. the analo g inputs and outputs are on opposite sides, and each channel is separated by a power-supply line or quie t digital logic line. ________________________applic a t ions video test equipment video security systems video editing ____________________________fe a t ure s ? routes any input channel to any output channel ? switches standard video signals ? serial or parallel digital interface ? expandable for larger switch matrices ? 80db all-channel off isolation at 5mhz ? 8 internal buffers with:250v/s slew rate, three-state output capability, power-saving disable feature, 35mhz bandwidth ______________orde ring i nform a t ion ordering information continued on last page. * dice are specified at t a = +25 c, dc parameters only. m ax 4 5 6 8 x 8 vide o crosspoint sw it c h ________________________________________________________________ maxim integrated products 1 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 v+ out0 d2 out1 a1 a2 d0/ser in d1/ser out top view max456 d3 out2 v- out3 load in1 a0 in0 agnd out4 dgnd in2 30 29 28 27 26 25 24 23 22 21 agnd out5 agnd out6 v+ out7 ce ce latch wr 11 12 13 14 15 16 17 18 19 20 edge/level in4 dgnd in3 ser/par in6 v+ in5 v- in7 dip plcc on last page _________________pin configura t ions output select 8 x 8 t-switch matrix max470 a2 8 input channels a1 a0 d3 d2 d1/ser out d0/ser in input select or serial i/o max456 latch wr 75 w 75 w a v = 2 max470 a v = 2 ________typic a l applic a t ion circ uit ca ll t oll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 for fre e sa m ple s or lit e ra t ure . 19-2858; rev 2; 2/94 part temp. range pin-package max456cpl 0c to +70c 40 plastic dip max456cqh 0c to +70c 44 plcc max456c/d 0c to +70c dice* downloaded from: http:///
m ax 4 5 6 8 x 8 vide o crosspoint sw it c h 2 _______________________________________________________________________________________ absolute maximum ratings total supply voltage (v+ to v-) .................... .......................+12v positive supply voltage v+ referred to agnd......-0 .3v to +12v negative supply voltage v- referred to agnd .....-12 v to +0.3v dgnd voltage....................................... ..................agnd 0.3v buffer short circuit to ground when not exceeding package power dissipation ............ .indefinite analog input voltage ............................(v+ + 0.3v) to (v- - 0.3v) digital input voltage .............................( v+ + 0.3v) to (v- - 0.3v) input current, power on or off digital inputs..................................... ............................20ma analog inputs ...................................... .........................50ma continuous power dissipation (t a = +70c) 40-pin plastic dip (derate 11.3mw/c above +70c).. ..889mw 40-pin cerdip (derate 20.0mw/c above +70c)....160 0mw 44-pin plcc (derate 13.3mw/c above +70c) .......10 66mw operating temperature ranges: max456c _ _ ........................................ ..............0c to +70c max456e _ _ ........................................ ...........-40c to +85c storage temperature range .......................... ...-65c to +160c lead temperature (soldering, 10 sec) ............... .............+300c electrical characteristics (v+ = 5.0v, v- = -5.0v, -1.3v v in +1.3v; load = +5v; internal load resistors on; agnd = dgnd = 0v; t a = +25c, unless otherwise noted.) stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device . these are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of the specifications is not implied. exposur e to absolute maximum rating conditions for extended per iods may affect device reliability. parameter conditions min typ max units t a = +25c 39 45 operating supply voltage 4.5 5.5 v offset voltage drift t a = t min to t max 20 v/c buffer offset voltage t a = +25c 7 supply current, all buffers on (no external load) t a = t min to t max 60 ma 1.5 3.0 supply current, all buffers off t a = t min to t max 4 ma power-supply rejection ratio 4.5v to 5.5v, dc measurement 50 64 db input voltage range -1.3 1.3 v t a = t min to t max 0.99 1.0 1.01 voltage gain 0.98 1.0 1.02 v/v analog input current 0.1 10 na output leakage current internal load resistors off, all buffers off, t a = t min to t max 100 na internal load resistors on, no external load, v in = 0v to 1v t a = +25c t a = t min to t max t a = t min to t max 12 mv t a = +25c t a = +25c 250 400 600 internal amplifier load resistor (load pin = 5v) t a = t min to t max 200 765 buffer output voltage swing internal load resistors on, no external load 1.3 v digital input current t a = t min to t max 1 output impedance at dc 10 input logic low threshold 0.8 v input logic high threshold 2.4 v ser out output logic low 0.4 ser out output logic high 4 v serial mode, ser/ C p a r C = 5v i oh = -0.4ma i ol = 1.6ma a downloaded from: http:///
note 1: guaranteed by design. note 2: see dynamic test circuits on page 11. note 3: 3db typical crosstalk improvement when r s = 0 . note 4: input test signal: 3.58mhz sine wave of amplitude 40ire superimposed on a linear ramp (0 to 100ire). ire is a unit of video-signal amplitude developed by the internation al radio engineers. 140ire = 1.0v. m ax 4 5 6 8 x 8 vide o crosspoint sw it c h _______________________________________________________________________________________ 3 parameter conditions min typ max units all-channel crosstalk 5mhz, v in = 2v p-p (notes 2, 3) 57 db output-buffer slew rate x internal load resistors on, 10pf load 250 v/s single-channel crosstalk 5mhz, v in = 2v p-p (note 2) 60 70 db all-channel off isolation 5mhz, v in = 2v p-p (note 2) 80 db -3db bandwidth 10pf load, v in = 2v p-p (note 2) 25 35 mhz differential phase error (note 4) 1.0 deg electrical characteristics (v+ = 5.0v, v- = -5.0v, -1.3v v in +1.3v, load = +5v, internal load resistors on, agnd = dgnd = 0v, t a = +25c, unless otherwise noted.) differential gain error (note 4) 0.5 % input noise dc to 40mhz 0.3 1.0 mv rms input capacitance all buffer inputs grounded 6 pf buffer input capacitance additional capacitance for each out- put buffer connected to channel input 2 pf output capacitance output buffer off 7 pf dynamic specifications (note 1) parameter latch delay symbol min typ max t d 80 units ns switch break-before-make delay t on - t off 15 ns latch edge to switch off t off 35 ns latch edge to switch on t on 50 ns write pulse width low t wl 80 ns chip-enable to write setup t ce 0 ns write pulse width high t wh 80 ns 240 data hold t dh 0 ns latch pulse width t l 80 ns conditions latch on parallel mode 32-bit serial mode data setup t ds 160 ns switching characteristics (note 1) (figure 4, v+ = 5.0v, v- = -5.0v, -1.3v v in +1.3v, load = +5v, internal load resistors on, agnd = dgnd = 0v, t a = t min to t max , unless otherwise noted.) downloaded from: http:///
m ax 4 5 6 8 x 8 vide o crosspoint sw it c h 4 _______________________________________________________________________________________ ___________________________________________________ ___________pin de sc ript ion note 1: buffer inputs are internally grounded with a 1000 o r 1001 command from the d3-d0 lines. agnd must be a t 0.0v since the gain setting resistors of the buffers are internall y tied to agnd. pin name function 1, 12, 23, 34 n.c. no connect. not internally connected. 1 2 d1/ser out parallel data bit d1 when ser/p a r C = 0v. serial output for cascading multiple parts when ser/p a r C = 5v. 2 3 d0/ser in parallel data bit d0 when ser/p a r C = 0v. a serial input when ser/p a r C = 5v. 3, 4, 6 4, 5, 7 a2, a1, a0 output buffer address lines 5, 7, 9, 11, 13, 15, 17, 19 6, 8, 10, 13, 15, 17, 19, 21 in0Cin7 video lnput lines 8 9 load asynchronous control line. when load = 1, all the 4 00 internal active loads are on. when load = 0, external 400 loads must be used. the buffers must have a resistive load to maintain stab ility. 10, 12 11, 14 dgnd digital ground pins. both dgnd pins must have the s ame potential and be bypassed to agnd. dgnd should be within 0.3v of agnd. 14 16 edge/ C l e v e l C when this control line is high, the 2nd-rank regist ers are loaded with the rising edge of the latch line. if this control line is low, the 2nd-rank reg- isters are transparant when latch is low, passing d ata directly from the 1st-rank registers to the decoders. 16, 26, 40 18, 29, 44 v+ all v+ pins must be tied to each other and bypassed to agnd separately (figure 2). 18 20 ser/p a r C 5v = 32-bit serial, 0v = 7-bit parallel 20, 34 22, 38 v- both v- pins must be tied to each other and bypasse d to agnd separately (figure 2). 21 24 wr write in the serial mode, shifts data in. in the par allel mode, wr loads data into the 1st-rank registers. data is latched o n the rising edge. 22 25 latch if edge/ C l e v e l C = 5v, data is loaded from the 1st-rank registers to the 2nd- rank registers on the rising edge of latch. if edge / C l e v e l C = 0v, data is loaded while latch = 0v. in addition, data is loade d during the execution of parallel-mode functions 1011 through 1110, or if latch = 5v during the execution of the parallel-mode "software-latch" com mand (1111). 23 26 c e C C c h i p e n a b l e C . when C c e C = 0v and ce = 5v, the wr line is enabled. 24 27 ce chip enable. when C c e C = 0v and ce = 5v, the wr line is enabled. 25, 27, 29, 31, 33, 35, 37, 39 28, 30, 32, 35, 37, 39, 41, 43 out7-out0 output buffers 7-0 (note 1) 28, 30, 32 31, 33, 36 agnd analog ground must be at 0.0v since the gain resist ors of the buffers are tied to these 3 pins. 36 40 d3 parallel data bit d3 when ser/ C p a r C = 0v. when d3 = 0v, d0-d2 specifies the input channel to be connected to buffer. when d 3 = 5v, then d0-d2 specify control codes. d3 is not used when ser/ C p a r C = 5v. 38 42 d2 parallel data bit d2 when ser/ C p a r C = 0v. not used when ser/ C p a r C = 5v. dip plcc downloaded from: http:///
m ax 4 5 6 8 x 8 vide o crosspoint sw it c h _______________________________________________________________________________________ 5 _______________de t a ile d de sc ript ion out put buffe rs the max456 video crosspoint switch consists of 64 t-switches in an 8 x 8 grid (figure 1). the 8 matr ix out- puts are followed by 8 wideband buffers optimized f or driving 400 and 20pf loads. each buffer has an internal active load on the output that can be read ily shut off via the load input (off when load = 0v). the shut-off is useful when two or more max456 circuits are connected in parallel to create more input channels . with more input channels, only one set of buffers c an be active and only one set of loads can be driven. and, when active, the buffer must have either 1) an internal load, 2) the internal load of anothe r buffer in another max456, or 3) an external load. each max456 output can be disabled under logic con- trol. when a buffer is disabled, its output enters a high- impedance state. in multichip parallel application s, the disable function prevents inactive outputs from loa ding lines driven by other devices. disabling the inact ive buffers reduces power consumption. the max456 outputs connect easily to max470 quad, gain-of-two buffers when 75 loads must be driven. pow e r-on reset the max456 has an internal power-on reset (por) cir - cuit that remains low for 5s when power is applied . por also remains low if the total supply voltage is less than 4v. the por disables all buffer outputs at power-up , but the switch matrix is not preset to any ini- tial condition. the desired switch state should be pro- grammed before the buffer outputs are enabled. ___________________digit a l i nt e rfa c e the desired switch state can be loaded in a 7-bit p aral- lel-interface mode or 32-bit serial-interface mode (see table 3 and figures 4-6). all action associated wi th the wr line occurs on its rising edge. the same is tru e for the latch line if edge/ C l e v e l C is high. otherwise, the second-rank registers update while latch is low (when edge/ C l e v e l C is low). wr is logically anded with ce and C c e C to allow active-high or active-low chip enable. 7 -bit pa ra lle l m ode in the parallel-interface mode, the 7 data bits a2- a0 and d3-d0 specify an output channel (a2-a0) and the input channel to which it connects (d3-d0). the da ta is loaded on the rising edge of wr. the 8 input chann els are selected by 0000 through 0111 (d3-d0). the remaining 8 codes (1000-1111) control other max456 functions, as listed in table 1. 3 2 -bit se ria l-i nt e rfa c e m ode in serial mode (ser/ C p a r C = high), all first-rank registers are loaded with data, making it unnecessary to spec ify an output address (a2, a1, a0). the input data for mat is d3-d0, starting with out0 and ending with out7 f or 32 total bits. only codes 0000 through 1010 are va lid. code 1010 disables a buffer, while code 1001 enable s it. after data is shifted into the 32-bit first-ra nk register, it is transferred to the second rank by the latch l ine (see table 2). downloaded from: http:///
8 x 8 vide o crosspoint sw it c h m ax 4 5 6 6 _______________________________________________________________________________________ table 1. parallel-interface mode functions a2-a0 d3-d0 function 0000 to 0111 connect the buffer selected by a2-a0 to the input c hannel selected by d3-d0. 1000 connect the buffer selected by a2-a0 to dgnd. note , if the buffer output is on, its output is its offset voltage. 1011 shut off the buffer selected by a2-a0, and retain 2 nd-rank contents. 1100 turn on the buffer selected by a2-a0, or restore th e previously connected channel. 1101 turn off all buffers, or leave 2nd-rank registers u nchanged. 1110 turn on all buffers, or restore the previously conn ected channels. 1111 send a pulse to the 2nd-rank registers to load them with the contents of the 1st-rank registers. when latch is held high, this "software -latch" command performs the same function as pulsing latch low. selects output buffer, out0 to out7 1001 and 1010 do not use these codes in the parallel-interface mo de. these codes are for the serial- interface mode only. table 2. serial-interface mode functions d3-d0 function 0000 to 0111 connect the selected buffer to the input channel selected by d3-d0. 1000 connect the input of the selected buffer to gnd. note, if the buffer output remains on, its input is its offset voltage. 1001 turn on the selected buffer and connect its input to gnd. use this code to turn on buffers after power is applied. the default power-up state is all buffers disabled. 1010 shut off the selected buffer at the speci- fied channel, and erase data stored in the 2nd rank of registers. the 2nd rank now holds the command word 1010. 1011 to 1111 do not use these codes in the serial-inter- face mode. they inhibit the latching of the 2nd-rank registers, which prevents proper data loading. downloaded from: http:///
m ax 4 5 6 8 x 8 vide o crosspoint sw it c h _______________________________________________________________________________________ 7 a = 1 in0 in1 in2 in3 in4 in5 in6 in7 output buffers out0 400 w load latch edge/level 2nd-rank registers 1st-rank registers wr ce ce a0 a1 a2 d3 d2 v+ v- agnd dgnd d1/ser out d0/ser in ser/par max456 8 x 8 switch matrix a = 1 out7 400 w figure 1. max456 functional diagram serial/ parallel d3 h x l h l a2-a0 x output buffer address output buffer address d1 serial output parallel input parallel input d2 x parallel input parallel input d0 serial input parallel input parallel input comment 32-bit serial mode parallel mode, d0-d2 = control code parallel mode, d0-d2 = input address l table 3. input/output line configurationsnote : x = don't care, h = 5v, l = 0v downloaded from: http:///
m ax 4 5 6 ________________typic a l applic a t ion figure 2 shows a typical application of the max456 with max470 quad, gain-of-two buffers at the outputs to drive 75 loads. this application shows the max456 digital-switch control interface set up in the 7-bi t paral- lel mode. the max456 uses 7 data lines and 2 contr ol lines (wr and latch). two additional lines may be needed to control ce and load when using multiple max456s. the input/output information is presented to the ch ip at a2-a0 and d3-d0 by a parallel printer port. the da ta is stored in the 1st-rank registers on the rising edge of wr. when the latch line goes high, the switch con- figuration is loaded into the 2nd-rank registers, a nd all 8 outputs enter the new configuration at the same tim e. each 7-bit word updates only one output buffer at a time. if several buffers are to be updated, the da ta is individually loaded into the 1st-rank registers. t hen, a single latch pulse is used to reconfigure all chann els simultaneously. the short basic program in figure 3 loads programmi ng data into the max456 from any ibm pc or compatible. it uses the computers lpt1 output to interface t o the circuit, then automatically finds the address for l pt1 and displays a table of valid input values to be us ed. the program does not keep track of previous com- mands, but it does display the last data sent to lp t1, which is written and latched with each transmission . 8 x 8 vide o crosspoint sw it c h 8 _______________________________________________________________________________________ 5 7 11 9 13 15 17 19 39 37 35 33 1 3 6 8 10 2,7,15 4,5,12,13 -5v 16 75 w 75 w 14 11 9 31 29 27 25 24 14 8 40 26 22 21 3 4 6 36 38 1 2 28, 30, 32 10, 12 20 34 23 18 16 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25 14 8-input video channels in0 in1 in2 in3 in4 in5 in6 in7 latch wr d0/ser in d1/ser out d2 d3 a0 a1 a2 out0 out1 out2 out3 out4 out5 out6 out7 ce edge/level load v+ v+ agnd dgnd v- v- ce ser/par v+ +5v -5v +5v all bypass capacitors 0.1 m f ceramic db-25 max456 in1 in2 in3 v+ gnd v- out1 in0 out0 a v = 2 out2 out3 max470 figure 2. typical application circuit downloaded from: http:///
m ax 4 5 6 8 x 8 vide o crosspoint sw it c h _______________________________________________________________________________________ 9 a0-a2 d0-d3 wr latch valid data n-1 valid data n t ds t wl t dh t wh t d t l ___________________________________________________ _________t im ing dia gra m s figure 3. basic program for loading data into the max456 from a pc using figure 2's circuit figure 4. write timing for serial- and parallel-in terface modes downloaded from: http:///
m ax 4 5 6 8 x 8 vide o crosspoint sw it c h 10 ______________________________________________________________________________________ data (n) data (n) data (n) data (n + 1) data (n + 1) data (n + 1) data (n + 2) data (n) data (n + 1) data (n + 2) see figure 4 for wr and latch timing wr latch first-rank register data second-rank register data (edge/level = low) second-rank register data (edge/level = high) _______________________________________________t im i ng dia gra m s (c ont inue d) figure 5. parallel-interface mode format (ser/ C p a r C = low) 0d3 0d2 0d1 0d0 1d3 1d2 7d3 7d2 7d1 7d0 data valid data valid see table 2 for input data see figure 4 for wr and latch timing wr latch input data for out0 input data for out1 to out6 input data for out7 second-rank register data (edge/level = low) second-rank register data (edge/level = high) figure 6. 32-bit serial-mode interface format (ser / C p a r C = high) downloaded from: http:///
m ax 4 5 6 8 x 8 vide o crosspoint sw it c h ______________________________________________________________________________________ 11 note 1: connect load (pin 8) to +5v (internal 400 loads on at all outputs). note 2: program any one input to connect to any one output (see table 1 or 2 for programming codes). note 3: turn on buffer at the selected output (see table 1 or 2). note 4: drive the selected input with v in , and measure v out at the -3db frequency at the selected output. note 5: program each numbered input to connect to the same numbered output (in0 to out0, in1 to out1, etc.). see table 1 or 2 for programming codes. note 6: turn off all output buffers (see table 1 or 2). note 7: drive all inputs with v in and measure v out at any output. note 8: isolation (in db) = 20log 10 (v out /v in ). note 9: turn on all output buffers (see table 1 or 2). note 10: drive any one input with v in and measure v out at any undriven output. note 11: crosstalk (in db) = 20log 10 (v out /v in ). note 12: drive all but one input with v in and measure v out at the undriven output. max456 out0 out1 out2 out3 out4 out5 out6 out7 load in0 in1 in2 in3 in4 in5 in6 in7 v out v out v out v out v out v out v out v out +5v max456 out0 out1 out2 out3 out4 out5 out6 out7 load in0 in1 in2 in3 in4 in5 in6 in7 v out +5v max456 out0 out1 out2 out3 out4 out5 out6 out7 load in0 in1 in2 in3 in4 in5 in6 in7 v out v out v out v out v out v out v out +5v max456 out0 out1 out2 out3 out4 out5 out6 out7 load in0 in1 in2 in3 in4 in5 in6 in7 v out +5v v in = 2vp-p, sweep frequency r s = 75 w v in = 2vp-p @ 5mhz r s = 75 w v in = 2vp-p @ 5mhz r s = 75 w v in = 2vp-p @ 5mhz r s = 75 w - 3db bandwidth (notes 1-4) all-channel off isolation (notes 1, 5-8) all-channel crosstalk (notes 1, 5, 9, 11, 12) single-channel crosstalk (notes 1, 5, 9-11) 75 w 75 w 7x ___________________________________________________ ____dyna m ic te st circ uit s downloaded from: http:///
maxim cannot assume responsibility for use of any c ircuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the cir cuitry and specifications without notice at any tim e. 12 __________________m a x im i nt e gra t e d produc t s, 1 2 0 sa n ga brie l drive , sunnyva le , ca 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0 ? 1994 maxim integrated products printed usa is a reg istered trademark of maxim integrated products. m ax 4 5 6 8 x 8 vide o crosspoint sw it c h ____pin configura t ions (c ont inue d) 1234 54 0 414243 44 6 20 23 25 24 26 27 28 21 22 18 19 78 9 1011 12 13 14 15 16 17 29 30 31 32 33 34 35 36 37 38 39 in5 out2 in6 in0 max456 plcc top view a1 a2 d0/ser in d1/ser out n.c. v+ out0 d2 out1 d3 v+ in7 ser/par n.c. v- latch wr ce ce out7 v- out3 agnd out4 n.c. agnd out5 agnd out6 v+ edge/level in4 dgnd in3 n.c. dgnd in2 load in1 a0 ___________________chip topogra phy d2 out0 v+ in6 ce in5 edge/level out3 out6 v+ agnd 0. 167" (4. 242mm) 0. 184" (4. 674mm) ser/par in7 wr latch ce out7 out4 agnd agnd out5 v+ d1/ser out d0/ser in a2 a1 in0 in4 dgnd in2 load in1 ao v- out1 d3 v- out2 dgnd in3 transistor count: 3820; substrate connected to v+. __orde ring i nform a t ion (c ont inue d) 44 plcc -40c to +85c max456eqh 40 plastic dip -40c to +85c max456epl pin-package temp. range part 40 cerdip -40c to +85c max456ejl downloaded from: http:///

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