1 tm fn2449.4 hsp43881/883 digital filter the hsp43881/883 is a video speed digital filter (df) designed to efficiently implement vector operations such as fir digital filters. it is comprised of eight filter cells cascaded internally and a shift and add output stage, all in a single integrated circuit. each filter cell contains a 8 x 8-bit multiplier, three decimation registers and a 26-bit accumulator. the output stage contains an additional 26-bit accumulator which can add the contents of any filter cell accumulator to the output stage accumulator shifted right by 8-bits. the hsp43881/883 has a maximum sample rate of 25.6mhz. the effective multiply accumulate (mac) rate is 204mhz. the hsp43881/883 df can be configured to process expanded coefficient and word sizes. multiple dfs can be cascaded for larger filter lengths without degrading the sample rate or a single df can process larger filter lengths at less than 25.6mhz with multiple passes. the architecture permits processing filter lengths of over 1000 taps with the guarantee of no overflows. in practice, most filter coefficients are less than 1.0, making even larger filter lengths possible. the df provides for 8-bit unsigned or two?s complement arithmetic, independently selectable for coefficients and signal data. each df filter cell contains three resampling or decimation registers which permit output sample rate reduction at rates of 1 / 2 , 1 / 3 or 1 / 4 the input sample rate. these registers also provide the capability to perform 2-d operations such as matrix multiplication and n x n spatial correlations/convolutions for image processing applications. features this circuit is processed in accordance to mil-std-883 and is fully conformant under the provisions of paragraph 1.2.1. 0mhz to 25.6mhz sample rate eight filter cells 8-bit coefficients and signal data low power cmos operation i ccsb 500 a maximum i ccop 160ma maximum at 20mhz 26-bit accumulator per stage filter lengths up to 1032 taps expandable coefficient size, data size and filter length decimation by 2, 3 or 4 applications 1-d and 2-d fir filters radar/sonar adaptive filters echo cancellation complex multiply-add sample rate converters block diagram ordering information part number temp. range ( o c) package pkg. no. hsp43881gm-25/883 -55 to 125 85 ld pga g85.a tcco tcci cin0 - 7 df filter cell 7 cout0 - 7 erase dcmo - 1 dienb cienb coenb mux clk adr0 - 2 reset 26 adr0, adr1, adr2 clk reset shadd senbh senbl output stage 8 v cc v ss din0 - din7 tcs sum0 - 25 3 8 df filter cell 6 26 8 8 df filter cell 5 26 8 8 df filter cell 4 26 8 8 df filter cell 3 26 8 8 df filter cell 2 26 8 8 df filter cell 1 26 8 8 df filter cell 0 26 8 8 8 5 5 2 26 26 2 8 5 data sheet may 1999 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 pinouts 85 pin pga top view, pins down a b c d e f g h j k l 2 17 3456 891011 coenb reset din7 v cc din6 din3 din0 tcci v cc v cc cout7 erase din1 din2 cienb cin7 cin6 cin4 cout5 cout6 align pin dienb din5 din4 cin5 cin3 cin2 v cc cin1 cin0 senbl cout3 cout4 cout1 v ss cout2 v ss cout0 shadd adr2 dcm0 clk sum0 v cc v ss sum1 sum3 sum2 sum5 sum4 adr0 sum25 v cc sum7 v ss sum16 sum17 sum20 senbh sum24 v ss v cc sum19 v ss sum15 sum12 sum10 sum8 sum6 sum9 sum11 v ss sum13 v cc sum14 sum18 sum21 sum22 sum23 dcm1 v ss tcco tcs adr1 v ss hsp43881/883
3 85 pin pga bottom view, pins up note: an overbar on a signal name represents an active low signal. pinouts (continued) dcm1 sum23 sum22 sum21 sum18 sum14 sum13 sum11 sum9 v ss v cc sum20 sum17 sum16 sum7 adr0 sum5 sum4 adr2 dcm0 clk v ss cout0 shadd sum1 sum3 sum2 sum0 v cc v ss cin2 v cc cout3 cout4 align pin a b c d e f g h j k l 1234 567 891011 adr1 sum25 v cc v ss v ss v cc v ss senbh sum24 sum19 sum15 sum12 sum10 sum8 sum6 cin1 cin0 senbl cout1 v ss cout2 cout5 cout6 dienb din5 din4 cin5 cin3 v cc v ss din0 din3 din6 din7 v ss coenb v cc reset cin8 v cc cin4 cin6 cin7 cienb din2 din1 erase cout7 tcs cout8 hsp43881/883
4 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0v input, output voltage . . . . . . . . . . . . . . . . . . gnd -0.5 to v cc +0.5v esd rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) pga package. . . . . . . . . . . . . . . . . . . . 36.0 7.0 maximum package power dissipation at 125 o c pga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.44w maximum junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 175 o c maximum storage temperate range . . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17,762 gates caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. table 1. dc electrical performance specifications parameter symbol test conditions group a subgroups temperature ( o c) min max units logical one input voltage v ih v cc = 5.5v 1, 2, 3 -55 t a 125 2.2 - v logical zero input voltage v il v cc = 4.5v 1, 2, 3 -55 t a 125 - 0.8 v output high voltage v oh i oh = -400 a v cc = 4.5v (note 2) 1, 2, 3 -55 t a 125 2.6 - v output low voltage v ol i oh = -400ma v cc = 4.5v (note 2) 1, 2, 3 -55 t a 125 - 0.4 v input leakage current i i v in = v cc or gnd v cc = 4.5v 1, 2, 3 -55 t a 125 -10 +10 a output leakage current i o v in = v cc or gnd v cc = 5.5v 1, 2, 3 -55 t a 125 -10 +10 a clock input high v ihc v cc = 5.5v 1, 2, 3 -55 t a 125 3.0 - v clock input low v ilc v cc = 4.5v 1, 2, 3 -55 t a 125 - 0.8 v standby power supply current i ccsb v in = v cc or gnd v cc = 5.5v, outputs open 1, 2, 3 -55 t a 125 - 500 a operating power supply supply current i ccop f = 20.0mhz v cc = 5.5v (note 3) 1, 2, 3 -55 t a 125 - 160.0 ma functional test ft (note 4) 7, 8 -55 t a 125 - - notes: 2. interchanging of force and sense conditions is permitted. 3. operating supply current is proportional to frequency, typical rating is 8.0ma/mhz. 4. tested as follows: f = 1mhz, v ih = 2.6, v il = 0.4, v oh 1.5v, v ol 1.5v, v ihc = 3.4v and v ilc = 0.4v. hsp43881/883
5 table 2. ac electrical performance specifications device guaranteed and 100% tested parameter symbol notes group a subgroup s temperature ( o c) -25 (25.6mhz) units min max clock period t cp note 5 9, 10, 11 -55 t a 125 39 - ns clock low t cl note 5 9, 10, 11 -55 t a 125 16 - ns clock high t ch note 5 9, 10, 11 -55 t a 125 16 - ns input setup t is note 5 9, 10, 11 -55 t a 125 17 - ns input hold t ih note 5 9, 10, 11 -55 t a 125 0 - ns clk to coefficient output delay t odc note 5 9, 10, 11 -55 t a 125 - 20 ns output enable delay t oed note 5 9, 10, 11 -55 t a 125 - 15 ns clk to sum output delay t ods note 5 9, 10, 11 -55 t a 125 - 25 ns note: 5. ac testing: v cc - 4.5v and 5.5v. inputs are driven at 3.0v for a logic ?1? and 0.0v for a logic ?0?. input and output timing measurements are made at 1.5v for both a logic ?1? an?). clk is driven at 4.0v and 0v and measured at 2.0v. table 3. ac electrical performance specifications parameter symbol test conditions notes temp ( o c) -25 (25.6mhz) units min max input capacitance c in vcc = open, f = 1mhz all measurements are referenced to device gnd 6t a = 25 - 15 pf output capacitance c out 6t a = 25 - 15 pf output disable delay t odd 6, 7 -55 t a 125 - 15 ns output rise time t or 6, 7 -55 t a 125 - 6 ns output fall time t of 6, 7 -55 t a 125 - 6 ns notes: 6. the parameters listed in table 3 are controlled via design or process parameters and are not di rectly tested. these parameter s are characterized upon initial design and after major process and/or design changes. 7. loading is as specified in the test load circuit, c l = 40pf. table 4. applicable subgroups conformance groups method subgroups initial test 100%/5004 - interim test 100%/5004 - pda 100% 1 final test 100% 2, 3, 8a, 8b, 10, 11 group a - 1, 2, 3, 7, 8a, 8b, 9, 10, 11 groups c and d samples/5005 1, 7, 9 hsp43881/883
6 burn-in circuit bottom view, pins up dcm1 sum23 sum22 sum21 sum18 sum14 sum13 sum11 sum9 v ss v cc sum20 sum17 sum16 sum7 adr0 sum5 sum4 adr2 dcm0 clk v ss cout0 shadd sum1 sum3 sum2 sum0 v cc v ss cin2 v cc cout3 cout4 align pin a b c d e f g h j k l 1234 567 891011 adr1 sum25 v cc v ss v ss v cc v ss senbh sum24 sum19 sum15 sum12 sum10 sum8 sum6 cin1 cin0 senbl cout1 v ss cout2 cout5 cout6 dienb din5 din4 cin5 cin3 v cc v ss din0 din3 din6 din7 v ss coenb v cc reset tcci v cc cin4 cin6 cin7 cienb din2 din1 erase cout7 tcs tcco hsp43881/883
7 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com die characteristics die dimensions: 328 mils x 283 mils x 1 mil metallization: type: si-al or si-ai-cu thickness: 8k ? glassivation type: nitrox silox thickness: 10k ? worst case current density: 1.2 x 10 5 a/cm 2 burn-in signals pga pin pin name burn-in signal pga pin pin name burn-in signal pga pin pin name burn-in signal pga pin pin name burn-in signal a1 v ss gnd c1 cout5 v cc /2 f10 v cc v cc k4 v cc v cc a2 coenb f10 c2 cout6 v cc /2 f11 v ss gnd k5 sum19 v cc /2 a3 v cc v cc c3 align nc g1 adr2 f2 k6 v ss gnd a4 reset f11 c5 dienb f10 g2 dcmo f5 k7 sum15 v cc /2 a5 din7 f8 c6 din5 f5 g3 clk f0 k8 sum12 v cc /2 a6 din6 f6 c7 din4 f4 g9 sum1 v cc /2 k9 sum10 v cc /2 a7 din3 f3 c10 cin5 f5 g10 sum3 v cc /2 k10 sum8 v cc /2 a8 din0 f0 c11 cin3 f3 g11 sum2 v cc /2 k11 sum6 v cc /2 a9 cin8/5cci f8 d1 cout3 v cc /2 h1 adr1 f1 l1 dcm1 f6 a10 v cc v cc d2 cout4 v cc /2 h2 adr0 f0 l2 sum23 v cc /2 a11 v ss gnd d10 cin2 f2 h10 sum5 v cc /2 l3 sum22 v cc /2 b1 v cc v cc d11 v cc v cc h11 sum4 v cc /2 l4 sum21 v cc /2 b2 cout7 v cc /2 e1 cout1 v cc /2 j1 v cc v cc l5 sum18 v cc /2 b3 cout8/tcc0 v cc /2 e2 v ss gnd j2 sum25 v cc /2 l6 sum14 v cc /2 b4 erase f10 e3 cout2 v cc /2 j5 sum20 v cc /2 l7 v cc v cc b5 din8/tcs f7 e9 cin1 f1 j6 sum17 v cc /2 l8 sum13 v cc /2 b6 din1 f1 e10 cin0 f0 j7 sum16 v cc /2 l9 v ss gnd b7 din2 f2 e11 senbl f10 j10 sum7 v cc /2 l10 sum11 v cc /2 b8 cienb f10 f1 v ss gnd j11 v ss gnd l11 sum9 v cc /2 b9 cin7 f7 f2 cout0 v cc /2 k1 senbh f10 b10 cin6 f6 f3 shadd f9 k2 sum24 v cc /2 b11 cin4 f4 f9 sum0 v cc /2 k3 v ss gnd notes: 8. v cc /2 (2.7 10% used for outputs only. 9. 47k ? ( 20%) resistor connected to all pins except v cc and gnd. 10. v cc = 5.5v 0.5v. 11. 0.1 f (minimum) capacitor between v cc and gnd per device. 12. f0 = 100khz 10%, f1 = f0/2, f2 = f1/2..., f11 = f10/2, 40% - 60% duty cycle. 13. input voltage limits: v il = 0.8v maximum, v ih = 4.5v 10%. hsp43881/883
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