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xrp9710 and XRP9711 dual 6a programmable power module january 2014 rev. 1.0.1 exar corporation www.exar.com 48720 kato road, fremont ca 94538, usa tel. +1 510 668 - 70 00 C fax. +1 510 668 - 70 01 general description the xrp9710 and XRP9711 are programmable step down power module s providing two 6a outputs. the module package contains the switching controller , p ower mosfets, inductors and support components. as a result, external components are minimal . a wide input voltage range (4.75v to 5.5v or 5.5v to 2 2 v) allows for single supply operation from standard power rails. the module s measure only 12x12x2. 75 mm maki ng it half the size of competing 12v capable 6amp modules. the 2.75mm height allow s them to be placed on the back of boards or under heat sinks where other solutions cannot, yet they contain two full 6a buck power stages and two digital pulse width modula tor ( dpwm ) controllers with gate drivers . designed to operate at a constant pwm switching frequency between 500khz and 750khz, the d igital pulse frequency mode (dpfm) results in better than 80% efficiency at light load current s and low operating current allow for portable and energy star compliant applications. each xrp9710 or XRP9711 output can be individually programmed to as low as 0.6v with a resolution as fine as 2.5mv, and configurable for precise soft start and soft stop sequencing, including delay and ramp control. the xrp9710 /1 is fully controlled via a smbus - compliant i 2 c interface allowing for advanced local and/or remote reconfiguration, full performance monitoring and reporting as well as fault handling. built - in ou tput over - voltage, over - temperature, over - current and under voltage lockout protections insure safe operation under abnormal operating conditions. the xrp9710 /1 is offered in a rohs compliant, halogen - free lga package. features ? xrp9710 C dual 6a outputs w ith differential sensing ? XRP9711 C dual 6a outputs with control for two external power stages ? 12 x 12 x 2.75mm lga package ? wide input voltage range : 4.75v to 22v ? low range: 4.75v to 5 .5 v ? high range: 5.5v - 2 2 v ? output voltage range: 0.6v to 5.5v ? smbus compliant - i 2 c interface ? full power monitoring and reporting ? 3 x 15v capable psio s + 2 x gpios ? full start/stop sequencing support ? built - in thermal, over - current, uvlo and output over - voltage protections ? on - board 5v standby ldo ? on - board non - volatile m emory ? cispr22 level b radiated emissions ? powerarchitect? 5 .1 or later design tool applications ? servers ? base stations ? switches/routers ? broadcast equipment ? industrial control systems ? automatic test equipment ? video surveillance systems
xrp9710 and XRP9711 dual 6a programmable power module january 2014 rev. 1.0.1 exar corporation www.exar.com 48720 kato road, fremont ca 94538, usa tel. +1 510 668 - 70 00 C fax. +1 510 668 - 70 01 typical application diagram xrp9710 vcc ldo5 enable gpio0 sda scl gpio1 vout4- agnd (dap) pgnd3 pvout3 cout cout lx3 lx4 cin 1uf psio0 psio1 psio3 load vout4+ load vout3+ vout3- pvout4 pgnd4 pvin figure 1 xrp9710 application diagram with differential voltage sensing XRP9711 gl_rtn1 gl1 lx1 gh1 vcc ldo5 bst1 gl_rtn2 gl2 lx2 gh2 bst2 + + vout2 vin + + vout1 vin enable gpio0 sda scl gpio1 vout1 vout2 vout3 vout4 agnd (dap) pvin pgnd3 pvout3 vout3 cout cout vout4 lx3 lx4 cin 1uf psio0 psio1 psio3 pvout4 pgnd4 figure 2 xrp971 1 application diagram
xrp9710 and XRP9711 dual 6a programmable power module ? 2013 exar corporation confidential 3 / 36 rev. a0.0.5 features and benefit s worlds smallest 12v capable dual 6a module at 12x12x2.75mm programmable power benefits ? fully configurable ? output set point ? feedback compensation ? frequency set point ? under voltage lock out ? input voltage measurement ? gate drive dead time ? reduced development time ? configurable and re - configurable for different vout, iout, cout, and inductor values ? no need to change external p assives for a new output specification. ? higher integration and reliability ? lowest component count for a fully configurable module powerarchitect? 5 design and configuration software ? wizard quickly generates a base design ? calculates all configuration regist ers ? projects can be saved and/or recalled ? gpios can be configured easily and intuitively ? dashboard interface can be used for real - time monitoring and debug system benefits ? reliability is enhanced via communication with the system controller which can obt ain real - time data on an output voltage, input voltage and current. ? system processors can communicate with the xrp9710/1 directly to obtain data or make adjustments to react to circuit conditions ? system l og ging and history, diagnostics and remote reconfigu rability . system integration capabilities ? single supply operation ? i 2 c interface allows: ? communication with a system controller or other power management devices for optimized system functionality ? access to modify or read internal registers that control or monitor: ? output current ? input and output voltage ? soft - start/soft - stop time ? power good ? part temperature ? enable/disable outputs ? over current ? over voltage ? temperature faults ? adjusting fault limits and disabling/enabling faults ? packet error checking (pec) on i 2 c communication ? 5 gpio pins with a wide range of configurability ? fault reporting (including uvlo warn/fault, ocp warn/fault, ovp, temperature, soft - start in progress, power good, system reset) ? allows a logic level interface with other non - digital ics o r as logic inputs to other devices ? frequency and synchronization capability ? selectable switching frequency between 124khz and 1.23mhz (500khz to 750khz internal power stages) ? main oscillator clock and dpwm clock can be synchronized to external sources ? inte rnal mosfet drivers (XRP9711) ? internal fet drivers (4/2) per channel ? built - in automatic dead - time adjustment ? 17ns rise and 11ns fall times
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 4 / 36 rev. 1.0.1 absolute maximum rat ings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ldo 5 , gl x , vout x .................................... - 0.3v to 7 .0v en able .................................................... - 0.3v to 7 .0v gpio0/1, scl, sda ............................................... 6.0v psio inputs ........................................................... 18v v cc ....................................................................... 28v lx x .............................................................. - 1v to 28v bstx, ghx .................................................... vlxx + 6v storage temperature .............................. - 65c to 150c power dissipation ................................ internally limited lead temperature (soldering, 10 sec) ................... 2 45 c esd rating (hbm - human body model) .................... 2kv operating ratings input voltage range v cc ............................... 5.5v to 25 v pvin voltage range ....................................... 3.0 to 2 2 v input voltage range v cc = ldo5 ................ 4.75v to 5.5 v vout1, 2, 3, 4 ...................................................... 5.5v juncti on temperature range .................... - 40c to 125 c package power dissipation max at 25c .................. 5.5w jedec 51 - 2a package thermal resistance ja ........ 1 8 c/w complies with cispr22 ....................................... level b electrical specifica tions specifications with standard type are for an operating junction temperature of t j = 25c only; limits applying over the full operating junction temperature range are denoted by a ?. typical values represent the most likely parametric norm at t j = 25c, and are provided for reference purposes only. unless otherwise indicated, v cc = 5.5 v to 2 2 v . q uiescent c urrent parameter min. typ. max. units conditions v cc supply current in shutdown 10 20 a en = 0v, v cc = 12v enable turn on threshold 0 .82 0.95 v v cc = 12v enable rising enable pin leakage current 10 ua en=5v - 10 en=0v v cc supply current in standby 440 600 a a ll channels disabled gpios programmed as inputs v cc =12v,en = 5v v cc supply current 2ch pfm 3.1 ma 2 channels on set at 5v, vout forced to 5.1v, no load, non - switching, ultra - sonic off, v cc =12 v, no i 2 c activity. v cc supply current 4ch pfm 4.0 ma 4 channels on set at 5v, vout forced to 5.1v, no load, non - switching, ultra - sonic off, v cc =12v , no i 2 c activity. v cc supply current on 18 ma all channels enabled, fsw =600khz, gate drivers unloaded , no i 2 c activity. i nput v oltage r ange and u ndervoltage l ockout parameter min. typ. max. units conditions v cc range 5.5 25 v ? 4.75 5.5 v ? with v cc connected to ldo5 pvin range 3.0 2 2 v ?
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 5 / 36 rev. 1.0.1 v oltage f eedback a ccuracy and o utput v oltage s et p oint r esolution parameter min. typ. max. units conditions vout regulation accuracy low output range 0.6v to 1.6v pwm operation - 5 5 mv 0.6 vout 1. 6 v - 20 20 mv ? - 7.5 7.5 mv 0.6 vout 1.6v v cc =ldo5 - 22.5 2 2.5 mv ? vout regulation accuracy mid output range 0.6v to 3.2 v pwm operation - 15 15 mv 0.6 vout 3.2 v - 45 45 mv ? - 20 20 mv 0.6 vout 3.2 v v cc =ldo5 - 50 50 mv ? vout regulation accuracy high output range 0.6v to 5.5v pwm operation - 30 30 mv 0.6 vout 5.5v - 90 90 mv ? - 40 40 mv 0.6 vout 4.2v v cc =ldo5 - 100 100 mv ? vout r egulation r ange 0.6 5.5 v ? without external divider network vout native set point r esolution 12.5 25 50 mv low range mid range high range vout fine set point resolution 1 2.5 5 10 mv low range mid range high range vout input resistance 120 90 75 k ? low range mid range high range vout input resistance in pfm operation 10 1 0.67 m ? low range mid range high range power good and ovp set point range ( from set point ) - 155 - 310 - 620 1 57.5 31 5 6 3 0 mv low range mid range high range power good and ovp set point accuracy - 5 - 10 - 20 5 10 20 mv low range mid range high range note 1: fine set point resolution not available in pfm
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 6 / 36 rev. 1.0.1 c urrent and aux adc (m onitoring adc s ) parameter min. typ. max. units conditions current sense accuracy - 3.75 1.25 3.75 m v low range ( 120mv) - 60mv applied - 10 10 mv ? - 5 2.5 5 m v high range ( 280mv ) - 150mv - 12.5 +12.5 mv ? current sense adc inl 0.4 lsb dnl 0.27 current limit set point resolution and current sense adc resolution 1.25 mv low range ( 120mv) 2.5 mv high range ( 280mv ) current sense adc range - 120 20 mv low range ( 120mv) - 280 40 high range ( 280mv ) vout adc resolution 15 30 60 mv low range mid range high range vout adc accuracy - 1 1 lsb v cc adc range 4.6 25 v note 2 uvlo warn set 4.4 4. 72 v uvlo warn set point 4.6v, v cc =ldo5 uvlo warn clear 4.4 4.72 v uvlo warn set point 4.6v, v cc =ldo5 v cc adc resolution 200 mv v cc adc accuracy - 1 1 lsb v cc < = 20v die temp adc resolution 5 c die temp adc range - 44 156 c output value is in kelvin note 2: although range of v cc adc is technically 0v to 25v, below 4. 55 the ldo5 hardware uvlo may have tripped. l inear r egulator parameter min. typ. max. units conditions ldo5 output voltage 4.85 5.0 5.15 v ? 5.5 v v cc 25 v 0ma < i ldo 5 out < 13 0ma ldo5 current limit 135 155 180 ma ? ldo5 fault set ldo5 uvlo 4.74 v ? v cc rising ldo5 pgood hysteresis 375 mv v cc falling maximum total ldo loading during enable start - up 30 ma enable transition from logic low to high. once ldo5 in regulation above limits apply.
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 7 / 36 rev. 1.0.1 pwm g enerators and o scillator parameter min. typ. max. units conditions switching frequency ( fsw ) range , channels 1 and 2 124 1230 khz see applications information switching frequency ( fsw ) range, channels 3 and 4 500 750 khz fsw accuracy C 5 5 % clock in synchronization frequency 20 25.7 3 1 mhz when synchronizing to an external clock (range 1) clock in synchronization frequency 10 12.8 15. 5 mhz when synchronizing to an external clock (range 2) gpio s 3 parameter min. typ. max. units conditions i nput pin low level 0.8 v input pin high level 2.0 v input pin leakage current 1 a output pin low level 0.4 v i sink = 1ma output pin high level 2.4 v i source = 1ma output pin high level 3.3 3.6 v i source = 0ma output pin high - z leakage current (gpio pins only) 10 a maximum sink current 1 ma open drain mode i/o frequency 30 mhz i/o configured for clock synchronization input or output note 3 : 3.3v cmos logic compatible , 5v tolerant . psio s 4 parameter min. typ. max. units conditions input pin low level 0.8 v input pin high level 2.0 v input pin leakage current 1 a output pin low level 0. 4 v i sink = 3ma output pin high level 15 v open drain. external pull - up resistor to user supply output pin high - z leakage current (p s io pins only) 10 a i/o frequency 5 mhz note 4 : 3.3v/5.0v cmos logic compatible, maximum rating of 15.0v
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 8 / 36 rev. 1.0.1 smb us (i 2 c) i nterface parameter min. typ. max. units conditions input pin low level, v il 0.3 v io v v io = 3.3 v 10% input pin high level, v ih 0.7 v io v v io = 3.3 v10% hysteresis of schmitt trigger inputs, v hys 0.05 v io v v io = 3.3 v10% output pin low level (open drain or collector), v ol 0.4 v i sink = 3ma input leakage current - 10 10 a input is between 0.1 vio and 0.9 v io output fall time from v ihmin to v ilmax 20 + 0.1 c b 250 ns w ith a bus capacitance (cb) from 10 pf to 400 pf internal pin capacitance 1 pf g ate d rivers parameter min. typ. max. units conditions gh, gl rise time 17 ns a t 10 - 90% of full scale, 1nf c load gh, gl fall time 11 n s gh, gl pull - u p on - state output resistance 4 5 ? gh, gl pull - d own on - state output resistance 2 2.5 ? gh, gl pull - down resistance in off - m ode 50 k ? v cc = vcc d = 0v. bootstrap diode forward resistance 9 ? @ 10ma minimum on time 50 ns 1nf of gate capacitance. minimum off time 125 ns 1nf of gate capacitance minimum programmable dead tim e 20 ns does not include dead time variation from driver output stage tsw=switching period maximum programmable dead time tsw programmable dead time adjustment step 60 7 ps
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 9 / 36 rev. 1.0.1 block diagram s bst3 gpio 0-1 channel 3 gh3 vcc gl3 lx3 pgnd3 ldo5 hybrid dpwm digital pid feedback adc v ref dac prescaler 1/2/4 ss & pd current adc dead time gate driver vout3+ mux vout3 vout4 vtj 5v ldo gpio i2c sda,scl nvm (flash) clock pwr good configuration registers fault handling otp uvlo ocp ovp logic psio 0-2 psio enable channel 4 sequencing internal por vcc 4ua + + pvin pvout3 vout3- vout4+ vout4- figure 3 xrp9710 block diagram
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 10/ 36 rev. 1.0.1 bst3 gpio 0-1 channel 3 gh3 vcc gl3 lx3 pgnd3 ldo5 hybrid dpwm digital pid feedback adc v ref dac prescaler 1/2/4 ss & pd current adc dead time gate driver vout3 mux vout3 vout4 vtj 5v ldo gpio i2c sda,scl nvm (flash) clock pwr good configuration registers fault handling otp uvlo ocp ovp logic psio 0-2 psio enable channel 4 sequencing internal por vcc 4ua + + pvin pvout3 vout4 bst1 channel 1 gh1 gl1 lx1 gl_rtn1 hybrid dpwm digital pid feedback adc v ref dac prescaler 1/2/4 ss & pd current adc dead time gate driver vout1 channel 2 vout2 vcc vout2 vout1 figure 4 xrp971 1 block diagram
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 11/ 36 rev. 1.0.1 xrp9710 pin assignment agnd vout3+ vout3- vout4- gpio0 gpio1 nc nc nc nc nc nc nc nc nc scl psio1 psio2 psio0 v cc enable 31 vout4+ sda nc 1 2 3 4 5 6 7 8 9 10 11 12 23 22 21 20 19 18 17 16 15 43 42 34 13 14 agnd 30 29 25 24 26 38 37 40 44 39 36 35 33 32 28 27 41 45 pvout3 pvout3 pgnd3 pvin pvin lx3 lx3 pvin pvin pgnd4 lx4 agnd agnd lx4 pvout4 lx4 pvout4 lx3 agnd ldo5 figure 5 xrp971 0 pin assignment , top view
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 12/ 36 rev. 1.0.1 xrp9710 pin description pin # name description 1 - 10 nc no connect 11 enable enable. if enable is pulled high or allowed to float high, the chip is powered up. the pin must be held low for the xrp9710 to be placed into shutdown. 12 v cc controller supply voltage. place a decoupling capacitor close to the controller ic. this input is used in uvlo fault generation. 13 agnd analog ground. this is the small signal ground connection. 14 agnd analog ground. this is the small signal ground connection. 15 vout 3+ feedback pin. positive input of remote sensing differential amplifier. connect to the remote voltage load, positive terminal. 16 vout 3 - feedback pin. negative input of remote sensing differential amplifier. connect to the remote voltage load, negative te rminal. 17 vout 4+ feedback pin. positive input of remote sensing differential amplifier. connect to the remote voltage load, positive terminal. 18 vout 4 - feedback pin. negative input of remote sensing differential amplifier. connect to the remote voltage load, negative terminal. 19 gpio0 i/o logic signal. can be configured as input or output. 20 gpio1 i/o logic signal. can be configured as input or output. 21 sda i 2 c data . smbus/i 2 c serial interface communication. 22 scl i 2 c clock. smbus/i 2 c serial interface communication. 23 psio0 i/o logic signal , hv. open drain , h i gh v oltage compliant. can be configured as input or output. 24 pvout3 channel output power . output voltage for the internal channel. 25 pvout3 channel output power . output voltage for the internal channel. 26 pgnd3 channel output ground. output ground for the internal channel. 27 pvin channel input power. internally connected to drain of upper switching mosfet 28 pvin channel input power. internally connected to drain of upper switching mosfet 29 lx3 switch node. switch node of the internal channel. 30 lx3 switch node. switch node of the internal channel. 31 lx3 switch node. switch node of the internal channel. 32 pvin channel input power. internally connected to drain of upper switching mosfet 33 pvin channel input power. internally connected to drain of upper switching mosfet 34 ldo 5 5v ldo output. used internally for power and may also be used for external power. ldo that can remain active while the rest of the ic is in standby mode. 35 agnd analog ground. this is the small signal ground connection. 36 agnd analog ground. this is the sma ll signal ground connection. 37 lx4 switch node. switch node of the internal channel. 38 pgnd4 channel output ground. output ground for the internal channel. 39 agnd analog ground. this is the small signal ground connection. 40 lx4 switch node. switch node of the internal channel. 41 pvout4 channel output power . output voltage for the internal channel. 42 psio1 i/o logic signal , hv. open drain , h i gh v oltage compliant. can be configured as input or output. 43 ps io 2 i/o logic signal , hv. open drain , h i gh v oltage compliant. can be configured as input or output. 44 lx4 switch node. switch node of the internal channel. 45 pvout4 channel output power . output voltage for the internal channel.
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 13/ 36 rev. 1.0.1 XRP9711 pin assignment agnd vout1 vout2 vout4 gpio0 gpio1 gl2 lx2 gh2 bst2 gl_rtn1 gl1 lx1 gh1 bst1 scl psio1 psio2 psio0 v cc enable 31 vout3 sda gl_rtn2 1 2 3 4 5 6 7 8 9 10 11 12 23 22 21 20 19 18 17 16 15 43 42 34 13 14 agnd 30 29 25 24 26 38 37 40 44 39 36 35 33 32 28 27 41 45 pvout3 pvout3 pgnd3 pvin pvin lx3 lx3 pvin pvin pgnd4 lx4 agnd agnd lx4 pvout4 lx4 pvout4 lx3 agnd ldo5 figure 6 xrp971 1 pin assignment , top view
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 14/ 36 rev. 1.0.1 XRP9711 pin description pin # name description 1 bst 2 boost pin. high side driver supply in put . 2 gh 2 high side gate drive out . connect directly to the gate of an external n - channel mosfet. 3 lx 2 switch node. return for the high - side gate driver. connect directly to the drain of the lower fet . also used to measure voltage drop across bottom mosfets 4 gl 2 low side gate drive out . connect directly to the gate of an external n - channel mosfet. 5 gl_rtn2 low side gate drive return . this should be routed as a differential trace with gl. connect to the source of the low side mosfet. 6 bst1 boost pin. high side driver supply input. 7 gh1 high side gate drive out . connect directly to the gate of an external n - channel mosfet. 8 lx1 switch node. return for the high - side gate driver. connect directly to the drain of the lower fet. also used to measure voltage drop across bottom mosfets 9 gl1 low side gate drive out . connect directly to the gate of an external n - channel mosfet. 10 gl_rtn1 low side gate drive return . this should be routed as a differential trace with gl. connect to the source of the low side mosfet. 11 enable enable. if enable is pulled high or allowed to float high, the chip is powered up. the pin must be held low for the xrp971 1 to be placed into shutdown. 12 v cc controller supply voltage. place a decoupling capacitor close to the controller ic. this input is used in uvlo fault generation. 13 agnd analog ground. this is the small signal ground connection. 14 agnd analog ground. this is the small signal ground connection. 15 vout 1 feedback pin. connect to the output of the corresponding power stage 16 vout 2 feedback pin. connect to the output of the corresponding power stage 17 vout 3 feedback pin. connect to the output of the corresponding power stage 18 vout 4 feedback pin. connect to the output of the corresponding power stage 19 gpio0 i/o logic signal. c an be configured as input or output . 20 gpio1 i/o logic signal. can be configured as input or output. 21 sda i 2 c data . smbus/i 2 c serial interface communication. 22 scl i 2 c clock. smbus/i 2 c serial interface communication. 23 psio0 i/o logic signal , hv. open drain , h i gh v oltage compliant. can be configured as input or output. 24 pvout3 channel output power . output voltage for the internal channel. 25 pvout3 channel output power . output voltage for the internal channel. 26 pgnd3 channel output ground. output ground for the internal channel. 27 pvin channel input power. internally connected to drain of upper switching mosfet 28 pvin channel input power. internally connected to drain of upper switching mosfet 29 lx3 switch node. switch node of the internal channel. 30 lx3 switch node. switch node of the internal channel. 31 lx3 switch node. switch node of the internal channel. 32 pvin channel input power. internally connected to drain of upper switching mosfet 33 pvin channel input power. internally connected to drain of upper switching mosfet 34 ldo 5 5v ldo output. used internally for power and may also be used for external power. ldo that can remain active while the rest of the ic is in standby mode. 35 agnd analog ground. this is the small signal ground connection. 36 agnd analog ground. this is the small signal ground connection. 37 lx4 switch node. switch node of the internal channel. 38 pgnd4 channel output ground. output ground for the internal channel. 39 agnd analog ground. this is the small signal ground connection. 40 lx4 switch node. switch node of the internal channel. 41 pvout4 channel output power . output voltage for the internal channel.
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 15/ 36 rev. 1.0.1 pin # name description 42 psio1 i/o logic signal , hv. open drain , h i gh v oltage compliant. can be configured as input or output. 43 ps io 2 i/o logic signal , hv. open drain , h i gh v oltage compliant. can be configured as input or output. 44 lx4 switch node. switch node of the internal channel. 45 pvout4 channel output power . output voltage for the internal channel. ordering information part number temperature range marking package packing quantity note 1 i 2 c default address xrp9710e y - f - 40c t j +12 5c 9710ey fwwyy lot # 12x12mm lga tray halogen free 0x28 (7bit) xrp9710e y tr - f 2.5 k/tape & reel XRP9711e y - f 9711e y fwwyy lot # tray XRP9711e y tr - f 2.5 k/tape & reel xrp9710evb - demo - 1 - kit evaluation kit includes xrp9710evb - demo - 1 evaluation board with power architect software and controller board XRP9711evb - demo - 1 - kit evaluation kit includes XRP9711evb - demo - 1 evaluation board with power architect software and controller board f denotes - f part number suffix C yy = year C ww = work week
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 16/ 36 rev. 1.0.1 typical performance characteristics all data taken at v cc = 12v , t j = t a = 2 5c, unless otherwise specified - schematic and bom from xrp971 1 evb. see xrp971 1 evb - demo - 1 manual. fig ure 7 pfm to pwm transition fig ure 8 pwm to pf m transition fig ure 9 0 - 6a transient 300khz pwm only fig ure 10 0 - 6a transient 300khz with ovs 5.5% fig ure 1 1 sequential start - up fig ure 1 2 sequential shut down
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 17/ 36 rev. 1.0.1 fig ure 1 3 simultaneous start - up fig ure1 4 simultaneous shut down fig ure1 5 pfm zero current accuracy fig ure1 6 ldo5 brown out recovery, no load fig ure 17 enable threshold over temp fig ure 1 8 package thermal derating 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 - 40 c 25 c 85 c 125 c vin=25v rising vin=25v falling vin=4.75 v rising vin=4.75 v falling vcc vcc vcc vcc
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 18/ 36 rev. 1.0.1 figure 19 vin = 5v power dissipation fig ure 20 vin = 12v power dissipation fig ure 21 efficiency, 12v in , 600khz 0.0 0.5 1.0 1.5 2.0 0 1 2 3 4 5 6 power dissipation (w) io (a) 3.3 1.8 1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 1 2 3 4 5 6 power dissipation (w) io (a) 5.0 3.3 1.8 1.0
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 19/ 36 rev. 1.0.1 functional overview the xrp9710 is a digital pulse width modulation (dpwm) power module with two 6a converter s . in addition, the XRP9711 provides two additional pwm controller outputs which can directly drive external power stage . each output voltage can be programmed from 0.6v to 5.5v without the need f or an external voltage divider. the wide range of programmable dp wm switching frequenc ies (from 124 khz to 1.2 3 mhz) enables the user to optimize for efficiency or component sizes. since t he digital regulation loop requires no external pa ssive components, loop performance is not compromised due to external component variation or operating condition s . the xrp9710 /1 provides a number of critical safety features, such as over - current protection (ocp), over - voltage protection (ovp), over - tempe rature protection (otp) plus input under - voltage lock o ut (uvlo). in addition, a number of key health monitoring features including warning level flags for the safety functions, power good ( pgood ), plus full monitoring of system voltages and currents. the a bove are all programmable and/or readable from the smbus and many are steerable to the gpios for hardware monitoring. for hardware communication, the xrp9710 /1 has two logic level general purpose input - output (gpio) pins and three, 15v, open - drain, power s ystem input - output (psio) pins. two pins are dedicated to the smbus data (sda) and clock (scl). the 5v ldo is used for internal power and is also optionally available to power external circuitry. the primary benefit of these modules is the ultra small footprint and height , b ut these come with a full suite of advanced power management capabilities. all outputs are independently programmable which provides the user full control of the d elay, r amp rate , and s equence during power up and power down . the use r may also control how the outputs interact and power down in the event of a fault. this includes active ramp down of the output voltages to take down an output voltage as quickly as possible. another useful feature is that the outputs can be defined and controlled as groups. the xrp9710 /1 has two main types of programmable memory. the first type is runtime registers that contain configuration, control and monitoring information for the chip. the second type is rewritable non - volatile flash memory (nv fm ) t hat is used for permanent storage of the configuration data along with various chip internal functions . during power up , the run time registers are loaded from the nv f m allowing for standalone operation . t he xrp9710 /1 bring s an extreme ly high level of func tionality and performance to a programmable power system . ever decreasing product budgets require the designer to quickly analyze cost/performance tradeoff s to be truly successful. by incorporating four switching channels, a user ldo, and internal gate drivers, all in a single package, the xrp9710 /1 allows for extremely cost effective power system designs. another key cost factor that is often overlooked is the unanticipated engineering change order (eco). the programmable versatility of t he xrp9710 /1 , along with the lack of hard wired , on board configuration components, allows for minor and major changes to be made on the board by simple reprogramming .
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 20/ 36 rev. 1.0.1 theory of operation c hip a rchitecture r egulation l oops error amp afe adc error register pid dpwm gate driver vref dac scalar 1,2,4 pfm / ultrasonic vin feed forward ghx glx lxx pwm - pfm sel current adc window comp. ovs vfb (voutx) vin (vcc) vdrive (vccd)x fine adjust afe figure 22 xrp9710 regulation loops figure 22 shows a functional block diagram of the regulation loops for an output channel. there are four separate parallel control loops; pulse width modulation (pwm), pulse frequency modulation (pfm), ultrasonic, and over sampling (ovs). each of these loops is fed by the analog front end (afe) as shown at the left of the diagram. the afe consist of an input voltage scal e r, a program m able voltage reference (vref) dac, error am plifier, and a window comparator. ( please not e that the block diagram shown is simplified for ease of understanding. some of the function al blocks are common and shared by each channel by means of a multiplexer . ) pwm loop the pwm loop operates in voltage c ontrol mode (vcm) with optional v in feed forward based on the voltage at the v cc pin . the reference voltage (vref) for t he error amp is generated by a 0.15 v to 1.6v dac that has a 12.5mv resolution. in order to provide a full 0.6v to 5.5v output voltage ra nge , an input scal e r is used to reduce feedback voltages for higher output voltages to bring them within the 0.15 v to 1.6v control range. so for output voltages up to 1.6v (low range) the scal e r has a gain of 1. for output voltages from 1.6v to 3. 2v (mid r ange) the scal e r gain is 1/2 and for voltages greater than 3. 2v (high range) the gain is 1/4 . this results in the low range having a reference voltage resolution of 12.5mv, the mid range having a resolution of 25mv and the high range having a resolution of 50mv. the error amp has a gain of 4 and compares the output voltage of the scal e r to vref to create an error voltage on its output. this is converted to a digital error term by the afe adc and is stored in the erro r register. the error register has a fine adjust function that can be used to improve the output voltage set point resolution by a factor of 5 resulting in a low range resolution of 2.5mv, a mid range resolution of 5mv and a high range resolution of 10 mv. the output of the error register is then used by the p roportional i ntegral d erivative (pid) controller to manage the loop dynamics . the xrp9710 /1 pid is a 17 - bit five - coefficient control engine that calculates the required duty cycle under the various ope rating conditions and feeds it to the digital pulse width modulator (dpwm). besides the normal
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 21/ 36 rev. 1.0.1 coefficients the pid also uses the v in voltage to provide a feed forward function. the xrp9710 /1 dpwm includes a special delay timing loop that provides a timing resolution that is 16 times the master oscillator frequency (103mhz) for a timing resolution of 60 7 p s for both the driver pulse width and dead time delays . the dwpm produces the gate high (gh) and gate low (gl) signals for the driver. the maximu m and minimum on - times and dead time delays are programmable by configuration resisters. to provide current information, t he o utput inductor current is measured by a differential amplifier that reads the voltage drop across the r ds of the lower fet during its on time. there are two selectable ranges, a low range with a gain of 8 for a +20mv to - 1 2 0 mv range , and a high range with a gain of 4 for a +40mv to - 2 80mv range . the optimum range to use will depend on the maximum output current and the r ds of the lower fet. the measure d voltage is then converted to a digital value by the current adc block. the resulting current value is stored in a readable register , and also used to determine when pwm to pfm transitions should occur . pfm mode loop the xrp 9710 /1 has a pfm loop that can be enabled to improve efficiency at light loads. by reducing switching frequency and operating in the discontinuous conduction mode (dcm), both switching and i 2 r losses are minimized . figure 23 shows a functional diagram of the pfm logic. # cycles reg default = 20 pfm current threshold reg a a xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 22/ 36 rev. 1.0.1 noise . the amplitude of the noise depend s m ain ly on the board design and on the manufacturer and construction details of the components. proper selection of components can reduce the sound to very low levels. in general ultrasonic mode is not used unless required as it reduces light load efficiency. ultrasonic mode ultrasonic mode is an extension of pfm to ensure that the switching frequency never enters the audible range. when this mode is entered , the switching frequency is set to 30 k h z and the duty cycle of the upper and lower fet s , which are fixed in pfm mode , ar e decrease d as required to keep the output voltage in regulation while maintaining the 30khz switching frequency . under extremely light or zero load currents , the gh on time pulse width can decrease to its minimum width. when this happens, the lower fet on time is increased slightly to allow a small amount of reverse inductor current to flow back in to v in to keep the output voltage in regulation while maintaining the switching frequency above the audio r ange. oversampling ovs mode oversampling (ovs) mode is a feature added to the XRP9711 to improve transient response for the two external channels . this mode can only be enabled when the channel switching freq uency is operating in 1x frequency mode. in ovs mode the output voltage is sampled four times per switching cycle and is monitored by the afe window comparator s . if the voltage goes outside the set high or low limits, the ovs control electronics can immediately modify the pulse width of the gh or gl dr iver s to respond accordingly , without having to wait for the next cycle to start. ovs has two types of response depending on whether the high limit is exceeded during an unloading transient ( o ver voltage) , or the low limit is exceeded during a loading tran sient ( u nder v oltage). under voltage ovs: if there is an increasing current load step, the output voltage will drop until the regulator loop adapts to the new conditions to return the voltage to the correct level. depending on where in the switching cy cle the load step happens there can be a delay of up to one switching cycle before the control loop can respond. with ovs enabled if the output voltage drops below the lower level, an immediate gh pulse will be generated and sent to the driver to increase the output inductor current toward the new load level without having to wait for the next cycle to begin. if the output voltage is still below the lower limit at the beginning of the next cycle , ovs will work in conjunction with the pid to inse rt additional gh pulse s to quickly return the output voltage back within its regulation band. the result of this system is transient response capabilities on par or exceeding those of a constant on - time control loop. over voltage ovs: when there is a step load current decrease, the output voltage will increase (bump up) as the excess inductor current that is no longer used by the load flows into the output capacitor s causing the output voltage to rise . the voltage will continue to rise until the inductor c urrent decreases to the new load current. with ovs enabled , if the output voltage exceeds the high limit of the window comparator, a blanking pulse is generated to truncate the gh signal . this causes inductor current to immediately begin decreasing to the new load level. the gh signal will continue to be blanked until the output voltage falls below the high limit. again, since the output voltage is sampled at four times the switching frequency, over shoot will be decreased and the time required to get back into the regulation band is also decreased. ovs can be used in conjunction with both the pwm and pfm operating modes. when it is activated it can noticeably decrease output voltage excursions when transitioning between pwm and pfm modes .
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 23/ 36 rev. 1.0.1 ldo s the xrp9710 /1 has an internal low drop - out (ldo) linear regulator that generate s 5.0v (ldo5 ) for both internal and external use. ldo5 is the main power input to the device and is supplied by an external 5.5v to 25v v cc supply. the 5v output is used by th e xrp9710 /1 as a standby power supply and supply power to the 5v gate drivers. the total output current that the 5v ldo can provide is 130ma. the xrp9710 /1 consumes approximately 20ma and the rest is the gate drive currents. during initial power up, the m aximum external load should be limited to 30ma. for operation with a v cc of 4.75v to 5.5v, the ldo5 output needs to be connected directly to v cc on the board . c locks and t iming pll x4/x reg ext clock input gpio0 ? figure 24 xrp9710 timing block diagram figure 24 shows a simplified block d iagram of the xrp9710 /1 timing. again, p lease note that the function blocks and signal names used are chosen for ease of understanding and do not necessarily reflect the actual desi gn. the system timing is generated by a 103mhz internal system clock (sys_clk). there are two ways that the 103mhz system clock can be generated. these include an internal oscillator and a phase locked loop (pll) that is synchronized to an external clock input . the basic timing architecture is to divide the sys_clk down to create a fundamental switching frequency (fsw_fund) for all the output channels that is settable from 1 24 khz to 306kh z. the switching frequency for a channel (fsw_chx) can then be selected as 1 time, 2 times or 4 times the fundamental switching frequency . to set the base frequency for the output channels , an fsw_set value representing the base frequency shown in table 1 , is entered into the switching frequency configuration register . note that fsw_set value is basically equal to the sys_clk divided by the base frequency. the system timing is then created by dividing down sys_clk to produce a base frequen cy clock, 2x and 4x times the base frequency clocks, and sequencing timing to position the output channels relative to each other. each output channel then has its own frequency multiplier register that is used to select its final output switching frequenc y. table 1 shows the available channel switching frequencies for the xrp9710 /1 device. the shaded areas show the allowable frequencies of the internal power stages. in practice the powerarchitect? 5 .1 (pa 5.1) design tool
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 24/ 36 rev. 1.0.1 handles all the details and the user only has to enter the fundamental switching frequency and the 1x, 2x, 4x frequency multiplier for each channel. if an external clock is used, the frequencies in this table will shift accordingly. base frequency khz available 2x frequencies khz availab le 4x frequencies khz 123.8 247.6 495.2 126.2 252.5 504.9 128.8 257.5 515.0 131.4 262.8 525.5 134.1 268.2 536.5 137.0 273.9 547.9 139.9 279.9 559.8 143.1 286.1 572.2 146.3 292.6 585.2 149.7 299.4 598.8 153.3 306.5 613.1 157.0 314.0 628.0 160.9 321.9 643.8 165.1 330.1 660.3 169.4 338.8 677.6 174.0 348.0 695.9 178.8 357.6 715.3 183.9 367.9 735.7 189.3 378.7 757.4 247.6 495.2 990.4 257.5 515.0 1030.0 268.2 536.5 1072.9 279.9 559.8 1119.6 292.6 585.2 1170.5 306.5 613.1 1226.2 table 1
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 25/ 36 rev. 1.0.1 s upervisory and c ontrol power system design with xrp9710 /1 is accomplished using pa 5.1 design tool. all figures referenced in the following sections are taken from pa 5 .1 . furthermore, the following sections reference i 2 c commands. for more information on these commands , refer to anp - 38. xrp9710/1 is supported with the commands listed in anp - 38 with the exception of xrp9710 using only the channel 3 and 4 related command s . d igital i/o xrp9710 /1 has two general purpose input output (gpio) and three power system input output (psio) user configurable pins. ? gpios are 3.3v cmos logic compatible and 5v tolerant. ? psio s which configured as outputs are open drain and require external pull - up resistor s . these i/os are 3.3v and 5v cmos logic compatible, and up to 15v capable. the polarit y of the gpio/psio pins is set in pa 5 .1 or with an i 2 c command. configuring gpio/psios the following functions can be controlled from or forwarded to any gpio/psio: ? general output C set with an i 2 c command ? general input C triggers an interrupt; state read with an i 2 c command ? power group enable C controls enabling and disabling of group 1 and group 2 . ? power channel enable C controls enabling and disabling of a n individual channel . ? i 2 c address bit C controls an i 2 c address bit . ? power ok C indicates that selected channels have reached their target levels and have not faulted . multiple channel selection is available , in which case the resulting signal is the and l ogic function of all channels selected . ? resetout C is delayed power ok. delay is programmable in 1msec increments with the range of 0 to 255 msecs . ? low vcc C indicates when vcc has fallen below the uvlo fault threshold and when the uvlo condition clears (v cc voltage rises above the uvlo warning level) . ? interrupt C the controller generated interrupt selection and clearing is done through i 2 c commands . interrupt, low vcc, power ok and resetout signals can only be forwarded to a single gpio/psio. in addition, the following are functions that are unique to gpio0 and gpio1.
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 26/ 36 rev. 1.0.1 ? hw flags C these are hardware monitoring functions forwarded to gpio0 only. the functions include under - voltage warning, over - temperature warning, over - voltage fault, over - current fault and over - current warning for every channel. multiple selection s will be combi ned using the or logic function . ? external clock - in C enables the controller to lock to an external clock including one from another xrp9710 /1 applied to the gpio0 pin. there are two ranges of clock frequencies the controller accepts, selectable by a user . ? hw power good C the power good hardware monitoring function. it can only be forwarded to gpio1. this is an output voltage monitoring function that is a hardware comparison of channel output vol tage against its user defined power good threshold limits (power good minimum and maximum levels). it has no hysteresis. multiple channel selection s will be combined using the and logic function of all channels selected . the power good minimum and maxi mum levels are expressed as percentages of the target voltage. pgood max is the upper window and pgood min is the lower window. the minimum and maximum for each of these values can be calculated with the following equation: ????? ( % ) = ? ? ??? ( ?? ) ? 10 5 ??????? ( ? ) where n=1 to 63 for the pgood max value and n=1 to 62 for the pgood min value. for example, with the target voltage of 1.5v and set point resolution of 2.5mv (lsb), the power good min and max values can range from 0. 17 % to 10.3 % and 0.17% to 10.5% respectively . a user can effectively double the range by changing to the next higher output voltage range setting, but at the expense of reduced set point resolution. ? external clock - out C clock sent out through gpio1 for sy nchronizing with another xrp9710 /1 (see the clock out section for more information). f ault h andling there are s ix different types of fault handling: ? under voltage lockout (uvlo) mo nitors voltage supplied to the vcc pin and will cause the controller to shut down
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 27/ 36 rev. 1.0.1 all channels if the supply drops to critical levels. ? over temperature protection (otp) monitors temperature of the chip and will cause the controller to shut down all channels if temperature rises to critical levels. ? over voltage protection (ovp) mon itors regulated voltage of a channel and will cause the controller to react in a user specified way if the regulated voltage surpasses threshold level. ? over current protection (ocp) monitors current of a channel and will cause the controller to react in a user specifi ed way if the current level surpasses threshold level. ? start - up time - out fault monitors whether a channel gets into regulation in a user defined time period ? ldo5 over current protection (ldo5 ocp) monitor s current drawn from the regulator and will cause the c ontroller to be res e t if the current exceeds ldo5 limit uvlo both uvlo warning and fault levels are user programmable and set at 200mv increments in pa 5 .1 . when the warning level is reached the controller will gener ate the uvlo_warning_event interrupt. in addition, the host can be informed about the event through hw flags on gpio0 (see the digital i/o section). when an under voltage fault condition occurs, the xrp9710 /1 outputs are shut down and the uvlo_fault_activ e_event interrupt is generated. in addition, the host can be informed by forwarding the low vcc signal to any gpio/psio (see the digital i/o section). this signal transitions when the uvlo fault occurs. when coming out of the fault, rising vcc crossing th e uvlo fault level will trigger the uvlo_fault_inactive_event interrupt. once the uvlo condition clears (vcc voltage rises a bove or to the user - defined uvlo warning level), the low vcc signal will transition and the controller will be reset. s pecial atten tion needs to be paid in the case when vcc = ldo5 = 4.75v to 5.5v. since the input voltage adc resolution is 200mv, the uvlo warning and fault set points are coarse for a 5v input. therefore, setting the warning level at 4.8v and the fault level at 4.6v ma y result in the outputs not being re - enable d until a full 5.0v is reached on vcc. setting the warning level to 4.6 v and the fault level at 4.4v would likely make uvlo handing as desired ; however, at a fault level below 4.6v the device has a hardware uvlo on ldo5 to ensure proper shutdown of the internal circuitry of the controller. this means the 4.4v uvlo fault level may never occur. otp user defined otp warning, fault and restart levels are set at 5c increment s in pa 5 .1 . when the warning level is reached the controller will generate the temp_warning_event interrupt. in addition, the host can be informed about the event through hw flags on gpio0 (see the digital i/o section). when an otp fault condition occurs, the xrp9710 /1 outputs are shut down and the temp_over_event interrupt is generated. once temperature reaches a user defined otp restart threshold level, the temp_under_event interrupt will be generated and the controlle r will reset. ovp a user defined ovp fault level is set in pa 5 .1 and is expressed in percentages of a regulated target voltage. resolution is the same as for the target voltage (expressed in percentages). the ovp minimum and maximum values are calcula ted
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 28/ 36 rev. 1.0.1 by the following equation where the range for n is 1 to 63 : ??? ( % ) = ? ? ??? ( ?? ) ? 10 5 ??????? ( ? ) when the ovp level is reached and the fault is generated, the host will be notified by the supply_fault_event interrupt generated by the controll er. the host then can use an i 2 c command to check which channel is at fault. in addition, ovp fault can be monitored through gpio0. a user can choose one of three options in response to an ovp event: shutdown the faulting channel, shut down faulting chann el and perform auto - restart of the channel, or restart the chip. in the case of shutting down the faulting channel and auto - restarting, the user has an option to specify startup timeout (the time in which the fault is validated) and hiccup timeout (the period after which the controller will try to restart the channel) periods in 1 msec increments with a maximum value of 255 msec. note: the channel fault action response is the same for an ovp or ocp event . ocp a user defined ocp fault level is set with 1 0 ma increments in pa 5 .1 . pa 5 .1 uses calculations to give the user the approximate dc output current entered in the current limit field . however the actual current limit trip value programmed into the part is limited to 280mv as defined in the ele ctrical characteristics. the maximum value the user can program is limited by rdson of the synchronous power fet and current monitoring adc range. for example, using a synchronous fet with r dson of 30m ? , and the wider adc range , the maximum current limit programmed would be: ??? ??? ( ? ) = 280 ?? 30 ? = 9. 33 ? the current is sampled approximately 30ns before the low side mosfet turns off, so the actual measured dc output current in this example would be 9.33a plus approximately half the inductor ripple. an ocp fault is considered to have occurred only if the fault threshold has been tripped in four consecutive switching cycles. when the switching frequency is set to the 4x multiplier, the current is sampled only every other cycle. as a result it can t ake as many as eight switching cycles for an over current event to
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 29/ 36 rev. 1.0.1 be detected. when operating in 4x mode an inductor with a soft saturation characteristic is recommended. when the ocp level is reached and the fault is generated, the host will be notified by the supply_fault_event interrupt generated by the controller. the host then can use an i 2 c command to check which channel is at fault. in addition, ocp fault s can be monitored through hw flags on gpio0. the host can also monitor the ocp warning flag through hw flags on gpio0. the ocp warning level is calculated by pa 5.1 as 85% of the ocp fault level. a user can choose one of three options in response to an ocp event: shutdown the faulting channel, shut down faulting channel and perfo rm auto - restart of the channel, or restart the chip. the output current reported by the xrp9710 /1 is processed through a seven sample median filter in order to reduce noise. the ocp limit is compared against unfiltered adc output. for the case of shut d own and a uto - restart channel , the user has an option to specify startup timeout (the time in which the fault is validated) and hiccup timeout (the period after which the controller will try to restart the channel) periods in 1 msec increments with a maximu m value of 255 msec. note: the channel fault action response is the same for an ovp or ocp event. start - up time - out fault a channel will be at startup timeout fault if it does not come - up in the time period specified in the startup timeout box . in addit ion, a channel is at startup timeout fault if its pre - bias configuration voltage is within a defined value too close to the target. when the fault is generated, the host will be notified by the supply_fault_event interrupt generated by the controller. the host then can use an i 2 c command to check which channel is at fault. ldo5 ocp when current is drawn from the ldo5 that exceeds the ldo5 current limit the controller will be reset . e xternal clock synchr onization xrp9710 /1 can be run off an external clock available in the system or another xrp9710 /1 . the external clock must be in the ranges of 10.9mhz to 14.7mhz or 21.8mhz to 29.6mhz. locking to the external clock is done through an internal phase lock loop (pll) . the ex ternal clock must be routed to gpio0. the gpio0 setting must reflect the range of the external clock applied to it: sys_clock/8 corresponds to the range of 10.9mhz to 14.7mhz while sys_clock/4 setting corresponds to the range of 21.8mhz to 29.6mhz. the fun ctionality is enabled in pa 5.1 by selecting external clock - in function under gpio0. for more details on how to monitor pll lock in - out, please contact exar or your local exar representative.
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 30/ 36 rev. 1.0.1 c lock o ut xrp9710 /1 can supply clock out to be used by anoth er xrp9710 /1 controller. the clock i s routed out through gpio1 and can be set to system clock divided by 8 (sys_clock/8) or system clock divided by 4 (sys_clock/4) frequencies. the functionality is enabled in pa 5.1 by selecting external clock - out function under gpio1. c hannel c ontrol channels can be controlled independently by any gpio/psio or i 2 c command. channels will start - up or shut - down following transitions of signals applied to gpio/psios set to control the channels. the control can always be over ridden with an i 2 c command. regardless of whether the channels are controlled independently or are in a group, the ramp rates will be followed as specified (see the power sequencing section). regulated voltages and voltage drops across the synchronous fet on each switching channel can be read back using i 2 c commands . the regulated voltage read back resolution is 15mv, 30mv and 60mv per lsb depending on the target voltage range. the voltage drop across synchronous fet read back resolution is 1.25mv and 2 .5mv per lsb depending on the range. through an i 2 c command the host can check the status of the channels; whether they are in regulation or at fault. regulated voltages can be dynamically changed on switching channels using i 2 c command s with r e solution of 2.5mv, 5mv and 10mv depending on the target voltage range (in pwm mode only). for more information on i 2 c commands please refer to anp - 38 or contact exar or your local exar representative. p ower s equencing all channels can be grouped together and wi ll start - up and shut - down in a user defined sequence. selecting none means the channel will not be assigned to any group and therefore will be controlled independently. group selection there are three groups: ? group 0 C is controlled by the chip enab le or an i 2 c command. channels assigned to this group will come up with the enable signal being high (plus additional delay needed to load configuration fr o m flash to run - time
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 31/ 36 rev. 1.0.1 registers) , and will go down with the enable signal being low. the control can always be overridden with an i 2 c command. since it is recommended to leave the enable pin floating in the applications when vcc = ldo5 = 4.75v to 5.5v, please contact exar for how to co nfigure the channels to come up at the power up in this scenario. ? group 1 C can be controlled by any gpio/psio or i 2 c command. channels assigned to this group will start - up or shut - down following transitions of a signal applied to the gpio/ psio set t o co n trol the group. the control can always be overridden with an i 2 c command. ? group 2 C can be controlled by any gpio/psio or i 2 c command. channels as signed to this group will start - up or shut - down following transitions of a signal applied to the gpio/psio set to control the group. the control can always be overridden with an i 2 c command. start - up for each channel within a group , a user can specify the following start - up characteristics: ? ramp rate C expressed in milliseconds per volt . ? order C position of a channel to come - up within the group ? wait pgood? C selecting this option for a channel means the next channel in the order will not start ramping - up until this channel reaches the target level and its power good flag is asserted. ? delay C an additional time delay a user can specify to postpone a channel start - up with respect to the previous channel in the order. the delay is expressed in milliseconds with a range of 0msec to 255msec. shut - down for each channel within a group a user can spec ify the following shut - down characteristics: ? ramp rate C expressed in milliseconds per volt . ? order C position of a channel to come - down within the group ? wait stop thresh ? C selecting this option for a channel means the next channel in the order will not s tart ramping - down until this channel reaches the stop threshold level. the stop threshold level is fixed at 600mv. ? delay C additional time delay a user can specify to postpone a channel shut - down with respect to the previous channel in the order. the delay is expressed in milliseconds with a range of 0msec to 255msec. m onitoring v cc and t emperature through i 2 c commands, the host can read back the voltage applied to the vcc pin and the die temperature respectively. the vcc read back resolution is 200mv per l sb; the die temperature read back resolution is 5c per lsb. for more on i 2 c commands please refer to anp - 38 . p rogramming xrp9710 /1 xrp9710 /1 is a flash based device which means its configuration can be programmed into flash nvm and re - programmed a number of times. programming of flash nvm is done through pa 5 .1 .
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 32/ 36 rev. 1.0.1 by clicking on the flash button , the user will start the programming seque nce of the design configuration into the flash nvm. after the programming sequence completes, the chip will reset (if a utomatically reset after flashing box is checked) and boot the design configuration from the flash. u sers who wish to create their own programming procedure so they can re - program flash in - circuit using their system software should contact exar for a list of needed i 2 c flash commands. xrp9710 the xrp9710 differs from the XRP9711 in that it eliminates the two external power stages but adds differential voltage sensing of the two remaining outputs. however, the two remaining channels remain designated 3 and 4. below in the pa 5.1 dashboard, one can see channels 1 and 2 grayed out when using a xrp9710. this methodology also ensures cod e development is easily ported between the two devices.
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 33/ 36 rev. 1.0.1 e nabling xrp9710 /1 xrp9710 /1 has a weak internal pull - up ensuring it becomes enabled as soon as internal voltage supplies have ramped up and are in regulation. driving the enable pin low externally will keep the controller in the shut - down mode. a simple open drain pull down is the recommended way to shut xrp9710 /1 down. if the enable pin is driven high externally to control xrp9710 /1 coming out of the shut - down mode, care must be taken to ensure the enable pin is driven high after vcc gets supplied to the controller. in the configuration when vcc = ldo5 = 4.75v to 5.5v, disabling the device by grounding the enable pin is not recommended. it is recommend ed to leav e the enable pin floating a nd plac e the controller in the standby mode instead in this scenario. the standby mode is defined as the state when all switching channels are disabled, all gpio/psios are programmed as inputs, and the system clock is disabled. in this state the device c onsumes 440ua typical ly . short duration enable pin toggled low short duration shutdown pulses to the enable pin of the xrp9710 /1 , which do not provide sufficient time for the ldo5 voltage to fall below 3.5v , can result in significant delay in re - enabling o f the device. some examples below show ldo5 and enable pins: no load on ldo5, blue trace. recovery time after the enable logic high is approximately 40ms. adding a 200 ohm load on ldo5 pulls the voltage below 3.5v and the restart is short. note that as v cc increases, the restart time falls as well. a 5.5v input voltage is shown as the worst case. since the enable pin has an internal current source, a simple open drain pull down is the recommended way to shut down the xrp9710 /1 . a diode in series with a resistor between the ldo5 and enable pins may offer a way to more quickly pull down the ldo5 output when the enable pin is pulled low.
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 34/ 36 rev. 1.0.1 application informat ion t hermal d esign proper thermal design is critical in controlling device temperatures and in achieving robust designs. there are a number of factors that affect the thermal performance. one key factor is the temperature rise of the devices in the package, which is a functi on of the thermal resistances of the devices inside the package and the power being dissipated (p diss ). the thermal resistance of the xrp9710/1 is shown in the operating ratings section of this datasheet. the jedec ja t hermal resistance provided is bas ed on tests that comply with the jesd51 - 2a integrated circuit thermal test method environmental conditions C natural convection standard. jesd51 - xx are a group of standards whose intent is to provide comparative data based on a standard test condition wh ich includes a defined board construction. since the actual board design in the final application will be different from the board defined in the standard, the thermal resistances in the final design may be different from those shown. the package thermal derating curve is shown in fig ure 1 8 . the total package power dissipation (p pkg ) is dependent on the final application design for channels three and four, and is the sum of the losses for the two channels. the power losses for a channel will depend mainly on the input voltage, output voltage, and output current. figure 1 9 and figure 20 show the power losses for input voltages of 5v and 12v respectively. first , determine the package power derating for a maximum ambient temperature (t amb ) us ing fig ure 1 8 . th en, based on the design input voltage, use fig ure s 1 9 or 20 accordingly. for example: consider a two channel design that has a t amb = 50c, v in = 12v, v out 3 = 1v, v out 4 = 3.3v. fig ure 1 8 show s p pkg max is 4.1 w atts at 50c. th e result is that the sum of th e power dissipation for both channels must be less than the 4.1w. fig ure 20 shows the power dissipation for v in = 12v designs. if the 1v output current is 6a , then its p diss is 2.1w. this leaves 2w for the 3.3v channel. the graph shows that at 2w the maximum 3.3v output current would be 4.7a. emi e missions the XRP9711 has been tested on the evaluation board and passes cispr22 level b radiated emissions. l ayout g uidelines re fer to application note anp - 32 practical layout gu idelines for power xr designs. these apply primarily to the two external power stages available on the XRP9711. also refer to the xrp9710 or XRP9711 evaluation board manual for specifics in grounding and heat sinking. b oard a ssembly detailed boards assembly information specifically to address the unique package requirement is available in an p - 45, lga module assembly application note .
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 35/ 36 rev. 1.0.1 package specificatio n 12mmx12 mm lga
xrp9710 and XRP9711 dual 6a programmable power module ? 2014 exar corporation 36/ 36 rev. 1.0.1 revision history revision date description 1.0.0 12/18/2013 initial release [ecn: 1352 - 06] 1.0.1 01/03/201 4 fix minor typographical items for consistency . formatting updates. [ecn: 140 2 - 03] 1.0.2 01/1 4 /2014 updated marking information in ordering table for further assistan ce email: customersupport@exar.com powertechsupport@exar.com exar technical documentation: http://www.exar.com/techdoc/default.aspx? e xar c orporation h eadquarters and s ales o ffices 48720 kato road fremont, ca 94538 C usa tel.: +1 (510) 668 - 7000 fax: +1 (510) 668 - 7030 www.exar.com notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no rep resentation that the circuits are free of patent infringement. charts and schedules contained herein are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage ha s been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited .

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