product brief preliminary chl8112a/b digital multi - phase buck controller trademarks and registered trademarks are the property of the respective owners. pb 0 0 12 rev. 0.0 4 , august 2 5 , 2010 page 1 of 2 one highwood drive, tewksbury, ma 01876 tel: +1( 978 ) - 640 - 0011 www.chilsemi.com ? 2010 chil semiconductor corp . all rights reserved features 5 - phase dual output pwm controller phases are flexibly assigned between loops 1 & 2 amd? svi/g34 & memory mpol modes dual ocp support for i - spike enhanced amd cpus smb_alert pin for servers pmbus address pin or variable gate drive (chl8112a) 2nd t emperature sense (chl8112b) overclocking & gaming mode with vmax setting switching frequency from 200khz to 1.2mhz per phase chil efficiency shaping features including variable gate drive (chl8112a only), dynamic phase control programmable 1 - phase or 2 - pha se for light loads and active diode emulation for very light loads chil adaptive transient algorithm (ata) on both loops minimizes output bulk capacitors and system cost designed for use with coupled inductors auto - phase detection with auto - compensation p er - loop fault protection: ovp, uvp, ocp, otp, cfp i2c/smbus/pmbus system interface for telemetry of temperature, voltage, current & power for both loops non - volatile memory (nvm) for custom configuration compatible with chil atl and 3.3v tri - state drivers +3.3v supply voltage; 0oc to 85oc ambient operation pb - free, rohs, 6x6 40 pin qfn package description the chl8112a/b are dual - loop digital multi - phase buck controllers that drive up to 5 phases. the chl8112a/b is fully amd? svi compliant on both loops an d provides a vtt tracking function for ddr memory. nvm storage saves pins and enables a small package size. the chl8112a/b includes the chil efficiency shaping technology to deliver exceptional efficiency at minimum cost across the entire load range. ch il variable gate drive optimizes the mosfet gate drive voltage as a function of real - time load current. chil dynamic phase control adds/drops active phases based upon load current. the chl8112a/b can be configured to enter 1 - phase operation and active diod e emulation mode automatically or by command. chils unique adaptive transient algorithm (ata), based on proprietary non - linear digital pwm algorithms, minimizes output bulk capacitors. in addition, a coupled inductor mode, with phases added/dropped in pa irs, enables further improvement in transient response and form factor. the i2c/pmbus interface can communicate with up to 16 chl8112a/b based vr loops. device configuration and fault parameters are easily defined using the chil intuitive power designer ( ipd) gui and stored in on - chip nvm. the chl8112a/b provides extensive ovp, uvp, ocp and otp fault protection and includes thermistor based temperature sensing with vrhot signal. the chl8112a/b also includes numerous features like register diagnostics for fast design cycles and platform differentiation, truly simplifying vrd design and enabling fastest time - to - market with its set - and - forget methodology. figure 1 . chl8112a & chl8112b packages applications amd? svi based syst ems ddr memory with vtt tracking overclocked & gaming platforms s m b _ d i o p w m 5 e n a b l e v r t n r c s m i s e n 5 i s e n 4 i s e n 3 v s e n s m b _ c l k p w m 4 v r _ r e a d y 1 / p w r g d 2 i r t n 3 i r t n 4 i r t n 5 r c s p t s e n v r _ h o t # 1 / v r h o t _ i c r i t # 2 p w m 3 s m b _ a l e r t # v 1 8 a r r e s v c c i s e n 2 i s e n 1 i r t n 1 i r t n 2 p w m 2 p w m 1 r c s m _ l 2 r c s p _ l 2 v a r _ g a t e _ p m _ a d d r ( c h l 8 1 1 2 a ) t s e n 2 ( c h l 8 1 1 2 b ) n c 1 / s v d 2 n c 1 / s v c 2 n c 1 / v f i x e n 2 v r _ r e a d y _ l 2 1 / p w r o k 2 v c c v i n s e n v r t n _ l 2 v s e n _ l 2 1 2 7 8 5 6 3 4 1 0 9 3 0 2 9 2 4 2 3 2 6 2 5 2 8 2 7 2 1 2 2 4 1 g n d c h l 8 1 1 2 a / b 4 0 p i n 6 x 6 q f n t o p v i e w 1 2 1 6 1 4 1 9 1 3 1 7 1 5 2 0 1 8 1 1 3 9 3 5 3 7 3 2 3 8 3 4 3 6 3 1 3 3 4 0 n o t e s 1 p i n d e f i n i t i o n i n m p o l m o d e 2 p i n d e f i n i t i o n i n a m d m o d e
product brief chl8112a/b digital multi - phase buck controller page 2 o f 2 pb00 12 rev. 0.0 4 , august 2 5 , 20 10 typical application s block diagrams ordering information chl8112 ? - ? ? ? ? ? package tape & reel qty part number qfn 3000 chl8112a - 00crt 1 qfn 3000 chl8112a - xxcrt 2 qf n 3000 chl8112b - 00crt 1 qfn 3000 chl8112b - xxcrt 2 notes 1. for unprogrammed/default parts, use configuration file 00. unprogrammed parts will not start up until programmed in order to insure a safe power up. 2. - xx indicates a customer specific configurat ion file t: tape & reel xx: configuration file operating tempera ture c: commercial standard range r : qfn package type r : qfn part a: chl8112a b: chl8112b + 3 . 3 v v _ c p u _ l 1 3 2 8 4 5 6 1 6 9 c h l 8 1 1 2 a 8 1 1 2 1 2 2 2 3 2 4 v i n s e n p w m 4 p w m 5 p w m 3 p w m 2 p w m 1 i s e n 5 v r _ r d y _ l 1 1 / p w r g d 2 v s e n v c c r r e s e n v 1 8 a v r t n i r t n 3 i s e n 4 2 1 3 9 i r t n 1 r c s p i r t n 2 r c s m i s e n 3 i s e n 2 i s e n 1 i r t n 4 + 1 2 v v f r o m s y s t e m l o a d r c s c c s r s e r i e s r s e r i e s r t h r v i n _ 1 r v i n _ 2 3 7 3 8 3 5 3 6 3 3 3 4 i r t n 5 2 5 3 1 3 2 1 0 v r _ r d y _ l 2 1 / p w r o k 2 t s e n r t h 2 7 g n d 4 0 h v c c l o g a t e h i g a t e v c c g n d p w m l v c c 1 2 v v b o o t s w i t c h v v _ v g d c h l 8 5 1 0 h v c c l o g a t e h i g a t e v c c g n d p w m l v c c 1 2 v v b o o t s w i t c h v v _ v g d c h l 8 5 1 0 h v c c l o g a t e h i g a t e v c c g n d p w m l v c c 1 2 v v b o o t s w i t c h v v _ v g d c h l 8 5 1 0 h v c c l o g a t e h i g a t e v c c g n d p w m l v c c 1 2 v v b o o t s w i t c h v v _ v g d c h l 8 5 1 0 h v c c l o g a t e h i g a t e v c c g n d p w m l v c c 1 2 v v b o o t s w i t c h v v _ v g d c h l 8 5 1 0 h v c c l o g a t e h i g a t e v c c g n d p w m l v c c 1 2 v v b o o t s w i t c h c h l 8 5 1 0 v _ v g d 2 0 v a r _ g a t e _ p m _ a d d r o p t i o n a l v a r i a b l e g a t e d r i v e c i r c u i t v _ c p u _ l 2 l o a d 1 5 v r _ h o t # 1 / v r h o t _ i c r i t # 2 1 7 + 3 . 3 v 1 8 1 9 s m b _ c l k s m b _ d i o s m b u s v v v s m b _ a l e r t # 2 9 3 0 r c s p _ l 2 r c s m _ l 2 r c s c c s r s e r i e s r s e r i e s r t h 2 7 2 6 v s e n _ l 2 v r t n _ l 2 1 7 1 8 1 9 n c 1 / s v c 2 n c 1 / s v d 2 v v v n c 1 / v f i x e n 2 c p u s e r i a l b u s n o t e s 1 p i n d e f i n i t i o n i n m p o l m o d e 2 p i n d e f i n i t i o n i n a m d m o d e
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