digital multi - phase buck controller chl8102/03/04/13 august 28, 2013 | final | v1.09 1 features ? dual output 2/ 3/4+1 - phase pwm controller (chl8102/03/04) and s ingle output 3 - phase pwm controller (chl8113) ? easiest layout and fewest pins in the industry ? footprint compatible with chl8 325 a/b (chl8103/4) ? fully supports intel? vr12 (chl8103/04/13 ) and amd? svi with dual ocp & programmable addressing (chl8103/04) ? i2c interface for configuration & telemetry ? pin programmable i2c address (chl8103/04/13) ? overclocking support with i2c voltage override and vmax setting ? flexible i2c bus security features ? i2c security enable pin (chl8103/04/13) ? independent loop switching frequencies from 200khz to 1.2mhz per phase ? ir efficiency shaping with dynamic phase control (dpc) ? 1 - phase & active diode emulation modes for light load efficiency ? ir adaptive transient al gorithm (ata) on both loops minimizes output bulk capacitors and system cost ? per - loop fault protection: ovp, uvp, ocp ? thermal protection (otp) and vrhot# flag (chl8103/04/13) ? multiple time programmable (mtp) memory for custom configuration ? compatible with ir atl and 3.3v tri - state drivers ? 3.3v +10%/ - 15% supply voltage; 0oc to 85oc operation ? pb - free, rohs, qfn packages applications ? intel? vr12 & amd? svi based systems ? high performance desktops cpu vrs ? value servers cpu & ddr memory vrs description the chl8102/03/04 are dual - loop , digital multi - phase buck controllers designed for cpu voltage regulation. the chl8113 is a single - loop , digital multiphase buck controller ideal for server ddr memory voltage regulation. they are fully compliant with the inte l? vr12 and amd? svi (chl8103/04) specifications. the chl8102/03/04/13 include s ir efficiency shaping technology to deliver exceptional efficiency at minimum cost across the entire load range. ir dynamic phase control adds/drops active phases based upon l oad current and can be configured to enter 1 - phase operation and diode emulation mode automatically or by command. ir s unique adaptive transient algorithm (ata), based on proprietary non - linear digital pwm algorithms, minimizes output bulk capacitors and multiple time programmable (mtp) storage saves pins and enables a small package size. device configuration and fault parameters are easily defined using the ir digital power design center ( dpdc ) gui and stored in on - chip mtp. the chl8102/03/04/13 provides extensive ovp, uvp, ocp and otp fault protection and the chl8103/04/13 includes thermistor based temperature sensing with vrhot signal. the chl8102/03/04/13 includes numerous features like register diagnostics for fast design cycles and platform different iation, truly simplifying vrd design and enabling fastest time - to - market (ttm) with set - and - forget methodology . pin diagram figur e 1: chl8103/04 package top view p w m _ l 2 v r t n r c s m i s e n 3 v s e n p w m 4 ( c h l 8 1 0 4 ) / n c ( c h l 8 1 0 3 ) v r _ r e a d y 1 / p w r g d 2 i r t n 3 r c s p t s e n 1 p w m 3 v 1 8 a r r e s v c c i s e n 2 i s e n 1 i r t n 1 i r t n 2 p w m 2 p w m 1 r c s m _ l 2 r c s p _ l 2 v p g m 2 v i n s e n v r t n _ l 2 v s e n _ l 2 1 2 7 8 5 6 3 4 1 0 9 3 0 2 9 2 4 2 3 2 6 2 5 2 8 2 7 2 1 2 2 4 1 g n d c h l 8 1 0 3 / 4 4 0 p i n 6 x 6 q f n t o p v i e w 1 2 1 6 1 4 1 9 1 3 1 7 1 5 2 0 1 8 1 1 3 9 3 5 3 7 3 2 3 8 3 4 3 6 3 1 3 3 4 0 v r _ r e a d y _ l 2 1 / p w r o k 2 1 i n t e l m o d e 2 a m d m o d e s v _ a l e r t 1 / n c 2 s v _ c l k 1 / s v c 2 s v _ d a t 1 / s v d 2 v r _ h o t # e n a b l e a d d r / p r o t / e n _ l 2 s m b _ d a t s m b _ c l k t s e n 2 i r t n 4 ( c h l 8 1 0 4 ) / n c ( c h l 8 1 0 3 ) i s e n 4 ( c h l 8 1 0 4 ) / n c ( c h l 8 1 0 3 ) i r t n _ l 2 i s e n _ l 2
digital multi - phase buck controller chl8102/03/04/13 august 28, 2013 | final | v1.09 2 pin diagram enlarged p w m _ l 2 v r t n r c s m i s e n 3 v s e n p w m 4 ( c h l 8 1 0 4 ) / n c ( c h l 8 1 0 3 ) v r _ r e a d y 1 / p w r g d 2 i r t n 3 r c s p t s e n 1 p w m 3 v 1 8 a r r e s v c c i s e n 2 i s e n 1 i r t n 1 i r t n 2 p w m 2 p w m 1 r c s m _ l 2 r c s p _ l 2 v p g m 2 v i n s e n v r t n _ l 2 v s e n _ l 2 1 2 7 8 5 6 3 4 1 0 9 3 0 2 9 2 4 2 3 2 6 2 5 2 8 2 7 2 1 2 2 4 1 g n d c h l 8 1 0 3 / 4 4 0 p i n 6 x 6 q f n t o p v i e w 1 2 1 6 1 4 1 9 1 3 1 7 1 5 2 0 1 8 1 1 3 9 3 5 3 7 3 2 3 8 3 4 3 6 3 1 3 3 4 0 v r _ r e a d y _ l 2 1 / p w r o k 2 1 i n t e l m o d e 2 a m d m o d e s v _ a l e r t 1 / n c 2 s v _ c l k 1 / s v c 2 s v _ d a t 1 / s v d 2 v r _ h o t # e n a b l e a d d r / p r o t / e n _ l 2 s m b _ d a t s m b _ c l k t s e n 2 i r t n 4 ( c h l 8 1 0 4 ) / n c ( c h l 8 1 0 3 ) i s e n 4 ( c h l 8 1 0 4 ) / n c ( c h l 8 1 0 3 ) i r t n _ l 2 i s e n _ l 2
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