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dual, 12 - bit nano dac+ with 2 ppm/c reference, i 2 c interface data sheet AD5697R rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specif ications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features low drift 2.5 v reference: 2 ppm/c typical tiny package: 3 mm 3 mm , 16 - lead lfcsp total unadjusted error (tue): 0.1% of full - scale range ( fsr ) maximum offset error: 1.5 mv maximum gain error: 0.1% of fsr maximum high drive capability: 20 ma, 0.5 v from supply rails user selectable gain of 1 or 2 (gain pin) reset to zero scale or midscale (rstsel pin) 1.8 v logic compatibility low g litch: 0.5 nv -s ec 400 khz i 2 c- compat i ble serial interface robust 3.5 kv hbm and 1.5 kv ficdm esd rating low power: 3.3 mw at 3 v 2.7 v to 5.5 v power supply ? 40c to +105c temperature range applications base station power amplifiers process control s ( programmable logic controller [ plc ] i/o cards) industrial a utomation data acquisition systems functional block dia gram figure 1. general description the AD5697R , a member of the nano dac+? family, is a low power, d ual, 12- bit buffered voltage out put digital - to - analog converter ( dac ) . the device include s a 2.5 v, 2 ppm/ c internal reference (enabled by default) and a gain select pin giving a full - scale output of 2.5 v ( gain = 1) or 5 v ( gain = 2). the AD5697R operate s from a single 2.7 v to 5.5 v supply, is guaranteed monotonic by design , and exhibit s less than 0.1% fsr gain error and 1.5 mv offset error performance. the device is available in a 3 mm 3 mm lfcsp and a tssop package. the AD5697R also incorporate s a power - on reset circuit and a rstsel pin that ensure that the dac outputs power up to zero scale or midscale and remain there until a valid write takes place. it contains a per channel power - down feature that reduces the current consumption of the device to 4 a at 3 v while in power - down mode. the AD5697R us es a versatile 2 - wire serial interface that operates at clock rates up to 400 khz and includes a v logic pin intended for 1.8 v/3 v/5 v logic. table 1 . dual nano dac+ devices interface reference 16 - bit 12 - bit spi internal ad5689r ad5687r external ad5689 ad5687 i 2 c internal AD5697R external product highlights 1. precision dc performance . tue: 0.1% of fsr max imum offset error: 1.5 mv max imum gain error: 0.1% of fsr max imum 2. low drift 2.5 v on- chip reference . 2 ppm/c typical temperature coefficient 5 ppm/c maximum temperature coefficient 3. two package options . 3 mm 3 mm , 16 - lead lfcsp 16- lead tssop scl v logic sda a1 a0 input register dac register string dac a buffer v out a input register dac register string dac b buffer v out b v ref gnd v dd power- down logic power-on reset gain = 1/2 interface logic rstsel gain ldac reset AD5697R 2.5v reference 1 1253-001
AD5697R data sheet rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac characteristics ........................................................................ 5 timing characteristics ................................................................ 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 15 theory of operation ...................................................................... 17 digital - to - analog converter .................................................... 17 transfer function ....................................................................... 17 dac architecture ....................................................................... 17 serial interface ............................................................................ 18 write and up date commands .................................................. 18 serial operation ......................................................................... 19 write operation .......................................................................... 19 read operation ........................................................................... 20 multiple dac readback sequence .......................................... 20 power - down operation ............................................................ 21 load dac (hardware ldac pin) ........................................... 22 ldac mask register ................................................................. 22 hardware reset ( reset ) .......................................................... 23 reset select pin (rstsel) ........................................................ 23 internal reference setup ........................................................... 23 sold er heat reflow ..................................................................... 23 long - term temperature drift ................................................. 23 thermal hysteresis .................................................................... 24 applications information .............................................................. 25 microprocessor interfacing ....................................................... 25 AD5697R - to - adsp - bf531 interface ...................................... 25 layout guidelines ....................................................................... 25 galvanically isolated interface ................................................. 25 outline dimensions ....................................................................... 26 ordering g uide .......................................................................... 26 revision history 2/1 3 revision 0: initial version
data sheet AD5697R rev. 0 | page 3 of 28 specifications v dd = 2.7 v to 5.5 v; 1.8 v v logic 5.5 v; and all specifications t min to t max , unless otherwise noted. r l = 2 k; and c l = 200 pf. table 2. parameter min typ max unit test conditions/comments static performance 1 resolution 12 bits relative accuracy 0.12 1 lsb differential nonlinearity 1 lsb guaranteed monotonic by design zero-code error 0.4 1.5 mv all 0s loaded to dac register offset error +0.1 1.5 mv full-scale error +0.01 0.1 % of fsr all 1s loaded to dac register gain error 0.02 0.1 % of fsr total unadjusted error 0.01 0.1 % of fsr external reference; gain = 2; tssop 0.2 % of fsr internal reference; gain = 1; tssop offset error drift 2 1 v/c gain temperature coefficient 2 1 ppm of fsr/c dc power supply rejection ratio 2 0.15 mv/v dac code = midscale; v dd = 5 v 10% dc crosstalk 2 2 v due to single channel, full-scale output change 3 v/ma due to load current change 2 v due to powering down (per channel) output characteristics 2 output voltage range 0 v ref v gain = 1 0 2 v ref v gain = 2, see figure 26 capacitive load stability 2 nf r l = 10 nf r l = 1 k resistive load 3 1 k load regulation 80 v/ma 5 v 10%, dac code = midscale; ?30 ma i out +30 ma 80 v/ma 3 v 10%, dac code = midscale; ?20 ma i out +20 ma short-circuit current 4 40 ma load impedance at rails 5 25 see figure 26 power-up time 2.5 s coming out of power-down mode; v dd = 5 v reference output output voltage 6 2.4975 2.5025 v at ambient reference temperature coefficient 7, 8 2 5 ppm/c see the terminology section output impedance 2 0.04 output voltage noise 2 12 v p-p 0.1 hz to 10 hz output voltage noise density 2 240 nv/hz at ambient; f = 10 khz, c l = 10 nf load regulation sourcing 2 20 v/ma at ambient load regulation sinking 2 40 v/ma at ambient output current load capability 2 5 ma v dd 3 v line regulation 2 100 v/v at ambient long-term stability/drift 2 12 ppm after 1000 hours at 125c thermal hysteresis 2 125 ppm first cycle 25 ppm additional cycles logic inputs 2 input current 2 a per pin input low voltage, v inl 0.3 v logic v input high voltage, v inh 0.7 v logic v pin capacitance 2 pf
AD5697R data sheet rev. 0 | page 4 of 28 parameter min typ max unit test conditions/comments logic outputs (sda) 2 output low voltage, v ol 0.4 v i sink = 3 ma floating state output capacitance 4 pf power requirements v logic 1.8 5.5 v i logic 3 a v dd 2.7 5.5 v gain = 1 v ref + 1.5 5.5 v gain = 2 i dd v ih = v dd , v il = gnd, v dd = 2.7 v to 5.5 v normal mode 9 0.59 0.7 ma internal reference off 1.1 1.3 ma internal reference on, at full scale all power - down modes 10 1 4 a ? 40c to +85c 6 a ? 40c to +105c 1 dc specifications tested with the outputs unloaded, unless otherwise noted. upper dead band = 10 mv and exists only when v ref = v dd with gain = 1 or when v ref /2 = v dd with gain = 2. linearity calculated using a reduced code range of 12 t o 4080. 2 guaranteed by design and characterization; not production tested. 3 channel a can have an output current of up to 30 ma. similarly, channel b can have an output current of up to 30 ma up to a junction temperature of 100 c. 4 v dd = 5 v . the device includes current limiting that is intended to protect the device during temporary overload conditions. junction temperature can be exc eed ed during current limit. operation above the specified max imum operation junction temperature may impair device reliability. 5 when drawing a load current at either rail, the output voltage headroom with respect t o that rail is limited by the 25 typ ical cha nnel res istance of the output device. for example , when sinking 1 m a, the minimum output voltage = 25 1 ma = 25 mv ( see figure 26) . 6 initial accuracy presolder reflow is 750 v; output voltage includes the effects of preconditioning drift. see the internal reference setup section. 7 reference is trimmed and tested at two temperatures and is characterized from ? 40c to +105c . 8 reference temperature coefficient is calculated as per the box method. see the term inology section for further information. 9 interface inactive. both dacs active. dac outputs unloaded. 10 both dacs powered down.
data sheet AD5697R rev. 0 | page 5 of 28 ac characteristics v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; 1.8 v v logic 5.5 v; all specifications t min to t max , unless otherwise noted. guaranteed by design and characterization; not production tested. table 3 . parameter 1 min typ max unit test conditions/comments 2 output voltage settling time 5 7 s ? to ? scale settling to 2 lsb slew rate 0.8 v/s digital -to - analog glitch impulse 0.5 nv - sec 1 lsb change around major carry digital feedthrough 0.13 nv - sec digital crosstalk 0.1 nv - sec analog crosstalk 0.2 nv - sec dac -to - dac crosstalk 0.3 nv - sec total harmonic distortion (thd) 3 ? 80 db at ambient, bandwidth = 20 khz, v dd = 5 v, f out = 1 khz output noise spectral density 300 nv/ hz dac code = midscale, 10 khz; gain = 2 output noise 6 v p -p 0.1 hz to 10 hz signal - to - noise ratio (snr) 90 db at ambient, bandwidth = 20 khz, v dd = 5 v, f out = 1 khz spurious - free dynamic range (sfdr) 83 db at ambient, bandwidth = 20 khz, v dd = 5 v, f out = 1 khz signal - to - noise - and - distortion ratio (sinad) 80 db at ambient, bandwidth = 20 khz, v dd = 5 v, f out = 1 khz 1 see the terminology section. 2 temperature range is ?40c to +105c, typical at 25c. 3 digitally generated sine wave at 1 khz.
AD5697R data sheet rev. 0 | page 6 of 28 timing characteristi cs v dd = 2.5 v to 5.5 v; 1.8 v v logic 5.5 v; all specifications t min to t max , unless otherwise noted. see figure 2 . table 4. parameter 1 min max unit test conditions/comments t 1 2.5 s scl cycle time t 2 0.6 s scl high time , t high t 3 1.3 s scl low time , t low t 4 0.6 s start/repeated start condition hold time, t hd,sta t 5 100 ns d ata setup time , t su, dat t 6 2 0 0.9 s d ata hold time , t hd,dat t 7 0.6 s s etup time for repeated start , t su,sta t 8 0.6 s s top condition setup time, t su,sto t 9 1.3 s b us free time between a stop and a start condition , t buf t 10 0 300 ns r ise time of scl and sda when receiving, t r t 11 20 + 0.1c b 3 300 ns f all time of sda and scl when transmitting/receiving , t f t 12 20 ns ldac pulse width t 13 400 ns scl rising edge to ldac rising edge c b 3 400 pf capacitive load for each bus line 1 guaranteed by design and characterization; not production tested. 2 a master device must provide a hold time of at least 300 ns for the sda signal (referred to the v ih min imum o f the scl signal) to bridge the undefined region of the falling edge of the scl. 3 c b is the total capacitance of one bus line in pf. t r and t f mea sured between 0.3 v dd and 0.7 v dd . figure 2. 2- wire serial interface timing diagram scl sda t 1 t 3 ldac 1 ldac 2 start condition repeated start condition stop condition notes 1 asynchronous ldac update mode. 2 synchronous ldac update mode. t 4 t 6 t 5 t 7 t 8 t 2 t 13 t 4 t 11 t 10 t 12 t 12 t 9 1 1253-002
data sheet AD5697R rev. 0 | page 7 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ? 0.3 v to +7 v v logic to gnd ? 0.3 v to +7 v v out to gnd ? 0.3 v to v dd + 0.3 v v ref to gnd ? 0.3 v to v dd + 0.3 v digital input voltage to gnd 1 ? 0.3 v to v logic + 0.3 v sda and scl to gnd ? 0.3 v to +7 v operating temperature range ? 40c to +105c storage temperature range ? 65c to +150c junction temperature 125c 16 - lead tssop, ja thermal impedance, 0 airflow ( 4- layer board) 112.6c/w 16 - lead lfcsp, ja thermal impedance, 0 airflow ( 4- layer board) 70 c/w reflow soldering peak temperature, pb free (j - std - 020) 260c esd 2 3.5 kv ficdm 1.5 kv 1 excluding sda and scl. 2 human body model (hbm) classification. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
AD5697R data sheet rev. 0 | page 8 of 28 pin configuration s and function descrip tions figure 3. 16 - lead lfcsp pin configuration figure 4. 16 - lead tssop pin configuration table 6 . pin function descriptions pin no. mnemonic description lfcsp tssop 1 3 v out a analog output voltage from dac a. the output amplifier has rail - to - rail operation. 16 2 nc no connect. do not connect to this pin. 2 4 gnd ground reference point for all circuitry on the part. 3 5 v dd power supply input. this part can be operated from 2.7 v to 5.5 v . d ecouple the supply with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 6 nc no connect. do not connect to this pin. 5 7 v out b analog output voltage from dac b. the output amplifier has rail -to - rail operation. 6 8 sda serial data input. this pin is used in conjunction with the scl line to clock data into or out of the 24 - bit input shift register. sda is a bidirectional, open - drain data line that should be pulled to the supply with an external pull - up resistor. 7 9 ldac ldac can be operated in two modes, asynchronous and synchronous. pulsin g this pin low allows either or both dac registers to be updated if the input register s have new data. this allows both dac outputs to simultaneously update. this pin can also be tied permanently low . 8 10 gain g ain select . when t his pin is tied to gnd, both dac outputs have a span from 0 v to v ref . if this pin is tied to v logic , both dacs output a span of 0 v to 2 v ref . 9 11 v logic digital power supply. voltage ranges from 1.8 v to 5.5 v. 10 12 a0 address input. sets the first lsb of the 7 - bit slave address. 11 13 scl serial clock line. this is used in conjunction with the sda line to clock data into or out of the 24 - bit input register. 12 14 a1 address input. sets the second lsb of the 7 - bit slave address. 13 15 reset asynchronous reset input. the reset input is falling edge sensitive. when reset is low, all ldac pulses are ignored. when reset is activated, the input register and the dac register are updated with zero scale or midscale, depending on the state of the rstsel pin. 14 16 rstsel power - on reset select . tying this pin to gnd powers up both dacs to zero scale. tying this pin to v logic powers up both dacs to midscale. 15 1 v ref reference voltage. the AD5697R has a common reference pin. when using the internal reference, this is the reference output pin. when using an external reference, this is the reference input pin. the default for this pin is as a reference output. 17 not applicable epad exposed pad. the exposed pad must be tied to gnd. 12 11 10 1 3 4 a1 scl a0 9 v logic v out a v dd 2 gnd nc 6 sda 5 v out b 7 ldac 8 gain 16 nc 15 v ref 14 rstsel 13 reset top view (not to scale) AD5697R notes 1. the exposed pad must be tied to gnd. 2. nc = no connect. do not connect to this pin. 1 1253-003 1 2 3 4 5 6 7 8 nc v out a gnd v out b nc v dd v ref sda 16 15 14 13 12 11 10 9 reset a1 scl gain ldac v logic a0 rstsel top view (not to scale) AD5697R 1 1253-004 notes 1. nc = no connect. do not connect to this pin.
data sheet AD5697R rev. 0 | page 9 of 28 typical performance characteristics figure 5. internal reference voltage vs. temperature figure 6. refer ence output temperature drift histogram figure 7. reference long- term stability/drift figure 8. internal reference noise spectral density vs. frequency figure 9. internal reference noise , 0.1 hz to 10 hz figure 10 . internal reference voltage vs. load current ?40 ?20 0 20 40 60 80 100 120 v ref (v) temperature (c) device 1 device 2 device 3 device 4 device 5 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 v dd = 5v 1 1253-005 90 0 10 20 30 40 50 60 70 80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 number of units temperature drift (ppm/c) v dd = 5v 1 1253-007 60 0 10 20 30 40 50 2.498 2.499 2.500 2.501 2.502 hits v ref (v) 0 hour 168 hours 500 hours 1000 hours v dd = 5.5v 1 1253-008 1600 0 200 400 600 800 1000 1200 1400 10 100 1k 10k 100k 1m nsd (nv/ hz) frequency (mhz) v dd = 5v t a = 25c 1 1253-009 ch1 10v m1.0s a ch1 160mv 1 t v dd = 5v t a = 25c 1 1253-010 2.5000 2.4999 2.4998 2.4997 2.4996 2.4995 2.4994 2.4993 ?0.005 ?0.003 ?0.001 0.001 0.003 0.005 v ref (v) i load (a) v dd = 5v t a = 25c 1 1253-0 11
AD5697R data sheet rev. 0 | page 10 of 28 figure 11 . internal reference voltage vs. supply voltage figure 12 . integral nonlinearity ( inl ) vs. code figure 13 . differential nonlinearity ( dnl ) vs. code figure 14 . inl error and dnl error vs. temperature figure 15 . inl error and dnl error vs. v ref figure 16 . inl error and dnl error vs. supply voltage 2.5002 2.5000 2.4998 2.4996 2.4994 2.4992 2.4990 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v ref (v) v dd (v) d1 d3 d2 t a = 25c 1 1253-012 10 ?1 0 ?8 ?6 ?4 ?2 0 2 4 8 6 0 62 5 125 0 187 5 250 0 312 5 375 0 409 6 inl (lsb) code v dd = 5v t a = 25 c inte rna l refere nc e = 2.5v 1 1253-013 1.0 ?1 .0 ?0 .8 ?0 .6 ?0 .4 ?0 .2 0 0.2 0.4 0.8 0.6 0 62 5 125 0 187 5 250 0 312 5 375 0 409 6 dn l (lsb) code v dd = 5v t a = 25 c inte rna l refere nc e = 2.5v 1 1253-014 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 ?40 110 60 10 error (lsb) temperature (c) inl dnl v dd = 5v t a = 25c internal reference = 2.5v 1 1253-015 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 0 5.04.54.03.53.02.52.01.51.00.5 error (lsb) v ref (v) inl dnl v dd = 5v t a = 25c internal reference = 2.5v 1 1253-016 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 2.7 5.2 4.7 4.2 3.7 3.2 error (lsb) supply voltage (v) inl dnl 1 1253-017 v dd = 5v t a = 25c internal reference = 2.5v
data sheet AD5697R rev. 0 | page 11 of 28 figure 17 . gain error and full - scale error vs. temperature figure 18 . zero - code error and offset error vs. temperature figure 19 . gain error and full - scale error vs. supply voltage figure 20 . zero - code error and offset error vs. supply voltage figure 21 . total unadjusted error vs. temperature figure 22 . total unadjusted error vs. supply voltage , gain = 1 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 ?40 ?20 0 20 40 60 80 100 120 error (% of fsr) temperature (c) gain error full-scale error 1 1253-018 v dd = 5v t a = 25c internal reference = 2.5v 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?40 ?20 0 20 40 60 80 100 120 error (mv) temperature (c) offset error zero-code error 1 1253-019 v dd = 5v t a = 25c internal reference = 2.5v 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 2.7 5.2 4.7 4.2 3.7 3.2 error (% of fsr) supply voltage (v) gain error full-scale error v dd = 5v t a = 25c internal reference = 2.5v 1 1253-020 1.5 ?1.5 ?1.0 ?0.5 0 0.5 1.0 2.7 5.2 4.7 4.2 3.7 3.2 error (mv) supply voltage (v) zero-code error offset error v dd = 5v t a = 25c internal reference = 2.5v 1 1253-021 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 ?4 0 ?2 0 0 20 40 60 80 10 0 12 0 tot al unadju sted e rr or (% o f f sr) tempe ra t ur e (c) v dd = 5v t a = 25 c inte rna l refere nc e = 2.5v 1 1253-022 0.10 0.08 0.06 0.04 0.02 0 ?0 .02 ?0 .04 ?0 .06 ?0 .08 ?0 .10 2.7 5.2 4.7 4.2 3.7 3.2 tot al unadju sted e rr or (% o f f sr) supply v olt age (v) v dd = 5v t a = 25 c inte rna l refere nc e = 2.5v 1 1253-023
AD5697R data sheet rev. 0 | page 12 of 28 figure 23 . total unadjusted error vs. code figure 24 . i dd his togram with external reference figure 25 . i dd histogram with internal reference, v refout = 2.5 v , gain = 2 figure 26 . headroom/footroom vs. load current figure 27 . source and sink capability at v dd = 5 v figure 28 . source and sink capability at v dd = 3 v 0 ?0 .01 ?0 .02 ?0 .03 ?0 .04 ?0 .05 ?0 .06 ?0 .07 ?0 .08 ?0 .09 ?0 .10 0 1000 0 2000 0 3000 0 4000 0 5000 0 6000 0 6553 5 tot al unadju sted e rr or (% o f f sr) code v dd = 5v t a = 25 c inte rna l refere nc e = 2.5v 1 1253-024 25 20 15 10 5 0 540 560 580 600 620 640 h it s i dd full scale (v) v dd = 5v t a = 25 c exte rnal refere nc e = 2.5v 1 1253-025 30 25 20 15 10 5 0 100 0 102 0 104 0 106 0 108 0 110 0 112 0 114 0 h it s v dd = 5v t a = 25 c inte rna l refere nc e = 2.5v 1 1253-026 i dd full scale (v) 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 5 10 15 20 25 30 v out (v) load current (ma) sourcing 2.7v sourcing 5v sinking 2.7v sinking 5v 1 1253-027 1 1253-028 7 ?2 ?1 0 1 2 3 4 5 6 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) full scale one-quarter scale midscale three-quarter scale zero scale v dd = 5v t a = 25c gain = 2 internal reference = 2.5v 5 ?2 ?1 0 1 2 3 4 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) v dd = 3v t a = 25c external reference = 2.5v gain = 1 1 1253-029 full scale one-quarter scale midscale three-quarter scale zero scale
data sheet AD5697R rev. 0 | page 13 of 28 figure 29 . supply current vs. temperature figure 30 . settling time figure 31 . power - on reset to 0 v figure 32 . exiting power - down to midscale figure 33 . digital -to- analog glitch impulse figure 34 . analog crosstalk, channel a 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ?4 0 11 0 60 10 curr ent ( ma ) tempe ra t ur e (c) fu ll s ca le zero code exte rna l refere nc e , f u ll s ca le 1 1253-030 0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 10 320 160 40 80 20 v out (v) time (s) dac a dac b v dd = 5v t a = 25c internal reference = 2.5v ? to ? scale 1 1253-031 ?0.01 0 0.06 0.01 0.02 0.03 0.04 0.05 ?1 0 6 1 2 3 4 5 ?10 15 10 0 5 ?5 v out (v) v dd (v) time (s) v dd channel a channel b t a = 25c internal reference = 2.5v 1 1253-032 0 1 3 2 ?5 10 0 5 v out (v) time (s) channel b sync channel a v dd = 5v t a = 25c internal reference = 2.5v gain = 1 gain = 2 1 1253-033 2.4988 2.5008 2.5003 2.4998 2.4993 0 12 8 10 4 6 2 v out (v) time (s) 1 1253-034 channel b t a = 25c v dd = 5.25v internal reference = 2.5v positive major code transition energy = 0.227206nv-sec ?0.002 ?0.001 0 0.001 0.002 0.003 0 25 20 10 15 5 v out ac-coupled (v) time (s) 1 1253-035 channel b
AD5697R data sheet rev. 0 | page 14 of 28 figure 35 . 0.1 hz to 10 hz output noise plot, external reference figure 36 . 0.1 hz to 10 hz output noise plot, 2.5 v internal reference figure 37 . noise spectral density figure 38 . total harmonic distortion at 1 khz figure 39 . settling time vs. capacitive load figure 40 . multiplying bandwidth, ext ernal reference = 2.5 v, 0.1 v p-p, 10 khz to 10 mhz ch1 10v m1.0s a ch1 802mv 1 t v dd = 5v t a = 25c external reference = 2.5v 1 1253-036 ch1 10 v m1.0s a ch1 802m v 1 t v dd = 5v t a = 25 c inte rna l referenc e = 2.5v 1 1253-038 0 20 0 40 0 60 0 80 0 100 0 120 0 140 0 160 0 10 1m 100 k 1k 10 k 10 0 nsd (nv/ hz) freque nc y (hz) fu ll s ca le mids ca le zero s ca le v dd = 5v t a = 25 c inte rna l refere nc e = 2.5v 1 1253-037 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 20000 16000 8000 12000 4000 2000 18000 10000 14000 6000 thd (dbv) frequency (hz) v dd = 5v t a = 25c internal reference = 2.5v 1 1253-039 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 1.590 1.630 1.620 1.600 1.610 1.625 1.605 1.615 1.595 v out (v) time (ms) 0nf 0.1nf 10nf 0.22nf 4.7nf v dd = 5v t a = 25c internal reference = 2.5v 1 1253-040 ?60 ?50 ?40 ?30 ?20 ?10 0 10k 10m 1m 100k bandwidth (db) frequency (hz) v dd = 5v t a = 25c external reference = 2.5v, 0.1v p-p 1 1253-041
data sheet AD5697R rev. 0 | page 15 of 28 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function . a typical inl vs. code plot is shown in figure 12. differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 13. zero - code error zero - code error is a measurement of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero - code error is always positive in the AD5697R because the output of the dac cannot go less than 0 v due to a combination of the offset errors in the dac and the output amplifier. zero - code error is expressed in mv. a plot of the zero - code error vs. the temperature can be seen in figure 18 . full - scale error full - scale error is a measurement of the output er ror when the full - scale c ode is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full - scale error is expressed in percent of full - scale range (% of fsr) . a plot of the full - scale error vs. the temperature can be seen in figure 17 . gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal expressed as % of fsr. offset error drift this is a measurement of the change in offset error with a change in temperature. it is expressed in v/c. gain temperature coefficient this is a measurement of the change in gain error with changes in temperature. it is expressed in ppm of fsr/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured on the AD5697R with code 5 12 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full - scale output of the dac. it is measured in mv/v . v ref is held at 2 v, and v dd is varied by 10%. output voltage settling time output voltage settling time is the time it takes for the output of a dac to settle to a specified level for a ? to ? full - scale input ch ange . digital -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv -s ec and is measured when the digital input code is changed by 1 lsb at the major carry transition , 0x7fff to 0x8000 (see figure 33). digital feedthrough digital feedthr ough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv -s ec , and measured with a full - scale code change on the data bus, that is, from all 0s to all 1s and vice versa. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in db. noise spectral density this is a measurement of the internally generated random noise . random noise is characterized as a spectral density (nv/hz). it is measured by loading the dac to midscale and measuring noise at the output. it is measured in nv/hz. a plot of noise spectral density is shown in figure 37. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full - scale output change on one dac (or soft power - down and power - up) while monitoring another dac kept at midscale. it is expressed in v. dc crosstalk due to load current change is a measure of the impact tha t a change in load current on one dac has to another dac kept at midscale. it is expressed in v/ma. digital crosstalk this is the glitch impulse transferred to the output of one d ac at midscale in response to a full - scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv -s ec . analog crosstalk this is the glitch impulse transferred to the outp ut of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full - scale code change (all 0s to all 1s and vice versa). then execute a software ldac and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv -s ec .
AD5697R data sheet rev. 0 | page 16 of 28 dac -to - dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent analog output change of another dac. it is measured by loading the attack channel with a full - scale code change (all 0s to all 1s and vice versa) , using the write to and update commands while monitoring the output of the victim channel that is at midscale. the energy of the glitch is expressed in nv -s ec . multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full - scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequ ency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) t hd is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measurement of the harmonics present on the dac output. it is measured in db. voltage reference temperature coefficient (tc) voltage reference tc is a measure of the change in the reference output voltage with a change in temperature. the reference tc is calculated using the box method, which defines the tc as the maximum change in the reference output over a given temperature range expressed in ppm/c as follows; 6 10 ? ? ? ? ? ? ? ? ? = temprange v vv tc refnom refmin refmax where: v refmax is the maximum reference output measured over the tota l temperature range. v refmin is the minimum reference output measured over the total temperature range. v refnom is the nominal reference output voltage, 2.5 v. temprange is the specified temperature range of ? 40c to +10 5c.
data sheet AD5697R rev. 0 | page 17 of 28 theory of operation digital - to - analog converter t he AD5697R is a d ual , 12- bit, serial input, voltage output dac with an internal reference. the part operate s from supply voltages of 2.7 v to 5.5 v. data is written to the AD5697R in a 24- bit word format via a 2 - wire serial interface. th e a d5697r incorporate s a power - on reset circuit to ensure that the dac output powers up to a known output state. the device also ha s a software power - down mode that reduces the typical current consumption to 4 a. transfer function the internal reference is o n by default. to use an external reference , only a nonreference option is available. because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n ref out d gainvv 2 where: gain is the gain of the output amplifier and is set to 1 by default. this can be set to 1 or 2 using the gain select pin. when t his pin is tied to gnd, both dac outputs have a span from 0 v to v ref . if this pin is tied to v logic , both dac output a span of 0 v to 2 v r ef . d is the decimal equivalent of the binary code that is loaded to the dac register as 0 to 4,0 95 for the 1 2- bit device. n is the dac resolution. dac architecture the dac architecture consists of a string dac followed by an output amplifier. figure 41 shows a block diagram of the dac arc hitecture. figure 41 . single dac channel architecture block diagram the resistor string struc ture is shown in figure 42 . it is a string of resistors, each of value r. the code loaded to the dac register determines the node on the string where the voltage is t o be tapped off and fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. figure 42 . resistor string structure internal reference the AD5697R on - chip reference is on at power - up but can be disabled via a write to a control register. see the internal reference setup section for details. the AD5697R ha s a 2.5 v, 2 ppm/c reference , giving a full - scale output of 2.5 v or 5 v depending o n the state of the gain pin. the internal reference associated with the device is available at the v ref pin. this buffe r ed reference is capable of driving external loads of up to 10 ma . output amplifiers the output buffer amplifier can generate rail - to - rail voltages on its output, which gives an output range of 0 v to v dd . the actual range depends on the value of v ref , the gain pin, the offset error , and the gain error. the gain pin selects the gain of the output . ? if gain is tied to gnd , both output s have a gain of 1 , and the output range is 0 v to v ref . ? if gain is tied to v logic , both output s have a gain of 2 , and the output range is 0 v to 2 v ref . these amplifiers are capable of driving a load of 1 k? in parallel with 2 n f to gnd. the slew rate is 0.8 v/ s with a ? to ? scale settling time of 5 s. input register 2.5v ref dac register resistor string ref (+) v ref gnd ref (?) v out x gain (gain = 1 or 2) 1 1253-042 r r r r r to output amplifier v ref 1 1253-043
AD5697R data sheet rev. 0 | page 18 of 28 serial interface t he AD5697R has a 2- wire i 2 c- compatible serial interface (refer to i 2 c- bus specification , version 2.1, january 2000, available from philips semiconductor) . see figure 2 for a timing diagram of a typi cal write sequence. the AD5697R can be connected to an i 2 c bus as a slave device, under the control of a master device . the AD5697R c an support sta ndard (100 khz) and fast (400 khz) data transfer modes. support is not provided for 1 2- bit addressing and general call addressing. input shift register the input shift register of the AD5697R is 24 bits wide. data is loaded into the device as a 24 - bit word under the control of a serial clock input, scl. the first eight msbs make up the command byte. the first four bits are the command bits (c3, c2, c1, and c0) that control the mode of operation of the device (s ee table 7 ). the last four bits of the first byte are the address bits ( dac b , 0, 0, and dac a, s ee table 8 ). the data - word comprises 12- bit input code, followed by four dont care bits for the AD5697R . these data bits are transfe rr ed to the input register on the 24 falling edges of scl . comm ands can be exec uted on individual dac channels or both dac channel s, depending on the address bits selected . table 7 . command definitions command c3 c2 c1 c0 description 0 0 0 0 no operation 0 0 0 1 write to input register n (d ependent on ldac ) 0 0 1 0 update dac register n with contents of input register n 0 0 1 1 wr ite to and update dac channel n 0 1 0 0 power down/power up dac 0 1 0 1 hardware ldac mask register 0 1 1 0 software r eset (power - on reset) 0 1 1 1 internal r eference setup register 1 0 0 0 reserved reserved 1 1 1 1 reserved table 8 . address commands address (n) dac b 0 0 dac a description 0 0 0 1 dac a 1 0 0 0 dac b 1 0 0 1 dac a and dac b write and update com mands write to input register n (dependent on ldac ) command 0001 allows the user to write to the dedicated input re gister of each dac individually. when ldac is low, the input register is transparent (if not controlled by the ldac mask register). update dac register n with contents of input register n command 0010 loads the dac registers/outputs with the contents of the input registers selected and updates the dac outputs directly. write to and update dac chan nel n (independent of ldac ) command 0011 allows the user to write to the dac registers and update the dac outputs directly. figure 43 . input shift register content db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c3 c2 c1 c0 dac b 0 0 dac a d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x command dac address dac data dac data command byte data high byte data low byte 1 1253-044
data sheet AD5697R rev. 0 | page 19 of 28 s erial operation the AD5697R has a 7 - bit slave address. the five msbs are 00011 and the two lsbs (a1 and a0) are set by the state of the a0 and a1 address pin s . the ability to make hardwired changes to a0 and a1 allows the user to incorporate up to four of these devices on one bus, as outlined in table 9 . table 9 . device address selection a0 pin connection a1 pin connection a0 a1 gnd gnd 0 0 v logic gnd 1 0 gnd v logic 0 1 v logic v logic 1 1 the 2 - wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition when a high - to - low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7 - bit slave address. the slave address corresponding to the transmitted address responds by pulling sda low during the 9 th clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shi ft register. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of sc l. 3. when all data bits have been read or written, a stop condition is established. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition . in read mode, the master issues a no acknowledge for the 9 th clo ck pulse (that is, the sda line remains high). the master then brings the sda line low before the 10 th clock pulse, and then high during the 10 th clock pulse to establish a stop condition. write operation when writing to the AD5697R , the user must begin with a start command followed by an address byte ( r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. the AD5697R require s two bytes of data for the dac and a command byte that controls various dac functions. three bytes of data must , therefore , be written to the dac with the command byte followed by the most significant data byte and the least significant data byte, as shown in figure 44 . all these data bytes are acknowledged by the AD5697R . a stop condition follows. figure 44 . i 2 c write operation frame 2 command byte frame 1 slave address 1 9 9 1 scl start by master ack. by AD5697R ack. by AD5697R sda r/w db23 a0a1 1 000 1 db22 db21 db20 db19 db18 db17 db16 1 9 9 1 ack. by AD5697R ack. by AD5697R frame 4 least significant data byte frame 3 most significant data byte stop by master scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 1 1253-045
AD5697R data sheet rev. 0 | page 20 of 28 r ead o peration when reading data back from the AD5697R dacs, the user begins with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. this addres s byte must be followed by the control byte that determines both the read command that is to follow and the pointer address to read from, which is also acknowledged by the dac. the user configures which channel to read back and sets the readback command to active using the control byte. following this, there is a repeated start condition by the master and the address is resent with r/ w = 1. this is acknowledged by the dac , indicating that it is prepared to transmit data. two bytes of data are then read fro m the dac, as shown in figure 45 . a nack condition from the master , followed by a stop condition , completes the read sequence. default readback is channel a if both dac s are selected. multiple dac readback sequenc e the user begins with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low . this address byte must be follo wed by the control byte, which is also acknowledged by the dac. the user configures which channel to start the readback using the control byte. following this, there is a repeated start condition by the master , and the address is resent with r/ w = 1. this is acknowledged by the dac, indicating that it is prepared to transmit data. the first two bytes of data are then read from dac input register a that is selected using the control byte, most significant byte first, as shown in figure 45 . the next four bytes read back are dont care bytes, and the next two bytes of data are the contents of dac input register b. data continues to be read from the dac input registers in this au to - incremental fashion, until a nack followed by a stop condition follows. if the contents of dac input register b are read out, the next bytes of data that are read are from the contents of dac input register a. figure 45 . i 2 c read operation frame 2 command byte frame 1 slave address 1 1000 1 a1 a0 r/w db23 db22 db21 db20 db19 db18 db17 db16 9 9 1 start by master ack. by AD5697R ack. by AD5697R scl scl sda 1 9 9 1 1 9 9 1 ack. by AD5697R repeated start by master ack. by AD5697R frame 4 most significant data byte n frame 3 slave address ack. by master nack. by AD5697R stop by master frame 4 most significant data byte n ? 1 frame 3 slave address significant data byte n 1000 1 a1 a0 r/w db15 db14 db13 db12 db11 db10 db9 db8 sda scl (continued) sda (continued) db7 db6 db5 db4 db3 db2 db1 db0 db15 db14 db13 db12 db11 db10 db9 db8 1 1253-046
data sheet AD5697R rev. 0 | page 21 of 28 power - down operation the AD5697R contain s three separate power - down mode s. command 0100 is designated for the power - down function (see table 7 ). thes e power - down modes are software programmable by setting eight bits, bit db7 to bit db0 , in the shift regi ster. there are two bits associated with each dac channel. table 10 shows how the state of the two bits corresponds to the mode of operation of the device. table 10 . modes of operation operating mode pdx1 pdx0 normal operation 0 0 power - down modes 1 k to gnd 0 1 100 k to gnd 1 0 three - state 1 1 either or both dacs (dac a and dac b ) can be powered down to the selected mode by setting th e corresponding bits . see table 11 for the contents of the input shift register during the power - down/ power - up operation. when both bit pd x 1 and bit pd x0 (where x is the channel selected) in the input shift register are set to 0, the part work s normally with its normal power consumption of 4 ma at 5 v. however, for the three power - down modes, the supply current falls to 4 a a t 5 v. not only does the supply current fall, but the output stage is also internally switch ed from the output of the amplifier to a resistor network of known values . this has the advantage that the output impedance of the part is known while the part is in power - down mode. there are three different power - down options. the output is connected int ernally to gnd through either a 1 k? or a 100 k? resistor, or it is left open - circuited (three - state). the output stage is illustrated in figure 46 . figure 46 . output stage during power - down the bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when the power - down mode is activated. however, the contents of the dac register are unaffe cted when in power - down. the dac register can be updated while the device is in power - down mode. the time required to exit power - down is typically 4.5 s for v dd = 5 v . to reduce the current consumption further , the on - chip reference can be powered off. se e the internal reference setup section. table 11 . 24- bit input shift register contents of power - down/power - up operation 1 db23 (msb ) db22 db21 db20 db19 to db16 db15 to db8 db7 db6 db5 db4 db3 db2 db1 db0 (lsb) 0 1 0 0 x x pd b1 pd b0 1 1 1 1 pda1 pda0 command bits (c3 to c0) address bits , d ont care power -d own , s elect dac b power -d own , s elect dac a 1 x = dont care. resis to r ne two rk v out x da c p ow er-d ow n ci rcu it ry amp lifi er 1 1253-047
AD5697R data sheet rev. 0 | page 22 of 28 load dac ( hardware ldac p in ) the AD5697R dacs have double buffered interfaces consisting of two banks of registers: input registers and dac registers. the user can write to any combination o f the input registers. updates to the dac register are controlled by the ldac pin. figure 47 . simplified diagram of input loading circuitry for a single dac instantaneous dac updating ( ldac held low ) ldac is held low while data is clocked into the inpu t register using command 0001 . both t he addressed input register and the dac register are updated on the 24th clock , and the output begins to change (see table 14 ). deferred dac updating ( ldac is pulsed low ) ldac is held high while data is clocked into the input register using command 0001 . both dac outputs are asynchronously updated by taking ldac low after the 24 th clock . the update t hen occurs on the falling edge of ldac . ldac mask register command 0101 is reserved for this software ldac mask function , which allows the a ddress bits to be ignored. writi ng to the dac u sing command 0101 loads the 4 - bit ldac register (db3 to db0 ). the default fo r each channel is 0; that is, the ldac pin works normally. setting the bits to 1 forces this dac channel to ignore transitions on the ldac pin, regardless of the state of the hardware ldac pin . this flexi bility is us e ful in applications where the user wishes to select which channels respond to the ldac pin . table 12. ldac overwrite definition load ldac register ldac bits (db3 or db0) ldac pin ldac operation 0 1 or 0 determined by the ldac pin. 1 x 1 dac channels update and override the ldac pin. dac channels see ldac pin as 1 . 1 x = dont care. the ldac register gives the user extra flexibility and control over the hardware ldac pin (see table 12 ). setting the ldac bits ( db3 or db0 ) to 0 for a dac channel means that th e update of the channel is controlled by the hardware ldac pin. table 13 . 24- bit input shift register contents for ldac operation 1 db 23 (msb) db22 db21 db20 db19 db18 db17 db16 dbb15 to db4 db3 db2 db1 db 0 (lsb) 0 0 0 1 x x x x x dac b 0 0 dac a command bits (c3 to c0) address bits , d ont care dont care setteing ldac to 1 overrides the ldac pin 1 x = dont care. table 14. write commands and ldac pin truth table 1 command description hardware ldac pin state input register contents dac register contents 0001 write to input register n ( d ependent on ldac ) v logic data u pdate no change (no update) gnd 2 data u pdate data u pdate 0010 update dac register n with contents of input register n v logic no c hange updated with i nput register contents gnd no c hange updated with i nput register contents 0011 write to and update dac channel n v logic data u pdate data u pdate gnd data u pdate data u pdate 1 a high - to - low hardware ldac pin transition always updates the contents of the dac register with the contents of the input register on channels that are n ot masked ( blocked) by the ldac mask register. 2 when the ldac pin is permanently tied low, the ldac mask bits are ignored. 1 1253-048 sdo scl v out dac register input shift register output amplifier ldac v ref input register 12-bit dac
data sheet AD5697R rev. 0 | page 23 of 28 hardware reset ( reset ) reset is an active low reset that allows the outputs to be cleared to either zero scale or midscale. the clear code value is user selectable via the power - on reset select ( rstsel ) pin . it is necessary to keep reset low for a minimum amount of time to complete the operation . when the reset signal is returned high , the output remains at the cleared value until a new value is programmed. the outputs cannot be updated with a new value while the reset pin is low. also, a software executable reset function can reset the dac to the p ower - on reset code. command 0110 is designated for this software reset function (see table 7 ). any events on ldac or reset during power - on reset are ignored . reset select p in (rstsel) the AD5697R contain s a power - on reset circuit that controls the output voltage durin g power - up. by connecting the r stsel pin low, the output powers up to zero scale. note that this is outside the line ar region of the dac; by connecting the rstsel pin high, v out powers up to midscale. the output remains powered up at this level until a valid write sequence is made to the dac. i nternal reference se tup command 0111 is reserved for setting up the internal reference (see table 7 ). by default, the on - chip reference is on at power - up. to reduce the supply current , this reference can b e turned off by setting the software - programmable bit, db0, as shown in table 16 . table 15 shows how the state of the bit corresponds to the mode of opera tion. table 15 . reference setup register internal reference setup register (db0) action 0 reference on (default) 1 reference off solder heat reflow as with all ic reference voltage circuits, the reference value experiences a shift induced by the soldering process. analog devices, inc., performs a reliability test called precondition to mimic the effect of soldering a device to a board. the outp ut voltage specification quoted in table 2 includes the effect of this reliability test. figure 48 shows the effect of solder heat reflow (shr) as measured through the reliability test (precondition). figure 48 . shr reference voltage shift l ong - term temperature d rift figure 49 shows the change in v ref value after 1000 h ou rs in life test at 150 c. figure 49 . reference drift through to 1000 hou rs table 16 . 24- bit input shift register contents for internal reference setup command 1 db23 (msb) db22 db21 db20 db19 db18 db17 db16 db15 to db1 db0 (lsb) 0 1 1 1 x x x x x 0/1 command bits (c3 to c0) address bits (a 3 to a0) dont care reference setup register 1 x = dont care. 60 0 10 20 30 40 50 2. 49 8 2. 49 9 2. 50 0 2. 50 1 2. 50 2 h it s v ref (v) posts ol der heat re flo w pres ol der heat re flo w 1 1253-049 60 0 10 20 30 40 50 2. 49 8 2. 49 9 2. 50 0 2. 50 1 2. 50 2 h it s v ref (v) 0 hour 168 ho ur s 500 ho ur s 1000 ho ur s 1 1253-050
AD5697R data sheet rev. 0 | page 24 of 28 thermal hysteresis thermal h ysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to c old , to hot , and then back to ambient. thermal h ysteresis data is shown in figure 50 . it is measured by sweeping temperature from ambient to ? 40 c, then to + 105 c, and returning to ambient. the v ref delt a is then measured between the two ambient measurements and shown in blue in figure 50. the same temperature sweep and measureme nts are immediately repeated , and the results are shown in red in figure 50 . figure 50 . thermal hysteresis 9 8 7 6 5 4 3 2 1 0 50 0 ?5 0 ?10 0 ?15 0 ?20 0 h it s dis to r tio n ( pp m) fi rs t t empe ra t ur e sweep s ub sequen t t empe ra t ur e sweeps 1 1253-051
data sheet AD5697R rev. 0 | page 25 of 28 applications informa tion microprocessor inter facing microprocessor interfacing to the AD5697R is via a serial bus that uses a standard protocol that is compatible with dsp proc essors and microcontrollers. the communications channel req uires a 2- wire interfa ce consisting of a clock signal and a data signal. AD5697R - to - adsp - bf531 interface the i 2 c interface of the AD5697R is designed to be easily connected to industry - standard dsps and microcontrollers. figure 51 shows the AD5697R connect ed to the analog devices blackfin? dsp ( adsp - bf531 ) . the blackfin has an integrated i 2 c port that can be connected directly to the i 2 c pins of the AD5697R . figure 51 . adsp - bf531 interface to the ad5338r layout guidelines in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. design t he printed circuit board ( pcb ) on which the AD5697R is mounted so that the AD5697R lie s on the analog plane. the AD5697R must have ample supply bypass ing of 10 f in parallel with 0.1 f on each supply , located a s close to the package as possible, ideally right up against the device. the 10 f capacitor is the tantalum bead type. the 0.1 f capacitor must have low effective series resistance (esr) and low effective series inductance (esi) , such as the common ceram ic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. in systems where there are many devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. the AD5697R lfcsp model ha s an exposed paddle beneath the device. connect this paddle to the gnd supply for the part. for optimum performance, use special considerations to design the motherboard and to mount the package. for enhanced thermal, electrical, and board level performance, solder the exposed paddle on the bottom of the package to the corresponding thermal land paddle on the pcb. design thermal via s into the pcb land paddle area to further improve heat dissipation. the gnd plane on the device can b e increased (as shown in figure 52 ) to provide a natural heat si nking effect. figure 52 . paddle connection to board galvanically isolate d interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common - mode voltages that may occur. i coupler? products from analog devices provide voltage isolation in excess of 2.5 kv. the serial loading structure of the AD5697R makes the part ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 53 shows a 4 - channel isolated interface to the AD5697R using the adum1400 . for further information, visit http://www.analog.com/icouplers . figure 53 . isolated interface adsp-bf531 scl gpio1 sda gpio2 ldac pf9 reset pf8 AD5697R 1 1253-052 AD5697R gnd plane board 1 1253-053 encode serial clock in controller adum1400 1 serial data out reset out load dac out decode to sclk to sdin to reset to ldac v ia v oa encode decode v ib v ob encode decode v ic v oc encode decode v id v od 1 additional pins omitted for clarity. 1 1253-054
AD5697R data sheet rev. 0 | page 26 of 28 outline dimensions figure 54 . 16 - lead lead frame chip scale package [lfcsp _wq ] 3 mm 3 mm body, very very thin quad (cp - 16 - 22 ) dimensions shown in millimeters figure 55 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters ordering guide model 1 resolution temperature range accuracy reference t emp erature coefficient (ppm/c) package description package option branding AD5697R bcpz - rl7 1 2 bits ? 40c to +105c 1 lsb inl 5 (max) 16 - lead lfcsp_wq cp -16 -22 d ky AD5697R bruz 12 bits ? 40c to +105c 1 lsb inl 5 (max) 16 - lead tssop ru -16 AD5697R bruz -rl7 12 bits ? 40c to +105c 1 lsb inl 5 (max) 16 - lead tssop ru -16 eval - AD5697Rsdz evaluation board 1 z = rohs compliant part. 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic at or 0.50 0.40 0.30 sea ting plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic at or for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab
data sheet AD5697R rev. 0 | page 27 of 28 notes
AD5697R data sheet rev. 0 | page 28 of 28 notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11253 -0- 2 /13(0)

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