1 may 5, 2014 short form datasheet IDT8V89317 10g ethernet pll and ieee 1588 synthesizer for industrial automa- idt and the idt logo are trademarks of integrated device technology, inc. ieee 1588 tm is a trademark of its respective owner ? 2014 integrated device technology, inc. idt confidential dsc-7238/- features highlights ? digital pll locks to gps or ethernet physical layer clocks ? provides clocks for 1 gigabi t and 10 gigabit ethernet, qsgmii and xaui ? internal digitally controlled oscill ator supports ieee 1588 clocks generation ? jitter generation <0.3ps rms ( 10 khz to 20 mhz), meets jitter requirements of leading phys supporting 10gbase-r, qsgmii and xaui main features ? digital pll synchronizes with gps or ethernet connected synchro - nization sources ? dpll bandwidth is selectable to be 15 mhz or 1.2 hz ? dpll holdover accuracy is 1.1x10-5 ppm and instantaneous hold - over accuracy is 4.4x10-8 ppm ? input references are monitored for frequency offset and activity ? dpll holdover, free run and hitless reference switching can be forced by the host processor or can be automatically controlled by an internal state machine ? internal dco has resolution of 0.01105 ppb and can be controlled by an external processor via i2 c interface for ieee 1588 clock gen - eration ? two analog plls for jitter attenuation and frequency translation ? in1, in2 and in3 accept single ended reference clocks whose fre - quencies can be 1pps (1 hz), 25 mhz, 125 mhz or 156.25 mhz ? out1 and out2 output differential clocks with frequencies of 125 mhz or 156.25 mhz ? out3 outputs a differential clock with frequency of ? 322.265625 mhz or 644.53125 mhz ? out4 outputs a free-running lvcmos clock with frequency of ? 25 mhz other features ? i2c microprocessor interface mode ? ieee 1149.1 jtag boundary scan ? 1mm ball pitch cabga green package applications ? industrial automation ? power systems figure 1. functional block diagram monitors apll microprocessor interface jtag input selector osci in1 in2 input pre-divider priority input pre-divider priority divider dpll/ dco out1_pos out1_neg out3_pos out3_neg i2c divider out2_pos out2_neg in3 input pre-divider priority apll1 (vcxo) out4 apll2 (vcxo) divider crystal crystal in_apll1_pos in_apll1_neg in_apll2_pos in_apll2_neg
description 2 may 5, 2014 IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthesizer for industrial automation and power systems IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthesizer for industrial automation and power systems idt confidential description the IDT8V89317 10g ethernet pll for industrial automation and power systems is used to synchr onize equipment with synchronization sources using the ethernet physical la yer, or with a 1 pps (1 hz) gps clock; it can also be used by exte rnal ieee 1588 clock recovery servos to synthesize ieee 1588 clocks. the IDT8V89317 ultra-low jitter output clocks can be used to directly sy nchronize 10gbase-r ethernet phys and xaui or qsgmii devices. the IDT8V89317 synchronization functi ons are provided by a digital pll (dpll) with an embedded clock synthesizer. the dpll accepts three single ended reference inputs that can operate at 1pps (1 hz), 25 mhz, 125 mhz or 156.25 mhz. the re ferences are continually moni - tored for loss of signal and for frequency offset per user programmed thresholds. the active reference for the dpll is determined by forced selection or by automatic selecti on based on user programmed priorities and locking allowances and based on the reference monitors. the dpll supports four primar y operating modes: free-run, locked, holdover and digitally contro lled oscillator (dco) control. in free-run mode the dpll generates a clock based on the master clock alone. in locked mode the dpll filters reference clock jitter with the selected bandwidth. in locked mode the long-term dpll frequency accuracy is the same as the long term frequency accuracy of the selected input reference. in hol dover mode the dpll uses frequency data acquired while in locked mode to generate accurate frequencies when input references are not avail able. in dco control mode the dpll control loop is opened and the dco can be used by an algorithm (e.g. ieee 1588 clock servo) running on an ex ternal processor to synthesize clock signals. the IDT8V89317 requires a 12.8 mhz master clock for its reference monitors and other digital circuitry. the frequency accuracy of the mas - ter clock determines the frequency accuracy of the dpll in free-run mode. the frequency stability of the master clock determines the fre - quency stability of the dpll in free-run mode and in holdover mode. the master clock must be sufficiently stable to support the selected dpll filtering bandwidth; in particula r, the 15 mhz bandwidth requires a very stable temperature compensated cr ystal oscillator (tcxo) or ove - nized crystal oscillator (ocxo). refer to the idt application note ?rec - ommended crystal oscillators for id t?s network synchronization wan- pll tm? for guidance. the dpll can be configured with a filtering bandwidth of 15 mhz or 1.2 hz. the 15 mhz bandwidth can be used to lock the dpll directly to a 1 pulse per second (pps) reference. 1.2 hz bandwidth can be used to lock to ethernet connected synchr onization sources operating at 25 mhz, 125 mhz or 156.25 mhz. the clock synthesized by the IDT8V89317 dpll is passed through two independent voltage controlled crystal oscillator (vcxo) based jitter attenuating analog plls (aplls). the aplls drive independent divid - ers that have differential outputs. the aplls use external crystal reso - nators with resonant frequencies equal to the apll base frequency divided by 25. the output clocks gener ated by the aplls exhibit jitter below 0.30ps rms over the integration range 10 khz to 20 mhz. the IDT8V89317 generates a 25 mhz single ended output that is based on the free running 12.8 mhz ma ster clock. the frequency accu - racy and the frequency stability of th is 25 mhz clock are determined by the master clock.
IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthesizer for industrial automation and power systems IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthes izer for industrial automation and power systems pin assignment 3 may 5, 2014 idt confidential 1 pin assignment figure 2. pin assignment (top view) i dt con f i d en t i al 1234567891011121314 a ic1 vdda xtal1_in cap1 in_apll1_n eg ic1 ic1 tdi ic1 ic2 osci tms ic1 trst a b ic1 vssa xtal1_out vssa in_apll1_p os ic1 ic1 tdo vssa tck vssa vssa vssdo vdddo b c ic1 vdda nc cap2 ic1 ic1 vdddo vssdo vdda vssa vdda vdda int_req ic1 c d vssa vssa cap3 vssa vdda ic1 vssd vddd ic1 vdda vssa vdda ic1 ic1 d e ic1 ic1 vssa vssa vssa ic3 vssd vddd ic1 vssa vdda vssa ic1 ic1 e f vddd vssd vssa vssa vdda vssa vssd vddd vssd vddd ic1 vdddo out4 vssdo f g vssd vddd vssa vssa vssa vssd vddd ic1 vddd vssd ic1 ic1 ic1 ic1 g h vddao vssao vddao vssao vssao vssao vssd vddd vssd vddd ic1 ic1 rst in1 h j out1_neg out1_pos vddao vssao vddao vssao vddao vssa vssa vdda dpll_lock ic1 in2 in3 j k vssao vssao vssao vddao vssao vddao vssao vssd vddd vssd ic1 ic1 i2c_scl i2c_sda k l out2_neg out2_pos vddao vssao vssao vssao vssao i2c_ad1 i2c_ad2 cap4 vssa cap5 vssa cap6 l m vddao vssao vssao vssao vddao vssao vddao vssa vssa vssa vssa nc ic ic m n vssao out3_pos vssao ic1 vssao in_apll2_p os ic2 ic2 vssa xtal2_out vssa ic1 vssa vssa n p vddao out3_neg vssao ic1 vddao in_apll2_n eg ic2 ic2 vdda xtal2_in vdda ic1 ic1 vdda p 1234567891011121314 diff ? outputs outputs inputs power ground key:
pin description 4 may 5, 2014 IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthesizer for industrial automation and power systems IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthes izer for industrial automation and power systems idt confidential 2 pin description table 1: pin description name pin no. i/o type description 1 global control signal osci a11 i cmos osci: crystal oscillator master clock a nominal 12.8000 mhz clock provided by a crystal oscillator is input on this pin. it is the master clock for the device. rst h13 i pull-up cmos rst: reset a low pulse of at least 50 s on this pin resets the device. after this pin is high, the device will still be held in reset state for 500 ms (typical). input clock in1 h14 i pull-down cmos in1: input clock 1 either a 1 pps, 25 mhz, 125 mhz or 156.25 mhz is input on this pin. in2 j13 i pull-down cmos in2: input clock 2 either a 1 pps, 25 mhz, 125 mhz or 156.25 mhz is input on this pin. in3 j14 i pull-down cmos in3: input clock 3 either a 1 pps, 25 mhz, 125 mhz or 156.25 mhz is input on this pin. in_apll1_pos in_apll1_neg b5 a5 i pull-down i pull-up/ pull-down lvpecl/ lvds in_apll1_pos / in_apll1_n eg: input clock to apll1 direct input clock to apll1. in_apll2_pos in_apll2_neg n6 p6 i pull-down i pull-up/ pull-down lvpecl/ lvds in_apll2_pos / in_apll2_neg: input clock apll2 direct input clock to apll2. output clock out1_pos out1_neg j2 j1 o lvpecl out1_pos / out1_neg: positive / negative output clock 1 a clock is differentially output on this pair of pins. it outputs either 125 mhz or 156.25 mhz out2_pos out2_neg l2 l1 o lvpecl out2_pos / out2_neg: positive / negative output clock 2 a clock is differentially output on this pair of pins. it outputs either 125 mhz or 156.25 mhz out3_pos out3_neg n2 p2 o lvpecl out3_pos / out3_neg: positive / negative output clock 3 a clock is differentially output on this pair of pins. it outputs 322.265625 mhz or 644.53125 mhz out4 f13 o cmos 0ut4: cmos output clock 4 a free run 25 mhz clock is output on this pin. miscellaneous cap1, cap2, cap3, cap4, cap5, cap6 a4, c4, d3, l10, l12, l14 output analog cap1 ~ cap6: analog power filter capacitor connection 1 to 6 connect a 10 uf capacitor in parallel with a low esr 100 nf capacitor between these pins and vss1 xtal1_in a3 input analog crystal 1 oscillator input. crystal oscillator input for apll. xtal1_out b3 output analog crystal 1oscillator output. crystal oscillator output for apll. xtal2_in p10 input analog crystal 2 oscillator input. crystal oscillator input for apll. xtal2_out n10 output analog crystal 2 oscillator output. crystal oscillator output for apll. lock indication signals
pin description 5 may 5, 2014 IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthesizer for industrial automation and power systems IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthes izer for industrial automation and power systems idt confidential dpll_lock j11 o cmos dpll lock indicator. this pin goes high when dpll is locked. microprocessor interface int_req c13 o cmos int_req: interrupt request this pin is used as an interrupt request. the output characteristics are determined by the hz_en bit (b1, 0ch) and the int_pol bit (b0, 0ch). i2c_scl k13 i open drain i2c_scl: serial clock line in i2c mode, the serial clock is input on this pin. i2c_sda k14 i/o open drain i2c_sda: serial data input/output in i2c mode, this pin is used as the input/output for the serial data. i2c_ad1 l8 i pull-up cmos i2c_ad1: device address bit 1 in i2c mode, i2c_ad[2:0] pins are the address bus of the microprocessor interface. i2c_ad2 l9 i pull-up cmos i2c_ad2: device address bit 2 in i2c mode, i2c_ad[2:0] pins are the address bus of the microprocessor interface. jtag (per ieee 1149.1) trst a14 i pull-down cmos trst: jtag test reset (active low) a low signal on this pin resets the jtag test port. this pin should be connected to ground when jtag is not used. tms a12 i pull-up cmos tms: jtag test mode select the signal on this pin controls the jtag test performance and is sampled on the rising edge of tck. tck b10 i pull-down cmos tck: jtag test clock the clock for the jtag test is input on this pin. tdi and tms are sampled on the rising edge of tck and tdo is updated on the falling edge of tck. if tck is idle at a low level, all stored-state devices contained in the test logic will indef - initely retain their state. tdi a8 i pull-up cmos tdi: jtag test data input the test data is input on this pin. it is clocked into the device on the rising edge of tck. tdo b8 o cmos tdo: jtag test data output the test data is output on this pin. it is clocked out of the device on the falling edge of tck. tdo pin outputs a high impedance signal except during the process of data scanning. this pin can indicate the interrupt of dpll selected input clock fail, as determined by the los_flag_on_tdo bit (b6, 0bh). power & ground vddd d8, e8, f1, f8, f10, g2, g7, g9, h8, h10, k9 power - digital core power - +3.3v dc nominal vdddo b14, c7, f12 power digital output power - +3.3v dc nominal vdda a2, c2, c9, c11, c12, d5, d10, d12, e11, f5, j10, p9, p11, p14 power analog core power - +3.3v dc nominal vddao h1, h3, j3, j5, j7, k4, k6, l3, m1, m5, m7, p1, p5 power analog output power - +3.3v dc nominal vssd d7, e7, f2, f7, f9, g1, g6, g10, h7, h9, k8, k10 ground - ground vssdo b13, c8, f14 ground - ground table 1: pin description (continued) name pin no. i/o type description 1
pin description 6 may 5, 2014 IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthesizer for industrial automation and power systems IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthes izer for industrial automation and power systems idt confidential 2.1 recommendations for unused input and output pins 2.1.1 inputs control pins all control pins have internal pul l-ups or pull-downs ; additional resis - tance is not required but can be added for additional protection. a 1 k resistor can be used. single-ended clock inputs for protection, unused single-ended clock inputs should be tied to ground. differential clock inputs for applications not requiring the use of a differential input, both *_pos and *_neg can be left floating. though not required, but for additional protection, a 1 k resistor can be tied from _pos to ground. xtal inputs for applications not requiring the use of a crystal oscillator input, both _in and _out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from _in to ground. 2.1.2 outputs status pins for applications not requiring the use of a status pin, we recommend bringing out to a test point for debugging purposes. single-ended clock outputs all unused single-ended clock outputs can be left floating, or can be brought out to a test point for debugging purposes. differential clock outputs all unused differential outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. vssa b2, b4, b9, b11, b12, c10, d1, d2, d4, d11, e3, e4, e5, e10, e12, f3, f4, f6, j9, g3, g4, g5, j8, l11, l13, m8, m9, m10, m11, n9, n11, n13, n14 ground - analog ground vssao h2, h4, h5, h6, j4, j6, k1, k2, k3, k5,k7, l4, l5, l6, l7, m2, m3, m4, m6, n1, n3, n5, p3 ground - analog output ground others ic1 a1, a6, a7, a9, a13, b1, b6, b7, c1, c5, c6, c14, d6, d9, d13, d14, e1, e2, e9, e13, e14, f11, g8, g11, g12, g13, g14, h11, h12, j12, k11, k12, m13, m14, n4, n12, p4, p12, p13 - - ic1: internal connection internal use. these pins should be left open for normal operation. ic2 a10, n7, n8, p7, p8 - - ic2: internal connection internal use. these pins should be left open for normal operation. ic3 e6 - - ic3: internal connection internal use. this pin should be left open for normal operation. nc c3, m12 - - nc: not connected these pins should be left open for normal operation. note: 1. all the unused input pins should be connected to ground; the output of all the unused output pins are don?t-care. table 1: pin description (continued) name pin no. i/o type description 1
7 may 5, 2014 IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthesizer for industrial automation and power systems IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthes izer for industrial automation and power systems idt confidential package dimensions figure 3. 196-pin bag package dimensions
8 may 5, 2014 IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthesizer for industrial automation and power systems IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthes izer for industrial automation and power systems idt confidential ordering information revision history xxxxxxx xx x device type blank process / temperature range industrial (-40 c to +85 c) ba 196 ball 15mmx15mm cabga package g green x 8v89317
9 may 5, 2014 disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at id t?s sole discretion. all information in this doc- ument, including descriptions of product feat ures and performance, is subject to cha nge without notice. performance specificati ons and the operating parameters of the described products are deter mined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provide d without representation or warranty of any ki nd, whether express or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an implied warranty of merchantability, or non-infrin gement of the intellectual propert y rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the fail ure or malfunction of an idt pr oduct can be reasonably expected to significantly affect the health or safety of users. anyone us ing an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2014. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support tsd@idt.com +480-763-2056 we?ve got your timing solution IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthesizer for industrial automation and power systems IDT8V89317 datasheet 10g ethernet pll and ieee 1588 synthes izer for industrial automation and power systems
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