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tinypower tm a/d flash mcu with lcd & eeprom HT67F60A ht67f70a revision: v1.10 date: de?e??e? 01? ?01? de?e??e? 01? ?01?
rev. 1.10 ? de?e??e? 01? ?01? rev. 1.10 3 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom table of contents eates cpu featu?es ......................................................................................................................... 7 pe?iphe?al featu?es ................................................................................................................. 7 gene?al des??iption ......................................................................................... 8 sele?tion ta?le ................................................................................................. 9 blo?k diag?a? .................................................................................................. 9 pin assign?ent .............................................................................................. 10 pin des??iptions ............................................................................................ 13 a?solute maxi?u? ratings .......................................................................... 19 d.c. cha?a?te?isti?s ....................................................................................... ?0 a.c. cha?a?te?isti?s ....................................................................................... ?? a/d conve?te? cha?a?te?isti?s ...................................................................... ?3 lvd/lvr ele?t?i?al cha?a?te?isti?s .............................................................. ?3 co?pa?ato? ele?t?i?al cha?a?te?isti?s ........................................................ ?4 lcd d?ive? ele?t?i?al cha?a?te?isti?s .......................................................... ?4 powe?-on reset cha?a?te?isti?s ................................................................... ?4 syste? a??hite?tu?e ...................................................................................... ?5 clo?king and pipelining ......................................................................................................... ?5 p?og?a? counte? ................................................................................................................... ?? sta?k ..................................................................................................................................... ?7 a?ith?eti? and logi? unit C alu ........................................................................................... ?7 flash p?og?a? me?o?y ................................................................................. ?8 st?u?tu?e ................................................................................................................................ ?8 spe? ial ve?to?s ..................................................................................................................... ?8 look-up ta ?le ........................................................................................................................ ?9 ta ?le p?og?a? exa?ple ........................................................................................................ ?9 in ci??uit p?og?a??ing C icp ............................................................................................... 30 on-chip de?ug suppo?t C ocds ......................................................................................... 31 in appli ?ation p?og?a??ing C iap ........................................................................................ 31 data me?o?y .................................................................................................. 40 st?u?tu?e ................................................................................................................................ 40 data me ?o?y add?essing ...................................................................................................... 41 gene?al pu?pose data me?o?y ............................................................................................ 41 spe?ial pu?pose data me?o?y ............................................................................................. 41
rev. 1.10 ? de?e??e? 01? ?01? rev. 1.10 3 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom special function register description ........................................................ 43 indi?e? t add?essing registe?s C iar0? iar1? iar? ............................................................... 43 me?o?y pointe?s C mp0? mp1h/mp1l? mp?h/mp?l ........................................................... 43 bank pointe? C bp ................................................................................................................. 45 a??u?ulato? C acc ............................................................................................................... 45 p?og?a? counte? low registe? C pcl .................................................................................. 4? look-up ta ? le registe? s C tblp ? tbhp ? tblh ..................................................................... 4? status registe? C status .................................................................................................... 4? eeprom data memory .................................................................................. 48 eeprom data me?o?y st?u?tu?e ........................................................................................ 48 eeprom registe?s .............................................................................................................. 48 reading data f?o? the eeprom ......................................................................................... 50 w ?iting data to the eeprom ................................................................................................ 50 w ?ite p?ote?tion ..................................................................................................................... 50 eeprom inte??upt ................................................................................................................ 50 p?og?a??ing conside?ations ................................................................................................ 51 oscillator ........................................................................................................ 52 os?illato? ove?view ............................................................................................................... 5? system clock confgurations ................................................................................................ 5? exte?nal c?ystal/ce?a?i? os?illato? C hxt ........................................................................... 53 inte?nal high speed rc os?illato? C hirc ........................................................................... 54 exte?nal 3?.7?8 khz c?ystal os?illato? C lxt ....................................................................... 54 inte?nal 3?khz os?illato? C lirc ........................................................................................... 5? supple?enta?y os?illato?s .................................................................................................... 5? operating modes and system clocks ......................................................... 56 syste? clo?ks ...................................................................................................................... 5? syste? ope?ation modes ...................................................................................................... 57 cont?ol registe?s .................................................................................................................. 59 fast wake-up ........................................................................................................................ ?1 ope?ating mode swit?hing .................................................................................................... ?? stand?y cu??ent conside?ations ........................................................................................... ?? wake-up ................................................................................................................................ ?7 watchdog timer ............................................................................................. 68 wat ? hdog ti?e? clo?k sou??e .............................................................................................. ?8 wat ? hdog ti?e? cont?ol registe? ......................................................................................... ?8 wat ? hdog ti?e? ope?ation ................................................................................................... ?9 reset and initialisation .................................................................................. 70 reset fun?tions .................................................................................................................... 71 reset initial conditions ......................................................................................................... 75
rev. 1.10 4 de?e??e? 01? ?01? rev. 1.10 5 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom input/output ports ......................................................................................... 80 pull-high resisto?s ................................................................................................................ 81 po? t a wake-up ..................................................................................................................... 81 i/o po?t cont?ol registe?s ..................................................................................................... 81 pin-sha?ed fun?tions ............................................................................................................ 81 i/o pin st?u?tu?es .................................................................................................................. 91 p?og?a??ing conside?ations ................................................................................................ 9? timer modules C tm ...................................................................................... 93 int?odu?tion ........................................................................................................................... 93 tm ope?ation ........................................................................................................................ 93 tm clo?k sou??e ................................................................................................................... 94 tm inte??upts ......................................................................................................................... 94 tm exte?nal pins ................................................................................................................... 94 tm input/output pin cont?ol registe? ................................................................................... 95 p?og?a??ing conside?ations ................................................................................................ 9? compact type tm C ctm .............................................................................. 97 co?pa? t tm ope?ation ......................................................................................................... 97 co?pa? t type tm registe? des??iption ................................................................................ 97 co?pa? t type tm ope? ation modes .................................................................................. 10? standard type tm C stm ............................................................................ 108 standa? d tm ope?ation ....................................................................................................... 108 standa? d type tm registe? des??iption ............................................................................. 109 standa? d type tm ope? ation modes ................................................................................... 113 enhanced type tm C etm ........................................................................... 123 enhan? ed tm ope?ation ..................................................................................................... 1?3 enhan? e type tm registe? des??iption .............................................................................. 1?4 enhan? ed type tm ope? ation modes ................................................................................. 130 analog to digital converter ........................................................................ 147 a/d ove?view ...................................................................................................................... 147 a/d conve?te? registe? des??iption .................................................................................... 148 a/d ope?ation ..................................................................................................................... 150 a/d input pins ..................................................................................................................... 151 conve? sion rate and ti?ing diag?a? ................................................................................ 15? su??a? y of a/d conve?sion steps ..................................................................................... 15? p?og?a??ing conside?ations .............................................................................................. 153 a/d t ?ansfe? fun?tion ......................................................................................................... 153 a/d p?og?a??ing exa?ples ............................................................................................... 154 comparators ................................................................................................ 156 co?pa?ato? ope?ation ........................................................................................................ 15? co?pa?ato? registe?s ......................................................................................................... 15? co?pa?ato? inte??upt ........................................................................................................... 158 p?og?a??ing conside?ations .............................................................................................. 158
rev. 1.10 4 de?e??e? 01? ?01? rev. 1.10 5 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom serial interface module C sim ..................................................................... 159 spi inte?fa?e ....................................................................................................................... 159 i ? c inte?fa?e ........................................................................................................................ 1?5 peripheral clock output .............................................................................. 175 pe?iphe?al clo?k ope?ation ................................................................................................. 175 pe?iphe?al clo?k registe?s .................................................................................................. 175 serial interface C spia ................................................................................. 176 spia inte ?fa?e ope?ation .................................................................................................... 17? spia registe ?s .................................................................................................................... 177 spia co ??uni?ation .......................................................................................................... 180 spia bus ena ?le/disa?le .................................................................................................... 18? spia ope ?ation ................................................................................................................... 183 e??o? dete?tion .................................................................................................................... 184 lcd driver .................................................................................................... 185 lcd me?o?y ....................................................................................................................... 18? lcd clo?k sou??e ............................................................................................................... 187 lcd registe?s ..................................................................................................................... 187 lcd voltage sou ??e biasing ............................................................................................... 189 lcd d?ive? output ............................................................................................................... 190 p?og?a??ing conside?ations .............................................................................................. 193 interrupts ...................................................................................................... 194 inte??upt registe?s ............................................................................................................... 194 inte??upt ope?ation .............................................................................................................. ?05 exte?nal inte??upt ................................................................................................................. ?07 co?pa?ato? inte??upt ........................................................................................................... ?07 a/d conve?te? inte??upt ....................................................................................................... ?07 ti ?e base inte??upt ............................................................................................................. ?08 multi-fun?tion inte??upt ........................................................................................................ ?10 se?ial inte?fa?e module inte??upt ......................................................................................... ?10 spia inte ?fa?e inte??upt ....................................................................................................... ?10 exte?nal pe?iphe?al inte??upt ................................................................................................ ? 11 lvd inte ??upt ........................................................................................................................ ? 11 eeprom inte??upt ............................................................................................................... ? 11 tm inte??upt ......................................................................................................................... ?1? inte?? upt wake-up fun?tion ................................................................................................. ?1? p?og?a??ing conside?ations .............................................................................................. ?1? low voltage detector C lvd ....................................................................... 213 lvd registe ? ....................................................................................................................... ?13 lvd ope ?ation ..................................................................................................................... ?14 confguration options ................................................................................. 215 application circuits ..................................................................................... 215
rev. 1.10 ? de?e??e? 01? ?01? rev. 1.10 7 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom instruction set .............................................................................................. 216 int?odu?tion ......................................................................................................................... ?1? inst?u? tion ti?ing ................................................................................................................ ?1? moving and t ?ansfe??ing data ............................................................................................. ?1? a?ith?eti? ope?ations .......................................................................................................... ?1? logi?al and rotate ope?ation ............................................................................................. ?17 b?an?hes and cont? ol t ?ansfe? ........................................................................................... ?17 bit ope?ations ..................................................................................................................... ?17 ta ?le read ope?ations ....................................................................................................... ?17 othe? ope?ations ................................................................................................................. ?17 instruction set summary ............................................................................ 218 ta ?le conventions ............................................................................................................... ?18 extended inst?u?tion set ..................................................................................................... ??0 instruction defnition ................................................................................... 222 ([whqghg,qvwuxfwlrqhqlwlrq ........................................................................................... ?31 package information ................................................................................... 238 48-pin lqfp (7 ?? 7??) outline di?ensions ................................................................ ?39 ? 4-pin lqfp (7?? 7??) outline di?ensions ................................................................ ?40 80-pin lqfp (10 ?? 10??) outline di?ensions ............................................................ ?41
rev. 1.10 ? de?e??e? 01? ?01? rev. 1.10 7 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom features cpu features ? operating voltage f sys = 8mhz : 2.2v ~ 5.5v f sys = 12mhz : 2.7v ~ 5.5v f sys =20mhz : 4.5v ~ 5.5v ? up to 0.2s instruction cycle with 20mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? oscillator type external crystal C hxt external 32.768khz crystal C lxt high speed internal rc C hirc low speed internal 32khz rc C lirc ? fully integrated internal 4/8/12mhz oscillator requires no external components ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one to three instruction cycles ? table read instructions ? 115 powerful instructions ? up to 16-level subroutine nesting ? bit manipulation instruction peripheral features ? program memory: 16k 16 ~ 32k 16 ? data memory: 1024 8 ~ 2048 8 ? true eeprom memory: 128 8 ? in application programming function C iap ? watchdog timer function ? up to 47 bidirectional i/o lines ? multiple pin-shared external interrupts ? multiple timer modules for time measure, input capture, compare match output, pwm output function or single pulse output function ? serial interfaces module C sim for spi or i 2 c ? single serial peripheral interface C spia ? dual comparator functions ? dual time-base functions for generation of fxed time interrupt signals ? 12-channel 12-bit resolution a/d converter ? low voltage reset function ? low voltage detect function ? wide range of available package types ? flash program memory can be re-programmed up to 100,000 times
rev. 1.10 8 de?e??e? 01? ?01? rev. 1.10 9 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ? flash program memory data retention > 10 years ? true eeprom data memory can be re-programmed up to 1,000,000 times ? true eeprom data memory data retention > 10 years general description the series of devices are lcd type flash memory 8-bit high performance risc architecture microcontroller which is designed for a wide range of applications. offering users the convenience of flash memory multi-programming features, these devices also include a wide range of functions and features. other memory includes an area of ram data memory as well as an area of true eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter and dual comparator functions. multiple and extremely flexible timer modules provide timing, pulse generation and pwm generation functions. communication with the outside world is catered for by including fully integrated spi or i 2 c interface functions, two popular interfaces which provide designers with a means of easy communication with external peripheral hardware. protective features such as an internal watchdog timer, low voltage reset and low voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of hxt, lxt, hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. the inclusion of fexible i/o programming features, time-base functions along with many other features ensure that the devices will fnd excellent use in applications such as electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others.
rev. 1.10 8 de?e??e? 01? ?01? rev. 1.10 9 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom selection table most features are common to all devices. the main features distinguishing them are program memory and data memory capacity. the following table summarises the main features of each device. part no. program memory data memory data eeprom i/o external interrupt a/d converter timer module ht?7f?0a 1?k 1? 10?4 8 1?8 8 47 4 1?-?it 1? 10-?it ctm ? 1?-?it stm 3 10-?it etm 1 ht?7f70a 3?k 1? ?048 8 1?8 8 47 4 1?-?it 1? 10-?it ctm ? 1?-?it stm 3 10-?it etm 1 part no. sim spia time base comp. lcd driver stacks package ht?7f?0a ? ? 5? 4 1? 48/?4/80 lqfp ht?7f70a ? ? 5? 4 1? 48/?4/80 lqfp note: as devices exist in more than one package format, the table reflects the situation for the package with the most pins. block diagram 8-bit risc mcu core i/o timer modules flash program memory eeprom data memory flash/eeprom programming circuitry (ocds/icp) time base sim (spi/i 2 c) low voltage reset watchdog timer low voltage detect interrupt controller reset circuit external hxt/lxt oscillators 12-bit a/d converter ram data memory iap spia internal rc oscillators lcd driver comparators
rev. 1.10 10 de?e??e? 01? ?01? rev. 1.10 11 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pin assignment HT67F60A/ht67f70a ht67v60a/ht67v70a 48 lqfp-a 13 14 15 1? 17 18 19 ?0 ?1 ?? ?3 ?4 1 ? 3 4 5 ? 7 8 9 10 11 1? 3? 35 34 33 3? 31 30 ?9 ?8 ?7 ?? ?5 37 38 39 40 41 4? 43 44 45 4? 47 48 pa7/int1/stp0/stp0i/an7 vdd pb1/xt1/scka/an9 vss pb?/osc1/int?/stck0/an10 pb3/osc?/int3/ctp1/an11 plcd/vmax com0 com1 pa?/int0/etck/an? com? pb0/xt?/scsa/ctck1/an8 s e g 3 ? s e g 3 7 s e g 4 5 s e g 4 ? s e g 4 7 s e g 4 8 s e g 4 9 c o m 3 s e g 3 5 s e g 3 4 s e g 3 3 s e g 3 ? p f 5 / s e g ? 9 p f ? / s e g 3 0 p f 7 / s e g 3 1 pe1/seg17/sdia/stp1/stp1i pe?/seg18 pe3/seg19 pe4/seg?0 pe5/seg?1 pe?/seg?? pe7/seg?3 pe0/seg1?/sdoa/stck1 p f 4 / s e g ? 8 p d 5 / s e g 1 3 / i n t ? / c t p 0 / c 0 p p a 1 / s d o / c t p 0 / a n 0 p a 3 / s d i / s d a / c t c k 0 / a n 1 / v r e f p a ? / a n 4 / i c p c k / o c d s c k p a 0 / a n 5 / i c p d a / o c d s d a p d 1 / s e g 9 / s c k / s c l / e t c k / c 1 p pd?/seg10/sdi/s da/etpb/etpib pd3/seg11/sdo/c1n pd4/seg1?/int3/ctck0 /etpa/etpia/c1x p a 5 / s c s / e t p b / e t p i b / a n 3 p c 0 / s e g 0 / c 1 p / r e s p a 4 / s c k / s c l / e t p a / e t p i a / a n ? / p i n t
rev. 1.10 10 de?e??e? 01? ?01? rev. 1.10 11 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a ht67v60a/ht67v70a 64 lqfp-a 1 ? 3 4 5 ? 7 8 9 10 11 1? 13 ?0 ?1 ?? ?3 ?4 ?5 ?? ?7 ?8 ?0 ?1 ?? ?3 ?4 ?9 30 31 3? 5? 53 54 55 5? 57 58 59 14 15 1? 43 44 45 4? 47 48 3? 37 38 39 40 41 4? 33 34 35 17 18 19 5? 53 54 p c 5 / s e g 5 / s d i a / c t c k 1 / c 0 x p a 1 / s d o / c t p 0 / a n 0 p a 3 / s d i / s d a / c t c k 0 / a n 1 / v r e f p a ? / a n 4 / i c p c k / o c d s c k p a 0 / a n 5 / i c p d a / o c d s d a pd4/seg1?/int3/ctck0 /etpa/etpia/c1x p a 5 / s c s / e t p b / e t p i b / a n 3 p d 0 / s e g 8 / s c s / s t p 0 / s t p 0 i p c ? / s e g ? / s c k a / c t p 1 p c 4 / s e g 4 / s d o a / s t p 1 / s t p 1 i p c 3 / s e g 3 / s t c k 1 / c 0 p / p c k p c ? / s e g ? / s t p ? / s t p ? i / c 1 x p c 1 / s e g 1 / s t c k ? / c 1 n / p i n t p a 4 / s c k / s c l / e t p a / e t p i a / a n ? / p i n t p c 7 / s e g 7 / s c s a / s t c k 0 / c 0 n p c 0 / s e g 0 / c 1 p / r e s p f 1 / s e g ? 5 p f ? / s e g ? ? p f 3 / s e g ? 7 pe1/seg17/sdia/stp1/stp1i pe?/seg18 pe3/seg19 pe4/seg?0 pe5/seg?1 pe?/seg?? pe7/seg?3 pe0/seg1?/sdoa/stck1 p f 0 / s e g ? 4 p f 5 / s e g ? 9 p f ? / s e g 3 0 p f 7 / s e g 3 1 p f 4 / s e g ? 8 s e g 3 ? s e g 3 7 s e g 4 0 s e g 4 1 s e g 4 ? s e g 4 3 s e g 4 4 c o m 3 com? s e g 3 5 s e g 3 4 s e g 3 3 s e g 3 ? s e g 4 5 s e g 3 8 s e g 3 9 pa7/int1/stp0/stp0i/an7 vdd pb1/xt1/scka/an9 vss pb?/osc1/int?/stck0/an10 pb3/osc?/int3/ctp1/an11 plcd com0 com1 pa?/int0/etck/an? pb0/xt?/scsa/ctck1/an8 vmax v1 pb4/v? pb5/c1 pb?/c?
rev. 1.10 1? de?e??e? 01? ?01? rev. 1.10 13 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a ht67v60a/ht67v70a 80 lqfp-a p f 1 / s e g ? 5 p f ? / s e g ? ? p f 3 / s e g ? 7 pe1/seg17/sdia/stp1/stp1i pe?/seg18 pe3/seg19 pe4/seg?0 pe5/seg?1 pe?/seg?? pe7/seg?3 pe0/seg1?/sdoa/stck1 p f 0 / s e g ? 4 p f 5 / s e g ? 9 p f ? / s e g 3 0 p f 7 / s e g 3 1 p f 4 / s e g ? 8 pd5/seg13/int?/ctp0/c0p pd?/seg14/int1/stck?/c0n pd7/seg15/int0/s tp?/stp?i/c0x s e g 3 ? s e g 3 ? s e g 3 7 s e g 4 0 s e g 4 1 s e g 4 ? s e g 4 3 s e g 4 4 s e g 5 1 seg5? s e g 3 5 s e g 3 4 s e g 3 3 s e g 4 5 s e g 3 8 s e g 3 9 s e g 4 9 seg50 s e g 4 8 s e g 4 7 s e g 4 ? pa7/int1/stp0/stp0i/an7 vdd pb1/xt1/scka/an9 vss pb3/osc?/int3/ctp1/an11 plcd com0 com1 pa?/int0/etck/an? pb0/xt?/scsa/ctck1/an8 vmax v1 pb4/v? pb5/c1 pb?/c? seg54 seg53 seg55 com? com3 pb?/osc1/int?/stck0/an10 p c 5 / s e g 5 / s d i a / c t c k 1 / c 0 x p a 1 / s d o / c t p 0 / a n 0 p a 3 / s d i / s d a / c t c k 0 / a n 1 / v r e f p a ? / a n 4 / i c p c k / o c d s c k p a 0 / a n 5 / i c p d a / o c d s d a pd4/seg1?/int3/ctck0/etpa/etpia/c1x p a 5 / s c s / e t p b / e t p i b / a n 3 p d 0 / s e g 8 / s c s / s t p 0 / s t p 0 i p c ? / s e g ? / s c k a / c t p 1 p c 4 / s e g 4 / s d o a / s t p 1 / s t p 1 i p c 3 / s e g 3 / s t c k 1 / c 0 p / p c k p c ? / s e g ? / s t p ? / s t p ? i / c 1 x p a 4 / s c k / s c l / e t p a / e t p i a / a n ? / p i n t p d 1 / s e g 9 / s c k / s c l / e t c k / c 1 p pd?/seg10/sdi/sda/etpb/etpib pd3/seg11/sdo/c1n p c 7 / s e g 7 / s c s a / s t c k 0 / c 0 n p c 1 / s e g 1 / s t c k ? / c 1 n / p i n t p c 0 / s e g 0 / c 1 p / r e s 47 4? 45 44 43 4? 41 1 ? 3 4 5 ? 7 8 9 10 11 1? 13 14 15 1? 17 18 19 ?0 ?1 ?? ?3 ?4 ?5 ?? ?7 ?8 ?9 30 31 3? 33 34 35 3? 3738 39 40 80 79 78 77 7? 75 74 73 7? 71 70 ?9 ?8 ?7 ?? ?5 ?4?3 ?? ?1 ?0 59 58 57 5? 55 54 53 5? 51 40 49 48 note: 1. for 48 lqfp package type, only the r type bias lcd driver can be used. 2. if the pin-shared pin functions have multiple outputs simultaneously, the desired pin-shared function is determined by the corresponding software control bits except the functions determined by the confguration options. 3. the ocdsda and ocdsck pins are the ocds dedicated pins and only available for the ht67vx0a device. the ht67vx0a device is the ocds ev chip of the ht67fx0a series of devices. it supports the on-chip debug function for debugging during development using the ocdsda and ocdsck pins connected to the holtek ht_ide development tools.
rev. 1.10 1? de?e??e? 01? ?01? rev. 1.10 13 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pin descriptions with the exception of the power pins and some relevant transformer control pins, all pins on these devices can be referenced by their port name, e.g. pa.0, pa.1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, timer module pins etc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. pad name function opt i/t o/t description pa0/an5/icpda/ ocdsda pa0 pawu papu pas0 st cmos gene ? al pu? pose i/o. registe? ena? led pull-up and wake-up. an5 pas0 an a/d conve?te? analog input icpda st cmos icp data/add ?ess ocdsda st cmos ocds data/add?ess? fo? ev ? hip only. pa1/sdo/ctp0/ an0 pa1 pawu papu pas0 st cmos gene ? al pu? pose i/o. registe? ena? led pull-up and wake-up. sdo pas0 cmos spi data output ctp0 pas0 cmos ctm0 output an0 pas0 an a/d conve?te? analog input pa ?/an4/icpck/ ocdsck pa ? pawu papu pas0 st cmos gene ? al pu? pose i/o. registe? ena? led pull-up and wake-up. an4 pas0 an a/d conve?te? analog input icpck st cmos icp clo ?k pin ocdsck st ocds clo?k pin? fo? ev ? hip only. pa3/sdi/sda/ ctck0/an1/ vref pa3 pawu papu pas0 st cmos gene ? al pu? pose i/o. registe? ena? led pull-up and wake-up. sdi pas0 ifs3 st spi data input sda pas0 ifs3 st nmos i ? c data line ctck0 pas0 ifs1 st ctm0 input an1 pas0 an a/d conve?te? analog input vref pas0 an a/d conve?te? ?efe?en?e input pa4/sck/scl/ etpa/etpia/ an?/ pint pa4 papu pawu pas1 st cmos gene ? al pu? pose i/o. registe? ena? led pull-up and wake-up. sck pas1 ifs3 st cmos spi se?ial ?lo?k scl pas1 ifs3 st nmos i ? c ?lo?k line etpa pas1 cmos etm a output etpia pas1 ifs1 st etm a input an? pas1 an a/d conve?te? analog input pint pas1 ifs0 st pe?iphe?al inte??upt
rev. 1.10 14 de?e??e? 01? ?01? rev. 1.10 15 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pad name function opt i/t o/t description pa5/ scs /etpb/ etpib/an3 pa5 pawu papu pas1 st cmos gene ? al pu? pose i/o. registe? ena? led pull-up and wake-up. scs pas1 ifs3 st cmos spi slave sele?t etpb pas1 cmos etm b output etpib pas1 ifs1 st etm b input an3 pas1 an a/d conve?te? analog input pa ?/int0/etck/ an? pa ? pawu papu pas1 st cmos gene ? al pu? pose i/o. registe? ena? led pull-up and wake-up. int0 pas1 integ intc0 ifs0 st exte?nal inte??upt 0 etck pas1 ifs1 st etm input an? pas1 an a/d conve?te? analog input pa7/int1/stp0/ stp0i/an7 pa7 pawu papu pas1 st cmos gene ? al pu? pose i/o. registe? ena? led pull-up and wake-up. stp0 pas1 cmos stm0 output stp0i pas1 ifs1 st stm0 input an7 pas1 an a/d conve?te? analog input pb0/xt?/ scsa / ctck1/an8 pb0 pbpu pbs0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up xt? co lxt lxt os ?illato? pin scsa pbs0 ifs3 st cmos spia slave sele ?t ctck1 pbs0 ifs? st ctm1 input an8 pbs0 an a/d conve?te? analog input pb1/xt1/scka/ an9 pb1 pbpu pbs0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up xt1 co lxt lxt os ?illato? pin scka pbs0 ifs3 st cmos spia se ?ial ?lo?k an9 pbs0 an a/d conve?te? analog input pb?/osc1/int?/ stck0/an10 pb? pbpu pbs0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up osc1 co hxt hxt os ?illato? pin int? pbs0 integ intc3 ifs0 st exte?nal inte??upt ? stck0 pbs0 ifs1 st stm0 input an10 pbs0 an a/d conve?te? analog input
rev. 1.10 14 de?e??e? 01? ?01? rev. 1.10 15 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pad name function opt i/t o/t description pb3/osc?/int3/ ctp1/an11 pb3 pbpu st cmos gene?al pu?pose i/o. registe? ena?led pull-up osc? co hxt hxt os ?illato? pin int3 pbs0 integ intc3 ifs0 st exte?nal inte??upt 3 ctp1 pbs0 cmos ctm1 output an11 pbs0 an a/d conve?te? analog input pb4/v? pb4 pbpu pbs1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up v? pbs1 lcd voltage pu?p pb5/c1 pb5 pbpu pbs1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up c1 pbs1 lcd voltage pu?p pb?/c? pb? pbpu pbs3 st cmos gene ? al pu? pose i/o. registe? ena? led pull-up and wake-up. c? pbs1 lcd voltage pu?p pc0/seg0/c1p/ res pc0 pcpu pcs0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg0 pcs0 lcd lcd seg?ent output c1p pcs0 ifs4 an co?pa?ato? 1 non-inve?ting input res rstc st reset pin pc1/seg1/ stck?/c1n/ pint pc1 pcpu pcs0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg1 pcs0 lcd lcd seg?ent output stck? pcs0 ifs? st stm? input c1n pcs0 ifs4 an co?pa?ato? 1 inve?ting input pint pcs0 ifs0 st pe?iphe?al inte??upt input pc?/seg?/ stp?/stp?i/c1x pc? pcpu pcs0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg? pcs0 lcd lcd seg?ent output stp? pcs0 cmos stm? output stp?i pcs0 ifs? st stm? input c1x pcs0 cmos co?pa?ato? 1 output pc3/seg3/ stck1/c0p/pck pc3 pcpu pcs0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg3 pcs0 lcd lcd seg?ent output stck1 pcs0 ifs? st stm1 input c0p pcs0 ifs4 an co?pa?ato? 0 non-inve?ting input pck pcs0 cmos pe?iphe?al ?lo?k output
rev. 1.10 1? de?e??e? 01? ?01? rev. 1.10 17 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pad name function opt i/t o/t description pc4/seg4/ sdoa/stp1/ stp1i pc4 pcpu pcs1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg4 pcs1 lcd lcd seg?ent output sdoa pcs1 st cmos spia se ?ial data output stp1 pcs1 cmos stm1 output stp1i pcs1 ifs? st stm1 input pc5/seg5/sdia/ ctck1/c0x pc5 pcpu pcs? st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg5 pcs1 lcd lcd seg?ent output sdia pcs1 ifs3 st cmos spia se ?ial data input ctck1 pcs1 ifs? st ctm1 input c0x pcs1 cmos co?pa?ato? 0 output pc?/seg?/ scka/ctp1 pc? pcpu pcs1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg? pcs1 lcd lcd seg?ent output scka pcs1 ifs3 st cmos spia se ?ial ?lo?k ctp1 pcs1 cmos ctm1 output pc7/seg7/ scsa / stck0/c0n pc7 pcpu pcs3 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg7 pcs1 lcd lcd seg?ent output scsa pcs1 ifs3 st cmos spia slave sele ?t stck0 pcs1 ifs1 st stm0 input c0n pcs1 ifs4 an co?pa?ato? 0 inve?ting input pd0/seg8/ scs / stp0/stp0i pd0 pdpu pds0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg8 pds0 lcd lcd seg?ent output scs pds0 ifs3 st cmos spi slave sele?t stp0 pds0 cmos stm0 inve?ted output stp0i pds0 ifs1 st stm0 input pd1/seg9/sck/ scl/etck/c1p pd1 pdpu pds0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg9 pds0 lcd lcd seg?ent output sck pds0 ifs3 st cmos spi se?ial ?lo?k scl pds0 ifs3 st nmos i ? c ?lo?k line etck pds0 ifs1 st etm input c1p pds0 ifs4 an co?pa?ato? 1 non-inve?ting input
rev. 1.10 1? de?e??e? 01? ?01? rev. 1.10 17 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pad name function opt i/t o/t description pd?/seg10/ sdi/sda/etpb/ etpib pd? pdpu pds0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg10 pds0 lcd lcd seg?ent output sdi pds0 ifs3 st spi data input sda pds0 ifs3 st nmos i ? c data line etpb pds0 cmos etm b output etpib pds0 ifs1 st etm b input pd3/seg11/ sdo/c1n pd3 pdpu pds0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg11 pds0 lcd lcd seg?ent output sdo pds0 cmos spi data output c1n pds0 ifs4 an co?pa?ato? 1 inve?ting input pd4/seg1?/ int3/ctck0/ etpa/etpia/c1x pd4 pdpu pds1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg1? pds1 lcd lcd seg?ent output int3 pds1 integ intc3 ifs0 st exte?nal inte??upt 3 ctck0 pds1 ifs1 st ctm0 input etpa pds1 cmos etm a output etpia pds1 ifs1 st etm a input c1x pds1 cmos co?pa?ato? 1 output pd5/seg13/ int?/ctp0/c0p pd5 pdpu pds1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg13 pds1 lcd lcd seg?ent output int? pds1 integ intc3 ifs0 st exte?nal inte??upt ? ctp0 pds1 cmos ctm0 output c0p pds1 ifs4 an co?pa?ato? 0 non-inve?ting input pd?/seg14/ int3/ctck1/ c0n pd? pdpu pds1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg14 pds1 lcd lcd seg?ent output int3 pds1 integ intc3 ifs0 st exte?nal inte??upt 3 ctck1 pds1 ifs? st ctm1 input c0n pds1 ifs4 an co?pa?ato? 0 inve?ting input
rev. 1.10 18 de?e??e? 01? ?01? rev. 1.10 19 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pad name function opt i/t o/t description pd7/seg15/ int0/stp?/ stp?i/c0x pd7 pdpu pds1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg15 pds1 lcd lcd seg?ent output int0 pds1 integ intc0 ifs0 st exte?nal inte??upt 0 stp? pds1 cmos stm? output stp?i pds1 ifs? st stm? input c0x pds1 cmos co?pa?ato? 0 output pe0/seg1?/ sdoa/stck1 pe0 pepu pes0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg1? pes0 lcd lcd seg?ent output sdoa pes0 st cmos spia se ?ial data output stck1 pes0 ifs? st stm1 input pe1/seg17/ sdia/stp1/ stp1i pe1 pepu pes0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg17 pes0 lcd lcd seg?ent output sdia ifs3 st cmos spi se?ial data input stp1 pes0 cmos stm1 output stp1i pes0 ifs? st stm1 input pe?/seg18 pe? pepu pes0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg18 pes0 lcd lcd seg?ent output pe3/seg19 pe3 pepu pes0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg19 pes0 lcd lcd seg?ent output pe4/seg?0 pe4 pepu pes1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg?0 pes1 lcd lcd seg?ent output pe5/seg?1 pe5 pepu pes1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg?1 pes1 lcd lcd seg?ent output pe?/seg?? pe? pepu pes1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg?? pes1 lcd lcd seg?ent output pe7/seg?3 pe7 pepu pes1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg?3 pes1 lcd lcd seg?ent output pf0/seg?4 pf0 pfpu pfs0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg?4 pfs0 lcd lcd seg?ent output pf1/seg?5 pf1 pfpu pfs0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg?5 pfs0 lcd lcd seg?ent output pf?/seg?? pf? pfpu pfs0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg?? pfs0 lcd lcd seg?ent output
rev. 1.10 18 de?e??e? 01? ?01? rev. 1.10 19 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pad name function opt i/t o/t description pf3/seg?7 pf3 pfpu pfs0 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg?7 pfs0 lcd lcd seg?ent output pf4/seg?8 pf4 pfpu pfs1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg?8 pfs1 lcd lcd seg?ent output pf5/seg?9 pf5 pfpu pfs1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg?9 pfs1 lcd lcd seg?ent output pf?/seg30 pf? pfpu pfs1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg30 pfs1 lcd lcd seg?ent output pf7/seg31 pf7 pfpu pfs1 st cmos gene?al pu?pose i/o. registe? ena?led pull-up seg31 pfs1 lcd lcd seg?ent output seg3?~seg55 segn lcd lcd seg?ent output com0~com3 comn lcd lcd ?o??on output v1 v1 lcd voltage pu?p vmax vmax pwr ic ?axi?u? voltage? ?onne?ted to vdd? plcd o? v1. plcd plcd pwr lcd powe? supply vdd vdd pwr positive powe? supply. vss vss pwr negative powe? supply. g?ound. note: opt: optional by confguration option (co) or register option; i/t: input type; o/t: output type; pwr: power; co: confguration option; st: schmitt trigger input; an: analog input; cmos: cmos output; nmos: nmos output; lcd: lcd seg/com output; hxt: high frequency crystal oscillator; lxt: low frequency crystal oscillator absolute maximum ratings supply voltage ................................................................................................. v ss ?0.3v to v ss +6.0v input voltage ................................................................................................... v ss ?0.3v to v dd +0.3v storage temperature ...................................................................................................... 50?c to 125?c operating temperature .................................................................................................... 40?c to 85?c i oh total ..................................................................................................................................... -80ma i ol total ...................................................................................................................................... 80ma total power dissipation .......................................................................................................... 500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to these devices. functional operation of these devices at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect devices reliability.
rev. 1.10 ?0 de?e??e? 01? ?01? rev. 1.10 ?1 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom d.c. characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope? ating voltage (hxt) f sys =f hxt =8mhz ?.? 5.5 v f sys =f hxt =1?mhz ?.7 5.5 v f sys =f hxt =?0mhz 4.5 5.5 v ope? ating voltage (hirc) f sys =f hirc =4mhz ?.? 5.5 v f sys =f hirc =8mhz ?.? 5.5 v f sys =f hirc =1?mhz ?.7 5.5 v i dd ope?ating cu??ent (hxt) 3v f sys =f hxt =8mhz no load? all pe?iphe? al off 1.? ?.0 ?a 5v ?.8 4.5 ?a 3v f sys =f hxt =1?mhz no load? all pe?iphe? al off 1.8 3.0 ?a 5v 4.0 ?.0 ?a 5v f sys =f hxt =?0mhz? no load? all pe?iphe? al off 5.5 8.5 ?a 3v f sys =f hxt /?? f hxt =1?mhz no load? all pe?iphe? al off 0.9 1.5 ?a 5v ?.1 3.3 ?a 3v f sys =f hxt /4? f hxt =1?mhz no load? all pe?iphe? al off 0.? 1.0 ?a 5v 1.? ?.5 ?a 3v f sys =f hxt /8? f hxt =1?mhz no load? all pe?iphe? al off 0.48 0.8 ?a 5v 1.? ?.0 ?a 3v f sys =f hxt /1?? f hxt =1?mhz no load? all pe?iphe? al off 0.4? 0.7 ?a 5v 1.1 1.7 ?a 3v f sys =f hxt /3?? f hxt =1?mhz no load? all pe?iphe? al off 0.38 0.? ?a 5v 1.0 1.5 ?a 3v f sys =f hxt /?4? f hxt =1?mhz no load? all pe?iphe? al off 0.3? 0.55 ?a 5v 1.0 1.5 ?a ope?ating cu??ent (hirc) 3v f sys =f hirc =4mhz no load? all pe?iphe? al off 0.7 1.? ?a 5v 1.5 ?.5 ?a 3v f sys =f hirc =8mhz no load? all pe?iphe? al off 1.? ?.0 ?a 5v ?.8 4.5 ?a 3v f sys =f hirc =1?mhz no load? all pe?iphe? al off 1.5 3.0 ?a 5v 3.0 ?.0 ?a ope?ating cu??ent (lxt) 3v f sys =f sub =f lxt =3?.7?8khz? lxtlp=0 no load? all pe?iphe? al off 10 ?0 a 5v 30 50 a 3v f sys =f sub =f lxt =3?.7?8khz? lxtlp=1 no load? all pe?iphe? al off 10 ?0 a 5v 30 50 a ope?ating cu??ent (lirc) 3v f sys =f sub =f lirc =3?khz no load? all pe?iphe? al off 10 ?0 a 5v 30 50 a
rev. 1.10 ?0 de?e??e? 01? ?01? rev. 1.10 ?1 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom symbol parameter test conditions min. typ. max. unit v dd conditions i stb stand?y cu??ent (idle0) 3v f sys off ? f sub on? lxtlp=1 no load? all pe?iphe? al off 1.3 3.0 a 5v ?.? 5.0 a stand?y cu??ent (idle1) 3v f sys =1?mhz on? f sub on no load? all pe?iphe? al off 0.? 1.0 ?a 5v 1.? ?.0 ?a 3v f sys =1?mhz/?4 on? f sub on no load? all pe?iphe? al off 0.34 0.? ?a 5v 0.85 1.? ?a 3v f sys =f lxt =3?.7?8khz on? f sub on? lxtlp=1? no load? all pe?iphe? al off 1.9 4.0 a 5v 3.3 7.0 a stand?y cu??ent (sleep0) 3v f sys off ? f sub off ? wdt disa?led no load? all pe?iphe? al off 0.1 1.0 a 5v 0.3 ?.0 a stan?y cu??ent (sleep1) 3v f sys off ? f sub =f lirc =3?khz on? wdt ena ?led? no load? all pe?iphe? al off 1.3 5.0 a 5v ?.? 10.0 a 3v f sys off ? f sub =f lxt =3?.7?8hz on? wdt ena ?led? no load? all pe?iphe? al off? lxtlp=0 1.3 5.0 a 5v ?.? 10.0 a 3v f sys off ? f sub =f lxt =3?.7?8hz on? wdt ena ?led? no load? all pe?iphe? al off? lxtlp=1 1.3 3.0 a 5v ?.? 5.0 a v il input low voltage fo ? i/o po?t (ex?ept res pin) 5v 0 1.5 v 0 0.?v dd v input low voltage ( res pin) 0 0.4v dd v v ih input high voltage fo ? i/o po?ts (ex?ept res pin) 5v 3.5 5 v 0.8v dd v dd v input high voltage ( res pin) 0.9v dd v dd v i ol sink cu??ent fo? i/o po?ts 3v v ol =0.1v dd 4 8 ?a 5v v ol =0.1v dd 10 ?0 ?a i oh sou??e cu??ent fo? i/o po?ts 3v v oh =0.9v dd -? -4 ?a 5v v oh =0.9v dd -5 -10 ?a r ph pull-high resistan?e fo? i/o po?ts 3v ?0 ?0 100 k 5v 10 30 50 k
rev. 1.10 ?? de?e??e? 01? ?01? rev. 1.10 ?3 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom a.c. characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions f sys syste? clo?k (hxt) ?.?v~5.5v 8 mhz ?.7v~5.5v 1? mhz 4.5v~5.5v ?0 mhz syste? clo?k (hirc) ?.?v~5.5v 4 mhz 8 mhz ?.7v~5.5v 1? mhz syste? clo?k (lxt) ?.?v~5.5v 3?.7?8 khz syste? clo?k (lirc) ?.?v~5.5v 3? khz f hxt high speed c?ystal os?illato? clo?k (hxt) ?.?v~5.5v 0.4 8 mhz ?.7v~5.5v 0.4 1? mhz 4.5v~5.5v 0.4 ?0 mhz f hirc high speed rc os?illato? clo?k (hirc) 5v ta = ?5c typ. -?% 4 typ. +?% mhz typ. -?% 8 typ. +?% mhz typ. -?% 1? typ. +?% mhz 3.0v~5.5v ta = 0c ~ +85c typ. -10% 4 typ. +10% mhz typ. -10% 4 typ. +10% mhz typ. -10% 4 typ. +10% mhz f lxt low speed c?ystal os?illato? clo?k (lxt) 3?.7?8 khz f lirc low speed rcl os?illato? clo?k (lirc) 5v ta = ?5c typ. -3% 3? typ. +3% khz t tck tm tck input mini ?u? pulse width 0.3 s t tp tm tpi input mini ?u? pulse width 0.3 s t int exte?nal inte??upt mini?u? input pulse width 10 s t res exte?nal reset mini?u? low pulse width 10 s t sst syste? sta? t-up ti?e pe?iod (wake-up f ?o? powe? down ?ode? f sys off) f sys = f hxt 10?4 t hxt f sys = f hirc 1? t hirc f sys = f lxt 10?4 t lxt f sys = f lirc ? t lirc syste? sta? t-up ti?e pe?iod (wake-up f ?o? powe? down ?ode? f sys on) ? t sys syste? sta? t-up ti?e pe?iod (mode swit?hing ? etween normal and slow) f hxt off on 10?4 t hxt f hirc off on 1? t hirc f lxt off on 10?4 t lxt f lirc off on ? t lirc t rstd syste? reset delay ti?e (powe? on reset? rstc softwa?e ?eset lvr ha ?dwa?e ?eset? lvrc softwa?e ?eset? wdtc softwa?e ?eset) ?5 50 100 ?s syste? reset delay ti?e ( res reset, wdt overfow reset) 8.3 1?.7 33.3 ?s t eerd eeprom read ti ?e 4 t sys t eewr eeprom w ? ite ti?et ? 4 ?s 1rwhw sys sys
rev. 1.10 ?? de?e??e? 01? ?01? rev. 1.10 ?3 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom a/d converter characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope? ating voltage ?.7 5.5 v v adi input voltage 0 v dd /v ref v v ref refe?en? e voltage ? v dd +0.1v v dnl diffe ?ential non-linea?ity 3v v ref =v dd ? t adck =0.5s 3 lsb 5v inl integ?al non-linea?ity 3v v ref =v dd ? t adck =0.5s 4 lsb 5v i adc additional cu ?? ent fo? a/d conve?te? ena?le 3v no load? t adck =0.5s 1.0 ?.0 ?a 5v 1.5 3.0 ?a t adck clo?k pe?iod 0.5 10 s t adc conve? sion ti?e (in?luding sa? ple and hold ti?e) 1? t adck t on?st a/d conve?te? on-to-sta? t ti?e 4 s lvd/lvr electrical characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr low voltage reset voltage lvr ena ?le? voltage sele?t ?.1v typ. - 5% ?.1 typ. + 5% v lvr ena ?le? voltage sele?t ?.55v ?.55 lvr ena ?le? voltage sele?t 3.15v 3.15 lvr ena ?le? voltage sele?t 3.8v 3.8 v lvd low voltage dete ?to? voltage lvd ena ?le? voltage sele?t ?.0v typ. - 5% ?.0 typ. + 5% v lvd ena ?le? voltage sele?t ?.?v ?.? lvd ena ?le? voltage sele?t ?.4v ?.4 lvd ena ?le? voltage sele?t ?.7v ?.7 lvd ena ?le? voltage sele?t 3.0v 3.0 lvd ena ?le? voltage sele?t 3.3v 3.3 lvd ena ?le? voltage sele?t 3.?v 3.? lvd ena ?le? voltage sele?t 4.0v 4.0 v bg bandgap refe?en? e voltage typ. - 5% 1.04 typ. + 5% v i op lvd/lvr ope ?ating cu??ent 5v lvd/lvr ena ?le? vbgen=0 ?0 ?5 a 5v lvd/lvr ena ?le? vbgen=1 180 ?00 a t bgs v bg tu ? n on sta? le ti?e no load 150 s t lvds lvdo sta ?le ti?e fo? lvr ena?le? vbgen=0? lvd disable enable 15 s fo? lvr disa?le? vbgen=0? lvd disable enable 150 s t lvr mini?u? low voltage width to reset 1?0 ?40 480 s t lvd mini?u? low voltage width to inte??upt ?0 1?0 ?40 s
rev. 1.10 ?4 de?e??e? 01? ?01? rev. 1.10 ?5 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom comparator electrical characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope? ating voltage ?.7 5.5 v i cmp additional cu??ent fo? co?pa?ato? ena?led 3v 50 75 a 5v 85 130 a v os input offset voltage 5v -10 +10 ?v v hys heste?esis 5v ?0 40 ?0 ?v v cm co?? on mode voltage range 0 v dd -1.4 v a ol open loop gain ?0 80 db t rp response ti ?e 3v/5v with 100?v ove?d? ive (note) ? s ote: easured with comparator one input pin at v c = v dd u s s ud up ss puup dd p lcd driver electrical characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions i ol sink cu??ent fo? lcd pins 3v v plcd =3v ? v ol =0.1v plcd ?10 4?0 ?a 5v v plcd =5v ? v ol =0.1v plcd 350 700 ?a i oh sou??e cu??ent fo? lcd pins 3v v plcd =3v ? v ol =0.9v plcd -80 -1?0 ?a 5v v plcd =5v ? v ol =0.9v plcd -180 -3?0 ?a i lcd lcd ope?ating cu??ent (r type) 3v no load? 1/3 ?ias? r t =1170k 5 a 5v 7.5 a 3v no load? 1/3 ?ias? r t =2250k ?3 a 5v 40 a 3v no load? 1/3 ?ias? r t =60k 8? a 5v 145 a lcd ope?ating cu??ent (c type) 3v no load? 1/3 ?ias 1 a 5v ? a power-on reset characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd sta? t voltage to ensu?e powe?-on reset 100 ?v rr por v dd rising rate to ensu?e powe?-on reset 0.035 v/?s t por mini?u? ti?e fo? v dd stays at v por to ensu?e powe?-on reset 1 ?s
rev. 1.10 ?4 de?e??e? 01? ?01? rev. 1.10 ?5 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and fexibility. this makes these devices suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt, lxt, hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.
? ? ? ? ? ? ? ? system clock and pipelining
rev. 1.10 ?? de?e??e? 01? ?01? rev. 1.10 ?7 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address which is located in a certain program memory bank selected by the program memory bank pointer bits. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter high byte low byte (pcl) ht?7f?0a bp0? pc1?~pc8 pc7~pc0 ht?7f?0a bp1~bp0? pc1?~pc8 pc7~pc0 program counter the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.10 ?? de?e??e? 01? ?01? rev. 1.10 ?7 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has multiple levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.
arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations:add, addm, adc, adcm, sub, subm, sbc, sbcm, daa, ladd, laddm, ladc, ladcm, lsub, lsubm, lsbc, lsbcm, ldaa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla, land, lor, lxor, landm, lorm, lxorm, lcpl, lcpla ? rotation: rra, rr, rrca, rrc, rla, rl, rlca, rlc, lrra, lrr, lrrca, lrrc, lrla, lrl, lrlca, lrlc ? increment and decrement: inca, inc, deca, dec, linca, linc, ldeca, ldec ? branch decision: jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti, lsz, lsza, lsnz, lsiz, lsdz, lsiza, lsdza
rev. 1.10 ?8 de?e??e? 01? ?01? rev. 1.10 ?9 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom flash program memory the program memory is the location where the user code or program is stored. for these devices series the program memory are flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. by using the appropriate programming tools, these flash devices offer users the fexibility to conveniently debug and develop their applications while also offering a means of feld programming and updating. structure the program memory has a capacity of 16k16 to 32k16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer registers. device capacity banks ht?7f?0a 1?k 1? 0~1 ht?7f70a 3?k 1? 0~3 the series of devices have their program memory divided into two or four banks, bank 0~bank 1 or bank 0~bank 3 respectively. the required bank is selected using bit 0 or bit 0~1 of the bp register dependent upon which device is selected. 0000h 0004h 0038h reset interrupt vector 16 bits HT67F60A 1fffh bank 1 2000h 3fffh reset interrupt vector 16 bits ht67f70a bank 1 bank 2 bank 3 4000h 5fffh 6000h 7fffh program memory structure special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 000h is reserved for use by these devices reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution.
rev. 1.10 ?8 de?e??e? 01? ?01? rev. 1.10 ?9 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the corresponding table read instruction such as tabrd [m] or tabrdl [m] respectively when the memory [m] is located in sector 0. if the memory [m] is located in other sectors, the data can be retrieved from the program memory using the corresponding extended table read instruction such as ltabrd [m] or ltabrdl [m] respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defned data memory register [m] as specifed in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. the accompanying diagram illustrates the addressing data fow of the look-up table.

table program example the accompanying example shows how the table pointer and table data is defined and retrieved from the device. this example uses raw table data located in the last page which is stored there using the org and rombank statements. the value at this org statement is 1f00h which is located in rom bank 3 which refers to the start address of the last page within the 8k words program memory in bank 3 of the device with 32k words program memory. the table pointer low byte register is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 7f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd [m] instruction is executed. because the tblh register is a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
rev. 1.10 30 de?e??e? 01? ?01? rev. 1.10 31 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom table read program example rombank 3 code3 ds .section data tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : code0 .section code mov a,06h ; initialise table pointer - note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,7fh ; initialise high table pointer mov tbhp,a ; it is not necessary to set tbhp if executing tabrdl : tabrdc tempreg1 tabrdl tempreg1 ; transfers value in table referred by table pointer to tempregl ; data at program memory address 7f06h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdc tempreg2 tabrdl tempreg2 ; transfers value in table referenced by table pointer to tempreg2 ; data at program memory address 7f05h transferred to tempreg2 and ; tblh ; in this example the data 1ah is transferred to tempreg1 ; and data 0fh to tempreg2 ; the value 00h will be transferred to the high byte register tblh : code3 .section code org 1f00h ; sets initial address of lastpage dc 00ah,00bh,00ch,00dh,00eh,00fh,01ah,01bh : in circuit programming C icp the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in- circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re- insertion of the device. holtek writer pins mcu programming pins pin description icpda pa0 p?og?a??ing se?ial data/add?ess icpck pa ? p?og?a??ing clo?k vdd vdd powe? supply vss vss g?ound the program memory and eeprom data memory can be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply. the technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. during the programming process, the user must take care of the icpda and icpck pins for data and clock programming purposes to ensure that no other outputs are connected to these two pins.
rev. 1.10 30 de?e??e? 01? ?01? rev. 1.10 31 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom
note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. on-chip debug support C ocds there is an ev chip named ht67vx0a which is used to emulate the real mcu device named ht67fx0a. the ev chip device also provides the on-chip debug function to debug the real mcu device during development process. the ev chip and real mcu devices, ht67vx0a and ht67fx0a respectively, are almost functional compatible except the on-chip debug function and package types. users can use the ev chip device to emulate the real mcu device behaviors by connecting the ocdsda and ocdsck pins to the holtek ht-ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip device for debugging, the corresponding pin functions shared with the ocdsda and ocdsck pins in the real mcu device will have no effect in the ev chip. however, the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp. for more detailed ocds information, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip ocds pins pin description ocdsda ocdsda on-chip de?ug suppo?t data/add?ess input/output ocdsck ocdsck on-chip de?ug suppo?t clo?k input vdd vdd powe? supply vss vss g?ound in application programming C iap this device offers iap function to update data or application program to flash rom. users can defne any rom location for iap, but there are some features which user must notice in using iap function. ? erase page: 64 words/page ? writing: 64 words/time ? reading: 1 word/time
rev. 1.10 3? de?e??e? 01? ?01? rev. 1.10 33 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom in application program control registers the address register, farl and farh, the data registers, fd0l/fd0h, fd1l/fd1h, fd2l/fd2h and fd3l/fd3h, and the control registers, fc0, fc1 and fc2, are the corresponding flash access registers located in data memory sector 1 for iap. if using the indirect addressing method to access the fc0, fc1 and fc2 registers, all read and write operations to the registers must be performed using the indirect addressing register, iar1 or iar2, and the memory pointer pair, mp1l/mp1h or mp2l/mp2h. because the fc0, fc1 and fc2 control registers are located at the address of 43h~45h in data memory sector 1, the desired value ranged from 43h to 45h must frst be written into the mp1l or mp2l memory pointer low byte and the value 01h must also be written into the mp1h or mp2h memory pointer high byte. register name bit 7 6 5 4 3 2 1 0 fc0 cfwen fmod? fmod1 fmod0 fwpen fwt frden frd fc1 d7 d? d5 d4 d3 d? d1 d0 fc? clwb farl a7 a? a5 a4 a3 a? a1 a0 farh (ht ?7f?0a) a13 a1? a11 a10 a9 a8 farh (ht ?7f70a) a14 a13 a1? a11 a10 a9 a8 fd0l d7 d? d5 d4 d3 d? d1 d0 fd0h d15 d14 d13 d1? d11 d10 d9 d8 fd1l d7 d? d5 d4 d3 d? d1 d0 fd1h d15 d14 d13 d1? d11 d10 d9 d8 fd?l d7 d? d5 d4 d3 d? d1 d0 fd?h d15 d14 d13 d1? d11 d10 d9 d8 fd3l d7 d? d5 d4 d3 d? d1 d0 fd3h d15 d14 d13 d1? d11 d10 d9 d8 iap registers list fc0 register bit 7 6 5 4 3 2 1 0 na?e cfwen fmod? fmod1 fmod0 fwpen fwt frden frd r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 1 1 0 0 0 0 bit 7 cfwen : flash memory write enable control 0: flash memory write function is disabled 1: flash memory write function has been successfully enabled when this bit is cleared to 0 by application program, the flash memory write function is disabled. note that writing a 1 into this bit results in no action. this bit is used to indicate that the flash memory write function status. when this bit is set to 1 by hardware, it means that the flash memory write function is enabled successfully. otherwise, the flash memory write function is disabled as the bit content is zero. bit 6~4 fmod2~fmod0 : mode selection 000: write program memory 001: page erase program memory 010: reserved 011: read program memory 10x: reserved 110: fwen mode C flash memory write function enabled mode 111: reserved
rev. 1.10 3? de?e??e? 01? ?01? rev. 1.10 33 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom bit 3 fwpen : flash memory write procedure enable control 0: disable 1: enable this bit is set to 1 by application program and then cleared to 0 by hardware. when this bit is set to 1 and the fmod feld is set to 110, the iap controller will execute the flash memory write function enable procedure. once the flash memory write function is successfully enabled, it is not necessary to set the fwpen bit any more. bit 2 fwt : flash memory write initiate control 0: do not initiate flash memory write or flash memory write process is completed 1: initiate flash memory write process this bit is set by software and cleared by hardware when the flash memory write process is completed. bit 1 frden : flash memory read enable control 0: flash memory read disable 1: flash memory read enable bit 0 frd : flash memory read initiate control 0: do not initiate flash memory read or flash memory read process is completed 1: initiate flash memory read process this bit is set by software and cleared by hardware when the flash memory read process is completed. fc1 register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : whole chip reset pattern when user writes a specific value of 55h to this register, it will generate a reset signal to reset whole chip. fc2 register bit 7 6 5 4 3 2 1 0 na?e clwb r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 clwb : flash memory write buffer clear control 0: do not initiate write buffer clear process or write buffer clear process is completed 1: initiate write buffer clear process this bit is set by software and cleared by hardware when the write buffer clear process is completed. farl register bit 7 6 5 4 3 2 1 0 na?e a7 a? a5 a4 a3 a? a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 flash memory address bit 7 ~ bit 0
rev. 1.10 34 de?e??e? 01? ?01? rev. 1.10 35 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom farh register C HT67F60A bit 7 6 5 4 3 2 1 0 na?e a13 a1? a11 a10 a9 a8 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 flash memory address bit 13 ~ bit 0 farh register C ht67f70a bit 7 6 5 4 3 2 1 0 na?e a14 a13 a1? a11 a10 a9 a8 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6~0 flash memory address bit 14 ~ bit 0 fd0l register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the frst flash memory data bit 7 ~ bit 0 fd0h register bit 7 6 5 4 3 2 1 0 na?e d15 d14 d13 d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the frst flash memory data bit 15 ~ bit 8 fd1l register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the second flash memory data bit 7 ~ bit 0 fd1h register bit 7 6 5 4 3 2 1 0 na?e d15 d14 d13 d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the second flash memory data bit 15 ~ bit 8
rev. 1.10 34 de?e??e? 01? ?01? rev. 1.10 35 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom fd2l register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the third flash memory data bit 7 ~ bit 0 fd2h register bit 7 6 5 4 3 2 1 0 na?e d15 d14 d13 d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the third flash memory data bit 15 ~ bit 8 fd3l register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the fourth flash memory data bit 7 ~ bit 0 fd3h register bit 7 6 5 4 3 2 1 0 na?e d15 d14 d13 d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the fourth flash memory data bit 15 ~ bit 8 flash memory write function enable procedure in order to allow users to change the flash memory data through the iap control registers, users must frst enable the flash memory write operation by the following procedure: 1. write 110 into the fmod2~fmod0 bits to select the fwen mode. 2. set the fwpen bit to 1. the step 1 and step 2 can be executed simultaneously. 3. the pattern data with a sequence of 00h, 04h, 0dh, 09h, c3h and 40h must be written into the fd1l, fd1h, fd2l, fd2h, fd3l and fd3h registers respectively. 4. a counter with a time-out period of 300s will be activated to allow users writing the correct pattern data into the fd1l/fd1h ~ fd3l/fd3h register pairs. the counter clock is derived from lirc oscillator. 5. when the counter overflows, the fwpen bit will automatically be cleared to 0 by hardware followed by pattern check. 6. if the pattern data is correct, the cfwen bit will be set to 1 by hardware to indicate that the flash memory write operation is successfully enabled. 7. once the flash memory write operation is enabled, the user can change the flash rom data through the flash control register. 8. to disable the flash memory write operation, the user can clear the cfwen bit to 0.
rev. 1.10 3? de?e??e? 01? ?01? rev. 1.10 37 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom flash memory write function enable procedure set fmod [2:0] =110 & fwpen=1 select fwen mode & start flash write hardware activate a counter wrtie the following pattern to flash data registers fd1l= 00h , fd1h = 04h fd2l= 0dh , fd2h = 09h fd3l= c3h , fd3h = 40h success end yes failed cfwen=0 cfwen = 1 no is counter overflow ? no fwpen=0 is pattern correct ? yes flash memory write function enable procedure flash memory write procedure iwhu wkh )odvk phpru zulwh ixqfwlrq lv vxffhvvixoo hqdeohg wkurxjk wkh suhfhglqj ,3 surfhgxuh xvhuv pxvw uvw hudvh wkh fruuhvsrqglqj )odvk phpru eorfn dqg wkhq lqlwldwh wkh )odvk phpru zulwh rshudwlrq 6lqfh wkh qxpehu ri wkh sdjh hudvh rshudwlrq lv zrugv shu sdjh wkh dydlodeoh sdjh hudvh dgguhvv lv vshflilhg e )5 uhjlvwhu dqg wkh frqwhqw ri elw a elw lq wkh )5/ uhjlvwhu
rev. 1.10 3? de?e??e? 01? ?01? rev. 1.10 37 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom erase page farh farl [7:6] farl [5:0] 0 0000 0000 00 xxxx 1 0000 0000 01 xxxx ? 0000 0000 10 xxxx 3 0000 0000 11 xxxx 4 0000 0001 00 xxxx 5 0000 0001 01 xxxx ? 0000 0001 10 xxxx 7 0000 0001 11 xxxx 8 0000 0010 00 xxxx 9 0000 0010 01 xxxx : : : : : : : : ?5? 0011 1111 00 xxxx ?53 0011 1111 01 xxxx ?54 0011 1111 10 xxxx ?55 0011 1111 11 xxxx : : : : : : : : 508 0111 1111 00 xxxx 509 0111 1111 01 xxxx 510 0111 1111 10 xxxx 511 0111 1111 11 xxxx xxxx: dont ?a?e note: there are 256 iap erase pages in the HT67F60A device while there are 512 iap erase pages in the ht67f70a device.
rev. 1.10 38 de?e??e? 01? ?01? rev. 1.10 39 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom read flash memory clear frden bit end read finish ? yes no set fmod [2:0]=011 & frden=1 set flash address registers fah=xxh, fal=xxh frd=0 ? yes no read data value: fd0l=xxh, fd0h=xxh set frd=1 read flash memory procedure
rev. 1.10 38 de?e??e? 01? ?01? rev. 1.10 39 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom write flash memory flash memory write function enable procedure set fwt=1 fwt=0 ? yes no set page erase address: farh/farl set fmod [2:0]=001 & fwt=1 select page erase mode & initiate write operation fwt=0 ? yes no end write finish ? yes no clear cfwen=0 set fmod [2:0]=000 select write flash mode set write starting address: farh/farl write data to data register: fd0l/fd0h page data write finish yes no write flash memory procedure 1rwh :khqwkh):7 ru)5elwlvvhwwrwkh0&8lvvwrsshg
rev. 1.10 40 de?e??e? 01? ?01? rev. 1.10 41 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom data memory the data memory is an 8-bit wide ram internal memory and is the location where temporary information is stored. divided into three types, the first of data memory is an area of ram where special function registers are located. these registers have fxed locations and are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. the third area is reserved for the lcd memory. this special area of data memory is mapped directly to the lcd display so data written into this memory area will directly affect the displayed data. switching between the different data memory sectors is achieved by properly setting the memory pointers to correct value. structure the data memory is subdivided into several sectors, all of which are implemented in 8-bit wide memory. each of the data memory sectors is categorized into two types, the special purpose data memory and the general purpose data memory. the address range of the special purpose data memory for the device is from 00h to 7fh while the address range of the general purpose data memory is from 80h to ffh. device special puroise data memory lcd data memory general puroise data memory capacity sectors capacity sectors capacity sectors ht?7f?0a 19? 8 0? ?~8: 00h~7fh 1: 40h~7fh 5? 4 1: 80h~b7h 10?4 8 0: 80h~ffh ?: 80h~ffh : 8: 80h~ffh ht?7f70a 19? 8 0? ?~1?: 00h~7fh 1: 40h~7fh 5? 4 1: 80h~b7h ?048 8 0: 80h~ffh ?: 80h~ffh : 1?: 80h~ffh data memory summary sector 2 00h 7fh 80h ffh special purpose data memory general purpose data memory sector 0 lcd memory in sector 1 40h sector n note: n=8 for HT67F60A; n=16 for ht67f70a sector 1 data memory structure
rev. 1.10 40 de?e??e? 01? ?01? rev. 1.10 41 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom data memory addressing for this device that supports the extended instructions, there is no bank pointer for data memory. the bank pointer, bp, is only available for program memory. for data memory the desired sector is pointed by the mp1h or mp2h register and the certain data memory address in the selected sector is specifed by the mp1l or mp2l register when using indirect addressing access. direct addressing can be used in all sectors using the corresponding instruction which can address all available data memory space. for the accessed data memory which is located in any data memory sectors except sector 0, the extended instructions can be used to access the data memory instead of using the indirect addressing access. the main difference between standard instructions and extended instructions is that the data memory address m in the extended instructions can be at least 12-bit, the high byte indicates a sector and the low byte indicates a specifc address. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user programing for both reading and writing operations. by using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of fexibility for bit manipulation in the data memory. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h.
rev. 1.10 4? de?e??e? 01? ?01? rev. 1.10 43 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom 00h iar 0 01h mp 0 0?h iar 1 03h mp 1 l 04h 05h acc 0?h pcl 07h tblp 08h tblh 09h tbhp 0 ah status 0 bh 0 ch lvdc 0 dh integ 0 eh 0 fh 10h intc 0 11h intc 1 1?h 19h papu 18h pawu 1 bh 1 ah 1 dh 1 ch 1 fh pa pac ht 67 f 60 a special purpose data memory 13h 14h mfi 0 15h mfi 1 1?h 17h : unused ? ?ead as 00h intc ? mfi ? tb 0 c ?0h ?1h ??h ?9h ?8h ? bh ? ah ? dh ? ch ? fh ? eh ?3h ?4h ?5h ??h ?7h eea stm 0 c 0 stm 0 c 1 stm 0 dl stm 0 dh stm 0 al stm 0 ah 40h 41h 4?h 43h 44h 45h 4?h 47h 48h 49h 4 ah 4 bh 4 ch 4 dh 4 eh 4 fh 50h 51h 5?h 53h 54h mfi 3 lvrc eed 1 eh intc 3 eec se?to? 0 ~ 8 se?to? 0 ? ? ~ 8 se?to? 1 stm 0 rp 55h 5?h ?0h ?1h ??h ?3h ?4h ?5h ??h ?7h ?8h ?9h ? ah ? bh ? ch ? dh ? eh ? fh 70h etmc 0 etmc 1 30h 31h 3?h 38h 3 ch 33h 34h 35h 3?h 37h etmdl etmdh etmal etmah 3 bh 39h 3 ah 71h 7?h 73h 74h 75h 7?h 77h pbc pbpu pb 3 dh 3 fh 3 eh 7 fh mp 1 h iar ? mp ? l mp ? h psc 0 tb 1 c smod rstc smod ? 57h pas 0 58h 59h pas 1 5 ah pbs 0 pcs 0 pcs 1 pds 0 5 bh 5 ch 5 dh pds 1 5 eh 5 fh ifs 0 i ? ctoc simc 0 simc 1 simd sima / simc ? spiac 0 spiac 1 spiad sadc 0 sadc 1 sadol sadoh fc 0 fc 1 fc ? farl farh fd 0 l fd 0 h fd 1 l fd 1 h fd ? l fd ? h fd 3 l fd 3 h bp pcc pcpu pc pdc pdpu pd pec pepu pe pfc pfpu pf lcdc 0 lcdc 1 mfi 4 smod 1 wdtc cp 0 c cp 1 c etmc ? etmbl etmbh ctm 1 c 0 ctm 1 c 1 ctm 1 dl ctm 1 dh ctm 1 al ctm 1 ah ctm 0 c 0 ctm 0 c 1 ctm 0 dl ctm 0 dh ctm 0 al ctm 0 ah psc 1 78h 79h 7 ah 7 bh 7 ch 7 dh 7 eh tbc ? ifs 1 ifs ? ifs 3 ifs 4 stm 1 c 0 stm 1 c 1 stm 1 dl stm 1 dh stm 1 al stm 1 ah stm 1 rp stm ? c 0 stm ? c 1 stm ? dl stm ? dh stm ? al stm ? ah stm ? rp pbs 1 pes 0 pes 1 pfs 0 pfs 1 00h iar 0 01h mp 0 0?h iar 1 03h mp 1 l 04h 05h acc 0?h pcl 07h tblp 08h tblh 09h tbhp 0 ah status 0 bh 0 ch lvdc 0 dh integ 0 eh 0 fh 10h intc 0 11h intc 1 1?h 19h papu 18h pawu 1 bh 1 ah 1 dh 1 ch 1 fh pa pac ht 67 f 70 a special purpose data memory 13h 14h mfi 0 15h mfi 1 1?h 17h : unused ? ?ead as 00h intc ? mfi ? tb 0 c ?0h ?1h ??h ?9h ?8h ? bh ? ah ? dh ? ch ? fh ? eh ?3h ?4h ?5h ??h ?7h eea stm 0 c 0 stm 0 c 1 stm 0 dl stm 0 dh stm 0 al stm 0 ah 40h 41h 4?h 43h 44h 45h 4?h 47h 48h 49h 4 ah 4 bh 4 ch 4 dh 4 eh 4 fh 50h 51h 5?h 53h 54h mfi 3 lvrc eed 1 eh intc 3 eec se?to? 0 ~ 1? se?to? 0 ? ? ~ 1? se?to? 1 stm 0 rp 55h 5?h ?0h ?1h ??h ?3h ?4h ?5h ??h ?7h ?8h ?9h ? ah ? bh ? ch ? dh ? eh ? fh 70h etmc 0 etmc 1 30h 31h 3?h 38h 3 ch 33h 34h 35h 3?h 37h etmdl etmdh etmal etmah 3 bh 39h 3 ah 71h 7?h 73h 74h 75h 7?h 77h pbc pbpu pb 3 dh 3 fh 3 eh 7 fh mp 1 h iar ? mp ? l mp ? h psc 0 tb 1 c smod rstc smod ? 57h pas 0 58h 59h pas 1 5 ah pbs 0 pcs 0 pcs 1 pds 0 5 bh 5 ch 5 dh pds 1 5 eh 5 fh ifs 0 i ? ctoc simc 0 simc 1 simd sima / simc ? spiac 0 spiac 1 spiad sadc 0 sadc 1 sadol sadoh fc 0 fc 1 fc ? farl farh fd 0 l fd 0 h fd 1 l fd 1 h fd ? l fd ? h fd 3 l fd 3 h bp pcc pcpu pc pdc pdpu pd pec pepu pe pfc pfpu pf lcdc 0 lcdc 1 mfi 4 smod 1 wdtc cp 0 c cp 1 c etmc ? etmbl etmbh ctm 1 c 0 ctm 1 c 1 ctm 1 dl ctm 1 dh ctm 1 al ctm 1 ah ctm 0 c 0 ctm 0 c 1 ctm 0 dl ctm 0 dh ctm 0 al ctm 0 ah psc 1 78h 79h 7 ah 7 bh 7 ch 7 dh 7 eh tbc ? ifs 1 ifs ? ifs 3 ifs 4 stm 1 c 0 stm 1 c 1 stm 1 dl stm 1 dh stm 1 al stm 1 ah stm 1 rp stm ? c 0 stm ? c 1 stm ? dl stm ? dh stm ? al stm ? ah stm ? rp pbs 1 pes 0 pes 1 pfs 0 pfs 1
rev. 1.10 4? de?e??e? 01? ?01? rev. 1.10 43 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom special function register description most of the special function register details will be described in the relevant functional section. however, several registers require a separate description in this section. indirect addressing registers C iar0, iar1, iar2 the indirect addressing registers, iar0, iar1 and iar2, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0, iar1 and iar2 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0, mp1l/mp1h or mp2l/mp2h. acting as a pair, iar0 and mp0 can together access data only from sector 0 while the iar1 register together with mp1l/mp1h register pair and iar2 register together with mp2l/mp2h register pair can access data from any data memory sector. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1h/mp1l, mp2h/mp2l five memory pointers, known as mp0, mp1l, mp1h, mp2l and mp2h, are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from sector 0, while mp1l/mp1h together with iar1 and mp2l/mp2h together with iar2 are used to access data from all data sectors according to the corresponding mp1h or mp2h register. direct addressing can be used in all data sectors using the corresponding instruction which can address all available data memory space. indirect addressing program example example 1 data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp0,a ; setup memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: :
rev. 1.10 44 de?e??e? 01? ?01? rev. 1.10 45 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom example 2 data .section at 01f0h data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,01h ; setup the memory sector mov mp1h,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp1l,a ; setup memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp1 inc mp1l ; increment memory pointer mp1l sdz block ; check if last memory location has been cleared jmp loop continue: : the important point to note here is that in the example shown above, no reference is made to specifc ram addresses. direct addressing program example using extended instructions data .section data temp db ? code .section at 0 code org 00h start: lmov a,[m] ; move [m] data to acc lsub a, [m+1] ; compare [m] and [m+1] data snz c ; [m]>[m+1]? jmp continue ; no lmov a,[m] ; yes, exchange [m] and [m+1] data mov temp,a lmov a,[m+1] lmov [m],a mov a,temp lmov [m+1],a continue: : note: here m is a data memory address located in any data memory sectors. for example, m=1f0h, it indicates address 0f0h in sector 1.
rev. 1.10 44 de?e??e? 01? ?01? rev. 1.10 45 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom bank pointer C bp depending upon which device is used, the program memory is divided into several banks. selecting the required program memory area is achieved using the bank pointer. the bank pointer should be properly confgured before the device executes the branch operation using the jmp or call instruction. after that a jump to a non-consecutive program memory address which is located in a certain bank selected by the program memiry bank pointer bits will occur. device bit 7 6 5 4 3 2 1 0 ht?7f?0a bp0 ht?7f70a bp1 bp0 bp register list bp register C HT67F60A bit 7 6 5 4 3 2 1 0 na?e bp0 r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 bp0 : program memory bank point bit 0 0: bank 0 1: bank 1 bp register C ht67f70a bit 7 6 5 4 3 2 1 0 na?e bp1 bp0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 bp1~bp0 : program memory bank point bit 1~0 00: bank 0 01: bank 1 10: bank 2 11: bank 3 accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted.
rev. 1.10 4? de?e??e? 01? ?01? rev. 1.10 47 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointer and indicates the location where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), sc fag, cz fag, power down fag (pdf), and watchdog time-out fag (to). these arithmetic/ logical operation and system management fags are used to record the status and operation of the microcontroller. with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt instruction. the pdf fag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac, c, sc and cz fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. ? sc is the result of the xor operation which is performed by the ov fag and the msb of the current instruction operation result. ? cz is the operational result of different fags for different instuctions. refer to register defnitions for more details. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.10 4? de?e??e? 01? ?01? rev. 1.10 47 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom status register bit 7 6 5 4 3 2 1 0 na?e sc cz to pdf ov z ac c r/w r r r r r/w r/w r/w r/w por x x 0 0 x x x x x: unknown bit 7 sc : the result of the xor operation which is performed by the ov fag and the msb of the instruction operation result. bit 6 cz : the the operational result of different fags for different instuctions. for sub/subm/lsub/lsubm instructions, the cz fag is equal to the z fag. for sbc/ sbcm/ lsbc/ lsbcm instructions, the cz fag is the and operation result which is performed by the previous operation cz fag and current operation zero fag. for other instructions, the cz fag willl not be affected. bit 5 to : watchdog time-out fag 0: after power up ow executing the clr wdt or halt instruction 1: a watchdog time-out occurred bit 4 pdf : power down fag 0: after power up ow executing the clr wdt instruction 1: by executing the halt instructin bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles, in addition, or no borrow from the high nibble into the low nibble in substraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation the c fag is also affected by a rotate through carry instruction.
rev. 1.10 48 de?e??e? 01? ?01? rev. 1.10 49 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom eeprom data memory the device contains an area of internal eeprom data memory. eeprom, which stands for electrically erasable programmable read only memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. by incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. device capacity address ht?7f?0a 1?8 8 00h ~ 7fh ht?7f70a eeprom data memory structure the eeprom data memory capacity is 1288 bits. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. read and write operations to the eeprom are carried out in single byte operations using an address and data register in sector 0 and a single control register in sector 1. eeprom registers three registers control the overall operation of the internal eeprom data memory. these are the address register, eea, the data register, eed and a single control register, eec. as both the eea and eed registers are located in sector 0, they can be directly accessed in the same was as any other special function register. the eec register, however, being located in sector 1, can be read from or written to indirectly using the mp1h/mp1l or mp2h/mp2l memory pointer pair and indirect addressing register, iar1 or iar2. because the eec control register is located at address 40h in sector 1, the memory pointer low byte register, mp1l or mp2l, must frst be set to the value 40h and the memory pointer high byte register, mp1h or mp2h, set to the value, 01h, before any operations on the eec register are executed. register name bit 7 6 5 4 3 2 1 0 eea eea? eea5 eea4 eea3 eea? eea1 eea0 eed d7 d? d5 d4 d3 d? d1 d0 eec wren wr rden rd eeprom registers list eea register bit 7 6 5 4 3 2 1 0 na?e eea? eea5 eea4 eea3 eea? eea1 eea0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6~0 eea6~eea0 : data eeprom address bit 6~bit0
rev. 1.10 48 de?e??e? 01? ?01? rev. 1.10 49 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom eed register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : data eeprom data bit 7~bit0 eec register bit 7 6 5 4 3 2 1 0 na?e wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 wren : data eeprom write enable 0: disable 1: enable this is the data eeprom write enable bit which must be set high before data eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom write control 0: write cycle has fnished 1: activate a write cycle this is the data eeprom write control bit and when set high by the application program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no effect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no effect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time.
rev. 1.10 50 de?e??e? 01? ?01? rev. 1.10 51 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom reading data from the eeprom to read data from the eeprom, the read enable bit, rden, in the eec register must frst be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register. the data will remain in the eed register until another read or write operation is executed. the application program can poll the rd bit to determine when the data is valid for reading. writing data to the eeprom to write data to the eeprom, the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register. then the write enable bit, wren, in the eec register must first be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should also first be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered on, the write enable bit in the control register will be cleared preventing any write operations. also at power-on the memory pointer high byte register, mp1h or mp2h, will be reset to zero, which means that data memory sector 0 will be selected. as the eeprom control register is located in sector 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register. however, as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must also be set. when an eeprom write cycle ends, the def request flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program.
rev. 1.10 50 de?e??e? 01? ?01? rev. 1.10 51 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be periodic by ensuring that the write enable bit is normally cleared to zero when not writing. also the memory pointer high byte register could be normally cleared to zero as this would inhibit access to sector 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly. the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the device should not enter the idle or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. programming example reading data from the eeprom C polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, 040h ; setup memory pointer low byte mp1l mov mp1l, a ; mp1l points to eec register mov a, 01h ; setup memory pointer high byte mp1h mov mp1h, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom write clr bp mov a, eed ; move read data to register mov read_data, a writing data to the eeprom C polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, eeprom_data ; user defned data mov eed, a mov a, 040h ; setup memory pointer low byte mp1l mov mp1l, a ; mp1l points to eec register mov a, 01h ; setup memory pointer high byte mp1h mov mp1h, a clr emi set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bit set emi back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom write clr mp1h
rev. 1.10 5? de?e??e? 01? ?01? rev. 1.10 53 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom oscillator various oscillator types offer the user a wide range of functions according to their various application requirements. the fexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and relevant control registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer and time base interrupts. external oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. all oscillator options are selected through register programming. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capability of dynamically switching between fast and slow system clock, the device has the fexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. pins exte?nal high speed c?ystal hxt 400khz~?0 mhz osc1/osc? inte?nal high speed rc hirc 4/8/1? mhz exte?nal low speed c?ystal lxt 3?.7?8 khz xt1/xt? inte?nal low speed rc lirc 3? khz oscillator types system clock confgurations there are four methods of generating the system clock, two high speed oscillator and two low speed oscillators. the high speed oscillators are the external crystal/ceramic and the internal 4/8/12mhz rc oscillator. the two low speed oscillators are the internal 32 khz rc oscillator and the external 32.768 khz crystal oscillator. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2~cks0 bits in the smod register and as the system clock can be dynamically selected. the actual source clock used for the low speed oscillators is chosen via the confguration option. the frequency of the slow speed or high speed system clock is determined using the hlclk bit and cks2~cks0 bits in the smod register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator.
rev. 1.10 5? de?e??e? 01? ?01? rev. 1.10 53 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom hxt hirc prescaler f h lirc lxt high speed oscillation (hosc) low speed oscillation (losc) f h /2 f h /16 f h /64 f h /8 f h /4 f h /32 high speed oscillation configuration option low speed oscillation configuration option cks[2:0], hlclk f sys fast wake-up from sleep mode or idle mode control (for hxt only) f sub wdt f sub system clock confgurations external crystal/ceramic oscillator C hxt 7kh ([whuqdo &uvwdo&hudplf 6vwhp 2vfloodwru lv rqh ri wkh kljk iuhtxhqf rvfloodwru fkrlfhv zklfk lv vhohfwhg yld frqiljxudwlrq rswlrq )ru prvw fuvwdo rvfloodwru frqiljxudwlrqv wkh vlpsoh frqqhfwlrqridfuvwdodfurvv26&dqg26&zloofuhdwhwkhqhfhvvduskdvhvkliwdqgihhgedfniru rvfloodwlrq zlwkrxw uhtxlulqj h[whuqdo fdsdflwruv rzhyhu iru vrph fuvwdo wshv dqg iuhtxhqflhv wr hqvxuh rvfloodwlrq lw pd eh qhfhvvdu wr dgg wzr vpdoo ydoxh fdsdflwruv & dqg & 8vlqj d fhudplf uhvrqdwru zloo xvxdoo uhtxluh wzr vpdoo ydoxh fdsdflwruv & dqg & wr eh frqqhfwhg dv vkrzq iru rvfloodwlrq wr rffxu 7kh ydoxhv ri & dqg & vkrxog eh vhohfwhg lq frqvxowdwlrq zlwk wkh fuvwdoruuhvrqdwru pdqxidfwxuhuvvshflfdwlrq )ru rvfloodwru vwdelolw dqg wr plqlplvh wkh hiihfwv ri qrlvh dqg furvvwdon lw lv lpsruwdqw wr hqvxuh wkdw wkh fuvwdo dqg dq dvvrfldwhg uhvlvwruv dqg fdsdflwruv dorqj zlwk lqwhufrqqhfwlqj olqhv duh doo orfdwhgdvforvhwrwkh0&8dvsrvvleoh

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crystal/resonator oscillator
rev. 1.10 54 de?e??e? 01? ?01? rev. 1.10 55 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom hxt oscillator c1 and c2 values crystal frequency c1 c2 1?mhz 0 pf 0 pf 8mhz 0 pf 0 pf 4mhz 0 pf 0 pf 1mhz 100 pf 100 pf note: c1 and c? values a?e fo? guidan? e only. crystal recommended capacitor values internal high speed rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a fixed frequency of 4/8/12mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25c degrees, the fixed oscillation frequency of 4mhz, 8mhz or 12mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins are free for use as normal i/o pins. external 32.768 khz crystal oscillator C lxt the external 32.768 khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via a confguration option. this clock source has a fxed frequency of 32.768 khz and requires a 32.768 khz crystal to be connected between pins xt1 and xt2. the external resistor and capacitor components connected to the 32.768 khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. during power-up there is a time delay associated with the lxt oscillator waitingi for it to start-up. when the microcontroller enters the sleep or idle mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. to do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specification. the external parallel feedback resistor, rp, is required. note that the wire connected between the 32.768 khz crystal and the xt1/ xt2 pins should be kept as short as possible to minimise the stray noise interference. the pin-shared software control bits determine if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o pins. ? if the lxt oscillator is used for any clock source, the 32.768 khz crystal should be connected to the xt1/xt2 pins. for oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the mcu as possible.
rev. 1.10 54 de?e??e? 01? ?01? rev. 1.10 55 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom
? ?? ?? ? - - external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 1?mhz 0 pf 0 pf 8mhz 0 pf 0 pf 4mhz 0 pf 0 pf 1mhz 100 pf 100 pf note: c1 and c? values a?e fo? guidan? e only. crystal recommended capacitor values lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low-power mode. the mode selection is executed using the lxtlp bit in the smod2 register lxtlp lxt operating mode 0 qui?k sta?t 1 low powe? smod2 register bit 7 6 5 4 3 2 1 0 na?e lxtlp r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 lxtlp : lxt low power control 0: disable C quick start mode 1: enable C low power mode after power on the lxtlp bit will be automatically cleared to zero to ensure that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. however, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always function normally, the only difference is that it will take more time to start up if in the low- power mode.
rev. 1.10 5? de?e??e? 01? ?01? rev. 1.10 57 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom internal 32khz oscillator C lirc the internal 32 khz system oscillator is one of the low frequency oscillator choices, which is selected via a confguration option. it is a fully integrated rc oscillator with a typical frequency of 32 khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25?c degrees, the fxed oscillation frequency of 32 khz will have a tolerance within 3%. supplementary oscillators the low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to two other device functions. these are the watchdog timer and the time base interrupts. operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conficting requirements that are especially true in battery powered portable applications. the fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. as holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using confguration options and register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency, f h , or low frequency, f sub , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from an hxt or hirc oscillator, selected via a confguration option. the low speed system clock source can be sourced from the clock, f sub . if f sub is selected then it can be sourced by either the lxt or lirc oscillators, selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. the f sub clock is also used to provide the clock source for time base and watchdog timer functions.
rev. 1.10 5? de?e??e? 01? ?01? rev. 1.10 57 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom hxt hirc prescaler f h lirc lxt high speed oscillation (hosc) low speed oscillation (losc) f h /2 f h /16 f h /64 f h /8 f h /4 f h /32 high speed oscillation configuration option low speed oscillation configuration option cks[2:0], hlclk f sys fast wake-up from sleep mode or idle mode control (for hxt only) f sys /4 f sub f tb wdt time base clks0[1:0] f sub f sub f sys f h prescaler f p clks1[1:0] prescaler peripheral clock output (pck) tb2 [2:0] tb0 [2:0] tb1 [2:0] f sys /4 f sub f sys f h lcd f sub idlen f tbc system clock confgurations ote en te system clock source sys sub up s d d ss uy su uuu ~f ususudu system operation modes 7khuh duh vl[ gliihuhqw prghv ri rshudwlrq iru wkh plfurfrqwuroohu hdfk rqh zlwk lwv rzq vshfldo fkdudfwhulvwlfv dqg zklfk fdq eh fkrvhq dffruglqj wr wkh vshflilf shuirupdqfh dqg srzhu uhtxluhphqwv ri wkh dssolfdwlrq 7khuh duh wzr prghv doorzlqj qrupdo rshudwlrq ri wkh plfurfrqwuroohu wkh 1250/ 0rgh dqg 6/2: 0rgh 7kh uhpdlqlqj irxu prghv wkh 6/((3 6/((3 ,/( dqg ,/( 0rgh duh xvhg zkhq wkh plfurfrqwuroohu &38 lv vzlwfkhg rii wr frqvhuyh srzhu
rev. 1.10 58 de?e??e? 01? ?01? rev. 1.10 59 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom operating mode description cpu f sys f tbc f sub normal on f h ~f h /?4 on on slow on f sub on on idle0 off off on on idle1 off on on on sleep0 off off off off sleep1 off off off on normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt or hirc oscillators. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep0 mode is entered when an halt instruction is executed and the idlen bit in the smod register is low. in the sleep0 mode the cpu will be stopped and the f sub clock will be stopped too, and the watchdog timer function is disabled. in this mode, the lvden is must set to 0. if the lvden is set to 1, it wont enter the sleep0 mode. sleep1 mode the sleep1 mode is entered when an halt instruction is executed and the idlen bit in the smod register is low. in the sleep1 mode the cpu will be stopped. however the f sub will continue to operate if the lvden is 1 or the watchdog timer function is enabled. idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the smod1 register is low. in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer and tms. in the idle0 mode, the system oscillator will be stopped while the f sub clock will be on. idle1 mode the idle1 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the smod1 register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the watchdog timer and tms. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode the f sub clock will also be on.
rev. 1.10 58 de?e??e? 01? ?01? rev. 1.10 59 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom control registers the registers, smod and smod1, are used to control the system clock and the corresponding oscillator confgurations. register name bit 7 6 5 4 3 2 1 0 smod cks? cks1 cks0 fsten lto hto idlen hlclk smod1 fsyson lvrf lrf wrf system operating mode control registers list smod register bit 7 6 5 4 3 2 1 0 na?e cks? cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 cks2~cks0 : system clock selection 000: f (f lxt or f lirc ) 001: f (f lxt or f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or the lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fsten : fast wak-up control (only for hxt) 0: disable 1: enable this is the fast wake-up control bit which determines if the f clock source is initially used after the device wakes up. when the bit is high, the f clock source can be used as a temporary system clock to provide a faster wake up time as the f clock is available. bit 3 lto : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed sysem oscillator ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the lxt oscillator is used or 1~2 clock cycles if the lirc oscillator is used. bit 2 hto : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed sysem oscillator ready fag which indicates when the high speed system oscillator is stable. the fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as 1 by application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used or 15~16 clock cycles if the hirc oscillator is used.
rev. 1.10 ?0 de?e??e? 01? ?01? rev. 1.10 ?1 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed, the device will enter the idle mode. in the idle1 mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational if the fsyson bit is high. if the fsyson bit is low, the cpu and the system clock will stop in idle0 mode. if the bit is low, the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk : system clock selection 0: f h /2~f h /64 or f sub 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f sub clock is used as the system clock. when the bit is high, the f h clock will be selected and if low the f h /2~f h /64 or f sub clock will be selected. when the system clock switches from the f h clock to the f sub clock, the f h clock will be automatically switched off to conserve power. na?e fsyson rstf lvrf lrf wrf r/w r/w r/w r/w r/w r/w por 0 0 x 0 0 x: unknown bit 7 fsyson : system clock f sys control in idle mode 0: disable 1: enable bit 6~4 unimplemented, read as 0 bit 3 rstf : reset control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the rstc control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program. bit 2 lvrf : lvr function reset fag 0: not occurred 1: occurred this bit is set to 1 when a specifc low voltage reset condition occurs. note that this bit can only be cleared to 0 by the application program. bit 1 lrf : lvr control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the lvrc control register contains any undefned lvr voltage register values. this in effect acts like a software-reset function. note that this bit can only be cleared to 0 by the application program. bit 0 wrf : wdt control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program.
rev. 1.10 ?0 de?e??e? 01? ?01? rev. 1.10 ?1 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom fast wake-up to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilize and allow normal operation to resume. to ensure the device is up and running as fast as possible a fast wake-up function is provided, which allows f sub , namely either the lxt or lirc oscillator, to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast wake-up function is f sub , the fast wake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fastwake-up function has no effect because the f sub clock is stopped. the fastwake-up enable/disable function is controlled using the fsten bit in the smod1 register. if the hxt oscillator is selected as the normal mode system clock and if the fast wake-up function is enabled, then it will take one to two t sub clock cycles of the lxt or lirc oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hxt clock cycles have elapsed, at which point the hto fag will switch high and the system will switch over to operating from the hxt oscillator. if the hirc or lirc oscillator is used as the system oscillator, then it will take 15~16 clock cycles of the hirc oscillator or 1~2 clock cycles of the lirc osrillator respectively to wake up the system from the sleep or idle0 mode. the fast wake-up bit, fsten will have no effect in these cases. system oscillator fsten bit wake-up time (sleep0 mode) wake-up time (sleep1 mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hxt 0 10? 4 hxt ?y?les 10? 4 hxt ?y?les 1~? hxt ?y?les 1 10? 4 hxt ?y?les 1~? f sub ?y?les (syste? ?uns with f sub frst for 1024 hxt ?y?les and then swit?hes ove? to ? un with the hxt ?lo?k ) 1~? hxt ?y?les hirc x 15~1? hirc ?y?les 15~1? hirc ?y?les 1~? hirc ?y?les lirc x 1~? lirc ?y?les 1~? lirc ?y?les 1~? lirc ?y?les lxt x 10? 4 lxt ?y?les 10? 4 lxt ?y?les 1~? lxt ?y?les wake-up times note that if the watchdog timer is disabled, which means that the f sub clock derived from the lxt or lirc oscillator is off, then there will be no fast wake-up function available when the device wakes up from the sleep0 mode.
rev. 1.10 ?? de?e??e? 01? ?01? rev. 1.10 ?3 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom operating mode switching the device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the smod1 register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~ f h /64 or f sub . if the clock is from the f sub , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the tms. the accompanying fowchart shows what happens when the device moves between the various operating modes.

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rev. 1.10 ?? de?e??e? 01? ?01? rev. 1.10 ?3 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to 0 and set the cks2~cks0 bits to 000 or 001 in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lxt or the lirc oscillators and therefore requires these oscillators to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register.
? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ? ?- ?? ? ? - ?? ? ? ? ? ? ? ?- ?? ?? -? ?
rev. 1.10 ?4 de?e??e? 01? ?01? rev. 1.10 ?5 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom slow mode to normal mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0, but cks2~cks0 is set to 010, 011, 100, 101, 110 or 111. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used.
? ? ? ? ? ? ?? ?? ? - ?? ? ? ? ? ?? ?? ? - ?? ? ? ? ? ? ?? ?? ? - ? ?? ? ? ? ? ?? ?? ? - ?? ?
rev. 1.10 ?4 de?e??e? 01? ?01? rev. 1.10 ?5 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom entering the sleep0 mode there is only one way for the device to enter the sleep0 mode and that is to execute the halt instruction in the application program with the idlen bit in the smod register equal to 0 and the wdt and lvd both off. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and the f sub clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag to will be cleared. ? the wdt will be cleared and stopped as the wdt function is disabled. entering the sleep1 mode there is only one way for the device to enter the sleep1 mode and that is to execute the halt instruction in the application program with the idlen bit in the smod register equal to 0 and the wdt or lvd on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the "halt" instruction but the wdt or lvd will remain with the clock source coming from the f sub clock ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag to will be cleared. ? the wdt will be cleared and resume counting as the wdt function is enabled and the clock source is derived from the f sub clock. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in smod1 register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction, but the f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag to will be cleared. ? the wdt will be cleared and resume counting as the wdt clock source is derived from the f sub clock.
rev. 1.10 ?? de?e??e? 01? ?01? rev. 1.10 ?7 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in smod1 register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and the f sub clock will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag to will be cleared. ? the wdt will be cleared and resume counting as the wdt clock source is derived from the f sub clock. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of these devices to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on these devices. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonded pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps.
rev. 1.10 ?? de?e??e? 01? ?01? rev. 1.10 ?7 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom wake-up to minimise power consumption the device can enter the sleep or any idle mode, where the cpu will be switched off. however, when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stablise and allow normal operation to resume. after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow as the main reason for entering the sleep or idle mode is to keep the current consumption of these devices to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on these devices. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonded pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps.
rev. 1.10 ?8 de?e??e? 01? ?01? rev. 1.10 ?9 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the f sub clock. the f sub clock can be source from either the lxt or lirc oscillator selected by a configuration option. the lirc oscillator has an approximate frequency of 32 khz and this specified internal clock period can vary with v dd , temperature and process variations. the lxt oscillator is supplied by an external 32.768 khz crystal. the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. watchdog timer control register a single register, wdtc, controls the required timeout period as well as the enable/disable operation. this register controls the overall operation of the watchdog timer. wdtc register bit 7 6 5 4 3 2 1 0 na?e we4 we3 we? we1 we0 ws? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 : wdt function enable control 10101: disabled 01010: enabled other values: reset mcu if these bits are changed due to adverse environmental conditions, the microcontroller will be reset. the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the smod1 register will be set to 1. bit 2~0 : wdt time-out period selection 000: 2 8 /f sub 001: 2 10 /f sub 010: 2 12 /f sub 011: 2 14 /f sub 100: 2 15 /f sub 101: 2 16 /f sub 110: 2 17 /f sub 111: 2 18 /f sub these three buts determine the division ratio of the watchdog timer source clock, which in turn determines the time-out period.
rev. 1.10 ?8 de?e??e? 01? ?01? rev. 1.10 ?9 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom smod1 register bit 7 6 5 4 3 2 1 0 na?e fsyson rstf lvrf lrf wrf r/w r/w r/w r/w r/w r/w por 0 0 x 0 0 x: unknown bit 7 fsyson : system clock f control in idle mode described elsewhere bit 6~4 unimplemented, read as 0 bit 3 rstf : reset control register software reset fag described elsewhere bit 2 lvrf : lvr function reset fag described elsewhere bit 1 lrf : lvr control register software reset fag described elsewhere bit 0 wrf : wdt control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program. watchdog timer operation the watchdog timer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instruction. if the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, the clear instruction will not be executed in the correct manner, in which case the watchdog timer will overfow and reset the device. with regard to the watchdog timer enable/disable function, there are fve bits, we4~we0, in the wdtc register to offer the enable/disable control and reset control of the watchdog timer. the wdt function will be disabled when the we4~we0 bits are set to a value of 10101b while the wdt function will be enabled if the we4~we0 bits are equal to 01010b. if the we4~we0 bits are set to any other values, other than 01010b and 10101b, it will reset the device after 2~3 f lirc clock cycles. after power on these bits will have a value of 01010b. we4 ~ we0 bits wdt function 10101b disa?le 01010b ena?le any othe? value reset mcu watchdog timer enable/disable control under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. four methods can be adopted to clear the contents of the watchdog timer. the frst is an external hardware reset, which means a low level on the res pin. the second is a wdt software reset, which means a certain value except 01010b and 10101b written into the we4~we0 feld, the third is using the watchdog timer software clear instruction and the forth is via a halt instruction.
rev. 1.10 70 de?e??e? 01? ?01? rev. 1.10 71 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom there is only one method of using software instruction to clear the watchdog timer. that is to use the single clr wdt instruction to clear the wdt contents. the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. clr wdt instruction 8-stage divider wdt prescaler we4~we0 bits wdtc register reset mcu f sub f sub /2 8 8-to-1 mux clr ws2~ws0 (f sub /2 8 ~ f sub /2 18 ) wdt time-out (2 8 /f sub ~ 2 18 /f sub ) halt instruction res pin watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the device is running. one example of this is where after power has been applied and the device is already running, the res line is forcefully pulled low. in such a case, known as a normal operation reset, some of the registers remain unchanged allowing the device to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold.
rev. 1.10 70 de?e??e? 01? ?01? rev. 1.10 71 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and externally. power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. power-on reset timing chart res pin reset as the reset pin is shared with an i/o pin, the reset function must be selected using the rstc control register. the rstc register is used to determine that the pin is used as an external reset pin or an i/o pin. however, if the content of the rstc register is set to any value other than 01010101b or 10101010b, it will reset the device after 2~3 f lirc clock cycles. after power on the register will have a value of 01010101b. rstc7 ~ rstc0 bits pin function 01010101b i/o pin 10101010b res pin any othe? value reset mcu internal reset function control although the microcontroller has an internal rc reset function, if the v dd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the fgures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended.
rev. 1.10 7? de?e??e? 01? ?01? rev. 1.10 73 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is signifcant. external res circuit more information regarding external reset circuits is located in application note ha0075e on the holtek website. pulling the res pin low using external hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. res reset timing chart ? rstc register bit 7 6 5 4 3 2 1 0 na?e rstc7 rstc? rstc5 rstc4 rstc3 rstc? rstc1 rstc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 rstc7~rstc0 : reset pin function control 01010101: i/o pin 10101010: external reset pin other values: reset mcu if these bits are changed due to adverse environmental conditions, the microcontroller will be reset. the reset operation will be activated after 2~3 lirc clock cycles and the rstf bit in the smod1 register will be set to 1.
rev. 1.10 7? de?e??e? 01? ?01? rev. 1.10 73 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ? smod1 register bit 7 6 5 4 3 2 1 0 na?e fsyson rstf lvrf lrf wrf r/w r/w r/w r/w r/w r/w por 0 0 x 0 0 x: unknown bit 7 fsyson : system clock f control in idle mode described elsewhere bit 6~4 unimplemented, read as 0 bit 3 rstf : reset control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the rstc control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program. bit 2 lvrf : lvr function reset fag described elsewhere bit 1 lrf : lvr control register software reset fag described elsewhere bit 0 wrf : wdt control register software reset fag described elsewhere low voltage reset C lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the lvr function is always enabled with a specifc lvr voltage, v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally and the lvrf bit in the smod1 register will also be set to 1. for a valid lvr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specifed by t lvr in the lvd/lvr characteristics. if the low supply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be selected by the lvs bits in the lvrc register. if the lvs7~lvs0 bits have any other value, which may perhaps occur due to adverse environmental conditions such as noise, the lvr will reset the device after 2~3 f lirc clock cycles. when this happens, the lrf bit in the smod1 register will be set to 1. after power on the register will have the value of 01010101b. note that the lvr function will be automatically disabled when the device enters the power down mode. low voltage reset timing chart
rev. 1.10 74 de?e??e? 01? ?01? rev. 1.10 75 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ? lvrc register bit 7 6 5 4 3 2 1 0 na?e lvs7 lvs ? lvs5 lvs4 lvs3 lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0 : lvr voltage select 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v other values: generates a mcu reset C register is reset to por value when an actual low voltage condition occurs, as specifed by one of the four defned lvr voltage value above, an mcu reset will generated. the reset operation will be activated after 2~3 f lirc clock cycles. in this situation the register contents will remain the same after such a reset occurs. any register value, other than the four defned register values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 f lirc clock cycles. however in this situation the register contents will be reset to the por value. ? smod1 register bit 7 6 5 4 3 2 1 0 na?e fsyson rstf lvrf lrf wrf r/w r/w r/w r/w r/w r/w por 0 0 x 0 0 x: unknown bit 7 fsyson : system clock f control in idle mode described elsewhere bit 6~4 unimplemented, read as 0 bit 3 rstf : reset control register software reset fag described elsewhere bit 2 lvrf : lvr function reset fag 0: not occurred 1: occurred this bit is set to 1 when a specifc low voltage reset condition occurs. note that this bit can only be cleared to 0 by the application program. bit 1 lrf : lvr control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the lvrc control register contains any undefned lvr voltage register values. this in effect acts like a software-reset function. note that this bit can only be cleared to 0 by the application program. bit 0 wrf : wdt control register software reset fag described elsewhere
rev. 1.10 74 de?e??e? 01? ?01? rev. 1.10 75 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as the hardware res pin reset except that the watchdog time-out fag to will be set to 1. wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the to fag will be set to 1. refer to the a.c. characteristics for t sst details. wdt time-out reset during sleep or idle mode timing chart reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset function 0 0 powe?-on ?eset u u res o? lvr ?eset du? ing normal o? slow mode ope?ation 1 u wdt ti ?e-out ?eset du? ing normal o? slow mode ope?ation 1 1 wdt ti ?e-out ?eset du?ing idle o? sleep mode ope?ation u stands fo? un?hanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item reset function p?og?a? counte? reset to ze?o inte??upts all inte??upts will ?e disa?led wdt ? ti? e base clea? afte? ?eset? wdt ?egins ?ounting ti ?e? modules ti ?e? modules will ?e tu? ned off input/output po?ts i/o po?ts will ?e setup as inputs sta?k pointe? sta?k pointe? will point to the top of the sta?k the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects the microcontroller internal registers.
rev. 1.10 7? de?e??e? 01? ?01? rev. 1.10 77 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom register HT67F60A ht67f70a reset (power on) lvr reset (normal operation) wdt time-out (normal operation) wdt time-out (idle or sleep) iar0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp0 0000 0000 0000 0000 0000 0000 uuuu uuuu iar1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1l 0000 0000 0000 0000 0000 0000 uuuu uuuu mp1h 0000 0000 0000 0000 0000 0000 uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp --xx xxxx ---- uuuu ---- uuuu ---- uuuu tbhp -xxx xxxx ---- uuuu ---- uuuu ---- uuuu status xx00 xxxx uuuu uuuu uu1u uuuu uu11 uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---u bp ---- --00 ---- --00 ---- --00 ---- --uu iar? xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp?l 0000 0000 0000 0000 0000 0000 uuuu uuuu mp?h 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu -000 0000 -000 0000 -000 0000 -uuu uuuu pb -000 1111 -000 1111 -000 1111 -uuu uuuu pbc -111 1111 -111 1111 -111 1111 -uuu uuuu pcpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu pfpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pf 1111 1111 1111 1111 1111 1111 uuuu uuuu pfc 1111 1111 1111 1111 1111 1111 uuuu uuuu lcdc0 00-- 0000 00-- 0000 00-- 0000 uu-- uuuu lcdc1 000- 0000 000- 0000 000- 0000 uuu- uuuu rstc 0101 0101 0101 0101 0101 0101 uuuu uuuu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc? 0000 0000 0000 0000 0000 0000 uuuu uuuu intc3 -000 -000 -000 -000 -000 -000 -uuu -uuu mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 -000 -000 -000 -000 -000 -000 -uuu -uuu
rev. 1.10 7? de?e??e? 01? ?01? rev. 1.10 77 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom register HT67F60A ht67f70a reset (power on) lvr reset (normal operation) wdt time-out (normal operation) wdt time-out (idle or sleep) mfi? 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi3 -000 -000 -000 -000 -000 -000 -uuu -uuu mfi4 0000 0000 0000 0000 0000 0000 uuuu uuuu integ 0000 0000 0000 0000 0000 0000 uuuu uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu smod1 0--- 0x00 0--- 0x00 0--- 0x00 u--- uuuu lvrc 0101 0101 0101 0101 0101 0101 uuuu uuuu lvdc --00 0000 --00 0000 --00 0000 --uu uuuu wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu smod? ---- ---0 ---- ---0 ---- ---0 ---- ---u eea -000 0000 -000 0000 -000 0000 -uuu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu cp0c -000 ---1 -000 ---1 -000 ---1 -uuu ---u cp1c -000 ---1 -000 ---1 -000 ---1 -uuu ---u etmc0 0000 0000 0000 0000 0000 0000 uuuu uuuu etmc1 0000 0000 0000 0000 0000 0000 uuuu uuuu etmc? 0000 0000 0000 0000 0000 0000 uuuu uuuu etmdl 0000 0000 0000 0000 0000 0000 uuuu uuuu etmdh ---- --00 ---- --00 ---- --00 ---- --uu etmal 0000 0000 0000 0000 0000 0000 uuuu uuuu etmah ---- --00 ---- --00 ---- --00 ---- --uu etmbl 0000 0000 0000 0000 0000 0000 uuuu uuuu etmbh ---- --00 ---- --00 ---- --00 ---- --uu stm0c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- stm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu stm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu stm0dh 0000 0000 0000 0000 0000 0000 uuuu uuuu stm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu stm0ah 0000 0000 0000 0000 0000 0000 uuuu uuuu stm0rp 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm1dh ---- --00 ---- --00 ---- --00 ---- --uu ctm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm1ah ---- --00 ---- --00 ---- --00 ---- --uu ctm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm0dh ---- --00 ---- --00 ---- --00 ---- --uu ctm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu ctm0ah ---- --00 ---- --00 ---- --00 ---- --uu psc0 ---- --00 ---- --00 ---- --00 ---- --uu tbc0 0--- -000 0--- -000 0--- -000 u--- -uuu tbc1 0--- -000 0--- -000 0--- -000 u--- -uuu
rev. 1.10 78 de?e??e? 01? ?01? rev. 1.10 79 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom register HT67F60A ht67f70a reset (power on) lvr reset (normal operation) wdt time-out (normal operation) wdt time-out (idle or sleep) psc1 ---- --00 ---- --00 ---- --00 ---- --uu sadc0 0110 0000 0110 0000 0110 0000 uuuu uuuu sadc1 -000 -000 -000 -000 -000 -000 -uuu Cuuu sadol (adrfs=0) xxxx ---- xxxx ---- xxxx ---- uuuu ---- sadol (adrfs=1) xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu sadoh (adrfs=0) xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu sadoh (adrfs=1) ---- xxxx ---- uuuu ---- uuuu ---- uuuu simc0 111- 000- 111- 000- 111- 000- uuu- uuu- simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu simc1/sima 0000 0000 0000 0000 0000 0000 uuuu uuuu i? ctoc 0000 0000 0000 0000 0000 0000 uuuu uuuu spiac0 111- --0- 111- --0- 111- --0- uuu- --u- spiac1 0000 0000 0000 0000 0000 0000 uuuu uuuu spiad 0000 0000 0000 0000 0000 0000 uuuu uuuu farl 0000 0000 0000 0000 0000 0000 uuuu uuuu farh --00 0000 --00 0000 --00 0000 --uu uuuu farh -000 0000 -000 0000 -000 0000 -uuu uuuu fd0l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd0h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd1l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd1h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd?l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd?h 0000 0000 0000 0000 0000 0000 uuuu uuuu fd3l 0000 0000 0000 0000 0000 0000 uuuu uuuu fd3h 0000 0000 0000 0000 0000 0000 uuuu uuuu tbc? 0--- -000 0--- -000 0--- -000 u--- -uuu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu fc0 0000 0000 0000 0000 0000 0000 uuuu uuuu fc1 0000 0000 0000 0000 0000 0000 uuuu uuuu fc? ---- ---0 ---- ---0 ---- ---0 ---- ---u ifs0 0000 0000 0000 0000 0000 0000 uuuu uuuu ifs1 0000 0000 0000 0000 0000 0000 uuuu uuuu ifs? 0000 0000 0000 0000 0000 0000 uuuu uuuu ifs3 0000 0000 0000 0000 0000 0000 uuuu uuuu ifs4 0000 0000 0000 0000 0000 0000 uuuu uuuu stm1c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- stm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu stm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu stm1dh 0000 0000 0000 0000 0000 0000 uuuu uuuu stm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu stm1ah 0000 0000 0000 0000 0000 0000 uuuu uuuu stm1rp 0000 0000 0000 0000 0000 0000 uuuu uuuu stm?c0 0000 0000 0000 0000 0000 0000 uuuu uuuu stm?c1 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.10 78 de?e??e? 01? ?01? rev. 1.10 79 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom register HT67F60A ht67f70a reset (power on) lvr reset (normal operation) wdt time-out (normal operation) wdt time-out (idle or sleep) stm?dl 0000 0000 0000 0000 0000 0000 uuuu uuuu stm?dh 0000 0000 0000 0000 0000 0000 uuuu uuuu stm?al 0000 0000 0000 0000 0000 0000 uuuu uuuu stm?ah 0000 0000 0000 0000 0000 0000 uuuu uuuu stm?rp 0000 0000 0000 0000 0000 0000 uuuu uuuu pas0 0000 0000 0000 0000 0000 0000 uuuu uuuu pas1 0000 0000 0000 0000 0000 0000 uuuu uuuu pbs0 0000 0000 0000 0000 0000 0000 uuuu uuuu pbs1 0000 0000 0000 0000 0000 0000 uuuu uuuu pcs0 0000 0000 0000 0000 0000 0000 uuuu uuuu pcs1 0000 0000 0000 0000 0000 0000 uuuu uuuu pds0 0000 0000 0000 0000 0000 0000 uuuu uuuu pds1 0000 0000 0000 0000 0000 0000 uuuu uuuu pes0 0000 0000 0000 0000 0000 0000 uuuu uuuu pes1 0000 0000 0000 0000 0000 0000 uuuu uuuu pfs0 0000 0000 0000 0000 0000 0000 uuuu uuuu pfs1 0000 0000 0000 0000 0000 0000 uuuu uuuu note: u stands for unchanged x stands for unknown - stands for unimplemented
rev. 1.10 80 de?e??e? 01? ?01? rev. 1.10 81 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom input/output ports holtek microcontrollers offer considerable fexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. these devices provide bidirectional input/output lines labeled with port names pa~pf. these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pawu pawu7 pawu ? pawu5 pawu4 pawu3 pawu ? pawu1 pawu0 papu papu7 papu ? papu5 papu4 papu3 papu ? papu1 papu0 pa pa7 pa ? pa5 pa4 pa3 pa ? pa1 pa0 pac pac7 pac ? pac5 pac4 pac3 pac ? pac1 pac0 pbpu pbpu? pbpu5 pbpu4 pbpu3 pbpu? pbpu1 pbpu0 pb pb? pb5 pb4 pb3 pb? pb1 pb0 pbc pbc? pbc5 pbc4 pbc3 pbc? pbc1 pbc0 pcpu pcpu7 pcpu? pcpu5 pcpu4 pcpu3 pcpu? pcpu1 pcpu0 pc pc7 pc? pc5 pc4 pc3 pc? pc1 pc0 pcc pcc7 pcc? pcc5 pcc4 pcc3 pcc? pcc1 pcc0 pdpu pdpu7 pdpu? pdpu5 pdpu4 pdpu3 pdpu? pdpu1 pdpu0 pd pd7 pd? pd5 pd4 pd3 pd? pd1 pd0 pdc pdc7 pdc? pdc5 pdc4 pdc3 pdc? pdc1 pdc0 pepu pepu7 pepu? pepu5 pepu4 pepu3 pepu? pepu1 pepu0 pe pe7 pe? pe5 pe4 pe3 pe? pe1 pe0 pec pec7 pec? pec5 pec4 pec3 pec? pec1 pec0 pfpu pfpu7 pfpu? pfpu5 pfpu4 pfpu3 pfpu? pfpu1 pfpu0 pf pf7 pf? pf5 pf4 pf3 pf? pf1 pf0 pfc pfc7 pfc? pfc5 pfc4 pfc3 pfc? pfc1 pfc0 i/o registers list : unimplemented, read as 0 pawun : pa wake-up function control 0: disable 1: enable papun/pbpun/pcpun/pdpun/pepun/pfpun : i/o pin pull-high function control 0: disable 1: enable pan/pbn/pcn/pdn/pen/pfn : i/o pin data bit 0: data 0 1: data 1 pacn/pbcn/pccn/pdcn/pecn/pfcn : i/o pin type selection 0: output 1: input
rev. 1.10 80 de?e??e? 01? ?01? rev. 1.10 81 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers papu~pfpu, and are implemented using weak pmos transistors. port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 na?e pawu7 pawu ? pawu5 pawu4 pawu3 pawu ? pawu1 pawu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 i/o port a bit 7 ~ bit 0 wake-up function control 0: disable 1: enable i/o port control registers each port has its own control register, known as pac~pfc, which controls the input/output configuration. with this control register, each i/o pin with or without pull-high resistors can be reconfigured dynamically under software control. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these diffculties can be overcome. for these pins, the desired function of the multi-function i/o pins is selected by a series of registers via the application program control.
rev. 1.10 8? de?e??e? 01? ?01? rev. 1.10 83 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pin-shared function selection registers the limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. the device includes port x output function selection register n, labeled as pxsn, and input function selection register i, labeled as ifsi, which can select the desired functions of the multi-function pin-shared pins. when the pin-shared input function is selected to be used, the corresponding input and output functions selection should be properly managed. for example, if the i 2 c sda line is used, the corresponding output pin-shared function should be configured as the sdi/sda function by confguring the pxsn register and the sda signal input should be properly selected using the ifsi register. however, if the external interrupt function is selected to be used, the relevant output pin- shared function should be selected as an i/o function and the interrupt input signal should be selected, as well as the timer module input. the most important point to note is to make sure that the desired pin-shared function is properly selected and also deselected. to select the desired pin-shared function, the pin-shared function should frst be correctly selected using the corresponding pin-shared control register. after that the corresponding peripheral functional setting should be confgured and then the peripheral function can be enabled. to correctly deselect the pn-shared function, the peripheral function should frst be disabled and then the corresponding pin-shared function control register can be modifed to select other pin-shared functions. register name bit 7 6 5 4 3 2 1 0 pas0 pa3s1 pa3s0 pa ?s1 pa ?s0 pa1s1 pa1s0 pa0s1 pa0s0 pas1 pa7s1 pa7s0 pa ?s1 pa ?s0 pa5s1 pa5s0 pa4s1 pa4s0 pbs0 pb3s1 pb3s0 pb?s1 pb?s0 pb1s1 pb1s0 pb0s1 pb0s0 pbs1 pb?s1 pb?s0 pb5s1 pb5s0 pb4s1 pb4s0 pcs0 pc3s1 pc3s0 pc?s1 pc?s0 pc1s1 pc1s0 pc0s1 pc0s0 pcs1 pc7s1 pc7s0 pc?s1 pc?s0 pc5s1 pc5s0 pc4s1 pc4s0 pds0 pd3s1 pd3s0 pd?s1 pd?s0 pd1s1 pd1s0 pd0s1 pd0s0 pds1 pd7s1 pd7s0 pd?s1 pd?s0 pd5s1 pd5s0 pd4s1 pd4s0 pes0 pe3s1 pe3s0 pe?s1 pe?s0 pe1s1 pe1s0 pe0s1 pe0s0 pes1 pe7s1 pe7s0 pe?s1 pe?s0 pe5s1 pe5s0 pe4s1 pe4s0 pfs0 pf3s1 pf3s0 pf?s1 pf?s0 pf1s1 pf1s0 pf0s1 pf0s0 pfs1 pf7s1 pf7s0 pf?s1 pf?s0 pf5s1 pf5s0 pf4s1 pf4s0 ifs0 pintbs int3s int?s int1s int0s ifs1 stck0s stp0is etcks etpibs etpias ctck0s ifs? stck?s stp?is stck1s stp1is ctck1s ifs3 sdias sdis sckas scks scsas scss ifs4 c1ns c1ps c0ns c0ps pin-shared function selection registers list
rev. 1.10 8? de?e??e? 01? ?01? rev. 1.10 83 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pas0 register bit 7 6 5 4 3 2 1 0 na?e pa3s1 pa3s0 pa ?s1 pa ?s0 pa1s1 pa1s0 pa0s1 pa0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pa3s1~pa3s0 : pa3 pin function selection 00: pa3/ctck0 01: sdi/sda 10: vref 11: an1 bit 5~4 pa2s1~pa2s0 : pa2 pin function selection 00/01/10: pa2 11: an4 bit 3~2 pa1s1~pa1s0 : pa1 pin function selection 00: pa1 01: sdo 10: ctp0 11: an0 bit 1~0 pa0s1~pa0s0 : pa0 pin function selection 00/01/10: pa0 11: an5 pas1 register bit 7 6 5 4 3 2 1 0 na?e pa7s1 pa7s0 pa ?s1 pa ?s0 pa5s1 pa5s0 pa4s1 pa4s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pa7s1~pa7s0 : pa7 pin function selection 00/10: pa7/int1/stp0i 01: stp0 11: an7 bit 5~4 pa6s1~pa6s0 : pa6 pin function selection 00/01/10: pa6/int0/etck 11: an6 bit 3~2 pa5s1~pa5s0 : pa5 pin function selection 00: pa5/etpib 01: scs 10: etpb 11: an3 bit 1~0 pa4s1~pa4s0 : pa4 pin function selection 00: pa4/etpia/ pint 01: sck/scl 10: etpa 11: an2
rev. 1.10 84 de?e??e? 01? ?01? rev. 1.10 85 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pbs0 register bit 7 6 5 4 3 2 1 0 na?e pb3s1 pb3s0 pb?s1 pb?s0 pb1s1 pb1s0 pb0s1 pb0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pb3s1~pb3s0 : pb3 pin function selection 00/01: pb3/int3 10: ctp1 11: an11 bit 5~4 pb2s1~pb2s0 : pb2 pin function selection 00/01/10: pb2/int2/stck0 11: an10 bit 3~2 pb1s1~pb1s0 : pb1 pin function selection 00/10: pb1 01: scka 11: an9 bit 1~0 pb0s1~pb0s0 : pb0 pin function selection 00/10: pb0/ctck1 01: scsa 11: an8 pbs1 register bit 7 6 5 4 3 2 1 0 na?e pb?s1 pb?s0 pb5s1 pb5s0 pb4s1 pb4s0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~4 pb6s1~pb6s0 : pb6 pin function selection 00/01/10: pb6 11: c2 bit 3~2 pb5s1~pb5s0 : pb5 pin function selection 00/01/10: pb5 11: c1 bit 1~0 pb4s1~pb4s0 : pb4 pin function selection 00/01/10: pb4 11: v2
rev. 1.10 84 de?e??e? 01? ?01? rev. 1.10 85 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pcs0 register bit 7 6 5 4 3 2 1 0 na?e pc3s1 pc3s0 pc?s1 pc?s0 pc1s1 pc1s0 pc0s1 pc0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pc3s1~pc3s0 : pc3 pin function selection 00: pc3/stck1 01: pck 10: c0p 11: seg3 bit 5~4 pc2s1~pc2s0 : pc2 pin function selection 00: pc2/stp2i 01: stp2 10: c1x 11: seg2 bit 3~2 pc1s1~pc1s0 : pc1 pin function selection 00/01: pc1/stck2/ pint 10: c1n 11: seg1 bit 1~0 pc0s1~pc0s0 : pc0 pin function selection 00/01: pc0 10: c1p 11: seg0 pcs1 register bit 7 6 5 4 3 2 1 0 na?e pc7s1 pc7s0 pc?s1 pc?s0 pc5s1 pc5s0 pc4s1 pc4s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pc7s1~pc7s0 : pc7 pin function selection 00: pc7/stck0 01: scsa 10: c0n 11: seg7 bit 5~4 pc6s1~pc6s0 : pc6 pin function selection 00: pc6 01: scka 10: ctp1 11: seg6 bit 3~2 pc5s1~pc5s0 : pc5 pin function selection 00: pc5/ctck1 01: sdia 10: c0x 11: seg5 bit 1~0 pc4s1~pc4s0 : pc4 pin function selection 00: pc4/stp1i 01: sdoa 10: stp1 11: seg4
rev. 1.10 8? de?e??e? 01? ?01? rev. 1.10 87 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pds0 register bit 7 6 5 4 3 2 1 0 na?e pd3s1 pd3s0 pd?s1 pd?s0 pd1s1 pd1s0 pd0s1 pd0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pd3s1~pd3s0 : pd3 pin function selection 00: pd3 01: sdo 10: c1n 11: seg11 bit 5~4 pd2s1~pd2s0 : pd2 pin function selection 00: pd2/etpib 01: sdi/sda 10: etpb 11: seg10 bit 3~2 pd1s1~pd1s0 : pd1 pin function selection 00: pd1/etck 01: sck/scl 10: c1p 11: seg9 bit 1~0 pd0s1~pd0s0 : pd0 pin function selection 00: pd0/stp0i 01: scs 10: stp0 11: seg8 pds1 register bit 7 6 5 4 3 2 1 0 na?e pd7s1 pd7s0 pd?s1 pd?s0 pd5s1 pd5s0 pd4s1 pd4s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pd7s1~pd7s0 : pd7 pin function selection 00: pd7/int0/stp2i 01: stp2 10: c0x 11: seg15 bit 5~4 pd6s1~pd6s0 : pd6 pin function selection 00/01: pd6/int1/stck2 10: c0n 11: seg14 bit 3~2 pd5s1~pd5s0 : pd5 pin function selection 00: pd5/int2 01: ctp0 10: c0p 11: seg13 bit 1~0 pd4s1~pd4s0 : pd4 pin function selection 00: pd4/int3/ctck0/etpia 01: etpa 10: c1x 11: seg12
rev. 1.10 8? de?e??e? 01? ?01? rev. 1.10 87 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pes0 register bit 7 6 5 4 3 2 1 0 na?e pe3s1 pe3s0 pe?s1 pe?s0 pe1s1 pe1s0 pe0s1 pe0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pe3s1~pe3s0 : pe3 pin function selection 00/01/10: pe3 11: seg19 bit 5~4 pe2s1~pe2s0 : pe2 pin function selection 00/01/10: pe2 11: seg18 bit 3~2 pe1s1~pe1s0 : pe1 pin function selection 00: pe1/stp1i 01: sdia 10: stp1 11: seg17 bit 1~0 pe0s1~pe0s0 : pe0 pin function selection 00/10: pe0/stck1 01: sdoa 11: seg16 pes1 register bit 7 6 5 4 3 2 1 0 na?e pe7s1 pe7s0 pe?s1 pe?s0 pe5s1 pe5s0 pe4s1 pe4s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pe7s1~pe7s0 : pe7 pin function selection 00/01/10: pe7 11: seg23 bit 5~4 pe6s1~pe6s0 : pe6 pin function selection 00/01/10: pe2 11: seg22 bit 3~2 pe5s1~pe5s0 : pe5 pin function selection 00/01/10: pe5 11: seg21 bit 1~0 pe4s1~pe4s0 : pe4 pin function selection 00/01/10: pe4 11: seg20
rev. 1.10 88 de?e??e? 01? ?01? rev. 1.10 89 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom pfs0 register bit 7 6 5 4 3 2 1 0 na?e pf3s1 pf3s0 pf?s1 pf?s0 pf1s1 pf1s0 pf0s1 pf0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pf3s1~pf3s0 : pf3 pin function selection 00/01/10: pf3 11: seg27 bit 5~4 pf2s1~pf2s0 : pf2 pin function selection 00/01/10: pf2 11: seg26 bit 3~2 pf1s1~pf1s0 : pf1 pin function selection 00/01/10: pf1 11: seg25 bit 1~0 pf0s1~pf0s0 : pf0 pin function selection 00/01/10: pf0 11: seg24 pfs1 register bit 7 6 5 4 3 2 1 0 na?e pf7s1 pf7s0 pf?s1 pf?s0 pf5s1 pf5s0 pf4s1 pf4s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pf7s1~pf7s0 : pf7 pin function selection 00/01/10: pf7 11: seg31 bit 5~4 pf6s1~pf6s0 : pf6 pin function selection 00/01/10: pf2 11: seg30 bit 3~2 pf5s1~pf5s0 : pf5 pin function selection 00/01/10: pf5 11: seg29 bit 1~0 pf4s1~pf4s0 : pf4 pin function selection 00/01/10: pf4 11: seg28
rev. 1.10 88 de?e??e? 01? ?01? rev. 1.10 89 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ifs0 register bit 7 6 5 4 3 2 1 0 na?e pintbs int3s int?s int1s int0s r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 pintbs : pint input source pin selection 0: pc1 1: pa4 bit 6~4 unimplemented, read as 0 bit 3 int3s : int3 input source pin selection 0: pb3 1: pd4 bit 2 int2s : int2 input source pin selection 0: pb2 1: pd5 bit 1 int1s : int1 input source pin selection 0: pa7 1: pd6 bit 0 int0s : int0 input source pin selection 0: pa6 1: pd7 ifs1 register bit 7 6 5 4 3 2 1 0 na?e stck0s stp0is etcks etpibs etpias ctck0s r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 stck0s : stck0 input source pin selection 0: pb2 1: pc7 bit 5 stp0is : stp0i input source pin selection 0: pa7 1: pd0 bit 4 etcks : etck input source pin selection 0: pa6 1: pd1 bit 3 etpibs : etpib input source pin selection 0: pa5 1: pd2 bit 2 etpias : etpia input source pin selection 0: pa4 1: pd4 bit 1 ctck0s : ctck0 input source pin selection 0: pa3 1: pd4 bit 0 unimplemented, read as 0
rev. 1.10 90 de?e??e? 01? ?01? rev. 1.10 91 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ifs2 register bit 7 6 5 4 3 2 1 0 na?e stck?s stp?is stck1s stp1is ctck1s r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 stck2s : stck2 input source pin selection 0: pc1 1: pd6 bit 4 stp2is : stp2i input source pin selection 0: pc2 1: pd7 bit 3 stck1s : stck1 input source pin selection 0: pc3 1: pe0 bit 2 stp1is : stp1i input source pin selection 0: pc4 1: pe1 bit 1 ctck1s : ctck1 input source pin selection 0: pb0 1: pc5 bit 0 unimplemented, read as 0 ifs3 register bit 7 6 5 4 3 2 1 0 na?e sdias sdis sckas scks scsas scss r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 sdias : sdia input source pin selection 0: pc5 1: pe1 bit 4 sdis : sdi input source pin selection 0: pa3 1: pd2 bit 3 sckas : scka input source pin selection 0: pb1 1: pc6 bit 2 scks : sck/scl input source pin selection 0: pa4 1: pd1 bit 1 scsas : scsa input source pin selection 0: pb0 1: pc7 bit 0 scss : scs input source pin selection 0: pa5 1: pd0
rev. 1.10 90 de?e??e? 01? ?01? rev. 1.10 91 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ifs4 register bit 7 6 5 4 3 2 1 0 na?e c1ns c1ps c0ns c0ps r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~5 unimplemented, read as 0 bit 4 c1ns : c1n input source pin selection 0: pc1 1: pd3 bit 3 c1ps : c1p input source pin selection 0: pc0 1: pd1 bit 2 unimplemented, read as 0 bit 1 c0ns : c0n input source pin selection 0: pc7 1: pd6 bit 0 c0ps : c0p input source pin selection 0: pc3 1: pd5 i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

??? ? ? ? ?? generic input/output structure
rev. 1.10 9? de?e??e? 01? ?01? rev. 1.10 93 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom

? ?
? ? ? ? - ? ? - ? ? ? ? a/d input/output structure programming considerations within the user program, one of the things frst to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set to high. this means that all i/o pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.10 9? de?e??e? 01? ?01? rev. 1.10 93 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom timer modules C tm one of the most fundamental functions in any microcontroller devices is the ability to control and measure time. to implement time related functions the device includes several timer modules, generally abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as timer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has multiple interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the different tm types are described here with more detailed information provided in the individual compact, standard and periodic tm sections. introduction the device contains six tms and each individual tm can be categorised as a certain type, namely compact type tm, standard type tm and enhanced type tm. although similar in nature, the different tm types vary in their feature complexity. the common features to all of the compact, standard and enhanced tms will be described in this section and the detailed operation regarding each of the tm types will be described in separate sections. the main features and differences between the three types of tms are summarised in the accompanying table. tm function ctm stm etm ti ?e?/counte? input captu?e co?pa?e mat?h output pwm channels 1 1 1 single pulse output 1 1 pwm align ?ent edge edge edge & cent?e pwm adjust ?ent pe?iod & duty duty o? pe?iod duty o? pe?iod duty o? pe?iod tm function summary device ctm stm etm ht?7f?0a 10-?it ctm0 10-?it ctm1 1?-?it stm0 1?-?it stm1 1?-?it stm? 10-?it etm ht?7f70a tm type reference tm operation the different types of tm offer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running count-up counter whose value is then compared with the value of pre-programmed internal comparators. when the free running count-up counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin.
rev. 1.10 94 de?e??e? 01? ?01? rev. 1.10 95 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the xtck2~xtck0 bits in the xtm control registers, where x can stand for c, s or e and n is the serial number. the clock source can be a ratio of the system clock, f sys , or the internal high clock, f h , the f tbc clock source or the external xtck pin. note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the tm clock source. the xtck pin clock source is used to allow an external signal to drive the tm as an external clock source for event counting. tm interrupts the compact or standard type tm has two internal interrupt, one for each of the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. as the enhanced type tm has three internal comparators and comparator a, comparator b or comparator p compare match functions, it consequently has three internal interrupts. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has two or three tm input pins, with the label xtckn and xtpni or etpia/etpib respectively. the tm input pin, xtckn, is essentially a clock source for the tm and is selected using the xtnck2~xtnck0 bits in the xtmnc0 register. this external tm input pin allows an external clock source to drive the internal tm. the tm input pin can be chosen to have either a rising or falling active edge. the stckn and etck pins are also used as the external trigger input pin in single pulse output mode for the stmn and etm respectively. the other tm input pin, stpni or etpia/etpib, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the stnio1~stnio0 or etaio1~etaio0/etbio1~etbio0 bits in the stmnc1 or etmc1/ etmc2 register respectively. the tms each have one or more output pins which is selected using the corresponding pin-shared function selection bits described in the pin-shared function section. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external xtp or etpia/etpib output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other functions, the tm output function must frst be setup using relevant pin-shared function selection register. type ctm stm etm pin control registers input ctck0? ctck1 stck0? stck1? stck? stp0i? stp1i? stp?i etck etpia? etpib ifsi output ctp0? ctp1 stp0? stp1? stp? etpa ? etpb pxsn tm external pins
rev. 1.10 94 de?e??e? 01? ?01? rev. 1.10 95 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom tm input/output pin control register selecting to have a tm input/output or whether to retain its other shared function is implemented using the relevant pin-shared function selection registers, with the corresponding selection bits in each pin-shared function register corresponding to a tm input/output pin. confguring the selection bits correctly will setup the corresponding pin as a tm input/output. the details of the pin-shared function selection are described in the pin-shared function section. ctmn ctckn ctpn ccr output ctmn functional pin diagram (n=0~1) stmn stckn stpn stpni capture input ccr output stmn functional pin diagram (n=0~2) etm etck etpa etpia capture input a ccra output etpib capture input b etpb ccrb output etm functional pin diagram
rev. 1.10 9? de?e??e? 01? ?01? rev. 1.10 97 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom programming considerations the tm counter registers and the capture/compare ccra and ccrb registers, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrb registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way as described above, it is recommended to use the mov instruction to access the ccra and ccrb low byte registers, named xtmal or etmal and etmbl, using the following access procedures. accessing the ccra or ccrb low byte registers without following these access procedures will result in unpredictable values. data bus 8-bit buffer xtmndh etmdh xtmndl or etmdl xtmnah or etmah xtmnal or etmal xtmn/etm counter register (read only) xtmn/etm ccra register (read/write) etm ccrb register (read/write) etmbh etmbl the following steps show the read and write procedures: ? writing data to ccra or ccrb ? step 1. write data to low byte xtmnal, etmal or etmbl C note that here data is only written to the 8-bit buffer. ? step 2. write data to high byte xtmnah, etmah or etmbh C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ccrb ? step 1. read data from the high byte xtmndh, etmdh, xtmnah, etmah or etmbh C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte xtmndl, etmdl, xtmnal, etmal or etmbl C this step reads data from the 8-bit buffer.
rev. 1.10 9? de?e??e? 01? ?01? rev. 1.10 97 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom compact type tm C ctm although the simplest form of the tm types, the compact tm type still contains three operating modes, which are compare match output, timer/event counter and pwm output modes. each compact tm can also be controlled with an external input pin and can drive one external output pin. device tm type tm input pin tm output pin ht?7f?0a/ht?7f70a 10-?it ctm (ctm0? ctm1) ctck0? ctck1 ctp0? ctp1 f sys f sys /4 f h /64 f h /16 f tbc reserved ctckn 000 001 010 011 100 101 110 111 ctnck2~ctnck0 10-bit count-up counter 3-bit comparator p ccrp b7~b9 b0~b9 10-bit comparator a ctnon ctnpau comparator a match comparator p match counter clear 0 1 output control polarity control pin control ctpn ctnoc ctnm1, ctnm0 ctnio1, ctnio0 ctmnaf interrupt ctmnpf interrupt ctnpol pxsn ccra ctncclr compact type tm block diagram (n = 0 or 1) compact tm operation the compact tm core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three-bit wide whose value is compared with the highest three bits in the counter while the ccra is ten-bit wide and therefore compares with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the ctnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. compact type tm register description overall operation of the compact tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ctmnc0 ctnpau ctnck? ctnck1 ctnck0 ctnon ctnrp? ctnrp1 ctnrp0 ctmnc1 ctnm1 ctnm0 ctnio1 ctnio0 ctnoc ctnpol ctndpx ctncclr ctmndl d7 d? d5 d4 d3 d? d1 d0 ctmndh d9 d8 ctmnal d7 d? d5 d4 d3 d? d1 d0 ctmnah d9 d8 10-bit compact tm registers list (n = 0 or 1)
rev. 1.10 98 de?e??e? 01? ?01? rev. 1.10 99 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ctmndl register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 ctmn counter low byte register bit 7 ~ bit 0 ctmn 10-bit counter bit 7 ~ bit 0 ctmndh register bit 7 6 5 4 3 2 1 0 na?e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 ctmn counter high byte register bit 1 ~ bit 0 ctmn 10-bit counter bit 9 ~ bit 8 ctmnal register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 ctmn ccra low byte register bit 7 ~ bit 0 ctmn 10-bit ccra bit 7 ~ bit 0 ctmnah register bit 7 6 5 4 3 2 1 0 na?e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 ctmn ccra high byte register bit 1 ~ bit 0 ctmn 10-bit ccra bit 9 ~ bit 8 ctmnc0 register bit 7 6 5 4 3 2 1 0 na?e ctnpau ctnck? ctnck1 ctnck0 ctnon ctnrp? ctnrp1 ctnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ctnpau : ctmn counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the ctmn will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again.
rev. 1.10 98 de?e??e? 01? ?01? rev. 1.10 99 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom bit 6~4 ctnck2~ctnck0 : select ctmn counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: reserved 110: ctckn rising edge clock 111: ctckn falling edge clock these three bits are used to select the clock source for the ctmn. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 ctnon : ctmn counter on/off control 0: off 1: on this bit controls the overall on/off function of the ctmn. setting the bit high enables the counter to run while clearing the bit disables the ctmn. clearing this bit to zero will stop the counter from counting and turn off the ctmn which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the ctmn is in the compare match output mode then the ctmn output pin will be reset to its initial condition, as specifed by the ctnoc bit, when the ctnon bit changes from low to high. bit 2~0 ctnrp2~ctnrp0 : ctmn ccrp 3-bit register, compared with the ctmn counter bit9~bit7 000: 1024 ctmn clocks 001: 128 ctmn clocks 010: 256 ctmn clocks 011: 384 ctmn clocks 100: 512 ctmn clocks 101: 640 ctmn clocks 110: 768 ctmn clocks 111: 896 ctmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counters highest three bits. the result of this comparison can be selected to clear the internal counter if the ctncclr bit is set to zero. setting the ctncclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
rev. 1.10 100 de?e??e? 01? ?01? rev. 1.10 101 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ctmnc1 register bit 7 6 5 4 3 2 1 0 na?e ctnm1 ctnm0 ctnio1 ctnio0 ctnoc ctnpol ctndpx ctncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 ctnm1~ctnm0 : select ctmn operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: timer/counter mode these bits setup the required operating mode for the ctmn. to ensure reliable operation the ctmn should be switched off before any changes are made to the ctnm1 and ctnm0 bits. in the timer/counter mode, the ctmn output pin control will be disabled. bit 5~4 ctnio1~ctnio0 : select ctmn external pin (ctpn) function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the ctmn output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the ctmn is running. in the compare match output mode, the ctnio1 and ctnio0 bits determine how the ctmn output pin changes state when a compare match occurs from the comparator a. the ctmn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the ctmn output pin should be setup using the ctnoc bit in the ctmnc1 register. note that the output level requested by the ctnio1 and ctnio0 bits must be different from the initial value setup using the ctnoc bit otherwise no change will occur on the ctmn output pin when a compare match occurs. after the ctmn output pin changes state, it can be reset to its initial level by changing the level of the ctnon bit from low to high. in the pwm mode, the ctnio1 and ctnio0 bits determine how the ctmn output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the ctnio1 and ctnio0 bits only after the ctmn has been switched off. unpredictable pwm outputs will occur if the ctnio1 and ctnio0 bits are changed when the ctmn is running.
rev. 1.10 100 de?e??e? 01? ?01? rev. 1.10 101 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom bit 3 ctnoc : ctpn output control compare match output mode 0: initial low 1: initial high pwm output mode 0: active low 1: active high this is the output control bit for the ctmn output pin. its operation depends upon whether ctmn is being used in the compare match output mode or in the pwm mode. it has no effect if the ctmn is in the timer/counter mode. in the compare match output mode it determines the logic level of the ctmn output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 ctnpol : ctpn output polarity control 0: non-inverted 1: inverted this bit controls the polarity of the ctpn output pin. when the bit is set high the ctmn output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 ctndpx : ctmn pwm duty/period control 0: ccrp C period; ccra C duty 1: ccrp C duty; ccra C period this bit determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 ctncclr : ctmn counter clear condition selection 0: ctmn comparator p match 1: ctmn comparator a match this bit is used to select the method which clears the counter. remember that the compact tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the ctncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the ctncclr bit is not used in the pwm mode.
rev. 1.10 10? de?e??e? 01? ?01? rev. 1.10 103 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom compact type tm operation modes the compact type tm can operate in one of three operating modes, compare match output mode, pwm mode or timer/counter mode. the operating mode is selected using the ctnm1 and ctnm0 bits in the ctmnc1 register. compare match output mode to select this mode, bits ctnm1 and ctnm0 in the ctmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the ctncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both ctmnaf and ctmnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the ctncclr bit in the ctmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the ctmnaf interrupt request fag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when ctncclr is high no ctmnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the ctmnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the ctmn output pin will change state. the ctmn output pin condition however only changes state when a ctmnaf interrupt request fag is generated after a compare match occurs from comparator a. the ctmnpf interrupt request fag, generated from a compare match occurs from comparator p, will have no effect on the ctmn output pin. the way in which the ctmn output pin changes state are determined by the condition of the ctnio1 and ctnio0 bits in the ctmnc1 register. the ctmn output pin can be selected using the ctnio1 and ctnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the ctmn output pin, which is setup after the ctnon bit changes from low to high, is setup using the ctnoc bit. note that if the ctnio1 and ctnio0 bits are zero then no pin change will take place.
rev. 1.10 10? de?e??e? 01? ?01? rev. 1.10 103 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value 0x3ff ccrp ccra ctnon ctnpau ctnpol ccrp int . flag ctmnpf ccra int . flag ctmnaf ctmn o/p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t ctncclr = 0; ctnm [1:0] = 00 output pin set to initial level low if ctnoc=0 output toggle with ctmnaf flag note ctnio [1:0] = 10 a?tive high output sele?t he?e ctnio [1:0] = 11 toggle output sele?t output not affe?ted ?y ctmnaf flag. re?ains high until ?eset ?y ctnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ctnpol is high compare match output mode C ctncclr = 0 note: 1. with ctncclr = 0, a comparator p match will clear the counter 2. the ctmn output pin controlled only by ctmnaf fag 3. the output pin is reset to its initial state by ctnon bit rising edge 4. n = 0 or 1
rev. 1.10 104 de?e??e? 01? ?01? rev. 1.10 105 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value 0x3ff ccrp ccra ctnon ctnpau ctnpol ctmn o / p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t ctncclr = 1; ctnm [1:0] = 00 output pin set to initial level low if ctnoc=0 output toggle with ctmnaf flag note ctnio [1:0] = 10 a?tive high output sele?t he?e ctnio [1:0] = 11 toggle output sele?t output not affe?ted ?y ctmnaf flag. re?ains high until ?eset ?y ctnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ctnpol is high ctmnpf not gene?ated no ctmnaf flag gene?ated on ccra ove?flow output does not ?hange ccra int . flag ctmnaf ccrp int . flag ctmnpf compare match output mode C ctncclr = 1 note: 1. with ctncclr = 1, a comparator a match will clear the counter 2. the ctmn output pin is controlled only by ctmnaf fag 3. the ctmn output pin is reset to initial state by ctnon rising edge 4. the ctmnpf fags is not generated when ctncclr = 1 5. n = 0 or 1
rev. 1.10 104 de?e??e? 01? ?01? rev. 1.10 105 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom timer/counter mode to select this mode, bits ctnm1 and ctnm0 in the ctmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the timer/counter mode the ctmn output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the ctmn output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits ctnm1 and ctnm0 in the ctmnc1 register should be set to 10 respectively. the pwm function within the ctmn is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the ctmn output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm mode, the ctncclr bit has no effect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the ctndpx bit in the ctmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the ctnoc bit in the ctmnc1 register is used to select the required polarity of the pwm waveform while the two ctnio1 and ctnio0 bits are used to enable the pwm output or to force the tm output pin to a fixed high or low level. the ctnpol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit ctmn, pwm mode, edge-aligned mode, ctndpx=0 ccrp 001b 011b 011b 100b 101b 110b 111b 000b pe?iod 1?8 ?5? 384 51? ?40 7?8 89? 10?4 duty ccra if f sys = 16mhz, ctmn clock source is f sys /4, ccrp = 2 and ccra = 128, the ctmn pwm output frequency = (f sys /4) / (2256) = f sys /2048 = 7.8125 khz, duty = 128/(2256)= 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 10-bit ctmn, pwm mode, edge-aligned mode, ctndpx=1 ccrp 001b 011b 011b 100b 101b 110b 111b 000b pe?iod ccra duty 1?8 ?5? 384 51? ?40 7?8 89? 10?4 the pwm output period is determined by the ccra register value together with the ctmn clock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.10 10? de?e??e? 01? ?01? rev. 1.10 107 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value ccrp ccra ctnon ctnpau ctnpol ctmn o / p pin ( ctnoc = 1 ) ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? stop if ctnon ?it low counte? reset when ctnon ?etu?ns high ctndpx = 0; ctnm [1:0] = 10 pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ctnpol = 1 pwm pe?iod set ?y ccrp ctmn o / p pin ( ctnoc = 0 ) ccra int . flag ctmnaf ccrp int . flag ctmnpf pwm output mode C ctndxp = 0 note: 1. here ctndpx = 0 C counter cleared by ccrp 2. a counter clear sets pwm period 3. the internal pwm function continues even when ctnio1, ctnio0 = 00 or 01 4. the ctncclr bit has no infuence on pwm operation 5. n = 0 or 1
rev. 1.10 10? de?e??e? 01? ?01? rev. 1.10 107 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value ccrp ccra ctnon ctnpau ctnpol ccrp int . flag ctmnpf ccra int . flag ctmnaf ctmn o / p pin ( ctnoc = 1 ) ti?e counte? ?lea?ed ?y ccra pause resu?e counte? stop if ctnon ?it low counte? reset when ctnon ?etu?ns high ctndpx = 1; ctnm [1:0] = 10 pwm duty cy?le set ?y ccrp pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when ctnpol = 1 pwm pe?iod set ?y ccra ctmn o / p pin ( ctnoc = 0 ) pwm output mode C ctndxp = 1 note: 1. here ctndpx = 1 C counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when ctnio [1:0] = 00 or 01 4. the ctncclr bit has no infuence on pwm operation 5. n = 0 or 1
rev. 1.10 108 de?e??e? 01? ?01? rev. 1.10 109 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom standard type tm C stm the standard type tm contains fve operating modes, which are compare match output, timer/ event counter, capture input, single pulse output and pwm output modes. each standard tm can also be controlled with two external input pins and can drive one external output pin. device tm type tm input pin tm output pin ht?7f?0a ht?7f70a 1?-?it stm (stm0? stm1? stm?) stck0? stck1? stck?; stp0i? stp1i? stp?i stp0? stp1? stp? f sys f sys /4 f h /64 f h /16 f tbc reserved stckn 000 001 010 011 100 101 110 111 stnck2~stnck0 16-bit count-up counter 8-bit comparator p ccrp b8~b15 b0~b15 16-bit comparator a stnon stnpau comparator a match comparator p match counter clear 0 1 output control polarity control pin control stpn stnoc stnm1, stnm0 stnio1, stnio0 stmnaf interrupt stmnpf interrupt stnpol pxsn ccra stncclr edge detector stpni stnio1, stnio0 standard type tm block diagram (n = 0, 1 or 2) standard tm operation the size of standard tm is 16-bit wide and its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is eight-bit wide whose value is compared with the highest eight bits in the counter while the ccra is sixteen-bit wide and therefore compares with all counter bits. the only way of changing the value of the 16-bit counter using the application program, is to clear the counter by changing the stnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a stmn interrupt signal will also usually be generated. the standard type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.10 108 de?e??e? 01? ?01? rev. 1.10 109 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit ccra value. the stmnrp register is used to store the 8-bit ccrp bits. the remaining two registers are control registers which setup the different operating and control modes. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 stmnc0 stnpau stnck? stnck1 stnck0 stnon stmnc1 stnm1 stnm0 stnio1 stnio0 stnoc stnpol stndpx stncclr stmndl d7 d? d5 d4 d3 d? d1 d0 stmndh d15 d14 d13 d1? d11 d10 d9 d8 stmnal d7 d? d5 d4 d3 d? d1 d0 stmnah d15 d14 d13 d1? d11 d10 d9 d8 stmnrp stnrp7 stnrp? stnrp5 stnrp4 stnrp3 stnrp? stnrp1 stnrp0 16-bit standard tm registers list (n = 0, 1 or 2) stmndl register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 stmn counter low byte register bit 7 ~ bit 0 stmn 16-bit counter bit 7 ~ bit 0 stmndh register bit 7 6 5 4 3 2 1 0 na?e d15 d14 d13 d1? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 stmn counter high byte register bit 7 ~ bit 0 stmn 16-bit counter bit 15 ~ bit 8 stmnal register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 stmn ccra low byte register bit 7 ~ bit 0 stmn 16-bit ccra bit 7 ~ bit 0 stmnah register bit 7 6 5 4 3 2 1 0 na?e d15 d14 d13 d1? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 stmn ccra high byte register bit 7 ~ bit 0 stmn 16-bit ccra bit 15 ~ bit 8
rev. 1.10 110 de?e??e? 01? ?01? rev. 1.10 111 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom stmnc0 register bit 7 6 5 4 3 2 1 0 na?e stnpau stnck? stnck1 stnck0 stnon r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 stnpau : stmn counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the stmn will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 stnck2~stnck0 : select stmn counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: reserved 110: stckn rising edge clock 111: stckn falling edge clock these three bits are used to select the clock source for the stmn. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 stnon : stmn counter on/off control 0: off 1: on this bit controls the overall on/off function of the stmn. setting the bit high enables the counter to run while clearing the bit disables the stmn. clearing this bit to zero will stop the counter from counting and turn off the stmn which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the stmn is in the compare match output mode then the stmn output pin will be reset to its initial condition, as specifed by the stnoc bit, when the stnon bit changes from low to high. bit 2~0 unimplemented, read as 0
rev. 1.10 110 de?e??e? 01? ?01? rev. 1.10 111 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom stmnc1 register bit 7 6 5 4 3 2 1 0 na?e stnm1 stnm0 stnio1 stnio0 stnoc stnpol stndpx ctncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 stnm1~stnm0 : select stmn operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the stmn. to ensure reliable operation the stmn should be switched off before any changes are made to the stnm1 and stnm0 bits. in the timer/counter mode, the stmn output pin control will be disabled. bit 5~4 stnio1~stnio0 : select stmn external pin (stpn or stpni) function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of stpni 01: input capture at falling edge of stpni 10: input capture at rising/falling edge of stpni 11: input capture disabled timer/counter mode unused these two bits are used to determine how the stmn output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the stmn is running. in the compare match output mode, the stnio1 and stnio0 bits determine how the stmn output pin changes state when a compare match occurs from the comparator a. the stmn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the stmn output pin should be setup using the stnoc bit in the stmnc1 register. note that the output level requested by the stnio1 and stnio0 bits must be different from the initial value setup using the stnoc bit otherwise no change will occur on the stmn output pin when a compare match occurs. after the stmn output pin changes state, it can be reset to its initial level by changing the level of the stnon bit from low to high. in the pwm mode, the stnio1 and stnio0 bits determine how the stmn output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the stnio1 and stnio0 bits only after the stmn has been switched off. unpredictable pwm outputs will occur if the stnio1 and stnio0 bits are changed when the stmn is running.
rev. 1.10 11 ? de?e??e? 01? ?01? rev. 1.10 113 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom bit 3 stnoc : stpn output control compare match output mode 0: initial low 1: initial high pwm output mode/single pulse output mode 0: active low 1: active high this is the output control bit for the stmn output pin. its operation depends upon whether stmn is being used in the compare match output mode or in the pwm mode/single pulse output mode. it has no effect if the stmn is in the timer/counter mode. in the compare match output mode it determines the logic level of he stmn output pin before a compare match occurs. in the pwm mode/single pulse output mode it determines if the pwm signal is active high or active low. bit 2 stnpol : stpn output polarity control 0: non-inverted 1: inverted this bit controls the polarity of the stpn output pin. when the bit is set high the stmn output pin will be inverted and not inverted when the bit is zero. it has no effect if the stmn is in the timer/counter mode. bit 1 stndpx : stmn pwm duty/period control 0: ccrp C period; ccra C duty 1: ccrp C duty; ccra C period this bit determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 stncclr : stmn counter clear condition selection 0: comparator p match 1: comparator a match this bit is used to select the method which clears the counter. remember that the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the stncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the stncclr bit is not used in the pwm output, single pulse output or capture input mode. stmnrp register bit 7 6 5 4 3 2 1 0 na?e stnrp7 stnrp? stnrp5 stnrp4 stnrp3 stnrp? stnrp1 stnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 stnrp7~stnrp0 : stmn ccrp 8-bit register, compared with the stmn counter bit15~bit8 comparator p match period = 0: 65536 stmn clocks 1~255: (1~255) 256 stmn clocks these eight bits are used to setup the value on the internal ccrp 8-bit register, which are then compared with the internal counters highest eight bits. the result of this comparison can be selected to clear the internal counter if the stncclr bit is set to zero. setting the stncclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value.
rev. 1.10 11 ? de?e??e? 01? ?01? rev. 1.10 113 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom standard type tm operation modes the standard type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the stnm1 and stnm0 bits in the stmnc1 register. compare match output mode to select this mode, bits stnm1 and stnm0 in the stmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the stncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both stmnaf and stmnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the stncclr bit in the stmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the stmnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when stncclr is high no stmnpf interrupt request fag will be generated. in the compare match output mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the stmn output pin, will change state. the stmn output pin condition however only changes state when a stmnaf interrupt request fag is generated after a compare match occurs from comparator a. the stmnpf interrupt request fag, generated from a compare match occurs from comparator p, will have no effect on the stmn output pin. the way in which the stmn output pin changes state are determined by the condition of the stnio1 and stnio0 bits in the stmnc1 register. the stmn output pin can be selected using the stnio1 and stnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the stmn output pin, which is setup after the stnon bit changes from low to high, is setup using the stnoc bit. note that if the stnio1 and stnio0 bits are zero then no pin change will take place.
rev. 1.10 114 de?e??e? 01? ?01? rev. 1.10 115 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value 0xffff ccrp ccra stnon stnpau stnpol ccrp int . flag stmnpf ccra int . flag stmnaf stmn o / p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t stncclr = 0; stnm [1:0] = 00 output pin set to initial level low if stnoc=0 output toggle with stmnaf flag note stnio [1:0] = 10 a?tive high output sele?t he?e stnio [1:0] = 11 toggle output sele?t output not affe?ted ?y stmnaf flag. re?ains high until ?eset ?y stnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when stnpol is high compare match output mode C stncclr = 0 note: 1. with stncclr=0 a comparator p match will clear the counter 2. the stmn output pin is controlled only by the stmnaf fag 3. the output pin is reset to itsinitial state by a stnon bit rising edge 4. n = 0, 1 or 2
rev. 1.10 114 de?e??e? 01? ?01? rev. 1.10 115 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value 0xffff ccrp ccra stnon stnpau stnpol ccrp int . flag stmnpf ccra int . flag stmnaf stmn o / p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t stncclr = 1; stnm [1:0] = 00 output pin set to initial level low if stnoc=0 output toggle with stmnaf flag note stnio [1:0] = 10 a?tive high output sele?t he?e stnio [1:0] = 11 toggle output sele?t output not affe?ted ?y stmnaf flag. re?ains high until ?eset ?y stnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when stnpol is high stmnpf not gene?ated no stmnaf flag gene?ated on ccra ove?flow output does not ?hange compare match output mode C stncclr = 1 note:1. with stncclr=1 a comparator a match will clear the counter 2. the stmn output pin is controlled only by the stmnaf fag 3. the output pin is reset to its initial state by a stnon bit rising edge 4. a stmnpf fag is not generated when stncclr=1 5. n = 0, 1 or 2
rev. 1.10 11 ? de?e??e? 01? ?01? rev. 1.10 117 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom timer/counter mode to select this mode, bits stnm1 and stnm0 in the stmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the timer/counter mode the stmn output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the stmn output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits stnm1 and stnm0 in the stmnc1 register should be set to 10 respectively and also the stnio1 and stnio0 bits should be set to 10 respectively. the pwm function within the stmn is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the stmn output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm mode, the stncclr bit has no effect as the pwm period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the stndpx bit in the stmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the stnoc bit in the stmnc1 register is used to select the required polarity of the pwm waveform while the two stnio1 and stnio0 bits are used to enable the pwm output or to force the stmn output pin to a fxed high or low level. the stnpol bit is used to reverse the polarity of the pwm output waveform. ? 16-bit stmn, pwm mode, edge-aligned mode, stndpx=0 ccrp 1~255 0 pe?iod ccrp?5? ?553? duty ccra if f sys = 16mhz, stmn clock source is f sys /4, ccrp = 2 and ccra = 128, the stmn pwm output frequency = (f sys /4) / (2256) = f sys /2048 = 7.8125 khz, duty = 128/(2256)= 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 16-bit stmn, pwm mode, edge-aligned mode, stndpx=1 ccrp 1~255 0 pe?iod ccra ccra duty ccrp?5? ?553? the pwm output period is determined by the ccra register value together with the stmn clock while the pwm duty cycle is defned by the ccrp register value except when the ccrp value is equal to 0.
rev. 1.10 11 ? de?e??e? 01? ?01? rev. 1.10 117 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value ccrp ccra stnon stnpau stnpol ccrp int . flag stmnpf ccra int . flag stmnaf stmn o / p pin ( stnoc = 1 ) ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? stop if stnon ?it low counte? reset when stnon ?etu?ns high stndpx = 0; stnm [1:0] = 10 pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when stnpol = 1 pwm pe?iod set ?y ccrp stmn o / p pin ( stnoc = 0 ) pwm output mode C stndxp = 0 note: 1. here stndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when stnio [1:0] = 00 or 01 4. the stncclr bit has no infuence on pwm operation 5. n = 0, 1 or 2
rev. 1.10 118 de?e??e? 01? ?01? rev. 1.10 119 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value ccrp ccra stnon stnpau stnpol ccrp int . flag stmnpf ccra int . flag stmnaf stmn o / p pin ( stnoc = 1 ) ti?e counte? ?lea?ed ?y ccra pause resu?e counte? stop if stnon ?it low counte? reset when stnon ?etu?ns high stndpx = 1; stnm [1:0] = 10 pwm duty cy?le set ?y ccrp pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when stnpol = 1 pwm pe?iod set ?y ccra stmn o / p pin ( stnoc = 0 ) pwm output mode C stndxp = 1 note: 1. here stndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when stnio [1:0] = 00 or 01 4. the stncclr bit has no infuence on pwm operation 5. n = 0, 1 or 2
rev. 1.10 118 de?e??e? 01? ?01? rev. 1.10 119 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom single pulse output mode to select this mode, bits stnm1 and stnm0 in the stmnc1 register should be set to 10 respectively and also the stnio1 and stnio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the stmn output pin. the trigger for the pulse output leading edge is a low to high transition of the stnon bit, which can be implemented using the application program. however in the single pulse mode, the stnon bit can also be made to automatically change from low to high using the external stckn pin, which will in turn initiate the single pulse output. when the stnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the stnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the stnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the stnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a stmn interrupt. the counter can only be reset back to zero when the stnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the stncclr and stndpx bits are not used in this mode. stnon ?it 0 1 s/w co??and setstnon o? stckn pin t?ansition stnon ?it 1 0 ccra t?ailing edge s/w co??and clrstnon o? ccra co?pa?e mat?h stpn output pin pulse width = ccra value ccra leading edge single pulse generation
rev. 1.10 1?0 de?e??e? 01? ?01? rev. 1.10 1?1 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value ccrp ccra stnon stnpau stnpol ccrp int . flag stmnpf ccra int . flag stmnaf stmn o / p pin ( stnoc = 1 ) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when stnon ?etu?ns high stnm [1:0] = 10 ; stnio [1:0] = 11 pulse width set ?y ccra output inve?ts when stnpol = 1 no ccrp inte??upts gene?ated stmn o / p pin ( stnoc = 0 ) stckn pin softwa?e t?igge? clea?ed ?y ccra ?at?h stckn pin t?igge? auto. set ?y stckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse output mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the stckn pin or by setting the stnon bit high 4. a stckn pin active edge will automatically set the stnon bit high. 5. in the single pulse mode, stnio [1:0] must be set to 11 and can not be changed. 6. n = 0, 1 or 2
rev. 1.10 1?0 de?e??e? 01? ?01? rev. 1.10 1?1 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom capture input mode to select this mode bits stnm1 and stnm0 in the stmnc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the stpni pin, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the stnio1 and stnio0 bits in the stmnc1 register. the counter is started when the stnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the stpni pin the present value in the counter will be latched into the ccra registers and a stmn interrupt generated. irrespective of what events occur on the stpni pin the counter will continue to free run until the stnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a stmn interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the stnio1 and stnio0 bits can select the active trigger edge on the stpni pin to be a rising edge, falling edge or both edge types. if the stnio1 and stnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the stpni pin, however it must be noted that the counter will continue to run. the stncclr and stndpx bits are not used in this mode.
rev. 1.10 1?? de?e??e? 01? ?01? rev. 1.10 1?3 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value yy ccrp stnon stnpau ccrp int . flag stmnpf ccra int . flag stmnaf ccra value ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? reset stnm [1:0] = 01 stmn captu ? e pin stpni xx counte? stop stnio [1:0] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e capture input mode note: 1. stnm [1:0] = 01 and active edge set by the stnio [1:0] bits 2. a stmn capture input pin active edge transfers the counter value to ccra 3. stncclr bit not used 4. no output function C stnoc and stnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. 6. n = 0, 1 or 2
rev. 1.10 1?? de?e??e? 01? ?01? rev. 1.10 1?3 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom enhanced type tm C etm the enhanced type tm contains fve operating modes, which are compare match output, timer/ event counter, capture input, single pulse output and pwm output modes. the enhanced tm can also be controlled with three external input pins and can drive two external output pins. device tm type tm input pin tm output pin ht?7f?0a/ht?7f70a 10-?it etm (etm) etck; etpia? etpib etpa ? etpb f sys f sys /4 f h /64 f h /16 f tbc reserved etck 000 001 010 011 100 101 110 111 etck2~etck0 10-bit count-up counter 3-bit comparator p ccrp b7~b9 b0~b9 10-bit comparator a eton etpau comparator a match comparator p match counter clear 0 1 output control polarity control pin control etpa etaoc etam1, etam0 etaio1, etaio0 etmaf interrupt etmpf interrupt etapol pxsn ccra etcclr edge detector etpia etaio1, etaio0 10-bit comparator b ccrb edge detector etpib etbio1, etbio0 comparator b match etmbf interrupt output control polarity control pin control etpb etboc etbm1, etbm0 etbio1, etbio0 etbpol pxsn enhanced type tm block diagram enhanced tm operation at its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. there are three internal comparators with the names, comparator a, comparator b and comparator p. these comparators will compare the value in the counter with the ccra, ccrb and ccrp registers. the ccrp comparator is 3-bit wide whose value is compared with the highest 3 bits in the counter while ccra and ccrb are 10-bit wide and therefore compared with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the eton bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a etm interrupt signal will also usually be generated. the enhanced type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control output pins. all operating setup conditions are selected using relevant internal registers.
rev. 1.10 1?4 de?e??e? 01? ?01? rev. 1.10 1?5 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom enhance type tm register description overall operation of the enhanced tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrb value. the remaining three two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. register name bit 7 6 5 4 3 2 1 0 etmc0 etpau etck? etck1 etck0 eton etrp? etrp1 etrp0 etmc1 etam1 etam0 etaio1 etaio0 etaoc etapol etcdn etcclr etmc? etbm1 etbm0 etbio1 etbio0 etboc etbpol etpwm1 etpwm0 etmdl d7 d? d5 d4 d3 d? d1 d0 etmdh d9 d8 etmal d7 d? d5 d4 d3 d? d1 d0 etmah d9 d8 etmbl d7 d? d5 d4 d3 d? d1 d0 etmbh d9 d8 10-bit enhanced tm registers list etmdl register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 etm counter low byte register bit 7 ~ bit 0 etm 10-bit counter bit 7 ~ bit 0 etmdh register bit 7 6 5 4 3 2 1 0 na?e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 etm counter high byte register bit 1 ~ bit 0 etm 10-bit counter bit 9 ~ bit 8 etmal register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 etm ccra low byte register bit 7 ~ bit 0 etm 10-bit ccra bit 7 ~ bit 0
rev. 1.10 1?4 de?e??e? 01? ?01? rev. 1.10 1?5 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom etmah register bit 7 6 5 4 3 2 1 0 na?e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 etm ccra high byte register bit 1 ~ bit 0 etm 10-bit ccra bit 9 ~ bit 8 etmbl register bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 etm ccrb low byte register bit 7 ~ bit 0 etm 10-bit ccrb bit 7 ~ bit 0 etmbh register bit 7 6 5 4 3 2 1 0 na?e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 etm ccrb high byte register bit 1 ~ bit 0 etm 10-bit ccrb bit 9 ~ bit 8 etmc0 register bit 7 6 5 4 3 2 1 0 na?e etpau etck? etck1 etck0 eton etrp? etrp1 etrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 etpau : etm counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the etm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 etck2~etck0 : select etm counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: reserved 110: etck rising edge clock 111: etck falling edge clock
rev. 1.10 1?? de?e??e? 01? ?01? rev. 1.10 1?7 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom these three bits are used to select the clock source for the etm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 eton : etm counter on/off control 0: off 1: on this bit controls the overall on/off function of the etm. setting the bit high enables the counter to run while clearing the bit disables the etm. clearing this bit to zero will stop the counter from counting and turn off the etm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the etm is in the compare match output mode then the etm output pin will be reset to its initial condition, as specified by the etoc bit, when the eton bit changes from low to high. bit 2~0 etrp2~etrp0 : etm ccrp 3-bit register, compared with the etm counter bit 9~bit 7 000: 1024 etm clocks 001: 128 etm clocks 010: 256 etm clocks 011: 384 etm clocks 100: 512 etm clocks 101: 640 etm clocks 110: 768 etm clocks 111: 896 etm clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counters highest three bits. the result of this comparison can be selected to clear the internal counter if the etcclr bit is set to zero. setting the etcclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
rev. 1.10 1?? de?e??e? 01? ?01? rev. 1.10 1?7 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom etmc1 register bit 7 6 5 4 3 2 1 0 na?e etam1 etam0 etaio1 etaio0 etaoc etapol etcdn etcclr r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 etam1~etam0 : select etm ccra operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the etm ccra. to ensure reliable operation the etm should be switched off before any changes are made to the etam1 and etam0 bits. in the timer/counter mode, the etm output pin control will be disabled. bit 5~4 etaio1~etaio0 : select etm external pin etpa or etpia function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of etpia 01: input capture at falling edge of etpia 10: input capture at rising/falling edge of etpia 11: input capture disabled timer/counter mode unused these two bits are used to determine how the etm etpa output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the etm is running. in the compare match output mode, the etaio1 and etaio0 bits determine how the etm etpa output pin changes state when a compare match occurs from the comparator a. the etm etpa output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the etm etpa output pin should be setup using the etaoc bit in the etmc1 register. note that the output level requested by the etaio1 and etaio0 bits must be different from the initial value setup using the etaoc bit otherwise no change will occur on the etm etpa output pin when a compare match occurs. after the etm etpa output pin changes state, it can be reset to its initial level by changing the level of the eton bit from low to high. in the pwm mode, the etaio1 and etaio0 bits determine how the etm etpa output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to only change the values of the etaio1 and etaio0 bits only after the etm has been switched off. unpredictable pwm outputs will occur if the etaio1 and etaio0 bits are changed when the etm is running.
rev. 1.10 1?8 de?e??e? 01? ?01? rev. 1.10 1?9 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom bit 3 etaoc : etpa output control compare match output mode 0: initial low 1: initial high pwm output mode/single pulse output mode 0: active low 1: active high this is the output control bit for the etm etpa output pin. its operation depends upon whether etm is being used in the compare match output mode or in the pwm output mode/single pulse output mode. it has no effect if the etm is in the timer/ counter mode. in the compare match output mode it determines the logic level of the etm etpa output pin before a compare match occurs. in the pwm output mode/ single pulse output mode it determines if the pwm signal is active high or active low. bit 2 etapol : etpa output polarity control 0: non-inverted 1: inverted this bit controls the polarity of the etpa output pin. when the bit is set high the etm etpa output pin will be inverted and not inverted when the bit is zero. it has no effect if the etm is in the timer/counter mode. bit 1 etcdn : etm counter count up or down fag 0: count up 1: count down bit 0 etcclr : etm counter clear condition selection 0: etm comparator p match 1: etm comparator a match this bit is used to select the method which clears the counter. remember that the enhanced tm contains three comparators, comparator a, comparator b and comparator p, but only comparator a or comparator p can be selected to clear the internal counter. with the etcclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the etcclr bit is not used in the pwm output, single pulse output or capture input mode.
rev. 1.10 1?8 de?e??e? 01? ?01? rev. 1.10 1?9 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom etmc2 register bit 7 6 5 4 3 2 1 0 na?e etbm1 etbm0 etbio1 etbio0 etboc etbpol etpwm1 etpwm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 etbm1~etbm0 : select etm ccrb operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the etm ccrb. to ensure reliable operation the etm should be switched off before any changes are made to the etbm1 and etbm0 bits. in the timer/counter mode, the etm output pin control will be disabled. bit 5~4 etbio1~etbio0 : select etm external pin etpb or etpib function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of etpib 01: input capture at falling edge of etpib 10: input capture at rising/falling edge of etpib 11: input capture disabled timer/counter mode unused these two bits are used to determine how the etm etpb output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the etm is running. in the compare match output mode, the etbio1 and etbio0 bits determine how the etm etpb output pin changes state when a compare match occurs from the comparator a. the etm etpb output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the etm etpb output pin should be setup using the etboc bit in the etmc2 register. note that the output level requested by the etbio1 and etbio0 bits must be different from the initial value setup using the etboc bit otherwise no change will occur on the etm etpb output pin when a compare match occurs. after the etm etpb output pin changes state, it can be reset to its initial level by changing the level of the eton bit from low to high. in the pwm mode, the etbio1 and etbio0 bits determine how the etm etpb output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to only change the values of the etbio1 and etbio0 bits only after the etm has been switched off. unpredictable pwm outputs will occur if the etbio1 and etbio0 bits are changed when the etm is running.
rev. 1.10 130 de?e??e? 01? ?01? rev. 1.10 131 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom bit 3 etboc : etpb output control compare match output mode 0: initial low 1: initial high pwm output mode/single pulse output mode 0: active low 1: active high this is the output control bit for the etm etpb output pin. its operation depends upon whether etm is being used in the compare match output mode or in the pwm output mode/single pulse output mode. it has no effect if the etm is in the timer/ counter mode. in the compare match output mode it determines the logic level of the etm etpb output pin before a compare match occurs. in the pwm output mode/ single pulse output mode it determines if the pwm signal is active high or active low. bit 2 etbpol : etpb output polarity control 0: non-inverted 1: inverted this bit controls the polarity of the etpb output pin. when the bit is set high the etm etpb output pin will be inverted and not inverted when the bit is zero. it has no effect if the etm is in the timer/counter mode. bit 1~0 etpwm1~etpwm0 : select etm pwm mode 00: edge aligned 01: centre aligned, compare match on counter count up 10: centre aligned, compare match on counter count down 11: centre aligned, compare match on counter count up or down enhanced type tm operation modes the enhanced type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the etam1 and etam0 bits in the etmc1 register and the etbm1 and etbm0 bits in the etmc2 register etm operation mode ccra compare match output mode ccra timer/ counter mode ccra pwm output mode ccra single pulse output mode ccra capture input mode ccrb co?pa?e mat?h output mode ccrb ti ?e?/ counte? mode ccrb pwm output mode ccrb single pulse output mode ccrb captu?e input mode ?: permitted; : not permitted
rev. 1.10 130 de?e??e? 01? ?01? rev. 1.10 131 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom compare match output mode to select this mode, bits etam1, etam0, etbm1 and etbm0 in the etmc1 and etmc2 registers should be all cleared to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the etcclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both etmaf and etmpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the etcclr bit in the etmc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the etmaf interrupt request fag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when etcclr is high no etmpf interrupt request fag will be generated. in the compare match output mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the etm output pin will change state. the etm output pin condition however only changes state when a etmaf or etmbf interrupt request fag is generated after a compare match occurs from comparator a or comparator b. the etmpf interrupt request fag, generated from a compare match occurs from comparator p, will have no effect on the etm output pin. the way in which the etm output pin changes state are determined by the condition of the etaio1 and etaio0 bits in the etmc1 register for etm ccra and the condition of the etbio1 and etbio0 bits in the etmc2 register for etm ccrb . the etm etpa or etpb output pin can be selected using the etaio1 and etaio0 or etbio1 and etbio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a or comparator b respectively. the initial condition of the etm etpa or etpb output pin, which is setup after the eton bit changes from low to high, is setup using the etaoc or etboc bit. note that if the etaio1, etaio0, etbio1 and etbio0 bits are zero then no pin change will take place.
rev. 1.10 13? de?e??e? 01? ?01? rev. 1.10 133 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value 0x3ff ccrp ccra eton etpau etapol ccrp int . flag etmpf ccra int . flag etmaf etpa o / p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t etcclr = 0; etam [1:0] = 00 output pin set to initial level low if etaoc=0 output toggle with etmaf flag note etaio [1:0] = 10 a?tive high output sele?t he?e etaio [1:0] = 11 toggle output sele?t output not affe?ted ?y etmaf flag. re?ains high until ?eset ?y eton ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when etapol is high 10-bit etm ccra compare match output mode C etcclr = 0 note: 1. with etcclr=0, a comparator p match will clear the counter 2. the etm etpa output pin is controlled only by the etmaf fag 3. the output pin is reset to its initial state by a eton bit rising edge
rev. 1.10 13? de?e??e? 01? ?01? rev. 1.10 133 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value 0x3ff ccrp ccrb eton etpau etbpol ccrp int . flag etmpf ccrb int . flag etmbf etpb o / p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t etcclr = 0; etbm [1:0] = 00 output pin set to initial level low if etboc=0 output toggle with etmbf flag note etbio [1:0] = 10 a?tive high output sele?t he?e etbio [1:0] = 11 toggle output sele?t output not affe?ted ?y etmbf flag. re?ains high until ?eset ?y eton ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when etbpol is high 10-bit etm ccrb compare match output mode C etcclr = 0 note: 1. with etcclr=0, a comparator p match will clear the counter 2. the etm etpb output pin is controlled only by the etmbf fag 3. the output pin is reset to its initial state by a eton bit rising edge
rev. 1.10 134 de?e??e? 01? ?01? rev. 1.10 135 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value 0x3ff ccrp ccra eton etpau etapol ccrp int . flag etmpf ccra int . flag etmaf etpa o / p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t etcclr = 1; etam [1:0] = 00 output pin set to initial level low if etaoc=0 output toggle with etmaf flag note etaio [1:0] = 10 a?tive high output sele?t he?e etaio [1:0] = 11 toggle output sele?t output not affe?ted ?y etmaf flag. re?ains high until ?eset ?y eton ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when etapol is high etmpf not gene?ated no etmaf flag gene?ated on ccra ove?flow output does not ?hange 10-bit etm ccra compare match output mode C etcclr = 1 note: 1. with etcclr=1, a comparator a match will clear the counter 2. the etm etpa output pin is controlled only by the etmaf fag 3. the output pin is reset to its initial state by a eton bit rising edge 4. a etmpf fag is not generated when etcclr =1
rev. 1.10 134 de?e??e? 01? ?01? rev. 1.10 135 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value 0x3ff ccrb ccra eton etpau etbpol ccrb int . flag etmbf ccra int . flag etmaf etpb o / p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t etcclr = 1; etbm [1:0] = 00 output pin set to initial level low if etboc=0 output toggle with etmbf flag note etbio [1:0] = 10 a?tive high output sele?t he?e etbio [1:0] = 11 toggle output sele?t output not affe?ted ?y etmbf flag. re?ains high until ?eset ?y eton ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when etbpol is high no etmaf flag gene?ated on ccra ove?flow 10-bit etm ccrb compare match output mode C etcclr = 1 note: 1. with etcclr=1, a comparator a match will clear the counter 2. the etm etpb output pin is controlled only by the etmbf fag 3. the output pin is reset to its initial state by a eton bit rising edge 4. a etmpf fag is not generated when etcclr =1
rev. 1.10 13? de?e??e? 01? ?01? rev. 1.10 137 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom timer/counter mode to select this mode, bits etam1, etam0, etbm1 and etbm0 in the etmc1 and etmc2 registers should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the etm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the etm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, the required bit pairs, etam1, etam0 and etbm1, etbm0 in the etmc1 and etmc2 register should be set to 10 respectively and also the etaio1, etaio0 and etbio1, etbio0 bits should be set to 10 respectively. the pwm function within the etm is useful for applications which require functions such as motor control, heating control, illumination control, etc. by providing a signal of fxed frequency but of varying duty cycle on the etm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm mode, the etcclr bit is used to determine in which way the pwm period is controlled. with the etcclr bit is high, the pwm period can be fnely controlled using the ccra registers. in this case the ccrb registers are used to set the pwm duty valye for etpb output pin. the ccrp bits are not used and etpa output pin is not used. the pwm output can only be generated on the etpb output pin. with the etcclr bit cleared to zero, the pwm period is set using one of the eight values of the three ccrp bits, in multiples of 128. now both ccra and ccrb registers can be used to setup different duty cycle values to provide dual pwm outputs on their relative etpa and etpb pins. the etpwm1 and etpwm0 bits determine the pwm alignment type, which can be either edge or centre type. in edge alignment, the leading edge of the pwm signals will all be generated concurrently when the counter is reset to zero. with all power currents switching on at the same time, this may give rise to problems in higher power applications. in centre alignment the centre of the pwm active signals will occur sequentially, this reducing the level of simultaneous power switching currents. interrupt fags, one for each of the ccra, ccrb and ccrp, will be generated when a compare match occurs from comparator a, comparator b or comparator p. the etaoc and etboc bits in the etmc1 and etmc2 registers are used to select the required polarity of the pwm waveform while the two etaio1, etaio0 and etbio1, etbio0 bit pairs are used to enable the pwm output or to force the etm output pin to a fxed high or low level. the etapol and etbpol bits are used to reverse the polarity of the pwm output waveform.
rev. 1.10 13? de?e??e? 01? ?01? rev. 1.10 137 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ? 10-bit etm, pwm mode, edge-aligned mode, etcclr=0 ccrp 001b 011b 011b 100b 101b 110b 111b 000b pe?iod 1?8 ?5? 384 51? ?40 7?8 89? 10?4 a duty ccra b duty ccrb if f sys =12mhz, etm clock source select f sys /4, ccrp=100b and ccra=128 and ccrb=256, the etpa pwm output frequency = (f sys /4)/512 = f sys /2048 = 5.8594khz, duty=128/512=25%. the etpb pwm output frequency = (f sys /4)/512 = f sys /2048 = 5.8594khz, duty=256/512=50%. if the duty value defned by the ccra or ccrb register is equal to or greater than the period value, then the pwm output duty is 100%. ? 10-bit etm, pwm mode, edge-aligned mode, etcclr=1 ccra 1 2 3 --- 511 512 --- --- 1021 1022 1023 pe?iod 1 ? 3 --- 511 51? --- --- 10?1 10?? 10?4 b duty ccrb ? 10-bit etm, pwm mode, centre-aligned mode, etcclr=0 ccrp 001b 011b 011b 100b 101b 110b 111b 000b pe?iod ?5? 51? 7?8 10?4 1?80 153? 179? ?04? a duty (ccra?)-1 b duty (ccrb?)-1 ? 10-bit etm, pwm mode, edge-aligned mode, etcclr=1 ccra 1 2 3 --- 511 512 --- --- 1021 1022 1023 pe?iod ? 4 ? --- 10?? 10?4 --- --- ?04? ?044 ?04? b duty (ccrb?)-1
rev. 1.10 138 de?e??e? 01? ?01? rev. 1.10 139 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value ccrp ccra eton etpau etapol ccra int . flag etmaf ccrb int . flag etmbf etpa pin (etaoc=1) ti?e counte? clea?ed ?y ccrp pause resu?e stop counte? resta?t etcclr = 0; etpwm [1:0] = 00 etam [1:0] = 10? etbm [1:0] = 10 output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when etapol is high ccrb ccrp int . flag etmpf etpb pin (etboc=1) etpb pin (etboc=0) duty cy?le set ?y ccra duty cy?le set ?y ccrb pwm pe?iod set ?y ccrp duty cy?le set ?y ccra duty cy?le set ?y ccra 10-bit etm pwm mode C edge aligned note: 1. here etcclr=0 therefore ccrp clears counter and determines the pwm period 2. the internal pwm function continues running even when etaio [1:0] (or etbio [1:0]) = 00 or 01 3. ccra controls the etpa pwm duty and ccrb controls the etpb pwm duty
rev. 1.10 138 de?e??e? 01? ?01? rev. 1.10 139 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value ccra eton etpau etbpol ccrb int . flag etmbf ti?e counte? clea?ed ?y ccra pause resu?e stop counte? resta?t etcclr = 1; etpwm [1:0] = 00; etbm [1:0] = 10 output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when etbpol is high ccrb ccrp int . flag etmpf etpb pin (etboc=1) etpb pin (etboc=0) duty cy?le set ?y ccrb pwm pe?iod set ?y ccra 10-bit etm pwm mode C edge aligned note: 1. here etcclr=1 therefore ccra clears counter and determines the pwm period 2. the internal pwm function continues running even when etbio [1:0] = 00 or 01 3. the ccra controls the etpb pwm period and ccrb controls the etpb pwm duty 4. here the etpa pin control register should not enable the etpa pin as an etm output pin
rev. 1.10 140 de?e??e? 01? ?01? rev. 1.10 141 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value ccrp ccra eton etpau etapol ccra int . flag etmaf ccrb int . flag etmbf etpa pin (etaoc=1) ti?e pause resu?e stop counte? resta?t etcclr = 0; etpwm [1:0] = 11 etam [1:0] = 10? etbm [1:0] = 10 output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when etapol is high ccrb ccrp int . flag etmpf etpb pin (etboc=1) etpb pin (etboc=0) duty cy?le set ?y ccra duty cy?le set ?y ccrb pwm pe?iod set ?y ccrp 10-bit etm pwm mode C centre aligned note: 1. here etcclr=0 therefore ccrp clears counter and determines the pwm period 2. etpwm [1:0] = 11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when etaio [1:0] (or etbio [1:0]) = 00 or 01 4. the ccra controls the etpa pwm duty and ccrb controls the etpb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value
rev. 1.10 140 de?e??e? 01? ?01? rev. 1.10 141 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value ccra eton etpau etbpol ccra int . flag etmaf ccrb int . flag etmbf ti?e pause resu?e stop counte? resta?t etcclr = 1; etpwm [1:0] = 11; etbm [1:0] = 10 output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion ccrb etpb pin (etboc=1) etpb pin (etboc=0) duty cy?le set ?y ccrb pwm pe?iod set ?y ccra output inve?ts when etbpol is high ccrp int . flag etmpf 10-bit etm pwm mode C centre aligned note: 1. here etcclr=1 therefore ccra clears counter and determines the pwm period 2. etpwm [1:0] = 11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when etbio [1:0] = 00 or 01 4. the ccra controls the etpb pwm period and ccrb controls the etpb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value
rev. 1.10 14? de?e??e? 01? ?01? rev. 1.10 143 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom single pulse output mode to select this mode, the required bit pairs, etam1, etam0 and etbm1, etbm0 should be set to 10 respectively and also the corresponding etaio1, etaio0 and etbio1, etbio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the etm output pin. the trigger for the pulse etpa output leading edge is a low to high transition of the eton bit, which can be implemented using the application program. the trigger for the pulse etpb output leading edge is a compare match from comparator b, which can be implemented using the application program. however in the single pulse mode, the eton bit can also be made to automatically change from low to high using the external etck pin, which will in turn initiate the single pulse output of etpa. when the eton bit transitions to a high level, the counter will start running and the pulse leading edge of etpa will be generated. the eton bit should remain high when the pulse is in its active state. the generated pulse trailing edge of etpa and etpb will be generated when the eton bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the eton bit and thus generate the single pulse output trailing edge of etpa and etpb. in this way the ccra value can be used to control the pulse width of etpa. the (ccra-ccrb) value can be used to control the pulse width of etpb. a compare match from comparator a and comparator b will also generate etm interrupts. the counter can only be reset back to zero when the eton bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the etcclr bit is also not used. eton ?it 0 1 s/w co??and seteton o? etck pin t?ansition ccrb leading edge eton ?it 1 0 ccra t?ailing edge s/w co??and clreton o? ccra co?pa?e mat?h etpa output pin etpb output pin pulse width = (ccra-ccrb) value pulse width = ccra value counte? value ccrb ccra 0 ti?e eton = 1 ccrb co?pa?e mat?h eton ?it 1 0 s/w co??and clreton o? ccra co?pa?e mat?h ccrb t?ailing edge ccra leading edge single pulse generation
rev. 1.10 14? de?e??e? 01? ?01? rev. 1.10 143 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value ccrb ccra eton etpau etapol ccrb int . flag etmbf ccra int . flag etmaf etpa pin (etaoc=1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when tnon ?etu?ns high etam [1:0] = 10? etbm [1:0] = 10; etaio [1:0] = 11? etbio [1:0 ] = 11 pulse width set ?y (ccra-ccrb) output inve?ts when etbpol=1 etck pin softwa?e t?igge? clea?ed ?y ccra ?at?h etck pin t?igge? auto. set ?y etck pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? etbpol etpa pin (etaoc=0) etpb pin (etboc=1) etpb pin (etboc=0) pulse width set ?y ccra output inve?ts when etapol=1 10-bit etm single pulse output mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the etck pin or by setting the eton bit high 4. an etck pin active edge will automatically set the eton bit high. 5. in the single pulse mode, etaio [1:0] and etbio [1:0] must be set to 11 and can not be changed.
rev. 1.10 144 de?e??e? 01? ?01? rev. 1.10 145 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom capture input mode to select this mode bits etam1, etam0 and etbm1, etbm0 in the etmc1 and etmc2 registers should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the etpia and etpib pins, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the etaio1, etaio0 and etbio1, etbio0 bits in the etmc1 and etmc2 registers. the counter is started when the eton bit changes from low to high which is initiated using the application program. when the required edge transition appears on the etpia and etpib pins, the present value in the counter will be latched into the ccra and ccrb registers and an etm interrupt generated. irrespective of what events occur on the etpia and etpib pins the counter will continue to free run until the eton bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, an etm interrupt will also be generated. counting the number of overflow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the etaio1, etaio0 and etbio1, etbio0 bits can select the active trigger edge on the etpia and etpib pins to be a rising edge, falling edge or both edge types. if the etaio1, etaio0 and etbio1, etbio0 bits are both set high, then no capture operation will take place irrespective of what happens on the etpia and etpib pins, however it must be noted that the counter will continue to run. as the etpia and etpib pins are pin shared with other functions, care must be taken if the etm is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the etcclr, etaoc, etboc, etapol and etbpol bits are not used in this mode.
rev. 1.10 144 de?e??e? 01? ?01? rev. 1.10 145 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value yy ccrp eton etpau ccrp int . flag etmpf ccra int . flag etmaf ccra value ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? reset etam [1:0] = 01 etm ? aptu ? e pin etpa xx counte? stop etaio [ 1 : 0 ] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e 10-bit etm ccra capture input mode note: 1. etam [1:0] = 01 and active edge set by the etaio [1:0] bits 2. an etm capture input pin active edge transfers the counter value to ccra 3. etcclr bit not used 4. no output function C etaoc and etapol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.10 14? de?e??e? 01? ?01? rev. 1.10 147 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom counte? value yy ccrp eton etpau ccrp int . flag etmpf ccrb int . flag etmbf ccrb value ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? reset etbm [1:0] = 01 etm ? aptu ? e pin etpb xx counte? stop etbio [ 1 : 0 ] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e 10-bit etm ccrb capture input mode note: 1. etbm [1:0] = 01 and active edge set by the etbio [1:0] bits 2. an etm capture input pin active edge transfers the counter value to ccra 3. etcclr bit not used 4. no output function C etboc and etbpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.10 14? de?e??e? 01? ?01? rev. 1.10 147 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. it also can convert the internal signals, such as the bandgap reference voltage, into a 12-bit digital value. the external or internal analog signal to be converted is determined by the sains2~sains0 bits together with the sacs3~sacs0 bits. note that when the internal analog signal is to be converted, the pin-shared control bits should also be properly confgured except the sains and sacs bit felds. more detailed information about the a/d input signal is described in the a/d converter control registers and a/d converter input signal sections respectively. the accompanying block diagram shows the internal structure of the a/d converter together with its associated registers. device input channel a/d channel select bits input pins ht?7f?0a/ht?7f70a 1? sacs3~sacs0 an0~an11 pin-shared selection bandgap reference sacs3~sacs0 sains2~sains0 a/d converter start adbz adcen v ss a/d clock 2 n (n=0~7) f sys sacks2~ sacks0 v dd vref savrs1~savrs0 adcen sadol sadoh an0 an1 an11 a/d reference voltage a/d data registers a/d converter structure
rev. 1.10 148 de?e??e? 01? ?01? rev. 1.10 149 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom a/d converter register description overall operation of the a/d converter is controlled using four registers. a read only register pair exists to store the a/d converter data 12-bit value. the remaining two registers are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 sadol (adrfs=0) d3 d? d1 d0 sadol (adrfs=1) d7 d? d5 d4 d3 d? d1 d0 sadoh (adrfs=0) d11 d10 d9 d8 d7 d? d5 d4 sadoh (adrfs=1) d11 d10 d9 d8 sadc0 start adbz adcen adrfs sacs3 sacs? sacs1 sacs0 sadc1 sains? sains10 sains0 savrs1 savrs0 sacks? sacks1 sacks0 a/d converter registers list a/d converter data registers C sadol, sadoh as the device contains an internal 12-bit a/d converter, it requires two data registers to store the converted value. these are a high byte register, known as sadoh, and a low byte register, known as sadol. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the sadc0 register as shown in the accompanying table. d0~d11 are the a/d conversion result data bits. any unused bits will be read as zero. note that the a/d converter data register contents will be cleared to zero if the a/d converter is disabled. adrfs sadoh sadol 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d? d5 d4 d3 d? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d? d5 d4 d3 d? d1 d0 a/d converter data registers a/d converter control registers C sadc0, sadc1 to control the function and operation of the a/d converter, two control registers known as sadc0, sadc1 are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter, the digitised data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter busy status. the sacs3~sacs0 bits in the sadc0 register are used to determine which external channel input is selected to be converted. the sains2~sains0 bits in the sadc1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. if the sains2~sains0 bits are set to 000, the external analog channel input is selected to be converted and the sacs3~sacs0 bits can determine which external channel is selected to be converted. if the sains2~sains0 bits are set to 001, the internal bandgap reference voltage is selected to be converted. care must be taken when the internal analog signal is selected to be converted. if the internal analog signal is selected to be converted, the sacs3~sacs0 bits must be set to a value of 11xx. otherwise, the external channel input will be connected together with the internal analog signal. this will result in unpredictable situations such as an irreversible damage.
rev. 1.10 148 de?e??e? 01? ?01? rev. 1.10 149 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom sains [2:0] sacs [3:0] input signals description 000? 101? 110? 111 0000~1011 an0~an11 exte?nal pin analog input 11xx floating 001 11xx v bg inte?nal bandgap ?efe?en?e voltage 010~100 xxxx rese?ved a/d converter input signal selection ? sadc0 register bit 7 6 5 4 3 2 1 0 na?e start adbz adcen adrfs sacs3 sacs? sacs1 sacs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 start : start the a/d conversion 010: start an a/d conversion this bit is used to initiate an a/d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. bit 6 adbz : a/d converter busy fag 0: no a/d conversion is in progress 1: a/d conversion is in progress this read only fag is used to indicate whether the a/d conversion is in progress or not. when the start bit is set fro, low to high and then to low again, the adbz fag will be set to 1 to indicate that the a/d conversion is initiated. the adbz fag will be cleared to 0 after the a/d conversion is complete. bit 5 adcen : a/d converter function enable control 0: disable 1: enable this bit controls the a/d internal function. this bit should be set to one to enable the a/d comverter. if the bit is set low, then the a/d converter will be switched off reducing the device power consumption. when the a/d converter function is disabled, the contents of the a/d data register pair, sadoh and sadol, will be cleared to 0. bit 4 adrfs : a/d converter data format control 0: a/d converter data format sadoh = d [11:4]; sadol = d [3:0] 1: a/d converter data format sadoh = d [11:8]; sadol = d [7:0] this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d converter data register section. bit 3~0 sacs3~sacs0 : a/d converter external analog input channel select 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 1000: an8 1001: an9 1010: an10 1011: an11 11xx: floating
rev. 1.10 150 de?e??e? 01? ?01? rev. 1.10 151 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ? sadc1 register bit 7 6 5 4 3 2 1 0 na?e sains? sains10 sains0 savrs1 savrs0 sacks? sacks1 sacks0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~5 sains2~sains0 : a/d converter input signal select 000: external source C external analog channel input 001: internal source C internal bandgap reference voltage 010~100: reserved 101~111: external source C external analog channel input care must be taken if the sains2~sains0 bits are set to 001 to select the internal analog signal to be converted. when the internal analog signal is selected to be converted, the sacs3~sacs0 bits must be set to a value of 11xx. otherwise, the external channel input will be connected together with the internal analog signal. this will result in unpredictable situations such as an irreversible damage. bit 4~3 savrs1~savrs0 : a/d converter reference voltage select 00: from vref pin 01: from vdd pin 1x: from vref pin bit 2~0 sacks2~sacks0 : a/d conversion clock source select 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: f /128 these bits are used to select the clock source for the a/d converter. a/d operation the start bit is used to start the a/d conversion. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the a/d conversion will not be initiated. the adbz bit in the sadc0 register is used to indicate whether the analog to digital conversion process is in progress or not. this bit will be automatically set to 1 by the microcontroller after an a/d conversion is successfully initiated. when the a/d conversion is complete, the adbz will be cleared to 0. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register, and if the interrupts are enabled, an internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program fow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can poll the adbz bit in the sadc0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. although the a/d clock source is determined by the system clock f , and by bits sacks2~sadcks0, there are some limitations on the maximum a/d clock source speed that can be selected. as the recommended range of permissible a/d clock period, t adck , is from 0.5s to 10s, care must be taken for selected system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the sacks2~sadcks0 bits should not be set to 000 or 11x. doing so will give a/d clock periods that are less than the minimum a/d clock period or greater than the maximum a/d clock period which may result in inaccurate a/d conversion values.
rev. 1.10 150 de?e??e? 01? ?01? rev. 1.10 151 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom f sys a/d clock period (t adck ) adck[2:0] = 000 (f sys ) adck[2:0] = 001 (f sys /2) adck[2:0] = 010 (f sys /4) adck[2:0] = 011 (f sys /8) adck[2:0] = 100 (f sys /16) adck[2:0] = 101 (f sys /62) adck[2:0] = 110 (f sys /64) adck[2:0] = 111 (f sys /128) 1 mhz 1s 2s 4s 8s 16s * 32s * 64s * 128s * ? mhz 500ns 1s 2s 4s 8s 16s * 32s * 64s * 4 mhz 250ns * 500ns 1s 2s 4s 8s 16s * 32s * 8 mhz 125ns * 250ns * 500ns 1s 2s 4s 8s 16s * 1? mhz 83ns * 167ns * 333ns * ??7ns 1.33s 2.67s 5.33s 10.67s * 1? mhz 62.5ns * 125ns * 250ns * 500ns 1s 2s 4s 8s ?0 mhz 50ns * 100ns * 200ns * 400ns * 800ns 1.6s 3.2s 6.4s a/d clock period examples controlling the power on/off function of the a/d converter circuitry is implemented using the adcen bit in the sadc0 register. this bit must be set high to power on the a/d converter. when the adcen bit is set high to power on the a/d converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by confguring the corresponding pin-shared control bits, if the adcen bit is high then some power will still be consumed. in power conscious applications it is therefore recommended that the adcen is set low to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref. the desired selection is made using the savrs1 and savrs0 bits. when the savrs bit feld is set to 01, the a/d converter reference voltage will come from the vdd pin. otherwise, if the savrs bit feld is set to any other value except 01, the a/d converter reference voltage will come from the vref pin. as the vref pin is pin-shared with other functions, when the vref pin is selected as the reference voltage supply pin, the vref pin-shared function control bits should be properly configured to disable other pin functions. savrs [1:0] reference voltage description 00 v ref a/d conve?te? refe?en?e voltage ?o?es f?o? vref pin 01 v dd a/d conve?te? refe?en?e voltage ?o?es f?o? vdd pin 1x v ref a/d conve?te? refe?en?e voltage ?o?es f?o? vref pin a/d converter reference voltage selection a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins as well as other functions. the corresponding pin-shared function selection bits for each pin in the pxs1 and pxs0 registers, determine whether the external pins are setup as a/d converter analog channel inputs or they have other functions. if the corresponding pin is setup to be an a/d converter analog channel input, the original pin functions will be disabled. in this way, pins can be changed under program control to change their function between a/d inputs and other functions. all pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the port control register to enable the a/d input as when the relevant pin-shared function selection bits enable an a/d analog channel input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref. however, the reference voltage can also be supplied from the power supply pin, a choice which is made through the savrs1 and savrs0 bits in the sadc1 register. the analog input values must not be allowed to exceed the value of v ref .
rev. 1.10 15? de?e??e? 01? ?01? rev. 1.10 153 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom conversion rate and timing diagram a complete a/d conversion contains two parts, data sampling and data conversion. the data sampling which is defned as t ads takes 4 a/d clock cycles and the data conversion takes 12 a/d clock cycles. therefore a total of 16 a/d clock cycles for an a/d conversion which is defned as t adc are necessary. maximum single a/d conversion rate = a/d clock period / 16 (1) the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16 t adck clock cycles where t adck is equal to the a/d clock period. enadc start adbz sacs[3:0] off on off on t on2st t ads a/d sampling time t ads a/d sampling time start of a/d conversion start of a/d conversion start of a/d conversion end of a/d conversion end of a/d conversion t adc a/d conversion time t adc a/d conversion time t adc a/d conversion time 0011b 0010b 0000b 0001b a/d channel switch a/d conversion timing summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion clock by properly programming the sacks2~sacks0 bits in the sadc1 register. ? step 2 enable the a/d converter by setting the adcen bit in the sadc0 register to one. ? step 3 select which signal is to be connected to the internal a/d converter by correctly confguring the sains2~sains0 bits. select the external channel input to be converted, go to step 4. select the internal analog signal to be converted, go to step 5. ? step 4 if the a/d input signal comes from the external channel input selecting by confguring the sains bit feld, the corresponding pins should frst be confgured as a/d input function by confguring the relevant pin-shared function control bits. the desired analog channel then should be selected by confguring the sacs bit feld. after this step, go to step 6.
rev. 1.10 15? de?e??e? 01? ?01? rev. 1.10 153 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ? step 5 before the a/d input signal is selected to come from the internal analog signal by confguring the sains bit feld, the sacs bit feld must be frst confgured to a value of 11xx to disconnect the external channel input. the desired internal analog signal then can be selected by confguring the sains bit feld. after this step, go to step 6. ? step 6 select the reference voltgage source by confguring the savrs1~savrs0 bits. ? step 7 select the a/d converter output data format by confguring the adrfs bit. ? step 8 if a/d conversion interrupt is used, the interrupt control registers must be correctly confgured to ensure the a/d interrupt function is active. the master interrupt bontrol bit, emi, and the a/d conversion interrupt control bit, ade, must both be set high in advance. ? step 9 the a/d conversion procedure can now be initialized by setting the start bit from low to high and then low again. ? step 10 if a/d conversion is in progress, the adbz flag will be set high. after the a/d conversion process is complete, the adbz flag will go low and then the output data can be read from sadoh and sadol registers. note: when checking for the end of the conversion process, if the method of polling the adbz bit in the sadc0 register is used, the interrupt enable step above can be omitted. programming considerations during microcontroller operations where the a/d converter is not being used, the a/d internal circuitry can be switched off to reduce power consumption, by setting bit adcen low in the sadc0 register. when this happens, the internal a/d converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the devices contain a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb = (v dd or v ref ) 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value (v dd or v ref ) 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output value for the a/d converter. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.
rev. 1.10 154 de?e??e? 01? ?01? rev. 1.10 155 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom

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? ideal a/d transfer function a/d programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the adbz bit in the sadc0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an adbz polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov sadc1,a ; select f sys /8 as a/d clock set adcen mov a,0ch ; setup pas0 to confgure pin an0 mov pas0,a mov a,20h mov sadc0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d : polling_eoc: sz adbz ; poll the sadc0 register adbz bit to detect end of a/d conversion jmp polling_eoc ; continue polling : mov a,sadol ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,sadoh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : jmp start_conversion ; start next a/d conversion
rev. 1.10 154 de?e??e? 01? ?01? rev. 1.10 155 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov sadc1,a ; select f sys /8 as a/d clock set adcen mov a,0ch ; setup pas0 to confgure pin an0 mov pas0,a mov a,20h mov sadc0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set ade ; enable adc interrupt set emi ; enable global interrupt : : adc_isr: ; adc interrupt service routine mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : mov a, sadol ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a, sadoh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,acc_stack ; restore acc from user defned memory reti
rev. 1.10 15? de?e??e? 01? ?01? rev. 1.10 157 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom comparators two independent analog comparators are contained within these devices. these functions offer fexibility via their register controlled features such as power-down, polarity select, hysteresis etc. in sharing their pins with normal i/o pins the comparators do not waste precious i/o pins if there functions are otherwise unused.

comparator comparator operation the device contains two comparator functions which are used to compare two analog voltages and provide an output based on their difference. full control over the two internal comparators is provided via two control registers, cp0c and cp1c, one assigned to each comparator. the comparator output is recorded via a bit in their respective control register, but can also be transferred out onto a shared i/o pin. additional comparator functions include, output polarity, hysteresis functions and power down control. any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. as the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. this can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level, however, unavoidable input offsets introduce some uncertainties here. the hysteresis function, if enabled, also increases the switching offset value. comparator registers there are two registers for overall comparator operation, one for each comparator. as corresponding bits in the two registers have identical functions, the following table applies to both registers. register name bit 7 6 5 4 3 2 1 0 cp0c c0en c0pol c0out c0hyen cp1c c1en c1pol c1out c1hyen comparator registers list
rev. 1.10 15? de?e??e? 01? ?01? rev. 1.10 157 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom cp0c register bit 7 6 5 4 3 2 1 0 na?e c0en c0pol c0out c0hyen r/w r/w r/w r r/w por 0 0 0 1 bit 7 unimplemented, read as 0 bit 6 c0en : comparator on/off control 0: off 1: on this is the comparator on/off control. if the bit is zero, the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the sleep or idle mode. bit 5 c0pol : comparator output polarity control 0: not inverted 1: inverted this is the comparator polarity bit. if the bit is zero, then the c0out bit will refect the non-inverted output condition of the comparator. if the bit is high, the comparator c0out bit will be inverted. bit 4 c0out : comparator output c0pol=0 0: c0+ < c0C 1: c0+ > c0C c0pol=1 0: c0+ > c0C 1: c0+ < c0C this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the c0pol bit. bit 3~1 unimplemented, read as 0 bit 0 c0hyen : comparator hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specifed in the comparator electrical characteristics table. the positive feedback induced by hesteresus reduces the effect of spurious switching near the comparator threshold. cp1c register bit 7 6 5 4 3 2 1 0 na?e c1en c1pol c1out c1hyen r/w r/w r/w r r/w por 0 0 0 1 bit 7 unimplemented, read as 0 bit 6 c1en : comparator on/off control 0: off 1: on this is the comparator on/off control. if the bit is zero, the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the sleep or idle mode.
rev. 1.10 158 de?e??e? 01? ?01? rev. 1.10 159 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom bit 5 c1pol : comparator output polarity control 0: not inverted 1: inverted this is the comparator polarity bit. if the bit is zero, then the c1out bit will refect the non-inverted output condition of the comparator. if the bit is high, the comparator c1out bit will be inverted. bit 4 c1out : comparator output c1pol=0 0: c1+ < c1C 1: c1+ > c1C c1pol=1 0: c1+ > c1C 1: c1+ < c1C this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the c1pol bit. bit 3~1 unimplemented, read as 0 bit 0 c1hyen : comparator hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specifed in the comparator electrical characteristics table. the positive feedback induced by hesteresus reduces the effect of spurious switching near the comparator threshold. comparator interrupt each also possesses its own interrupt function. when any one of the changes state, its relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. note that it is the changing state of the c0out or c1out bit and not the output pin which generates an interrupt. if the microcontroller is in the sleep or idle mode and the comparator is enabled, then if the external input lines cause the comparator output to change state, the resulting generated interrupt fag will also generate a wake-up. if it is required to disable a wake-up from occurring, then the interrupt fag should be frst set high before entering the sleep or idle mode. programming considerations if the comparator is enabled, it will remain active when the microcontroller enters the sleep or idle mode. however, as it will consume a certain amount of power, the user may wish to consider disabling it before the sleep or idle mode is entered. as comparator pins are shared with normal i/o pins the i/o registers for these pins will be read as zero (port control register is 1) or read as port data register value (port control register is 0) if the comparator function is enabled.
rev. 1.10 158 de?e??e? 01? ?01? rev. 1.10 159 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom serial interface module C sim the device contains a serial interface module, which includes both the four-line spi interface and two-line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim interface pins are pin-shared with other i/o pins and therefore the sim interface functional pins must first be selected using the corresponding pin-shared function selection bits. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. these pull-high resistors of the sim pin-shared i/o pins are selected using pull- high control registers when the sim function is enabled and the corresponding pins are used as sim input pins. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices, etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the devices can be either master or slave. although the spi interface specifcation can control multiple slave devices from a single master, these devices provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface pins must frst be selected by confguring the pin-shared function selection bits and setting the correct bits in the simc0 and simc2 registers. after the desired spi confguration has been set it can be disabled or enabled using the simen bit in the simc0 register. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to 1 to enable scs pin function, set csen bit to 0 the scs pin will be foating state. the spi function in this device offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen.
rev. 1.10 1?0 de?e??e? 01? ?01? rev. 1.10 1?1 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom spi master/slave connection

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? ? ? ? - ? ?? ? ??? ? ? ? spi block diagram spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim? sim1 sim0 simdeb1 simdeb0 simen simd d7 d? d5 d4 d3 d? d1 d0 simc? d7 d? ckpolb ckeg mls csen wcol trf spi registers list simd register the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the device can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: unknown
rev. 1.10 1?0 de?e??e? 01? ?01? rev. 1.10 1?1 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi function, only by the i 2 c function. register simc0 is used to control the enable/disable function and to set the data transmission clock frequency. register simc2 is used for other control functions such as lsb/msb selection, write collision fag, etc. ? simc0 register bit 7 6 5 4 3 2 1 0 na?e sim? sim1 sim0 simdeb1 simdeb0 simen r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 bit 7~5 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is ctm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from ctm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as 0 bit 3~2 : i 2 c debounce time selection 00: no debounce 01: 2 system clock debounce 1x: 4 system clock debounce bit 1 : sim enable control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will lose their spi or i 2 c function and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective.if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as 0
rev. 1.10 1?? de?e??e? 01? ?01? rev. 1.10 1?3 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ? simc2 register bit 7 6 5 4 3 2 1 0 na?e d7 d? ckpolb ckeg mls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 undefned bits these bits can be read or written by the application program. bit 5 ckpolb : spi clock line base condition selection 0: the sck line will be high when the clock is inactive. 1: the sck line will be low when the clock is inactive. the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. bit 4 ckeg : spi sck clock active edge type selection ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is executed otherwise an erroneous clock edge may be generated. the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb frst 1: msb frst this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low, then the scs pin will be disabled and placed into i/o pin or other pin-shared functions. if the bit is high, the scs pin will be enabled and used as a select pin. bit 1 wcol : spi write collision fag 0: no collision 1: collision the wcol fag is used to detect whether a data collision has occurred or not. if this bit is high, it means that data has been attempted to be written to the simd register duting a data transfer operation. this writing operation will be ignored if data is being transferred. this bit can be cleared by the application program. bit 0 trf : spi transmit/receive complete fag 0: spi data is being transferred 1: spi data transfer is completed the trf bit is the transmit/receive complete flag and is set to 1 automatically when an spi data transmission is completed, but must cleared to 0 by the application program. it can be used to generate an interrupt.
rev. 1.10 1?? de?e??e? 01? ?01? rev. 1.10 1?3 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom spi communication after the spi interface is enabled by setting the simen bit high, then in the master mode, when data is written to the simd register, transmission/reception will begin simultaneously. when the data transfer is complete, the trf flag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register. the master should output a scs signal to enable the slave devices before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode.
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? ? ? ? ??? ? - ? ? ?? spi slave mode timing C ckeg = 0
rev. 1.10 1?4 de?e??e? 01? ?01? rev. 1.10 1?5 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom

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rev. 1.10 1?4 de?e??e? 01? ?01? rev. 1.10 1?5 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data transfer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for these devices, which only operate in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode.

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rev. 1.10 1?? de?e??e? 01? ?01? rev. 1.10 1?7 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom
the simdbc1 and simdbc0 bits determine the debounce time of the i 2 c interface. this uses the system clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 2 or 4 system clocks. to achieve the required i 2 c data transfer speed, there exists a relationship between the system clock, f sys , and the i 2 c debounce time. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the confgured debounce time to match the criterion shown in the following table. i 2 c debounce time selection i 2 c standard mode (100khz) i 2 c fast mode (400khz) no devoun?e f sys > ? mhz f sys > 5 mhz ? syste? ?lo?k de?oun?e f sys > 4 mhz f sys > 10 mhz 4 syste? ?lo?k de?oun?e f sys > 8 mhz f sys > ?0 mhz i 2 c minimum f sys frequency i 2 c registers there are three control registers associated with the i 2 c bus, simc0, simc1 and sima, and one data register, simd. the simd register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the microcontroller can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim? sim1 sim0 simdeb1 simdeb0 simen simc1 hcf haas hbb htx txak srw iamwu rxak simd d7 d? d5 d4 d3 d? d1 d0 sima iica? iica5 iica4 iica3 iica? iica1 iica0 d0 i 2 c registers list
rev. 1.10 1?? de?e??e? 01? ?01? rev. 1.10 1?7 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ? simd register the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the device can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: unknown ? sima register the sima register is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of the sima register defne the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register, the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 7 6 5 4 3 2 1 0 na?e iica? iica5 iica4 iica3 iica? iica1 iica0 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: unknown bit 7~1 : i 2 c slave address iica6~iica0 is the i 2 c slave address bit 6 ~ bit 0 bit 0 undefned bit the bit can be read or written by the application program. there are also two control registers for the i 2 c interface, simc0 and simc1. the register simc0 is used to control the enable/disable function and to set the data transmission clock frequency.the simc1 register contains the relevant fags which are used to indicate the i 2 c communication status.
rev. 1.10 1?8 de?e??e? 01? ?01? rev. 1.10 1?9 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ? simc0 register bit 7 6 5 4 3 2 1 0 na?e sim? sim1 sim0 simdeb1 simdeb0 simen r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f /4 001: spi master mode; spi clock is f /16 010: spi master mode; spi clock is f /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is ctm0 ccrp match frequency/2 101: spi slave mode 110: i c slave mode 111: non sim function these bits setup the overall operating mode of the sim function. as well as selecting if the i c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from ctm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as 0 bit 3~2 simdeb1~simdeb0 : i c debounce time selection 00: no debounce 01: 2 system clock debounce 1x: 4 system clock debounce bit 1 simen : sim enable control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will lose their spi or i c function and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective.if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as 0
rev. 1.10 1?8 de?e??e? 01? ?01? rev. 1.10 1?9 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ? simc1 register bit 7 6 5 4 3 2 1 0 na?e hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r/w r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf : i c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas : i c bus data transfer completion fag 0: not address match 1: address match the haas fag is the address match fag. this fag is used to determine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb : i c bus busy fag 0: i c bus is not busy 1: i c bus is busy the hbb flag is the i c busy flag. this flag will be 1 when the i c bus is busy which will occur when a start signal is detected. the fag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 htx : i c slave device transmitter/receiver selection 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak : i c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave does not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9 th clock from the slave device. the slave device must always set txak bit to 0 before further data is received. bit 2 srw : i c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the srw flag is the i c slave read/write flag. this flag determines whether the master device wishes to transmit or receive data from the i c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the srw fag to determine whether it should be in transmit mode or receive mode. if the srw fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the srw flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu : i c address match wake-up control 0: disable 1: enable C must be cleared by the application program after wake-up this bit should be set to 1 to enable the i c address match wake up from the sleep or idle mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i c address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation.
rev. 1.10 170 de?e??e? 01? ?01? rev. 1.10 171 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom bit 0 rxak : i 2 c bus receive acknowledge fag 0: slave receives acknowledge fag 1: slave does not receive acknowledge fag the rxak flag is the receiver acknowledge flag. when the rxak flag is 0, it means that a acknowledge signal has been received at the 9 th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receiver wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the rxak fag is 1. when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. communication on the i 2 c bus requires four separate steps, a start signal, a slave device address transmission, a data transmission and finally a stop signal. when a start signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8 th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 and simen bits in the simc0 register to 1 to enable the i 2 c bus. ? step 2 write the slave address of the device to the i 2 c bus address register sima. ? step 3 set the sime and sim muti-function interrupt enable bit of the interrupt control register to enable the sim interrupt and multi-function interrupt.

? ? ? ? ? ? - ? ? ? ? ? ?? ? ? ? ? ? - i 2 c bus initialisation flow chart
rev. 1.10 170 de?e??e? 01? ?01? rev. 1.10 171 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom i 2 c bus start signal the start signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this start signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8 th bit, defnes the read/write status and will be saved to the srw bit of the simc1 register. the slave device will then transmit an acknowledge bit, which is a low level, as the 9 th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. when a slave address is matched, the devices must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the srw bit in the simc1 register defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver. if the srw fag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw fag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the srw fag to determine if it is to be a transmitter or a receiver. if the srw fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to 1. if the srw fag is low, then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to 0.
rev. 1.10 17? de?e??e? 01? ?01? rev. 1.10 173 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom i 2 c bus data and acknowledge signal the transmitted data is 8-bit wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb frst and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level 0, before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter, the slave device must frst write the data to be transmitted into the simd register. if setup as a receiver, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9 th clock. the slave device, which is setup as a transmitter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master.
? ? ? ? ? ? ? ? - ?
- ? ? note: * when a slave address is matched, the devices must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c communication timing diagram
rev. 1.10 17? de?e??e? 01? ?01? rev. 1.10 173 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom
? ?
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i 2 c bus isr flow chart i 2 c time-out control in order to reduce the i 2 c lockup problem due to reception of erroneous clock sources, a time-out function is provided. if the clock source connected to the i 2 c bus is not received for a while, then the i 2 c circuitry and registers will be reset after a certain time-out period. the time-out counter starts to count on an i 2 c bus start & address matchcondition, and is cleared by an scl falling edge. before the next scl falling edge arrives, if the time elapsed is greater than the time-out period specifed by the i2ctoc register, then a time-out condition will occur. the time-out function will stop when an i 2 c stop condition occurs.

i 2 c time-out
rev. 1.10 174 de?e??e? 01? ?01? rev. 1.10 175 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom when an i 2 c time-out counter overfow occurs, the counter will stop and the i2ctoen bit will be cleared to zero and the i2ctf bit will be set high to indicate that a time-out condition has occurred. the time-out condition will also generate an interrupt which uses the i 2 c interrrupt vector. when an i 2 c time-out occurs, the i 2 c internal circuitry will be reset and the registers will be reset into the following condition: register after i 2 c time-out simd? sima? simc0 no ?hange simc1 reset to por ?ondition i 2 c register after time-out the i2ctof fag can be cleared by the application program. there are 64 time-out period selections which can be selected using the i2ctos bits in the i2ctoc register. the time-out duration is calculated by the formula: ((1~64) (32/f sub )). this gives a time-out period which ranges from about 1ms to 64ms. ? i2ctoc register bit 7 6 5 4 3 2 1 0 na?e i? ctoen i? ctof i? ctos5 i? ctos4 i? ctos3 i? ctos? i? ctos1 i? ctos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 : i 2 c time-out control 0: disable 1: enable bit 6 : i 2 c time-out fag 0: no time-out occurred 1: time-out occurred bit 5~0 : i 2 c time-out period selection i 2 c time-out clock source is f sub /32 i 2 c time-out period is equal to (i2ctos[5:0]+1) 32 f sub
rev. 1.10 174 de?e??e? 01? ?01? rev. 1.10 175 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with i/o line, the required pin function is chosen using the relevant pin-shared function selection bit. the peripheral clock function is controlled using the tb2en bit in the tbc2 register. the clock source for the peripheral clock output can originate from the system clock f sys , the instruction clock, the high speed oscillator clock f h or the f sub clock which can be selected by the clks11 and clks10 bits in the psc1 register. the tb2en bit in the tbc2 register is the overall on/off control, setting tb2en bit to 1 enables the peripheral clock while setting tb2en bit to 0 disables it. the required division ratio of the peripheral clock is selected using the tb22, tb21 and tb20 bits in the tbc2 register. if the peripheral clock source is switched off when the device enters the power down mode, this will disable the peripheral clock output. f sys /4 f p clks1[1:0 ] f tbc f sys f h prescaler tb2en tb2[2:0 ] f p /2 0 ~ f p /2 7 pck peripheral clock output peripheral clock registers there are two internal registers which control the overall operation of the peripheral clock output. these are the psc1 and tbc2 registers. name bit 7 6 5 4 3 2 1 0 psc1 clks11 clks10 tbc? tb?en tb?? tb?1 tb?0 pck register list psc1 register bit 7 6 5 4 3 2 1 0 na?e clks11 clks10 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 : peripheral clock source f p selection 00: f sys 01: f sys /4 10: f tbc 11: f h
rev. 1.10 17? de?e??e? 01? ?01? rev. 1.10 177 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom tbc2 register bit 7 6 5 4 3 2 1 0 na?e tb?en tb?? tb?1 tb?0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 tb2en : peripheral clock function enable control 0: disable 1: enable bit 6~3 unimplemented, read as 0 bit 1~0 tb22, tb21, tb20 : peripheral clock output division selection 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: f /128 serial interface C spia the device contains an independent spi function. it is important not to confuse this independent spi function with the additional one contained within the combined sim function, which is described in another section of this datasheet. this independent spi function will carry the name spia to distinguish it from the other one in the sim. this spia interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices, etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the spia interface specifcation can control multiple slave devices from a single master, this device is provided only one scsa pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pins to select the slave devices. spia interface operation the spia interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdia, sdoa, scka and scsa . pins sdia and sdoa are the serial data input and serial data output lines, scka is the serial clock line and scsa is the slave select line. as the spia interface pins are pin-shared with other functions, the spia interface pins must first be selected by configuring the corresponding selection bits in the pin-shared function selection registers. the spia interface function is disabled or enabled using the spiaen bit in the spiac0 register. communication between devices connected to the spia interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock/signal. as the device only contains a single scsa pin only one slave device can be utilised. the scsa pin is controlled by the application program, set the the sacsen bit to 1 to enable the scsa pin function and clear the sacsen bit to 0 to place the scsa pin into an i/o function.
rev. 1.10 17? de?e??e? 01? ?01? rev. 1.10 177 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom spia master/slave connection the spia serial interface function includes the following features: ? full-duplex synchronous data transfer ? both master and slave mode ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge the status of the spia interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as sacsen and spiaen.

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? ? ? ? - ? ? ? ? ? ??? ? ? ? spia block diagram spia registers there are three internal registers which control the overall operation of the spia interface. these are the simd data register and two registers spiac0 and spiac1. register name bit 7 6 5 4 3 2 1 0 spiac0 saspi? saspia1 saspia0 spiaen spiac1 sackpolb sackeg samls sacsen sawcol satrf spiad d7 d? d5 d4 d3 d? d1 d0 spia registers list
rev. 1.10 178 de?e??e? 01? ?01? rev. 1.10 179 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ? spiad register the spiad register is used to store the data being transmitted and received. before the device writes data to the spia bus, the actual data to be transmitted must be placed in the spiad register. after the data is received from the spia bus, the device can read it from the spiad register. any transmission or reception of data from the spia bus must be made via the spia register. bit 7 6 5 4 3 2 1 0 na?e d7 d? d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: unknown there are also two control registers for the spia interface, spiac0 and spiac1. register spiac0 is used to control the enable/disable function and to set the data transmission clock frequency. register spiac1 is used for other control functions such as lsb/msb selection, write collision fag, etc. ? spiac0 register bit 7 6 5 4 3 2 1 0 na?e saspi? saspia1 saspia0 spiaen r/w r/w r/w r/w r/w por 1 1 1 0 bit 7~5 saspi2~saspi0 : spia master/slave clock select 000: spia master mode with clock f /4 001: spia master mode with clock f /16 010: spia master mode with clock f /64 011: spia master mode with clock f tbc 100: spia master mode with clock ctm0 ccrp match frequency/2 101: spia slave mode 11x: reserved bit 4~2 unimplemented, read as 0 bit 1 spiaen : spia enable control 0: disable 1: enable the bit is the overall on/off control for the spia interface. when the spiaen bit is cleared to zero to disable the spia interface, the sdia, sdoa, scka and scsa lines will lose the spi function and the spia operating current will be reduced to a minimum value. when the bit is high the spia interface is enabled. bit 0 unimplemented, read as 0
rev. 1.10 178 de?e??e? 01? ?01? rev. 1.10 179 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom ? spiac1 register bit 7 6 5 4 3 2 1 0 na?e sackpolb sackeg samls sacsen sawcol satrf r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 sackpolb : spia clock line base condition selection 0: the scka line will be high when the clock is inactive. 1: the scka line will be low when the clock is inactive. the sackpolb bit determines the base condition of the clock line, if the bit is high, then the scka line will be low when the clock is inactive. when the sackpolb bit is low, then the scka line will be high when the clock is inactive. bit 4 sackeg : spia scka clock active edge type selection sackpolb=0 0: scka is high base level and data capture at scka rising edge 1: scka is high base level and data capture at scka falling edge sackpolb=1 0: scka is low base level and data capture at scka falling edge 1: scka is low base level and data capture at scka rising edge the sackeg and sackpolb bits are used to setup the way that the clock signal outputs and inputs data on the spia bus. these two bits must be confgured before data transfer is executed otherwise an erroneous clock edge may be generated. the sackpolb bit determines the base condition of the clock line, if the bit is high, then the scka line will be low when the clock is inactive. when the sackpolb bit is low, then the scka line will be high when the clock is inactive. the sackeg bit determines active clock edge type which depends upon the condition of sackpolb bit. bit 3 samls : spia data shift order 0: lsb frst 1: msb frst this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 sacsen : spia scsa pin control 0: disable 1: enable the sacsen bit is used as an enable/disable for the scsa pin. if this bit is low, then the scsa pin function will be disabled and can be placed into i/o pin or other pin- shared functions. if the bit is high, the scsa pin will be enabled and used as a select bit 1 sawcol : spia write collision fag 0: no collision 1: collision the sawcol flag is used to detect whether a data collision has occurred or not. if this bit is high, it means that data has been attempted to be written to the spiad register duting a data transfer operation. this writing operation will be ignored if data is being transferred. this bit can be cleared by the application program. bit 0 satrf : spia transmit/receive complete fag 0: spia data is being transferred 1: spia data transfer is completed the satrf bit is the transmit/receive complete fag and is set to 1 automatically when an spia data transfer is completed, but must cleared to 0 by the application program. it can be used to generate an interrupt.
rev. 1.10 180 de?e??e? 01? ?01? rev. 1.10 181 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom spia communication after the spia interface is enabled by setting the spiaen bit high, then in the master mode, when data is written to the spiad register, transmission/reception will begin simultaneously. when the data transfer is complete, the satrf fag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the spiad register will be transmitted and any data on the sdia pin will be shifted into the spiad registers. the master should output a scsa signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scsa signal depending upon the configurations of the sackpolb bit and sackeg bit. the accompanying timing diagram shows the relationship between the slave data and scsa signal for various confgurations of the sackpolb and sackeg bits. the spia will continue to function if the spia clock source is active.
rev. 1.10 180 de?e??e? 01? ?01? rev. 1.10 181 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom d7/d0 d6/d1 d5/d2 d4/d3 d3/d4 d2/d5 d1/d6 d0/d7 d7/d0 d6/d1 d5/d2 d4/d3 d3/d4 d2/d5 d1/d6 d0/d7 spia master mode sdia data capture d7/d0 d6/d1 d5/d2 d4/d3 d3/d4 d2/d5 d1/d6 d0/d7 ( sdoa not change until first scka edge) spia slave mode ( sackeg =0 ) sdia data capture d7/d0 d6/d1 d5/d2 d4/d3 d3/d4 d2/d5 d1/d6 d0/d7 (sdoa change as soon as writing occur ; sdoa =floating if =1) spiaen =1,sacsen =0 ( external pull-high) write to spiad scka ( sackpolb= 1 sackeg = 0 ) sdoa ( = 0) scka ( sackpolb =1 ) scka (sackpolb =0 ) sdoa scka ( = 0 = 0 ) scka ( = 1 = 1 ) scka ( = 0 = ) 1 sdoa ( = 1) write to spiad write to spiad spia slave mode (sackeg =1 ) scsa sackpolb sackeg sackpolb sackeg sackpolb sackeg sackeg sackeg spiaen =1, sacsen =1 scsa scsa sdia data capture scka ( sackpolb =1 scka (sackpolb =0 sdoa scsa ) ) note: for spia slave mode, if spiaen=1 and sacsen=0, spia is always enabled and ignore the scsa level. spia master/slave mode timing diagram
rev. 1.10 18? de?e??e? 01? ?01? rev. 1.10 183 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom

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? ? ? ? ? ?
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? ? ? ? - ? ? ? ? ?? ? ? ?? ?? ? ???? ??? ??? ? ?? ?? ?? ? ? spia transfer control flow chart spia bus enable/disable to enable the spia bus, set sacsen=1 and scsa =0, then wait for data to be written into the spiad (txrx buffer) register. for the master mode, after data has been written to the spiad (txrx buffer) register, then transmission or reception will start automatically. when all the data has been transferred the satrf bit should be set. for the slave mode, when clock pulses are received on scka, data in the txrx buffer will be shifted out or data on sdia will be shifted in. when the spia bus is disabled, the scka, sdia, sdoa and scsa pins can become i/o pins or other pin-shared functions using the corresponding pin-shared function control bits.
rev. 1.10 18? de?e??e? 01? ?01? rev. 1.10 183 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom spia operation all communication is carried out using the 4-line interface for either master or slave mode. the sacsen bit in the spiac1 register controls the overall function of the spia interface. setting this bit high will enable the spia interface by allowing the scsa line to be active, which can then be used to control the spia interface. if the sacsen bit is low, the spia interface will be disabled and the scsa line will be an i/o pin or other pin-shared functions and can therefore not be used for control of the spia interface. if the sacsen bit and the spiaen bit in the spiac0 register are set high, this will place the sdia line in a foating condition and the sdoa line high. if in master mode the scka line will be either high or low depending upon the clock polarity selection bit sackpolb in the spiac1 register. if in slave mode the scka line will be in a foating condition. if spiaen is low then the bus will be disabled and scsa , sdia, sdoa and scka pins can be used as i/o pins or other pin-shared functions. in the master mode the master will always generate the clock signal. the clock and data transmission will be initiated after data has been written into the spiad register. in the slave mode, the clock signal will be received from an external master device for both data transmission and reception. the following sequences show the order to be followed for data transfer in both master and slave mode. master mode: ? step 1 select the clock source and master mode using the saspi2~saspi0 bits in the spiac0 control register. ? step 2 setup the sacsen bit and setup the samls bit to choose if the data is msb or lsb shifted frst, this must be same as the slave device. ? step 3 setup the spiaen bit in the spiac0 control register to enable the spia interface. ? step 4 for write operations: write the data to the spiad register, which will actually place the data into the txrx buffer. then use the scka and scsa lines to output the data. after this go to step 5. for read operations: the data transferred in on the sdia line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the spiad register. ? step 5 check the sawcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the satrf bit or wait for a spia serial bus interrupt. ? step 7 read data from the spiad register. ? step 8 clear satrf. ? step 9 go to step 4.
rev. 1.10 184 de?e??e? 01? ?01? rev. 1.10 185 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom slave mode: ? step 1 select the spi slave mode using the saspi2~saspi0 bits in the spiac0 control register. ? step 2 setup the sacsen bit and setup the samls bit to choose if the data is msb or lsb shifted frst, this setting must be the same with the master device. ? step 3 setup the spiaen bit in the spiac0 control register to enable the spia interface. ? step 4 for write operations: write the data to the spiad register, which will actually place the data into the txrx buffer. then wait for the master clock scka and scsa signal. after this, go to step 5. for read operations: the data transferred in on the sdia line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the spiad register. ? step 5 check the sawcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the satrf bit or wait for a spia serial bus interrupt. ? step 7 read data from the spiad register. ? step 8 clear satrf. ? step 9 go to step 4. error detection the sawcol bit in the spiac1 register is provided to indicate errors during data transfer. the bit is set by the spia serial interface but must be cleared by the application program. this bit indicates a data collision has occurred which happens if a write to the spiad register takes place during a data transfer operation and will prevent the write operation from continuing.
rev. 1.10 184 de?e??e? 01? ?01? rev. 1.10 185 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom lcd driver for large volume applications, which incorporate an lcd in their design, the use of a custom display rather than a more expensive character based display reduces costs signifcantly. however, the corresponding com and seg signals required, which vary in both amplitude and time, to drive such a custom display require many special considerations for proper lcd operation to occur. this series of devices all contain an lcd driver function, which with their internal lcd signal generating circuitry and various options, will automatically generate these time and amplitude varying signals to provide a means of direct driving and easy interfacing to a range of custom lcds. all devices include a wide range of options to enable lcd displays of various types to be driven. the table shows the range of options available across the device range. device duty driver output bias bias type wave type ht?7f?0a 1/4 5?x4 1/3 c o? r a o ? b ht?7f70a note: for 48 lqfp package type, only the r type bias cab be used. lcd selections charge pump va=v1=3/2*v in vb=plcd=v in vc=v2=1/2*v in 0.1 f 0.1 f 0.1 f c1 c2 v1 v2 vmax plcd v in power supply from pin plcd note: the pin vmax must be connected to the maximum voltage in this device to prevent from the pad leakage. c type bias power supply confguration C 1/3 bias
rev. 1.10 18? de?e??e? 01? ?01? rev. 1.10 187 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom qt: quick charging time determined by qct [2:0] qt comn note: when the r type lcd is disabl ed, the dc path will be switched. plcd v a control v a quick charging control qct v b v c r type bias confguration C 1/3 bias lcd memory an area of data memory is especially reserved for use for the lcd display data. this data area is known as the lcd memory. any data written here will be automatically read by the internal display driver circuits, which will in turn automatically generate the necessary lcd driving signals. therefore any data written into this memory will be immediately refected into the actual display connected to the microcontroller. as the lcd memory addresses overlap those of the general purpose data memory, it s stored in its own independent sector 1 area. the data memory sector to be used is chosen by using the memory pointer high byte register, which is a special function register in the data memory, with the name, mp1h or mp2h. to access the lcd memory therefore requires frst that sector 1 is selected by writing a value of 01h to the mp1h or mp2h register. after this, the memory can then be accessed by using indirect addressing through the use of memory pointer low byte mp1l or mp2l. with sector 1 selected, then using mp1l or mp2l to read or write to the memory area, starting with address 80h for all the devices, will result in operations to the lcd memory. directly addressing the display memory is carried out using the corresponding extended instructions. the accompanying lcd memory map diagrams shows how the internal lcd memory is mapped to the segments and commons of the display for the devices. lcd memory maps for devices with smaller memory capacities can be extrapolated from these diagrams.
rev. 1.10 18? de?e??e? 01? ?01? rev. 1.10 187 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom 80h 81h 8?h b5h b?h com3 com? com1 com0 seg55 seg54 seg53 seg? seg1 seg0 ?it 7 ?it ? ?it 5 ?it 4 ?it 3 ?it ? ?it 1 ?it 0 b7h : unused? ?ead as 0. lcd memory map lcd clock source the lcd clock source is derived from the internal clock signal, f sub . the f sub internal clock is supplied by either the lirc or lxt oscillator, the choice of which is determined by a confguration option. for proper lcd operation, the lcd clock source, f sub , will be internally divided by 8 using the lcd internal divider circuit to generate an ideal lcd clock source frequency of 4 khz. lcd registers there are control registers, named as lcdc0 and lcdc1, in the data memory used to control the various setup features of the lcd driver. various bits in these registers control functions such as lcd wave type, bias type, bias resistor selection as well as overall lcd enable and disable control. the lcden bit in the lcdc0 register, which provides the overall lcd enable/disable function, will only be effective when the device is in the noamrl, slow or idle mode. if the device is in the sleep mode then the display will always be disabled. bits, rsel2 ~ rsel0, in the lcdc0 register are used to select the internal bias resistors to supply the lcd panel with the proper r type bias current. a choice to best match the lcd panel used in the application can be selected also to minimise bias current. the type bit in the lcdc0 register is used to select whether type a or type b lcd control signals are used. the rct bit in the same register is used to select whether r type or c type lcd bias is used. the plcd3~plcd0 bits in the lcdc1 register are used to select the v a voltage for r type bias circuitry. the qct2~qct0 bits in the same register are used to determine the quick charge time period. register name bit 7 6 5 4 3 2 1 0 lcdc0 type rct rsel? rsel1 rsel0 lcden lcdc1 qct? qct1 qct0 plcd3 plcd? plcd1 plcd0 lcd registers list
rev. 1.10 188 de?e??e? 01? ?01? rev. 1.10 189 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom lcdc0 register bit 7 6 5 4 3 2 1 0 na?e type rct rsel? rsel1 rsel0 lcden r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 type : lcd waveform type selection 0: type a 1: type b bit 6 rct : lcd bias type selection 0: r type bias 1: c type bias bit 5~4 unimplemented, read as 0 bit 3~1 rsel2~rsel0 : r type bias resistor selection 000: 1170 k 001: 225 k 010: 60 k 011: quick charge mode C switched between 60 k and 1170 k 1xx: quick charge mode C switched between 60 k and 225 k bit 0 lcden : lcd function enable control 0: disable 1: enable in the normal, slow or idle mode, the lcd on/off function can be controlled by this bit. however, in the sleep mode, the lcd function is always switched off. lcdc1 register bit 7 6 5 4 3 2 1 0 na?e qct? qct1 qct0 plcd3 plcd? plcd1 plcd0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7~5 qct2~qct0 : r type bias quick charge time period selection 000: 1 t 001: 2 t 010: 3 t 011: 4 t 100: 5 t 101: 6 t 110: 7 t 111: 8 t note that the t is the period of the lcd clock source, f bit 4 unimplemented, read as 0 bit 3~0 plcd3~plcd0 : r type bias v a voltage selection 0000: 8/16 v plcd 0001: 9/16 v plcd 0010: 10/16 v plcd 0011: 11/16 v plcd 0100: 12/16 v plcd 0101: 13/16 v plcd 0110: 14/16 v plcd 0111: 15/16 v plcd 1xxx: v plcd
rev. 1.10 188 de?e??e? 01? ?01? rev. 1.10 189 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom lcd voltage source biasing the time and amplitude varying signals generated by the lcd driver function require the generation of several voltage levels for their operation. the device can have either r type or c type biasing selected via a software control bit named rct. selecting the c type biasing will enable an internal charge pump circuitry. r type biasing for r type biasing an external lcd voltage source must be supplied on pin plcd to generate the internal biasing voltages. this could be the microcontroller power supply or some other voltage source. for the r type 1/3 bias scheme, four voltage levels v ss , v a , v b and v c are utilised. the voltage v a is selected by the plcd 3~plcd0 bits to be equal to a specifc ratio of v plcd varying from 8/16 v plcd to v plcd . the voltage v b is equal to v plcd 2/3 while the voltage v c is equal to v plcd 1/3. different values of internal bias resistors can be selected using the rsel2~resel0 bits in the lcdc0 register. this along with the voltage on pin plcd will determine the bias current. the connection to the vmax pin depends upon the voltage that is applied to the plcd pin. if the v dd voltage is greater than or equal to the voltage applied to the plcd pin then the vmax pin should be connected to vdd. note that for r type biasing the voltage on the plcd pin should not be greater than the vdd pin voltage. note that no external capacitors or resistors are required to be connected if r type biasing is used. condition vmax connection v dd v plcd conne?t vmax to vdd v dd < v plcd fo??idden ?ondition r type bias vmax pin connection c type biasing for c type biasing an external lcd voltage source is supplied on the plcd pin to generate the internal biasing voltages. the c type biasing scheme uses an internal charge pump circuit can generate voltages higher than what is supplied on the plcd or v2 pin. this feature is useful in applications where the microcontroller supply voltage is less than the supply voltage required by the lcd. an additional charge pump capacitor must also be connected between pins c1 and c2 to generate the necessary voltage levels. for the c type 1/3 bias scheme, four voltage levels v ss , v a , v b and v c are utilised. the voltage v a is generated internally and has a value of v plcd 3/2. the voltage v b will have a value equal to v plcd and v c will have a value equal to v plcd 1/2. the connection to the vmax pin depends upon the bias and the voltage that is applied to plcd. it is extremely important to ensure that these charge pump generated internal voltages do not exceed the maximum v dd voltage of 5.5v. condition vmax connection v dd > v plcd 1.5 conne?t vmax to vdd othe?wise conne?t vmax to v1 c type bias vmax pin connection
rev. 1.10 190 de?e??e? 01? ?01? rev. 1.10 191 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom lcd driver output the number of com and seg outputs supplied by the lcd driver, as well as its biasing and wave type selections, are dependent upon how the lcd control bits are programmed. the bias type, whether c or r type is also selected by a software control bit. the nature of liquid crystal displays require that only ac voltages can be applied to their pixels as the application of dc voltages to lcd pixels may cause permanent damage. for this reason the relative contrast of an lcd display is controlled by the actual rms voltage applied to each pixel, which is equal to the rms value of the voltage on the com pin minus the voltage applied to the seg pin. this differential rms voltage must be greater than the lcd saturation voltage for the pixel to be on and less than the threshold voltage for the pixel to be off. the requirement to limit the dc voltage to zero and to control as many pixels as possible with a minimum number of connections requires that both a time and amplitude signal is generated and applied to the application lcd. these time and amplitude varying signals are automatically generated by the lcd driver circuits in the microcontroller. what is known as the duty determines the number of common lines used, which are also known as backplanes or coms. the duty, which has a value of 1/4 and which equates to a com number of 4, therefore defnes the number of time divisions within each lcd signal frame. two types of signal generation are also provided, known as type a and type b, the required type is selected via the type bit in the lcdc0 register. type b offers lower frequency signals, however, lower frequencies may introduce fickering and infuence display clarity.
rev. 1.10 190 de?e??e? 01? ?01? rev. 1.10 191 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom lcd display off mode com0 ~ com3 va all sengment outputs normal operation mode com0 com1 com2 com3 all segments are off com0 side segments are on all sengments are on (other combinations are omitted) vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss 1 frame com1 side segments are on com2 side segments are on com3 side segments are on com0,1 side segments are on com0,2 side segments are on com0,3 side segments are on lcd driver output C type a C 1/4 duty, 1/3 bias
rev. 1.10 19? de?e??e? 01? ?01? rev. 1.10 193 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom lcd display off mode com0 ~ com3 va all sengment outputs normal operation mode com0 com1 com2 com3 all segments are off com0 side segments are on all sengments are on (other combinations are omitted) vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss 1 frame com1 side segments are on com2 side segments are on com3 side segments are on com0,1 side segments are on com0,2 side segments are on com0,3 side segments are on lcd driver output C type b C 1/4 duty, 1/3 bias note: for 1/3 r type bias, v a =v plcd , v =v plcd 2/3, v c =v plcd 1/3. for 1/3 c type bias, v a =v plcd 3/2, v =v plcd , v c =v plcd 1/2.
rev. 1.10 19? de?e??e? 01? ?01? rev. 1.10 193 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom programming considerations certain precautions must be taken when programming the lcd. one of these is to ensure that the lcd memory is properly initialised after the microcontroller is powered on. like the general purpose data memory, the contents of the lcd memory are in an unknown condition after power-on. as the contents of the lcd memory will be mapped into the actual display, it is important to initialise this memory area into a known condition soon after applying power to obtain a proper display pattern. consideration must also be given to the capacitive load of the actual lcd used in the application. as the load presented to the microcontroller by lcd pixels can be generally modeled as mainly capacitive in nature, it is important that this is not excessive, a point that is particularly true in the case of the com lines which may be connected to many lcd pixels. the accompanying diagram depicts the equivalent circuit of the lcd. one additional consideration that must be taken into account is what happens when the microcontroller enters the idle or slow mode. the lcden control bit in the lcdc0 register permits the display to be powered off to reduce power consumption. if this bit is zero, the driving signals to the display will cease, producing a blank display pattern but reducing any power consumption associated with the lcd. after power-on, note that as the lcden bit will be cleared to zero, the display function will be disabled. lcd panel euqivalent circuit
rev. 1.10 194 de?e??e? 01? ?01? rev. 1.10 195 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int0 ~ int3 pins, while the internal interrupts are generated by various internal functions such as the tms, time base, lvd, eeprom, sim and the a/d converter, etc. interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the frst is the intc0~intc3 registers which setup the primary interrupts, the second is the mfi0~mfi4 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual interrupts as well as interrupt fags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes glo?al emi intn pins intne intnf n = 0 ~ 3 ?o?pa?ato? cpne cpnf n = 0 ~ 1 a/d conve?te? ade adf ti ?e base tbne tbnf n = 0 ~ 1 multi-fun?tion mfne mfnf n = 0 ~ 4 lvd lve lvf eeprom w?ite ope?ation dee def sim sime simf pe?iphe?al inte??upt pint xpe xpf spia spiae spiaf ctm ctmnpe ctmnpf n = 0 ~ 1 ctmnae ctmnaf stm stmnpe stmnpf n = 0 ~ ? stmnae stmnaf etm etmpe etmpf etmae etmaf etmbe etmbf interrupt register bit naming conventions
rev. 1.10 194 de?e??e? 01? ?01? rev. 1.10 195 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom register name bit 7 6 5 4 3 2 1 0 integ int3s1 int3s0 int?s1 int?s0 int1s1 int1s0 int0s1 int0s0 intc0 cp0f int1f int0f cp0e int1e int0e emi intc1 adf mf1f mf0f cp1f ade mf1e mf0e cp1e intc? mf3f tb1f tb0f mf?f mf3e tb1e tb0e mf?e intc3 mf4f int3f int?f mf4e int3e int?e mfi0 stm0af stm0pf ctm0af ctm0pf stm0ae stm0pe ctm0ae ctm0pe mfi1 etmbf etmaf etmpf etmbe etmae etmpe mfi? simf xpf ctm1af ctm1pf sime xpe ctm1ae ctm1pe mfi3 spiaf def lvf spiae dee lve mfi4 stm?af stm?pf stm1af stm1pf stm?ae stm?pe stm1ae stm1pe interrupt registers list integ register bit 7 6 5 4 3 2 1 0 na?e int3s1 int3s0 int?s1 int?s0 int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 int3s1~int3s0 : interrupt edge control for int3 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 5~4 int2s1~int2s0 : interrupt edge control for int2 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 3~2 int1s1~int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1~int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges
rev. 1.10 19? de?e??e? 01? ?01? rev. 1.10 197 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom intc0 register bit 7 6 5 4 3 2 1 0 na?e cp0f int1f int0f cp0e int1e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 cp0f : comparator 0 interrupt request fag 0: no request 1: interrupt request bit 5 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 3 cp0e : comparator 0 interrupt control 0: disable 1: enable bit 2 int1e : int1 interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.10 19? de?e??e? 01? ?01? rev. 1.10 197 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom intc1 register bit 7 6 5 4 3 2 1 0 na?e adf mf1f mf0f cp1f ade mf1e mf0e cp1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 adf : a/d converter interrupt request fag 0: no request 1: interrupt request bit 6 mf1f : multi-function 1 interrupt request fag 0: no request 1: interrupt request bit 5 mf0f : multi-function 0 interrupt request fag 0: no request 1: interrupt request bit 4 cp1f : comparator 1 interrupt request fag 0: no request 1: interrupt request bit 3 ade : a/d converter interrupt control 0: disable 1: enable bit 2 mf1e : multi-function 1 interrupt control 0: disable 1: enable bit 1 mf0e : multi-function 0 interrupt control 0: disable 1: enable bit 0 cp1e : comparator 1 interrupt control 0: disable 1: enable
rev. 1.10 198 de?e??e? 01? ?01? rev. 1.10 199 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom intc2 register bit 7 6 5 4 3 2 1 0 na?e mf3f tb1f tb0f mf?f mf3e tb1e tb0e mf?e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf3f : multi-function 3 interrupt request fag 0: no request 1: interrupt request bit 6 tb1f : time base 1 interrupt request fag 0: no request 1: interrupt request bit 5 tb0f : time base 0 interrupt request fag 0: no request 1: interrupt request bit 4 mf2f : multi-function 2 interrupt request fag 0: no request 1: interrupt request bit 3 mf3e : multi-function 3 interrupt control 0: disable 1: enable bit 2 tb1e : time base 1 interrupt control 0: disable 1: enable bit 1 tb0e : time base 0 interrupt control 0: disable 1: enable bit 0 mf2e : multi-function 2 interrupt control 0: disable 1: enable
rev. 1.10 198 de?e??e? 01? ?01? rev. 1.10 199 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom intc3 register bit 7 6 5 4 3 2 1 0 na?e mf4f int3f int?f mf4e int3e int?e r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 mf4f : multi-function 4 interrupt request fag 0: no request 1: interrupt request bit 5 int3f : int3 interrupt request fag 0: no request 1: interrupt request bit 4 int2f : int2 interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 mf4e : multi-function 4 interrupt control 0: disable 1: enable bit 1 int3e : int3 interrupt control 0: disable 1: enable bit 0 int2e : int2 interrupt control 0: disable 1: enable
rev. 1.10 ?00 de?e??e? 01? ?01? rev. 1.10 ?01 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom mfi0 register bit 7 6 5 4 3 2 1 0 na?e stm0af stm0pf ctm0af ctm0pf stm0ae stm0pe ctm0ae ctm0pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 stm0af : stm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 stm0pf : stm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 ctm0af : ctm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 ctm0pf : ctm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 stm0ae : stm0 comparator a match interrupt control 0: disable 1: enable bit 2 stm0pe : stm0 comparator p match interrupt control 0: disable 1: enable bit 1 ctm0ae : ctm0 comparator a match interrupt control 0: disable 1: enable bit 0 ctm0pe : ctm0 comparator p match interrupt control 0: disable 1: enable
rev. 1.10 ?00 de?e??e? 01? ?01? rev. 1.10 ?01 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom mfi1 register bit 7 6 5 4 3 2 1 0 na?e etmbf etmaf etmpf etmbe etmae etmpe r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 etmbf : etm comparator b match interrupt request fag 0: no request 1: interrupt request bit 5 etmaf : etm comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 etmpf : etm comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 etmae : etm comparator b match interrupt control 0: disable 1: enable bit 1 etmae : etm comparator a match interrupt control 0: disable 1: enable bit 0 etmpe : etm comparator p match interrupt control 0: disable 1: enable
rev. 1.10 ?0? de?e??e? 01? ?01? rev. 1.10 ?03 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom mfi2 register bit 7 6 5 4 3 2 1 0 na?e simf xpf ctm1af ctm1pf sime xpe ctm1ae ctm1pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 simf : sim interrupt request fag 0: no request 1: interrupt request bit 6 xpf : external peripheral interrupt request fag 0: no request 1: interrupt request bit 5 ctm1af : ctm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 ctm1pf : ctm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 sime : sim interrupt control 0: disable 1: enable bit 2 xpe : external peripheral interrupt control 0: disable 1: enable bit 1 ctm1ae : ctm1 comparator a match interrupt control 0: disable 1: enable bit 0 ctm1pe : ctm1 comparator p match interrupt control 0: disable 1: enable
rev. 1.10 ?0? de?e??e? 01? ?01? rev. 1.10 ?03 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom mfi3 register bit 7 6 5 4 3 2 1 0 na?e spiaf def lvf spiae dee lve r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 spiaf : spia interrupt request fag 0: no request 1: interrupt request bit 5 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 4 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 spiae : spia interrupt control 0: disable 1: enable bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 lve : lvd interrupt control 0: disable 1: enable
rev. 1.10 ?04 de?e??e? 01? ?01? rev. 1.10 ?05 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom mfi4 register bit 7 6 5 4 3 2 1 0 na?e stm?af stm?pf stm1af stm1pf stm?ae stm?pe stm1ae stm1pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 stm2af : stm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 stm2pf : stm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 stm1af : stm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 stm1pf : stm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 stm2ae : stm2 comparator a match interrupt control 0: disable 1: enable bit 2 stm2pe : stm2 comparator p match interrupt control 0: disable 1: enable bit 1 stm1ae : stm1 comparator a match interrupt control 0: disable 1: enable bit 0 stm1pe : stm1 comparator p match interrupt control 0: disable 1: enable
rev. 1.10 ?04 de?e??e? 01? ?01? rev. 1.10 ?05 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom interrupt operation when the conditions for an interrupt event occur, such as a tm comparator p or comparator a or a/d conversion completion, etc, the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp instruction which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti instruction, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request fags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.10 ?0? de?e??e? 01? ?01? rev. 1.10 ?07 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom int0 pin int1 pin int0f int1f int0e int1e emi 04h emi 08h m. funct. 0 mf0f mf0e emi 0ch emi 10h emi 14h time base 0 tb0f tb0e emi 18h lvd lvf lve emi 1ch interrupt name request flags enable bits master enable vector emi auto disabled in isr priority high stm0 p stm0pf stm0pe stm0 a stm0af stm0ae m. funct. 1 mf1f mf1e ctm0 p ctm0pf ctm0pe ctm0 a ctm0af ctm0ae interrupts contained within multi-function interrupts xxe enable bits xxf request flag, auto reset in isr legend xxf request flag, no auto reset in isr emi 20h a/d adf ade emi 24h m. funct. 2 mf2f mf2e time base 1 tb1f tb1e emi 28h emi 2ch m. funct. 3 mf3f mf3e etm p etmpf etmpe etm a etmaf etmae emi 30h emi 34h eeprom def dee sim simf sime spia spiaf spiae low emi 38h comparator 0 cp0f cp0e comparator 1 cp1f cp1e int2 pin int2f int2e int3 pin int3f int3e m. funct. 4 mf4f mf4e etm b etmbf etmbe xpf xpe pint pin ctm1 p ctm1pf ctm1pe ctm1 a ctm1af ctm1ae stm1 p stm1pf stm1pe stm1 a stm1af stm1ae stm2 p stm2pf stm2pe stm2 a stm2af stm2ae interrupt scheme
rev. 1.10 ?0? de?e??e? 01? ?01? rev. 1.10 ?07 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom external interrupt the external interrupts are controlled by signal transitions on the pins int0~int3. an external interrupt request will take place when the external interrupt request fags, int0f~int3f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e~int3e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register as well as the relevant pin-shared function selection bits. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request fags, int0f~int3f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. comparator interrupt the comparator interrupts are controlled by the internal comparators. a comparator interrupt request will take place when the comparator interrupt request flags, cp0f or cp1f, are set, a situation that will occur when the comparator output changes state. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and comparator interrupt enable bits, cp0e and cp1e, must frst be set. when the interrupt is enabled, the stack is not full and the voice play timer time-out occurs, a subroutine call to the comparator interrupt vector will take place. when the interrupt is serviced, the comparator interrupt request fag will be automatically reset and the emi bit will also be automatically cleared to disable other interrupts. a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf, is set, which occurs when the a/d conversion process fnishes. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector, will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.10 ?08 de?e??e? 01? ?01? rev. 1.10 ?09 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom time base interrupt the function of the time base interrupt is to provide regular time signal in the form of an internal interrupt. it is controlled by the overflow signal from its internal timer. when this happens its interrupt request fag, tbnf, will be set. to allow the program to branch to its respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bit, tbne, must frst be set. when the interrupt is enabled, the stack is not full and the time base overfows, a subroutine call to its respective vector location will take place. when the interrupt is serviced, the interrupt request flag, tbnf, will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the time base interrupt is to provide an interrupt signal at fxed time periods. its clock source, f tp , originates from the internal clock source f sys , f sys /4, f sub or f h and then passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tb0c and tb1c registers to obtain longer interrupt periods whose value ranges. the clock source which in turn controls the time base interrupt period is selected using the clks01 and clks00 bits in the psc0 register. m u x f sys /4 f sys f tbc prescaler clks[0:0] f tp f tp /2 8 ~ f tp /2 15 m u x m u x tb0[2:0] tb1[2:0] time base 0 interrupt time base 1 interrupt tb0on tb1on f h time base interrupts psc0 register bit 7 6 5 4 3 2 1 0 na?e clks01 clks00 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 : time base prescaler clock source selection 00: f sys 01: f sys /4 10: f tbc 11: f h
rev. 1.10 ?08 de?e??e? 01? ?01? rev. 1.10 ?09 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom tb0c register bit 7 6 5 4 3 2 1 0 na?e tb0on tb0? tb01 tb00 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 tb0on : time base 0 enable control 0: disable 1: enable bit 6~3 unimplemented, read as 0 bit 2~0 tb02~tb00 : time base 0 time-out period selection 000: f tp /2 8 001: f tp /2 9 010: f tp /2 10 011: f tp /2 11 100: f tp /2 12 101: f tp /2 13 110: f tp /2 14 111: f tp /2 15 tb1c register bit 7 6 5 4 3 2 1 0 na?e tb1on tb1? tb11 tb10 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 tb1on : time base 1 enable control 0: disable 1: enable bit 6~3 unimplemented, read as 0 bit 2~0 tb12~tb10 : time base 1 time-out period selection 000: f tp /2 8 001: f tp /2 9 010: f tp /2 10 011: f tp /2 11 100: f tp /2 12 101: f tp /2 13 110: f tp /2 14 111: f tp /2 15
rev. 1.10 ?10 de?e??e? 01? ?01? rev. 1.10 ? 11 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom multi-function interrupt within the device there are up to five multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts, lvd interrupt, eeprom write operation interrupt, sim, external peripheral interrupt and spia interface interrupts. a multi-function interrupt request will take place when any of the multi-function interrupt request flags mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request fag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt request flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the multi-function interrupts will not be automatically reset and must be manually reset by the application program. serial interface module interrupt the serial interface module interrupt, also known as the sim interrupt, is contained within the multi-function interrupt. a sim interrupt request will take place when the sim interrupt request fag, simf, is set, which occurs when a byte of data has been received or transmitted by the sim interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, the serial interface interrupt enable bit, sime, and muti-function interrupt enable bit must frst be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the sim interface, a subroutine call to the respective multi-function interrupt vector, will take place. when the serial interface interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the simf fag will not be automatically cleared, it has to be cleared by the application program. spia interface interrupt the spia interface module interrupt is contained within the multi-function interrupt. a spia interrupt request will take place when the spia interrupt request fag, spiaf, is set, which occurs when a byte of data has been received or transmitted by the spia interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, the serial interface interrupt enable bit, spiae, and muti-function interrupt enable bit must frst be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the spia interface, a subroutine call to the respective multi-function interrupt vector, will take place. when the spia interface interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the spiaf fag will not be automatically cleared, it has to be cleared by the application program.
rev. 1.10 ?10 de?e??e? 01? ?01? rev. 1.10 ? 11 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom external peripheral interrupt the external peripheral interrupt operates in a similar way to the external interrupt and is contained within the multi-function interrupt. a peripheral interrupt request will take place when the external peripheral interrupt request fag, xpf, is set, which occurs when a negative edge transition appears on the pint pin. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, external peripheral interrupt enable bit, xpe, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a negative transition appears on the external peripheral interrupt pin, a subroutine call to the respective multi-function interrupt, will take place. when the external peripheral interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the xpf fag will not be automatically cleared, it has to be cleared by the application program. the external peripheral interrupt pin is pin-shared with several other pins with different functions. it must therefore be properly confgured to enable it to operate as an external peripheral interrupt pin. lvd interrupt the low voltage detector interrupt is contained within the multi-function interrupt. an lvd interrupt request will take place when the lvd interrupt request flag, lvf, is set, which occurs when the low voltage detector function detects a low power supply voltage. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low voltage interrupt enable bit, lve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the multi-function interrupt vector, will take place. when the low voltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts. however, only the multi-function interrupt request fag will be also automatically cleared. as the lvf fag will not be automatically cleared, it has to be cleared by the application program. eeprom interrupt the eeprom write interrupt is contained within the multi-function interrupt. an eeprom write interrupt request will take place when the eeprom write interrupt request fag, def, is set, which occurs when an eeprom write cycle ends. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, eeprom write interrupt enable bit, dee, and associated multi-function interrupt enable bit must first be set. when the interrupt is enabled, the stack is not full and an eeprom write cycle ends, a subroutine call to the respective multi-function interrupt vector will take place. when the eeprom write interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts. however, only the multi-function interrupt request flag will be automatically cleared. as the def flag will not be automatically cleared, it has to be cleared by the application program.
rev. 1.10 ?1? de?e??e? 01? ?01? rev. 1.10 ?13 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom tm interrupt the compact, standard and enhanced tms have two or three interrupts, each comes from the comparator a match situation, comparator b match situation or comparator p match situation respectively. all of the tm interrupts are contained within the multi-function interrupts. for all of the tm types there are two interrupt request fags and two enable control bits. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p, comparator a or comparator b match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts. however, only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. interrupt wake-up function each of the interrupt functions has the capability of waking up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though these devices are in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in the sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine.
rev. 1.10 ?1? de?e??e? 01? ?01? rev. 1.10 ?13 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. low voltage detector C lvd each device has a low voltage detector function, also known as lvd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vlvd0, are used to select one of eight fxed voltages below which a low voltage condition will be determined. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 na?e lvdo lvden vbgen vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 : lvd output fag 0: no low voltage detected 1: low voltage detected bit 4 : low voltage detector enable control 0: disable 1: enable bit 3 : bandgap buffer control 0: disable 1: enable note that the bandgap circuit is enabled when the lvd or lvr function is enabled or when the vbgen bit is set to 1. bit 2~0 : lvd voltage selection 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.10 ?14 de?e??e? 01? ?01? rev. 1.10 ?15 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed voltage level stored in the lvdc register. this has a range of between 2.0v and 4.0v. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. the low voltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low voltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. when the device is powered down the low voltage detector will remain active if the lvden bit is high. in this case, the lvf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode.
rev. 1.10 ?14 de?e??e? 01? ?01? rev. 1.10 ?15 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom confguration options confguration options refer to certain options within the mcu that are programmed into the devices during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the devices using the hardware programming tools, once they are selected they cannot be changed later using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options 1 high speed syste? os?illato? sele?tion C f h hxt o ? hirc ? low speed syste? os?illato? sele?tion C f sub lxt o ? lirc 3 high speed inte?nal rc os?illato? f?equen?y sele?tion C f hirc 4mhz? 8mhz o? 1?mhz application circuits vdd pc0/res vss pb0/xt2 pb1/xt1 pb2/osc1 pb3/osc2 osc circuit osc circuit lcd panel com[3:0] seg[55:0] plcd vmax 100k ? 0.1 f 0.1 f 0.1 f 0.1 f c1 c2 v1 v2 0.1 f pa0~pa7 pb0~pb6 pc0~pc7 pd0~pd7 pe0~pe7 pf0~pf7 v dd
rev. 1.10 ?1? de?e??e? 01? ?01? rev. 1.10 ?17 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontroller, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of several kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions such as inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.10 ?1? de?e??e? 01? ?01? rev. 1.10 ?17 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.10 ?18 de?e??e? 01? ?01? rev. 1.10 ?19 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom instruction set summary the instructions related to the data memory access in the following table can be used when the desired data memory is located in data memory sector 0. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a?[?] add data me?o? y to acc 1 z? c? ac? ov ? sc addm a?[?] add acc to data me ?o?y 1 note z? c? ac? ov ? sc add a?x add i?? ediate data to acc 1 z? c? ac? ov ? sc adc a?[?] add data me?o? y to acc with ca??y 1 z? c? ac? ov ? sc adcm a?[?] add acc to data ?e?o?y with ca??y 1 note z? c? ac? ov ? sc sub a?x su?t?a?t i??ediate data f?o? the acc 1 z? c? ac? ov ? sc? cz sub a?[?] su?t?a?t data me?o?y f?o? acc 1 z? c? ac? ov ? sc? cz subm a?[?] su?t?a?t data me?o?y f?o? acc with ?esult in data me?o?y 1 note z? c? ac? ov ? sc? cz sbc a?x su?t?a?t i??ediate data f?o? acc with ca??y 1 z? c? ac? ov ? sc? cz sbc a?[?] su?t?a?t data me?o?y f?o? acc with ca??y 1 z? c? ac? ov ? sc? cz sbcm a?[?] su?t?a?t data me?o?y f?o? acc with ca??y ? ?esult in data me?o?y 1 note z? c? ac? ov ? sc? cz daa [ ?] de?i? al adjust acc fo? addition with ?esult in data me?o?y 1 note c logic operation and a?[?] logi? al and data me?o? y to acc 1 z or a?[?] logi?al or data me?o? y to acc 1 z xor a?[?] logi?al xor data me?o? y to acc 1 z andm a?[?] logi? al and acc to data me?o?y 1 note z orm a?[?] logi? al or acc to data me?o?y 1 note z xorm a?[?] logi? al xor acc to data me?o?y 1 note z and a?x logi? al and i?? ediate data to acc 1 z or a?x logi?al or i?? ediate data to acc 1 z xor a?x logi?al xor i?? ediate data to acc 1 z cpl [ ?] co?ple?ent data me?o?y 1 note z cpla [ ?] co?ple?ent data me?o?y with ? esult in acc 1 z increment & decrement inca [ ?] in??e?ent data me?o?y with ? esult in acc 1 z inc [?] in??e?ent data me?o?y 1 note z deca [ ?] de??e?ent data me?o?y with ? esult in acc 1 z dec [?] de??e?ent data me?o?y 1 note z rotate rra [ ?] rotate data me?o?y ?ight with ? esult in acc 1 none rr [?] rotate data me?o?y ?ight 1 note none rrca [ ?] rotate data me?o?y ?ight th?ough ca??y with ? esult in acc 1 c rrc [?] rotate data me?o?y ?ight th?ough ca??y 1 note c rla [ ?] rotate data me?o?y left with ? esult in acc 1 none rl [ ?] rotate data me?o?y left 1 note none rlca [ ?] rotate data me?o?y left th?ough ca??y with ? esult in acc 1 c rlc [?] rotate data me?o?y left th?ough ca??y 1 note c
rev. 1.10 ?18 de?e??e? 01? ?01? rev. 1.10 ?19 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom mnemonic description cycles flag affected data move mov a ?[?] move data me?o? y to acc 1 none mov [?]?a move acc to data me ?o?y 1 note none mov a ?x move i?? ediate data to acc 1 none bit operation clr [?].i clea? ?it of data me?o?y 1 note none set [ ?].i set ?it of data me?o?y 1 note none branch operation jmp add ? ju?p un?onditionally ? none sz [?] skip if data me?o?y is ze?o 1 note none sza [ ?] skip if data me?o?y is ze?o with data ?ove? ent to acc 1 note none sz [?].i skip if ?it i of data me?o?y is ze?o 1 note none snz [?] skip if data me?o?y is not ze?o 1 note none snz [?].i skip if ?it i of data me?o?y is not ze?o 1 note none siz [?] skip if in??e?ent data me?o?y is ze?o 1 note none sdz [?] skip if de??e?ent data me?o?y is ze?o 1 note none siza [ ?] skip if in??e?ent data me?o?y is ze?o with ? esult in acc 1 note none sdza [ ?] skip if de??e?ent data me?o?y is ze?o with ? esult in acc 1 note none call add ? su??outine ?all ? none ret retu?n f?o? su??outine ? none ret a ?x retu?n f?o? su??outine and load i?? ediate data to acc ? none reti retu?n f?o? inte??upt ? none table read operation tabrd [ ?] read ta? le to tblh and data me?o?y ? note none tabrdl [ ?] read ta? le (last page) to tblh and data me?o?y ? note none miscellaneous nop no ope?ation 1 none clr [?] clea? data me?o?y 1 note none set [ ?] set data me?o?y 1 note none clr wdt clea? wat? hdog ti?e? 1 to ? pdf swap [ ?] swap ni??les of data me?o?y 1 note none swapa [ ?] swap ni??les of data me?o?y with ? esult in acc 1 none halt ente? powe? down ?ode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt instruction the to and pdf fags may be affected by the execution status. the to and pdf fags are cleared after the clr wdt instructions is executed. otherwise the to and pdf fags remain unchanged.
rev. 1.10 ??0 de?e??e? 01? ?01? rev. 1.10 ??1 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom extended instruction set the extended instructions are used to support the full range address access for the data memory. when the accessed data memory is located in any data memory sections except sector 0, the extended instruction can be used to access the data memory instead of using the indirect addressing access to improve the cpu frmware performance. mnemonic description cycles flag affected arithmetic ladd a?[?] add data me?o? y to acc ? z? c? ac? ov ? sc laddm a?[?] add acc to data me ?o?y ? note z? c? ac? ov ? sc ladc a?[?] add data me?o? y to acc with ca??y ? z? c? ac? ov ? sc ladcm a?[?] add acc to data ?e?o?y with ca??y ? note z? c? ac? ov ? sc lsub a?[?] su?t?a?t data me?o?y f?o? acc ? z? c? ac? ov ? sc? cz lsubm a?[?] su?t?a?t data me?o?y f?o? acc with ?esult in data me?o?y ? note z? c? ac? ov ? sc? cz lsbc a?[?] su?t?a?t data me?o?y f?o? acc with ca??y ? z? c? ac? ov ? sc? cz lsbcm a?[?] su?t?a?t data me?o?y f?o? acc with ca??y ? ?esult in data me?o?y ? note z? c? ac? ov ? sc? cz ldaa [ ?] de?i? al adjust acc fo? addition with ?esult in data me?o?y ? note c logic operation land a?[?] logi? al and data me?o? y to acc ? z lor a?[?] logi?al or data me?o? y to acc ? z lxor a?[?] logi?al xor data me?o? y to acc ? z landm a?[?] logi? al and acc to data me?o?y ? note z lorm a?[?] logi? al or acc to data me?o?y ? note z lxorm a?[?] logi? al xor acc to data me?o?y ? note z lcpl [ ?] co?ple?ent data me?o?y ? note z lcpla [ ?] co?ple?ent data me?o?y with ? esult in acc ? z increment & decrement linca [ ?] in??e?ent data me?o?y with ? esult in acc ? z linc [?] in??e?ent data me?o?y ? note z ldeca [ ?] de??e?ent data me?o?y with ? esult in acc ? z ldec [?] de??e?ent data me?o?y ? note z rotate lrra [ ?] rotate data me?o?y ?ight with ? esult in acc ? none lrr [?] rotate data me?o?y ?ight ? note none lrrca [ ?] rotate data me?o?y ?ight th?ough ca??y with ? esult in acc ? c lrrc [?] rotate data me?o?y ?ight th?ough ca??y ? note c lrla [ ?] rotate data me?o?y left with ? esult in acc ? none lrl [ ?] rotate data me?o?y left ? note none lrlca [ ?] rotate data me?o?y left th?ough ca??y with ? esult in acc ? c lrlc [?] rotate data me?o?y left th?ough ca??y ? note c data move lmov a?[?] move data me?o? y to acc ? none lmov [?]?a move acc to data me ?o?y ? note none bit operation lclr [?].i clea? ?it of data me?o?y ? note none lset [ ?].i set ?it of data me?o?y ? note none
rev. 1.10 ??0 de?e??e? 01? ?01? rev. 1.10 ??1 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom mnemonic description cycles flag affected branch lsz [?] skip if data me?o?y is ze?o ? note none lsza [ ?] skip if data me?o?y is ze?o with data ?ove? ent to acc ? note none lsnz [?] skip if data me?o?y is not ze?o ? note none lsz [?].i skip if ?it i of data me?o?y is ze?o ? note none lsnz [?].i skip if ?it i of data me?o?y is not ze?o ? note none lsiz [?] skip if in??e?ent data me?o?y is ze?o ? note none lsdz [?] skip if de??e?ent data me?o?y is ze?o ? note none lsiza [ ?] skip if in??e?ent data me?o?y is ze?o with ? esult in acc ? note none lsdza [ ?] skip if de??e?ent data me?o?y is ze?o with ? esult in acc ? note none table read ltabrd [ ?] read ta? le to tblh and data me?o?y 3 note none ltabrdl [ ?] read ta? le (last page) to tblh and data me?o?y 3 note none miscellaneous lclr [?] clea? data me?o?y ? note none lset [ ?] set data me?o?y ? note none lswap [ ?] swap ni??les of data me?o?y ? note none lswapa [ ?] swap ni??les of data me?o?y with ? esult in acc ? none note: 1. for these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. any extended instruction which changes the contents of the pcl register will also require three cycles for execution.
rev. 1.10 ??? de?e??e? 01? ?01? rev. 1.10 ??3 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom instruction defnition adc a,[m] add data memory to acc with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the accumulator. operation acc acc + [m] + c affected fag(s) ov, z, ac, c, sc adcm a,[m] add acc to data memory with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. operation [m] acc + [m] + c affected fag(s) ov, z, ac, c, sc add a,[m] add data memory to acc description the contents of the specifed data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected fag(s) ov, z, ac, c, sc add a,x add immediate data to acc description the contents of the accumulator and the specifed immediate data are added. the result is stored in the accumulator. operation acc acc + x affected fag(s) ov, z, ac, c, sc addm a,[m] add acc to data memory description the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. operation [m] acc + [m] affected fag(s) ov, z, ac, c, sc and a,[m] logical and data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected fag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specifed immediate data perform a bit wise logical and operation. the result is stored in the accumulator. operation acc acc and x affected fag(s) z andm a,[m] logical and acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected fag(s) z
rev. 1.10 ??? de?e??e? 01? ?01? rev. 1.10 ??3 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom call addr subroutine call description unconditionally calls a subroutine at the specifed address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specifed address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruction. operation stack program counter + 1 program counter addr affected fag(s) none clr [m] clear data memory description each bit of the specifed data memory is cleared to 0. operation [m] 00h affected fag(s) none clr [m].i clear bit of data memory description bit i of the specifed data memory is cleared to 0. operation [m].i 0 affected fag(s) none clr wdt clear watchdog timer description the to, pdf fags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf cpl [m] complement data memory description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected fag(s) z cpla [m] complement data memory with result in acc description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected fag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd (binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and fag conditions. only the c fag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected fag(s) c
rev. 1.10 ??4 de?e??e? 01? ?01? rev. 1.10 ??5 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom dec [m] decrement data memory description data in the specifed data memory is decremented by 1. operation [m] [m] ? 1 affected fag(s) z deca [m] decrement data memory with result in acc description data in the specifed data memory is decremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] ? 1 affected fag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down fag pdf is set and the wdt time-out fag to is cleared. operation to 0 pdf 1 affected fag(s) to, pdf inc [m] increment data memory description data in the specifed data memory is incremented by 1. operation [m] [m] + 1 affected fag(s) z inca [m] increment data memory with result in acc description data in the specifed data memory is incremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] + 1 affected fag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specifed address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected fag(s) none mov a,[m] move data memory to acc description the contents of the specifed data memory are copied to the accumulator. operation acc [m] affected fag(s) none mov a,x move immediate data to acc description the immediate data specifed is loaded into the accumulator. operation acc x affected fag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specifed data memory. operation [m] acc affected fag(s) none
rev. 1.10 ??4 de?e??e? 01? ?01? rev. 1.10 ??5 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected fag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected fag(s) z or a,x logical or immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or x affected fag(s) z orm a,[m] logical or acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected fag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the restored address. operation program counter stack affected fag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specifed immediate data. program execution continues at the restored address. operation program counter stack acc x affected fag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by setting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected fag(s) none rl [m] rotate data memory left description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 [m].7 affected fag(s) none
rev. 1.10 ??? de?e??e? 01? ?01? rev. 1.10 ??7 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom rla [m] rotate data memory left with result in acc description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 [m].7 affected fag(s) none rlc [m] rotate data memory left through carry description the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 c c [m].7 affected fag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 c c [m].7 affected fag(s) c rr [m] rotate data memory right description the contents of the specifed data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 [m].0 affected fag(s) none rra [m] rotate data memory right with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 [m].0 affected fag(s) none rrc [m] rotate data memory right through carry description the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 c c [m].0 affected fag(s) c
rev. 1.10 ??? de?e??e? 01? ?01? rev. 1.10 ??7 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom rrca [m] rotate data memory right through carry with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 c c [m].0 affected fag(s) c sbc a,[m] subtract data memory from acc with carry description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] ? c affected fag(s) ov, z, ac, c, sc, cz sbc a, x subtract immediate data from acc with carry description the immediate data and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc - [m] - c affected fag(s) ov, z, ac, c, sc, cz sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] ? c affected fag(s) ov, z, ac, c, sc, cz sdz [m] skip if decrement data memory is 0 description the contents of the specifed data memory are frst decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] ? 1 skip if [m]=0 affected fag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specifed data memory are frst decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] ? 1 skip if acc=0 affected fag(s) none
rev. 1.10 ??8 de?e??e? 01? ?01? rev. 1.10 ??9 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom set [m] set data memory description each bit of the specifed data memory is set to 1. operation [m] ffh affected fag(s) none set [m].i set bit of data memory description bit i of the specifed data memory is set to 1. operation [m].i 1 affected fag(s) none siz [m] skip if increment data memory is 0 description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] + 1 skip if [m]=0 affected fag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] + 1 skip if acc=0 affected fag(s) none snz [m].i skip if data memory is not 0 description if the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected fag(s) none snz [m] skip if data memory is not 0 description if the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m] 0 affected fag(s) none sub a,[m] subtract data memory from acc description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] affected fag(s) ov, z, ac, c, sc, cz
rev. 1.10 ??8 de?e??e? 01? ?01? rev. 1.10 ??9 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom subm a,[m] subtract data memory from acc with result in data memory description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] affected fag(s) ov, z, ac, c, sc, cz sub a,x subtract immediate data from acc description the immediate data specifed by the code is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? x affected fag(s) ov, z, ac, c, sc, cz swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specifed data memory are interchanged. operation [m].3~[m].0 ? [m].7~[m].4 affected fag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specifed data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected fag(s) none sz [m] skip if data memory is 0 description if the contents of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m]=0 affected fag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specifed data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m]=0 affected fag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i=0 affected fag(s) none
rev. 1.10 ?30 de?e??e? 01? ?01? rev. 1.10 ?31 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom tabrd [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected fag(s) z xorm a,[m] logical xor acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected fag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected fag(s) z
rev. 1.10 ?30 de?e??e? 01? ?01? rev. 1.10 ?31 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom extended instruction defnition the extended instructions are used to directly access the data stored in any data memory sections. ladc a,[m] add data memory to acc with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the accumulator. operation acc acc + [m] + c affected fag(s) ov, z, ac, c, sc ladcm a,[m] add acc to data memory with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. operation [m] acc + [m] + c affected fag(s) ov, z, ac, c, sc ladd a,[m] add data memory to acc description the contents of the specifed data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected fag(s) ov, z, ac, c, sc laddm a,[m] add acc to data memory description the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. operation [m] acc + [m] affected fag(s) ov, z, ac, c, sc land a,[m] logical and data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected fag(s) z landm a,[m] logical and acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected fag(s) z lclr [m] clear data memory description each bit of the specifed data memory is cleared to 0. operation [m] 00h affected fag(s) none lclr [m].i clear bit of data memory description bit i of the specifed data memory is cleared to 0. operation [m].i 0 affected fag(s) none
rev. 1.10 ?3? de?e??e? 01? ?01? rev. 1.10 ?33 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom lcpl [m] complement data memory description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected fag(s) z lcpla [m] complement data memory with result in acc description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected fag(s) z ldaa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd (binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and fag conditions. only the c fag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected fag(s) c ldec [m] decrement data memory description data in the specifed data memory is decremented by 1. operation [m] [m] ? 1 affected fag(s) z ldeca [m] decrement data memory with result in acc description data in the specifed data memory is decremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] ? 1 affected fag(s) z linc [m] increment data memory description data in the specifed data memory is incremented by 1. operation [m] [m] + 1 affected fag(s) z linca [m] increment data memory with result in acc description data in the specifed data memory is incremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] + 1 affected fag(s) z
rev. 1.10 ?3? de?e??e? 01? ?01? rev. 1.10 ?33 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom lmov a,[m] move data memory to acc description the contents of the specifed data memory are copied to the accumulator. operation acc [m] affected fag(s) none lmov [m],a move acc to data memory description the contents of the accumulator are copied to the specifed data memory. operation [m] acc affected fag(s) none lor a,[m] logical or data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected fag(s) z lorm a,[m] logical or acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected fag(s) z lrl [m] rotate data memory left description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 [m].7 affected fag(s) none lrla [m] rotate data memory left with result in acc description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 [m].7 affected fag(s) none lrlc [m] rotate data memory left through carry description the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 c c [m].7 affected fag(s) c lrlca [m] rotate data memory left through carry with result in acc description data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 c c [m].7 affected fag(s) c
rev. 1.10 ?34 de?e??e? 01? ?01? rev. 1.10 ?35 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom lrr [m] rotate data memory right description the contents of the specifed data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 [m].0 affected fag(s) none lrra [m] rotate data memory right with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 [m].0 affected fag(s) none lrrc [m] rotate data memory right through carry description the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 c c [m].0 affected fag(s) c lrrca [m] rotate data memory right through carry with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 c c [m].0 affected fag(s) c lsbc a,[m] subtract data memory from acc with carry description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] ? c affected fag(s) ov, z, ac, c, sc, cz lsbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] ? c affected fag(s) ov, z, ac, c, sc, cz
rev. 1.10 ?34 de?e??e? 01? ?01? rev. 1.10 ?35 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom lsdz [m] skip if decrement data memory is 0 description the contents of the specifed data memory are frst decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] ? 1 skip if [m]=0 affected fag(s) none lsdza [m] skip if decrement data memory is zero with result in acc description the contents of the specifed data memory are frst decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] ? 1 skip if acc=0 affected fag(s) none set data memory description each bit of the specifed data memory is set to 1. operation [m] ffh affected fag(s) none lset [m].i set bit of data memory description bit i of the specifed data memory is set to 1. operation [m].i 1 affected fag(s) none lsiz [m] skip if increment data memory is 0 description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] + 1 skip if [m]=0 affected fag(s) none lsiza [m] skip if increment data memory is zero with result in acc description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] + 1 skip if acc=0 affected fag(s) none lsnz [m].i skip if data memory is not 0 description if the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected fag(s) none
rev. 1.10 ?3? de?e??e? 01? ?01? rev. 1.10 ?37 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom lsnz [m] skip if data memory is not 0 description if the content of the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m] 0 affected fag(s) none lsub a,[m] subtract data memory from acc description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] affected fag(s) ov, z, ac, c, sc, cz lsubm a,[m] subtract data memory from acc with result in data memory description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] affected fag(s) ov, z, ac, c, sc, cz lswap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specifed data memory are interchanged. operation [m].3~[m].0 ? [m].7~[m].4 affected fag(s) none lswapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specifed data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected fag(s) none lsz [m] skip if data memory is 0 description if the contents of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m]=0 affected fag(s) none lsza [m] skip if data memory is 0 with data movement to acc description the contents of the specifed data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m]=0 affected fag(s) none
rev. 1.10 ?3? de?e??e? 01? ?01? rev. 1.10 ?37 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom lsz [m].i skip i f bit i of data memory is 0 description if bit i of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i=0 affected fag(s) none ltabrd [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none ltabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none lxor a,[m] logical xor data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected fag(s) z lxorm a,[m] logical xor acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected fag(s) z
rev. 1.10 ?38 de?e??e? 01? ?01? rev. 1.10 ?39 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product tape and reel specifcations) ? the operation instruction of packing materials ? carton information
rev. 1.10 ?38 de?e??e? 01? ?01? rev. 1.10 ?39 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom 48-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.354 bsc b 0.?7? bsc c 0.354 bsc d 0.?7? bsc e 0.0?0 bsc f 0.007 0.009 0.011 g 0.053 0.055 0.057 h 0.0?3 i 0.00? 0.00? j 0.018 0.0?4 0.030 k 0.004 0.008 0 7 symbol dimensions in mm min. nom. max. a 9.00 bsc b 7.00 bsc c 9.00 bsc d 7.00 bsc e 0.50 bsc f 0.17 0.?? 0.?7 g 1.35 1.40 1.45 h 1.?0 i 0.05 0.15 j 0.45 0.?0 0.75 k 0.09 0.?0 0 7
rev. 1.10 ?40 de?e??e? 01? ?01? rev. 1.10 ?41 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom 64-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.354 bsc b 0.?7? bsc c 0.354 bsc d 0.?7? bsc e 0.01? bsc f 0.005 0.007 0.009 g 0.053 0.055 0.057 h 0.0?3 i 0.00? 0.00? j 0.018 0.0?4 0.030 k 0.004 0.008 0 7 symbol dimensions in mm min. nom. max. a 9.00 bsc b 7.00 bsc c 9.00 bsc d 7.00 bsc e 0.40 bsc f 0.13 0.18 0.?3 g 1.35 1.40 1.45 h 1.?0 i 0.05 0.15 j 0.45 0.?0 0.75 k 0. 09 0.?0 0 7
rev. 1.10 ?40 de?e??e? 01? ?01? rev. 1.10 ?41 de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom 80-pin lqfp (10mm10mm) outline dimensions symbol dimensions in inch min. nom. max. a D 0.47? bsc D b D 0.394 bsc D c D 0.47? bsc D d D 0.394 bsc D e D 0.01? bsc D f 0.007 0.009 0.011 g 0.053 0.055 0.057 h D D 0.0?3 i 0.00? D 0.00? j 0.018 0.0?4 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 1?.00 bsc b 10.00 bsc c 1?.00 bsc d 10.00 bsc e D 0.40 bsc D f 0.13 0.18 0.?3 g 1.35 1.40 1.45 h D D 1.?0 i 0.05 0.15 j 0.45 0.?0 0.75 k 0.09 D 0.?0 0 D 7
rev. 1.10 ?4? de?e??e? 01? ?01? rev. 1.10 pb de?e??e? 01? ?01? HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom HT67F60A/ht67f70a tinypower tm a/d flash mcu with lcd & eeprom copy?ight ? ?01? ? y holtek semiconductor inc. the info?? ation appea?ing in this data sheet is ?elieved to ?e a??u? ate at the ti? e of pu ?li? ation. howeve ?? holtek assu? es no ?esponsi? ility a? ising f?o? the use of the specifcations described. the applications mentioned herein are used solely fo? the pu?pose of illust?ation and holtek ?akes no wa??anty o? ?ep?esentation that su? h appli? ations will ? e suita? le without fu?the? ?odifi?ation? no? ?e?o?? ends the use of its p?odu?ts fo? appli?ation that ?ay p?esent a ?isk to hu?an life due to ? alfun?tion o? othe? wise. holtek's p?odu? ts a? e not autho?ized fo? use as ?? iti? al ?o?ponents in life suppo?t devi?es o? syste?s. holtek ?ese?ves the ?ight to alte? its products without prior notifcation. for the most up-to-date information, please visit ou? we? site at http://www.holtek.?o? .tw.

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