? semiconductor components industries, llc, 2012 december, 2012 ? rev. 0 1 publication order number: esd5205/d esd5205 transient voltage suppressors low capacitance esd protection diode for high speed data line the esd5205 transient voltage suppressor is designed to protect high speed data lines from esd. low capacitance and low esd clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. features ? protection for the following iec standards: iec 61000 ? 4 ? 2 (level 4) ? low esd clamping voltage ? this is a pb ? free device typical applications ? sd connector maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit peak power dissipation, 8 x 20 s p pk 18 w operating junction temperature range t j ? 55 to +125 c storage temperature range t stg ? 55 to +150 c lead solder temperature ? maximum (10 seconds) t l 260 c iec 61000 ? 4 ? 2 contact (esd) iec 61000 ? 4 ? 2 air (esd) esd esd 15 15 kv kv stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. see application note and8308/d for further description of survivability specs. marking diagram device package shipping ordering information sot ? 963 case 527ad pin configuration and schematic http://onsemi.com ESD5205P6T6G sot ? 963 (pb ? free) 8000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. xm 1 x = specific device code m = month code 1 4 5 2 3 6
esd5205 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise specified) parameter symbol conditions min typ max unit reverse working voltage v rwm i/o pin to gnd 5.0 v breakdown voltage v br i t = 1 ma, i/o pin to gnd 5.5 v reverse leakage current i r v rwm = 5 v, i/o pin to gnd 1.0 a clamping voltage (note 1) v c i pp = 1 a, i/o pin to gnd (8 x 20 s pulse) i pp = 2 a, i/o pin to gnd (8 x 20 s pulse) 9 10 v clamping voltage (note 2) v c iec61000 ? 4 ? 2, 8 kv contact see figures 1 and 2 v clamping voltage tlp (note 3) v c i pp = 8 a i pp = 16 a i pp = ? 8 a i pp = ? 16 a 11.4 15.6 ? 4.5 ? 8.1 junction capacitance c j v r = 0 v, f = 1 mhz between i/o pins and gnd 9.0 pf 1. surge current waveform per figure 5. 2. for test procedure see figures 3 and 4 and application note and8307/d. 3. ansi/esd stm5.5.1 ? electrostatic discharge sensitivity testing using transmission line pulse (tlp) model. tlp conditions: z 0 = 50 , t p = 100 ns, t r = 4 ns, averaging window; t 1 = 30 ns to t 2 = 60 ns. figure 1. iec61000 ? 4 ? 2 +8 kv contact esd clamping voltage figure 2. iec61000 ? 4 ? 2 ? 8 kv contact clamping voltage
esd5205 http://onsemi.com 3 iec 61000 ? 4 ? 2 spec. level test voltage (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000 ? 4 ? 2 waveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 3. iec61000 ? 4 ? 2 spec figure 4. diagram of esd clamping voltage test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8308/d ? interpretation of datasheet parameters for esd devices. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000 ? 4 ? 2 waveform. since the iec61000 ? 4 ? 2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d. figure 5. 8 x 20 s pulse waveform 100 90 80 70 60 50 40 30 20 10 0 020406080 t, time ( s) % of peak pulse current t p t r pulse width (t p ) is defined as that point where the peak current decay = 8 s peak value i rsm @ 8 s half value i rsm /2 @ 20 s
esd5205 http://onsemi.com 4 package dimensions sot ? 963 case 527ad issue e dim min nom max millimeters a 0.34 0.37 0.40 b 0.10 0.15 0.20 c 0.07 0.12 0.17 d 0.95 1.00 1.05 e 0.75 0.80 0.85 e 0.35 bsc 0.95 1.00 1.05 h e e d c a h e 123 4 5 6 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e do not include mold flash, protrusions, or gate burrs. x y top view side view e b x 0.08 6x y bottom view 6x 0.35 pitch 1.20 0.20 dimensions: millimeters recommended package outline mounting footprint l 0.19 ref l2 0.05 0.10 0.15 l 6x l2 6x 6x 0.35 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 esd5205/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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