cystech electronics corp. spec. no. : c733fp issued date : 2011.03.14 revised date : page no. : 1/6 MTDA0P10FP cystek product specification p-channel logic level enha ncement mode power mosfet MTDA0P10FP bv dss -100v i d -22a r dson(max) 120m features ? low gate charge ? simple drive requirement ? pb-free lead plating package equivalent circuit outline MTDA0P10FP g gate d drain s source to-220fp absolute maximum ratings (t c =25 c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds -100 gate-source voltage v gs 20 v continuous drain current @ t c =25 c i d -22 continuous drain current @ t c =100c i d -15 pulsed drain current *1 i dm -75 avalanche current i as -15 a avalanche energy @ l=0.1mh, i d =-15a, r g =25 e as 22.5 repetitive avalanche energy @ l=0.05mh *2 e ar 11.25 mj total power dissipation @t c =25 62 total power dissipation @t c =100 pd 31 w operating junction and storage te mperature range tj, tstg -55~+175 c note : *1 . pulse width limited by maximum junction temperature *2. duty cycle 1%
cystech electronics corp. spec. no. : c733fp issued date : 2011.03.14 revised date : page no. : 2/6 MTDA0P10FP cystek product specification thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 2.42 c/w thermal resistance, junction-to-ambient, max r th,j-a 62.5 c/w characteristics (tc=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss -100 - - v v gs =0, i d =-250 a v gs(th) -1.5 -2.5 -4.0 v v ds =v gs , i d =-250 a i gss - - 100 na v gs = 20, v ds =0 - - -1 v ds =-80v, v gs =0 i dss - - -25 a v ds =-70v, v gs =0, t j =125 c i d(on) *1 -22 - - a v ds =-5v, v gs =-10v r ds(on) *1 - 105 120 m v gs =-10v, i d =-11a g fs *1 - 8 - s v ds =-5v, i d =-11a dynamic qg *1, 2 - 58 - qgs *1, 2 - 13.8 - qgd *1, 2 - 10.5 - nc i d =-11a, v ds =-80v, v gs =-10v t d(on) *1, 2 - 15 - tr *1, 2 - 67 - t d(off) *1, 2 - 50 - t f *1, 2 - 50 - ns v ds =-10v, i d =-1a, v gs =-10v, r g =6 ciss - 7760 - coss - 1683 - crss - 1643 - pf v gs =0v, v ds =-25v, f=1mhz rg - 4.5 - v gs =15mv, v ds =0, f=1mhz source-drain diode i s *1 - - -22 i sm *3 - - -75 a v sd *1 - - -1.3 v i f =i s , v gs =0v trr - 150 - ns qrr - 830 - nc i f =-5a, di f /dt=100a/ s note : *1.pulse test : pulse width 300 s, duty cycle 2% *2.independent of operating temperature *3.pulse width limited by maximum junction temperature. ordering information device package shipping MTDA0P10FP to-220fp (pb-free lead plating package) 50 pcs / tube, 20 tubes/box, 4 boxes/carton
cystech electronics corp. spec. no. : c733fp issued date : 2011.03.14 revised date : page no. : 3/6 MTDA0P10FP cystek product specification typical characteristics
cystech electronics corp. spec. no. : c733fp issued date : 2011.03.14 revised date : page no. : 4/6 MTDA0P10FP cystek product specification typical characteristics(cont.)
cystech electronics corp. spec. no. : c733fp issued date : 2011.03.14 revised date : page no. : 5/6 MTDA0P10FP cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c733fp issued date : 2011.03.14 revised date : page no. : 6/6 MTDA0P10FP cystek product specification to-220fp dimension inches millimeters inches millimeters dim min. max. min. max. marking: device name date code style: pin 1.gate 2.drain 3.source 3-lead to-220fp plastic package cystek package code: fp dim min. max. min. max. a 0.1654 0.1890 4.20 4.80 l2 0.2717 0.2953 6.90 7.50 a1 0.0768 0.1122 1.95 2.85 l3 0.6181 0.6417 15.70 16.30 b 0.0256 0.0413 0.65 1.05 l4 0.5315 0.5709 13.50 14.50 b1 0.0354 0.0591 0.90 1.50 0.1181 0.1339 3.00 3.40 c 0.0217 0.0315 0.55 0.80 e 0.0925 0.1083 2.35 2.75 c2 0.0984 0.1220 2.50 3.10 f 0.0512 0.0748 1.30 1.90 e 0.3819 0.4055 9.70 10.30 g 0.1339 0.1496 3.40 3.80 l1 0.1260 0.1496 3.20 3.80 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead : pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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