integrated circuit systems, inc. general description features ics9179-06 block diagram pentiumpro is a trademark of intel corporation i 2 c is a trademark of philips corporation zero delay buffers 9179-06 rev f 6/22/99 pin configuration the ics9179-06 generates low skew clock buffers required for high speed risc or cisc microprocessor systems such as intel pentiumpro. an output enable is provided for testability. the device is a buffer with low output to output skew. this is a zero delay buffer device, using an internal pll. this buffer can be used for phase synchronization to a master clock. with the wide pll loop bw, this buffer is compatible to spread spectrum input clocks from clock generator products such as the ics9148-27. the individual clock outputs are addressable through i 2 c to be enabled, or stopped in a low state for reduced emi when the lines are not needed. the device defaults to zero-delay mode, but can be programmed with i 2 c for selectable delays -2.7, +2.0, -0.7 ns (nominal target values). ? zero delay buffer, 16 outputs ? supports up to four sdram dimms ? wide pll loop bandwidth makes this part ideal in spread spectrum applications. ? skew input to fb_in 250ps default, with selectable skew -2.7, +2.0, -0.7ns nominal. ? synchronous clocks skew matched to 250 ps window on output. ? 33 to 133mhz input or output frequency. ? i 2 c serial configuration interface to allow individual clocks to be stopped, or selectable delays. ? multiple vdd, vss pins for noise reduction ? slew rate 1.5v/ns into 30pf. ? vdd = 3.3 5%, 0 to 70c ? all outputs (0:15) tristate with oe low (fb_out stays running). ? 48-pin ssop package 48-pin ssop ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. functionality # e o t u p t u o ) 5 1 : 0 ( t u o _ b f 0z - i ht u p n i x 1 1t u p n i x 1t u p n i x 1
2 ics9179-06 pin descriptions power groups vdd = power supply for output buffers vdds = power supply for i 2 c circuitry vdda = power supply for analog pll circuitry notes: 1. at power up all sixteen outputs are enabled and active. 2. oe has a 100k ohm internal pull-up resistor to keep all outputs active. 3. the sdata and sclk inputs both also have internal pull-up resistors with values above 100k ohms as well for complete platform flexibility. 4. i 2 c byte0, bits 0 & 1 used to select delay. default* values at power up is 0 5. subject to design engineering verification of target value. r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 2e on i l a n r e t n i s a h . w o l d l e h n e h w t u o _ b f t p e c x e s t u p t u o l l a s e t a t s - i r t . p u - l l u p 2 0 1 , 9 , 6 , 5) 3 : 0 ( t u p t u ot u os t u p t u o k c o l c 0 e t y b m a r d s 1 0 2 , 9 1 , 6 1 , 5 1) 7 : 4 ( t u p t u ot u os t u p t u o k c o l c 1 e t y b m a r d s 1 4 3 , 3 3 , 0 3 , 9 2) 1 1 : 8 ( t u p t u ot u os t u p t u o k c o l c 2 e t y b m a r d s 1 5 4 , 4 4 , 1 4 , 0 4) 5 1 : 2 1 ( t u p t u ot u os t u p t u o k c o l c 3 e t y b m a r d s 1 2 1t u p n in i. k c o l c e c n e r e f e r r o f t u p n i 3 1n i _ b fn i. t u p n i k c a b d e e f 4 2a t a d so / ii r o f n i p a t a d 2 y r t i u c r i c c 3 5 2k l c so / ii r o f n i p k c o l c 2 y r t i u c r i c c 3 7 3t u o _ b ft u o. n i _ b f t u p n i o t t u p t u o k c a b d e e f , 1 3 , 1 2 , 7 1 , 1 1 , 7 , 3 6 4 , 2 4 , 8 3 , 5 3 d d vr w ps r e f f u b t u p t u o r o f y l p p u s r e w o p v 3 . 3 , 2 3 , 8 2 , 8 1 , 4 1 , 8 , 4 7 4 , 3 4 , 9 3 , 6 3 d n gr w ps r e f f u b t u p t u o r o f d n u o r g 2 2a d d vr w ps e g a t s l l p g o l a n a r o f y l p p u s r e w o p v 3 . 3 3 2s d d vr w pi r o f y l p p u s r e w o p v 3 . 3 2 y r t i u c r i c c 6 2s d n gr w pi r o f d n u o r g 2 y r t i u c r i c c 7 2a d n gr w ps e g a t s l l p g o l a n a r o f d n u o r g 8 4 , 1c / n- d e t c e n n o c y l l a n r e t n i t o n e r a s n i p ground groups gnd = ground supply for output buffer gnds = ground supply for i 2 c circuitry gnda = ground supply for analog pll circuitry delay selection table 4 t u p n i l o r t n o c 1 t i b 0 e t y b n i _ b f l o r t n o c 0 t i b 0 e t y b t e g r a t l a n i m o n 5 o t t u p n i , y a l e d . s n i p n i _ b f * 0* 0s n 0 01 s n 7 . 2 - 10 s n 0 . 2 + 11 s n 7 . 0 -
3 ics9179-06 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending first byte (byte 0) through byte 5 ? ics clock will acknowledge each byte one at a time . ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controler (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends first byte (byte 0) through byte 5 ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ac k byte 2 ack byte 3 ac k byte 4 ac k byte 5 ac k stop bit how to write:
4 ics9179-06 byte 2: output clock register (default = 1) notes: 1 = enabled; 0 = disabled, outputs held low t i b# n i pd w pn o i t p i r c s e d 7 t i b5 41 ) t c a n i / t c a ( 5 1 t u p t u o 6 t i b4 41 ) t c a n i / t c a ( 4 1 t u p t u o 5 t i b1 41 ) t c a n i / t c a ( 3 1 t u p t u o 4 t i b0 41 ) t c a n i / t c a ( 2 1 t u p t u o 3 t i b4 31 ) t c a n i / t c a ( 1 1 t u p t u o 2 t i b3 31 ) t c a n i / t c a ( 0 1 t u p t u o 1 t i b0 31 ) e v i t c a n i / e v i t c a ( 9 t u p t u o 0 t i b9 21 ) e v i t c a n i / e v i t c a ( 8 t u p t u o byte 3: output clock register notes: 1 = enabled; 0 = disabled, outputs held low t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-1 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b-1 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-1 d e v r e s e r 0 t i b-1 d e v r e s e r ics9179-06 power management the values below are estimates of target specifications. n o i t i d n o c n o i t p m u s n o c y l p p u s v 3 . 3 x a m s d a o l p a c e t e r c s i d x a m v 5 6 4 . 3 = d d v d n g r o d d v = s t u p n i c i t a t s l l a e d o m k c o l c o n ) d n g r o 1 d d v - n i _ f u b ( i 2 e v i t c a y r t i u c r i c c a m 0 3 z h m 6 6 e v i t c a ) z h m 6 6 . 6 6 = n i _ f u b ( a m 0 5 1 z h m 0 0 1 e v i t c a ) z h m 0 0 . 0 0 1 = n i _ f u b ( a m 0 8 1 note: pwd = power-up default byte 0: output clock register (default = 0) notes: 2 = default = 0; 1 = delay element enabled, 0 = no delay path. t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 d e v r e s e r 6 t i b-0 d e v r e s e r 5 t i b-0 d e v r e s e r 4 t i b-0 d e v r e s e r 3 t i b-0 d e v r e s e r 2 t i b-0 d e v r e s e r 1 t i b 2 2 10 l o r t n o c w e k s t u p n i k c o l c 0 t i b 2 3 10 l o r t n o c w e k s n i b f serial configuration command bitmaps notes: 1 = enabled; 0 = disabled, outputs held low byte 1: output clock register t i b# n i pd w pn o i t p i r c s e d 7 t i b0 21 ) t c a n i / t c a ( 7 t u p t u o 6 t i b9 11 ) t c a n i / t c a ( 6 t u p t u o 5 t i b 6 11 ) t c a n i / t c a ( 5 t u p t u o 4 t i b5 11 ) t c a n i / t c a ( 4 t u p t u o 3 t i b 0 11 ) t c a n i / t c a ( 3 t u p t u o 2 t i b91 ) t c a n i / t c a ( 2 t u p t u o 1 t i b61 ) t c a n i / t c a ( 1 t u p t u o 0 t i b51 ) t c a n i / t c a ( 0 t u p t u o note: pwd = power-up default
5 ics9179-06 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input & supply t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 5ua input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 ua input low current i il2 v in = 0 v; inputs with pull-up resistors -60 -33 ua operating i dd c l = 0 pf; f in @ 66m 115 150 ma supply current c l = 0 pf; f in @ 100m 170 180 ma output disabled i dd c l = 0 pf; f in @ 66m 30 ma supply current c l = 0 pf; f in @ 100m 30 ma input frequency f i v dd = 3.3 v; all outputs loaded 33 105 mhz input capacitance c in logic inputs 5 pf 1 guarenteed by design, not 100% tested in production. electrical characteristics - input & supply t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% (unless otherwise stated) parameter symbol c onditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 5ua i il v in = 0 v; inputs with no pull-up resistors -5 ua i il v in = 0 v; inputs with 100k pull-up resistors -60 -33 ua operating i dd1 c l = 0 pf; f in @ 66m 115 150 ma supply current i dd2 c l = 0 pf; f in @ 100m 170 180 ma input frequency f i 1 v dd = 3.3 v; all outputs loaded 10 150 mhz input capacitance c in 1 logic inputs 5 pf 1 guarenteed by design, not 100% tested in production. input low current
6 ics9179-06 parameter symbol conditions min typ max units output frequency f o3 33 133 mhz output impedance r dsp3 v o = v dd *(0.5) 10 24 ohm output impedance r dsn3 v o = v dd *(0.5) 10 24 ohm output high voltage v oh3 i oh = -30 ma 2.6 v output low voltage v ol3 i ol = 23 ma 0.4 v output high current i oh3 v oh = 2.0 v -54 ma output low current i ol3 v ol = 0.8 v 40 ma rise time t r3 v ol = 0.4 v, v oh = 2.4 v 1.33 ns fall time t f3 v oh = 2.4 v, v ol = 0.4 v 1.33 ns duty cycle d t3 v t = 1.5 v 45 55 % output to output skew window t sk3 v t = 1.5 v 250 ps t skd1 v t = 1.5 v default zero delay i 2 c b0 bits 0, 1 = 00 -250 0 250 ps in to fb_in skew 1, 2 t skd2 v t = 1.5 v bits 0, 1 = 10 -2.2 -2.7 -3.2 ns t skd3 v t = 1.5 v bits 0, 1 = 01 +1.5 +2.0 +2.5 ns t skd4 v t = 1.5 v bits 0, 1 = 11 -0.2 -0.7 -1.2 ns electrical characteristics - sdram t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 - 30 pf (unless otherwise stated) notes: 1. guarenteed by design, not 100% tested in production 2. delay elements fbin and clock input path are selected by i 2 c byte2; bit 0 = clock input control, bit 1 = clock input control. (default is 0). a 0 = no delay in path, 1 = delay element selected. note: pwd = power-up default input pulse n i mp y tx a ms t i n u e s l u p t u p n i e m i t w o l t w o l - m i w o l _ e s l u p v v 8 . 00 . 1s n e s l u p t u p n i e m i t h g i h t h g i h - m i h g i h _ e s l u p v 3 v 0 . 25 . 1s n
7 ics9179-06 general layout precautions: 1) use a ground plane on the top layer of the pcb in all areas not used by traces. 2) make all power traces and vias as wide as possible to lower inductance. notes: 1 all clock outputs should have series terminating resistor. not shown in all places to improve readibility of diagram 2 optional emi capacitor should be used on all cpu, sdram, and pci outputs. capacitor values: all unmarked capacitors are 0.01f ceramic
8 ics9179-06 ordering information ics9179f-06 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx f - ppp ssop package l o b m y s s n o i s n e m i d n o m m o c s n o i t a i r a v d n . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .1 0 1 .0 1 1 .c a0 2 6 .5 2 6 .0 3 6 .8 4 1 a8 0 0 .2 1 0 .6 1 0 . 2 a8 8 0 .0 9 0 .2 9 0 . b8 0 0 .0 1 0 .5 3 1 0 . c5 0 0 .- 0 1 0 . ds n o i t a i r a v e e s e2 9 2 .6 9 2 .9 9 2 . ec s b 5 2 0 . 0 h0 0 4 .6 0 4 .0 1 4 . h0 1 0 .3 1 0 .6 1 0 . l4 2 0 .2 3 0 .0 4 0 . ns n o i t a i r a v e e s 0 5 8 x5 8 0 .3 9 0 .0 0 1 . ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
|
