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| march 2015 docid024110 rev 5 1/90 1 AN4228 application note migrating from stm32f1 to stm32f3 microcontrollers introduction for designers of stm32 microcontroller applicati ons, it is important to be able to easily replace one microcontroller type by another one in the same product family. migrating an application to a different microcontroller is often needed, when product requirements grow, putting extra demands on memory size, or in creasing the number of i/os. on the other hand, cost reduction objectives may induce to switch to smaller components and shrink the pcb area. this application note is written to help users, by presen ting the steps required to migrate from an existing stm32f1xx family device to an stm32f3xx family device. it gathers the most important information and lists the vital aspects that users must address. when migrating an application from stm32f1 series to stm32f3 series, users have to analyze the hardware migration, the perip heral migration and the firmware migration. to benefit fully from the information in this application note, users should be familiar with the stm32 microcontrollers. users can refer to the following documents that are available from www.st.com . ? stm32f1 series reference manuals (rm0008 and rm0041), the stm32f1 datasheets, and the stm32f1 flash programming manuals (pm0075, pm0063 and pm0068). ? stm32f3 series reference manuals and the stm32f3 datasheets. for an overview of the whole stm32 series and a comparison of the different features of each stm32 product series, please refer to the application note an3364 migration and compatibility guidelines for stm3 2 microcontroller applications . table 1 lists the microcontrollers concerned by this application note. table 1. applicable products type applicable products microcontrollers stm32f1 series, stm32f3 series. www.st.com
contents AN4228 2/90 docid024110 rev 5 contents 1 hardware migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 boot mode compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 peripheral migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 stm32 product cross-compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 reset and clock controller (rcc) interface . . . . . . . . . . . . . . . . . . . . . . . 17 3.4.1 system clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4.2 peripheral access configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.3 peripheral clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5 dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.6 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.7 gpio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.7.1 alternate function mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.8 exti source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.9 flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.10 sar adc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.11 pwr interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.12 real-time clock (rtc) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.13 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.14 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.15 usart interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.16 cec interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 firmware migration using the li brary . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1 migration steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2 rcc driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.1 system clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.2 peripheral access configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2.3 peripheral clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 docid024110 rev 5 3/90 AN4228 contents 3 4.3 flash driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.4 crc driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5 gpio configuration update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.5.1 output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.5.2 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5.3 analog mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5.4 alternate function mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.6 exti line0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.7 nvic interrupt configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.8 adc configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.9 dac driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.10 pwr driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.11 backup data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.12 cec application code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.13 i2c driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.14 spi driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.15 usart driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.16 iwdg driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.17 fmc driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.18 tim driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.19 dbgmcu driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 list of tables AN4228 4/90 docid024110 rev 5 list of tables table 1. applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f103 and stm32f3xx line available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. main pinout differences between stm32f10x a nd stm32f30x lines . . . . . . . . . . . . . . . . . 6 table 4. lqfp144 pinout in stm32f103xx and stm32f30xxd/e . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. main pinout differences between stm32f373xx and stm32f103xx . . . . . . . . . . . . . . . . . 7 table 6. boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. stm32 peripheral compatibility analysis stm32f1 versus stm32f3 series. . . . . . . . . . . 11 table 8. ip bus mapping differences between stm32f3 and stm32f1 series. . . . . . . . . . . . . . . . 15 table 9. rcc differences between stm32f1 and stm32f3 seri es . . . . . . . . . . . . . . . . . . . . . . . . 17 table 10. example of migrating system clock config uration code from stm3 2f100 to stm32f3xx. 20 table 11. rcc registers used for peripheral access configurat ion. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. dma request differences between stm32f3xx and stm32f1xx . . . . . . . . . . . . . . . . . . . 23 table 13. interrupt vector differences between stm32f 3 and stm32f1 series . . . . . . . . . . . . . . . . 25 table 14. gpio differences between stm32f1 and stm32f3 se ries. . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. flash differences between stm32f1 and stm32f3 series . . . . . . . . . . . . . . . . . . . . . . 28 table 16. adc differences between stm32f1 series and st m32f30x lines . . . . . . . . . . . . . . . . . . 29 table 17. adc channels mapping differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 18. pwr differences between stm32f1 and stm32f3 se ries . . . . . . . . . . . . . . . . . . . . . . . . 31 table 19. stm32f10x and stm32f3xx clock source api co rrespondence . . . . . . . . . . . . . . . . . . . 37 table 20. stm32f10x and stm32f3xx flash driver api co rrespondence. . . . . . . . . . . . . . . . . . . 38 table 21. stm32f10x and stm32f3xx crc dr iver api correspondence. . . . . . . . . . . . . . . . . . . . . 40 table 22. stm32f10x and stm32f3xx misc driver api corr espondence . . . . . . . . . . . . . . . . . . . . 45 table 23. stm32f10x and stm32f3xx adc driver api corres pondence. . . . . . . . . . . . . . . . . . . . . 47 table 24. stm32f10x and stm32f3xx dac driver api corres pondence. . . . . . . . . . . . . . . . . . . . . 59 table 25. stm32f10x and stm32f3xx pwr driver api corr espondence . . . . . . . . . . . . . . . . . . . . 60 table 26. stm32f10x and stm32f37x cec driver api corres pondence. . . . . . . . . . . . . . . . . . . . . 63 table 27. stm32f10x and stm32f3xx i2c driver api corres pondence. . . . . . . . . . . . . . . . . . . . . . 65 table 28. stm32f10x and stm32f3xx spi driver api corres pondence. . . . . . . . . . . . . . . . . . . . . . 69 table 29. stm32f10x and stm32f3xx usart driver api co rrespondence . . . . . . . . . . . . . . . . . . 72 table 30. stm32f10x and stm32f3xx iwdg driver api corr espondence. . . . . . . . . . . . . . . . . . . . 76 table 31. stm32f10x and stm32f303xd/e fmc driver api correspondence . . . . . . . . . . . . . . . . 77 table 32. stm32f10x and stm32f3xx tim driver api corres pondence . . . . . . . . . . . . . . . . . . . . . 80 table 33. stm32f10x and stm32f3xx dbgmcu driver api correspondence . . . . . . . . . . . . . . . . 87 table 34. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 docid024110 rev 5 5/90 AN4228 list of figures 5 list of figures figure 1. system architecture for stm32f30x and stm32f3x 8 lines . . . . . . . . . . . . . . . . . . . . . . . 14 figure 2. system architecture for stm32f37x lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 hardware migration AN4228 6/90 docid024110 rev 5 1 hardware migration the stm32f30x and stm32f1xx lines are pin-to-pin compatible. all peripherals share the same pins in the two lines, but there are some minor differences between packages. the transition from the stm32f1 series to the stm32f3 series is simple as only a few pins are impacted (as detailed in table 3 and table 5 ). table 2. stm32f103 and stm32f3xx line available packages (1) package stm32f103xx stm32f30xxb/c stm32f30xxd/e stm32f37xx stm32f302/ f301x6/8 stm32f303 x6/8 lqfp32 - - - - - x lqfp48 - x - x x x lqfp64 x x x x x x lqfp100 x x x x - - lqfp144 x - x - - ufqfn32 - - - - x - ufbga100 - - - x - - wlcsp49 - - - - x - 1. x = available. table 3. main pinout differences be tween stm32f10x and stm32f30x lines lqfp48 lqfp64 lqfp100 stm32f10xxx stm32f302xb/c stm32f303xb/c stm32f302xd/e stm32f303xd/e stm32f302x6/8 stm32f301x6/8 stm32f303x6/8 comments --10 v ss pf9 pf9 - one additional i/o --11 v dd pf10 pf10 - one additional i/o 5 5 12 osc_in pf0/osc_in pf0/osc_in pf0/osc_in - 6 6 13 osc_out pf1/osc_out p f1/osc_out pf1/osc_out - --19 v ssa pf2 pf2 - one additional i/o 81220 v ref- v ref- /v ssa v ref- /v ssa v ref- /v ssa - -1827 v ss pf4 v ss v ss one additional i/o docid024110 rev 5 7/90 AN4228 hardware migration 89 considering the 48-/64-/100-pin packages, the migration from stm32f1 to stm32f30xx has no impact on the pinout, except that us ers gain additional gpios for their application. table 4 shows the lqfp144 pinout compatib ility between stm32f302/f303xd/e and stm32f103xx products. 20 28 37 pb2/boot1 pb2 pb2 - one additional i/o. the bootloader strategy has changed in the stm32f30xx and boot1 is not necessary anymore. the boot memory (ram, flash or system memory) is selectable through an option bit. - - 73 not connected pf6 pf6 - one additional i/o table 3. main pinout differences between stm32f10x and stm32f30x lines (continued) lqfp48 lqfp64 lqfp100 stm32f10xxx stm32f302xb/c stm32f303xb/c stm32f302xd/e stm32f303xd/e stm32f302x6/8 stm32f301x6/8 stm32f303x6/8 comments table 4. lqfp144 pinout in stm32f103xx and stm32f30xxd/e lqfp144 stm32f103xx stm32f302xd/e, stm32f303xd/e 10 pf0 ph0 11 pf1 ph1 23 osc_in pf0/osc_in 24 osc_out pf1/osc_out 106 not connected ph2 table 5. main pinout differences between stm32f373xx and stm32f103xx pin number for 48-pin package pin number for 64-pin package pin number for 100-pin package stm32f373xx stm32f103xx comments --10pf9v ss - --11pf10v dd - --19pf2v ssa - --21v dda v ref+ supply compatible 91322v ref+ /v dda v dda supply compatible hardware migration AN4228 8/90 docid024110 rev 5 -17- v ref+ pa3 - -18- pa3 v ss supply compatible -19- v dd v dd supply compatible 17 - - v dd pa7 - 23 31 - v refsd- /v sssd v ss supply compatible 24 32 - v ddsd v dd supply compatible --27pf4v ss - --48v refsd- pb11 - --49v sssd v ss supply compatible --50v ddsd12 v dd supply compatible 25 33 51 v refsd+ /v ddsd3 pb12 - --52v refsd+ pb13 - 35 47 73 pf6 v ss supply compatible 36 48 - pf7 v dd supply compatible table 5. main pinout differences between stm32f373xx and stm32f103xx (continued) pin number for 48-pin package pin number for 64-pin package pin number for 100-pin package stm32f373xx stm32f103xx comments docid024110 rev 5 9/90 AN4228 boot mode compatibility 89 2 boot mode compatibility the way to select the boot mode on the st m32f3 series differs from stm32f1 series. instead of using two pins for this setting, stm32f3 series devices gets the nboot1 value from an option bit located in the user option bytes at 0x1ffff800 memory address. together with the boot0 pin, it selects th e boot mode to the main flash memory, the sram or to the system memory. table 6 summarizes the different configurations available for selecting the boot mode. note: the boot1 value is the opposite of the nboot1 option bit. table 6. boot modes stm32f3/stm32f1 boot mode selection boot mode aliasing boot1 boot0 x 0 main flash memory main flash memory is selected as boot space 0 1 system memory system memory is selected as boot space 1 1 embedded sram embedded sram is selected as boot space peripheral migration AN4228 10/90 docid024110 rev 5 3 peripheral migration as shown in table 7 , there are three categories of peri pherals. the common peripherals are supported with the dedicated firmware library without any modification, except if the peripheral instance is no longer present. you can change the instance and, of course, all the related features (clock configuration, pi n configuration, interrupt/dma request). the modified peripherals such as adc, rcc and rtc are different from the stm32f1 series ones and should be updated to take advantage of the enhancements and the new features in stm32f3 series. all these modified peripherals in the stm32f3 series are enhanced to obt ain smaller silicon print with features designed to offer advanced hi gh-end capabilities in economical end products and to fix some limitations present in the stm32f1 series. 3.1 stm32 product cross-compatibility the stm32 series embeds a set of peripherals which can be classed in three categories: ? the first category is for the peripherals which are, by definition, common to all products. those peripherals are identical, so they have the same structure, registers and control bits. there is no need to perform any firmwar e change to keep the same functionality, at the application level, after migration. a ll the features and behavior remain the same. ? the second category is for the peripherals which are shared by all products but have only minor differences (in general to support new features). the migration from one product to another is very easy and does not need any significant new development effort. ? the third category is for peripherals which have been considerably changed from one product to another (new architecture, new feat ures...). for this category of peripherals, the migration will require new development, at the application level. table 7 gives a general overview of this classification. docid024110 rev 5 11/90 AN4228 peripheral migration 89 table 7. stm32 peripheral compatibility analysis stm32f1 versus stm32f3 series peripheral stm32f1 series stm32f3 series compatibility feature pinout fw driver spi yes yes++ two fifo available, 4-bit to 16-bit data size selection identical partial compatibility wwdg yes yes same features na full compatibility iwdg yes yes+ added a window mode na full compatibility dbgmcu yes yes same features identical full compatibility crc yes yes++ added reverse capability and initial crc value na partial compatibility exti yes yes+ some peripherals are able to generate event in stop mode identical full compatibility cec yes yes++ kernel clock, arbitration lost flag and automatic transmission retry, multi- address config, wakeup from stop mode identical partial compatibility dma yes yes 2 dma controllers with 12 channels (1) na full compatibility tim yes yes+ enhancement identical full compatibility pwr yes yes+ v dda can be higher than v dd , 1.8 v mode for core, independent v dd for sdadcs identical for the same feature partial compatibility rcc yes yes+ - pd0 & pd1 => pf0 & pf1 for the oscillator partial compatibility usart yes yes+ choice for independent clock sources, timeout feature, wakeup from stop mode identical full compatibility i2c yes yes++ communication events managed by hw, fm+, wakeup from stop mode, digital filter identical new driver dac yes yes+ dma underrun interrupt identical full compatibility adc yes yes++ same adc or new fast adcs identical partial compatibility rtc yes yes++ subsecond precision, digital calibration circuit, time-stamp function for event saving, programmable alarm identical for the same feature new driver flash yes yes+ option byte modified na partial compatibility gpio yes yes++ new peripheral new gpios partial compatibility peripheral migration AN4228 12/90 docid024110 rev 5 note: yes++ = new featur e or new architecture ? yes+ = same feature, but spec ification change or enhancement ? yes = feature available ? na = feature not available can yes yes in stm32f303/302xb/c, 512 bytes sram is not shared with usb. in stm32f302x6/x8 and stm32f30xxd/e, 256 bytes shared sram with usb. identical full compatibility usb fs device yes yes in stm32f303/302xb/c, 512 bytes sram is not shared with can. in stm32f302x6/x8 and stm32f30xxd/e, 726 bytes dedicated sram and 256 bytes shared sram with can i.e. 1kbytes dedicated sram in case can is disabled. identical full compatibility for sm32f303/302xb/c. partial compatibility for stm32f302x6/x8 and stm32f30xxd/e as the usb is modified compared to stm32f1/f30xxb/c, comes with lpm support and has 726 bytes dedicated sram and 256 bytes shared sram with can, or 1kbytes dedicated sram in case can is disabled. ethernet yes na na na na sdio yes na na na na fmc yes yes available only on the stm32f30xxd/e. identical full compatibility. touch sensing na yes na na na comp na yes na na na opamp (2) na yes na na na syscfg na yes na na na sdadc (3) na yes na na na 1. in the in the stm32f303/302/301x6/x8, one dma controller is available, with 7 channels 2. the opamp is availabl e only on stm32f30xx/f358x. 3. the sdadc is available only on stm32f37xx/f378x. table 7. stm32 peripheral compatibility analysis stm32f1 versus stm32f3 series (continued) peripheral stm32f1 series stm32f3 series compatibility feature pinout fw driver docid024110 rev 5 13/90 AN4228 peripheral migration 89 3.2 system architecture the main system consists of: ? five masters: ? cortex-m4 core i-bus ? cortex-m4 core d-bus ? cortex-m4 core s-bus ? gp-dma1 and gp-dma2 (general-purpose dmas) ? seven or six slaves in stm32f30xx microcontrollers depending on the ccm ram and fmc availability in the product: ? internal flash memory on the dcode and icode ? ccm sram on stm32f303xb/c/d/e and stm32f303x6/x8 ? internal sram ? ahb to apbx (apb1 or apb2), wh ich connect all the apb peripherals ? ahb dedicated to gpio ports ? adcs ?fmc ? five slaves in stm32f37xx microcontrollers: ? internal flash memory on the dcode ? internal flash memory on the icode ? 2 kbyte internal sram memory ? ahb to apbx (apb1 or apb2) co nnecting all the apb peripherals ? ahb dedicated to gpio ports. these are interconnected using a multilayer ahb bus architecture as shown in figure 1 and figure 2 . peripheral migration AN4228 14/90 docid024110 rev 5 figure 1. system architecture for stm32f30x and stm32f3x8 lines 1. flash size, sram size, ccm and fmc availabi lity and number of adcs depend on the product. please refer to stm32f30x line datasheets. figure 2. system architecture for stm32f37x lines 0 6 y 9 ) / 7 , ) 6 5 $ 0 $ + % g h g l f d w h g w r * 3 , 2 s r u w v & & 0 5 $ 0 5 & & 7 6 & & 5 & d q g $ + % w r $ 3 % d q g $ 3 % $ ' & , e x v 6 e x v ' e x v ' 0 $ ' 0 $ $ 5 0 & 2 5 7 ( ; 0 * 3 ' 0 $ * 3 ' 0 $ ) / $ 6 + , & 2 ' ( ' & 2 ' ( % x v 0 d w u l [ 6 0 0 0 0 0 0 0 6 6 6 6 6 ) 0 & 0 " u s m a t r i x 3 3 3 3 3 3 - - - - - - 3 6 ! ( " d e d i c a t e d t o ' 0 ) / p o r t s 2 # # 4 3 # # 2 # a n d ! ( " t o ! 0 " a n d ! 0 " + " 3 2 ! - ) # / $ % $ # / $ % & , ) 4 & b i t + " & l a s h m e m o r y $ - ! $ - ! ! 2 - # o r t e x - ) b u s $ b u s 3 b u s $ - ! $ - ! docid024110 rev 5 15/90 AN4228 peripheral migration 89 3.3 memory mapping the peripheral address mapping has been changed in the stm32f3 series versus stm32f1 series. the main change concerns the gpios which have been moved from the apb bus to the ahb bus to allow them to operate at the maxi mum speed. table 8 provides the peripheral address mapp ing correspondence between stm32f3 and stm32f1 series. table 8. ip bus mapping di fferences between stm32f3 and stm32f1 series (1) peripheral stm32f30xx stm32f37x stm32f1 series bus base address bus base address bus base address tsc ahb1 0x4002 4000 ahb 0x4002 4000 na na gpioh ahb2 0x4800 1c00 na na apb2 0x4800 1fff gpiog 0x4800 1800 na na 0x4800 1bff gpiof 0x4800 1400 ahb2 0x4800 1400 0x4001 1800 gpioe 0x4800 1000 0x4800 1000 na gpiod 0x4800 0c00 0x4800 0c00 0x4001 1400 gpioc 0x4800 0800 0x4800 0800 0x4001 1000 gpiob 0x4800 0400 0x4800 0400 0x4001 0c00 gpioa 0x4800 0000 0x4800 0000 0x4001 0800 tim1 apb2 0x4001 2c00 na na 0x4001 2c00 adc/adc1 ahb3 0x5000 0000 apb2 0x4001 2400 0x4001 2400 adc2 na na 0x40012 800 adc3 0x5000 0400 na na 0x40013 c00 adc4 na na na na sdadc3 na na apb2 0x4001 6800 na na sdadc2 na na 0x4001 6400 na na sdadc1 na na 0x4001 6000 na na tim19 na na 0x4001 5c00 na na syscfg apb2 (through syscfg) 0x4001 0000 apb2 (through syscfg) 0x4001 0000 apb2 na comp na opamp na na na na peripheral migration AN4228 16/90 docid024110 rev 5 cec apb1 0x4000 7800 apb1 0x4000 7800 apb1 0x4000 7800 dac/dac1 0x4000 7400 0x4000 7400 0x400 07400 dac2 na 0x4000 9800 na i2s2ext apb1 0x4000 3400 apb1 na apb1 na tim14 apb1 na apb1 0x4000 2000 na na tim18 na 0x4000 9c00 na na fsmc registers na na na na ahb 0xa000 0000 usb otg fs na na na na 0x5000 0000 ethernet mac na na na na 0x4002 8000 sdio na na na na 0x4001 8000 tim20 apb2 0x4001 5000 na na na na spi4 apb2 0x4001 3c00 na na na na i2c3 apb1 0x4000 7800 na na na na tim11 na na na na apb2 0x40015 400 tim10 na na na na 0x40015 000 tim9 na na na na 0x40014 c00 tim8 apb2 0x4001 3400 na na 0x40013 400 table 8. ip bus mapping differences between stm32f3 and stm32f1 series (1) (continued) peripheral stm32f30xx stm32f37x stm32f1 series bus base address bus base address bus base address docid024110 rev 5 17/90 AN4228 peripheral migration 89 3.4 reset and clock controller (rcc) interface the main differences related to the rcc (reset and clock controller) in the stm32f3 series versus stm32f1 series are presented in table 9 . can2 na na na na apb1 0x40006 800 can1 apb1 0x4000 6400 apb1 0x4000 6400 0x4000 6400 uart5 0x4000 5000 na na 0x40005000 uart4 0x4000 4c00 na na 0x40004c00 i2s2ext 0x4000 4000 na na na tim13 na na apb1 0x4000 1c00 0x4000 1c00 tim12 na na 0x4000 1800 0x4000 1800 tim5 na na 0x4000 0c00 0x40000 c00 bkp registers na na na na 0x4000 6c00 afio na na na na apb2 0x4001 0000 1. na = not applicable table 8. ip bus mapping differences between stm32f3 and stm32f1 series (1) (continued) peripheral stm32f30xx stm32f37x stm32f1 series bus base address bus base address bus base address table 9. rcc differences between stm32f1 and stm32f3 series rcc stm32f1 series stm32f3 series hse 3 - 25 mhz depending on the product line used 4 - 32 mhz pll ? connectivity line: main pll + 2 plls for i2s, ethernet and otg fs clock ? other product lines: main pll main pll rtc clock source lsi, lse or hse/128 lsi, lse or hse clock divided by 32 peripheral migration AN4228 18/90 docid024110 rev 5 in addition to the differences described in the table above, the following additional adaptation steps may be needed for the migration: ? system clock configuration ? peripheral access configuration ? peripheral clock configuration 3.4.1 system clock configuration when moving from stm32f1 series to stm32f3 series, only a few settings need to be updated in the system clock configuration code; mainly the flash settings (configure the right wait states for the system frequency , prefetch enable/disable) or/and the pll parameters configuration: ? if hse or hsi is used directly as the s ystem clock source, only the flash parameters should be modified. ? if pll (clocked by hse or hsi) is used as the system clock source, the flash parameters and pll configuration need to be updated. table 10 below provides an example of how to port a system clock configuration from stm32f1 to stm32f3 series: ? stm32f100xx value line running at maximum performance: system clock at 24 mhz (pll, clocked by the hse (8 mhz), used as the system clock source), flash with 0 wait states and flash prefetch queue enabled. ? stm32f3 series running at maximum performance: system clock at 72 mhz (pll, clocked by the hse (8 mhz), used as the system clock source), flash with 2 wait states and flash prefetch enabled. note: in stm32f30xxd/e, we can reach the maximum system clock 72 mhz when pll is system clock source and pll clock source is the hsi. in stm32f1 and other stm32f3 series devices, when pll clock source is the hs i, the maximum system clock value is 64 mhz. as shown in table 10 , only the flash settings and pll parameters (code in bold italic ) need to be rewritten to run on stm32f3 series. however, hse, ahb prescaler and the mco clock source mco pin (pa8): ? connectivity line: hsi, hse, pllclk/2, sysclk, pll2, pll3 or xt1 ? other product lines: hsi, hse, pllclk/2 or sysclk stm32f302/303xb/c and stm32f37x: sysclk, hsi, hse, pllclk/2, lse, lsi. stm32f302/301/303x6/x8: sysclk, hsi, hse, pllclk/2 or pllclk, lse, lsi; with the possibility to reduce mco frequency by a configurable divider. internal oscillator measurement / calibration lsi connected to tim5 ch4 ic: can measure lsi with respect to hsi/hse clock ? lse & lsi clocks are indirectly measured through mco by tim16 timer (stm32f30/31xx) and tim14 (stm32f37/38xx) with respect to hsi/hse clock ? hse are indirectly measured through mco using tim16 timer (stm32f30/31xx) and tim14 (stm32f37/38xx) channel 1 input capture with respect to hsi clock. table 9. rcc differences between stm32f1 and stm32f3 series (continued) rcc stm32f1 series stm32f3 series docid024110 rev 5 19/90 AN4228 peripheral migration 89 system clock source configurat ion are left unchanged, and apb prescalers ar e adapted to the maximum apb frequency in the stm32f3 series. note: the source code presented in table 10 is intentionally simplifi ed (timeout in wait loop removed) and is based on the assumption that the rcc and flash registers are at their reset values. for stm32f3xx, you can use the clock configuration tool, stm32f3xx_clock_configuration. xls, to generate a customized system_stm32f3xx.c file containing a system clock configuration routine, depending on your application requirements. peripheral migration AN4228 20/90 docid024110 rev 5 table 10. example of migrating system clock configuration code from stm32f100 to stm32f3xx stm32f100 value line running at 24 mhz (pll as clock source) with 0 wait states stm32f3xx running at 48 mhz (pll as clock source) with 1 wait state /* enable hse -------------------------*/ rcc->cr |= ((uint32_t)rcc_cr_hseon); /* wait till hse is ready */ while((rcc->cr & rcc_cr_hserdy) == 0) { } /* flash configuration --------------*/ /* prefetch on, flash 0 wait state */ flash->acr |= flash_acr_prftbe | flash_acr_latency_0; /*ahb and apb prescaler configuration*/ /* hclk = sysclk */ rcc->cfgr |= (uint32_t)rcc_cfgr_hpre_div1; /* pclk2 = hclk */ rcc->cfgr |= (uint32_t)rcc_cfgr_ppre2_div1; /* pclk1 = hclk */ rcc->cfgr |= (uint32_t)rcc_cfgr_ppre1_div1; /* pll configuration = (hse / 2) * 6 = 24 mhz */ rcc->cfgr |= (uint32_t)(rcc_cfgr_pllsrc_prediv1 | rcc_cfgr_pllxtpre_prediv1_div2 | rcc_cfgr_pllmull6); /* enable pll */ rcc->cr |= rcc_cr_pllon; /* wait till pll is ready */ while((rcc->cr & rcc_cr_pllrdy) == 0) { } /* select pll as system clock source --*/ rcc->cfgr &= (uint32_t)((uint32_t)~(rcc_cfgr_sw)); rcc->cfgr |= (uint32_t)rcc_cfgr_sw_pll; /* wait till pll is used as system clock source */ while ((rcc->cfgr & (uint32_t)rcc_cfgr_sws) != (uint32_t)0x08) { } /* enable hse -------------------------*/ rcc->cr |= ((uint32_t)rcc_cr_hseon); /* wait till hse is ready */ while((rcc->cr & rcc_cr_hserdy) == 0) { } /* flash configuration ----------------*/ /* prefetch on, flash 1 wait state */ flash->acr |= flash_acr_prftbe | flash_acr_latency; /* ahb and apb prescaler configuration-*/ /* hclk = sysclk */ rcc->cfgr |= (uint32_t)rcc_cfgr_hpre_div1; /* pclk = hclk */ rcc->cfgr |= (uint32_t)rcc_cfgr_ppre_div1; /* pll configuration = hse * 6 = 48 mhz -*/ rcc->cfgr |= (uint32_t)(rcc_cfgr_pllsrc_prediv1 | rcc_cfgr_pllxtpre_prediv1 | rcc_cfgr_pllmull6); /* enable pll */ rcc->cr |= rcc_cr_pllon; /* wait till pll is ready */ while((rcc->cr & rcc_cr_pllrdy) == 0) { } /* select pll as system clock source ---*/ rcc->cfgr |= (uint32_t)rcc_cfgr_sw_pll; /* wait till pll is used as system clock source */ while ((rcc->cfgr & (uint32_t)rcc_cfgr_sws) != (uint32_t)rcc_cfgr_sws_pll) { } docid024110 rev 5 21/90 AN4228 peripheral migration 89 3.4.2 peripheral acce ss configuration since the address mapping of some peripherals has been changed in stm32f3 series versus stm32f1 series, you need to use differen t registers to [enable/disable] or [enter/exit] the peripheral [clock] or [from reset mode]. to configure the access to a given peripheral, you have first to k now to which bus this peripheral is connected; refer to table 8 then, depending on the action needed, program the right register as described in table 11 above. for example, if usart1 is connected to the apb2 bus, to enable the u sart1 clock you have to co nfigure apb2enr register as follows: rcc->apb2enr |= rcc_apb2enr_usart1en; table 11. rcc registers used for peripheral access configuration bus register comments ahb rcc_ahbrstr used to [enter/exit] the ahb peripheral from reset rcc_ahbenr used to [enable/disable] the ahb peripheral clock apb1 rcc_apb1rstr used to [enter/exit] the apb1 peripheral from reset rcc_apb1enr used to [enable/dis able] the apb1 per ipheral clock apb2 rcc_apb2rstr used to [enter/exit] the apb2 peripheral from reset rcc_apb2enr used to [enable/dis able] the apb2 per ipheral clock peripheral migration AN4228 22/90 docid024110 rev 5 3.4.3 peripheral clock configuration some peripherals have a dedicated clock source independent from the system clock, and used to generate the clock required for them to operate: ? adc in stm32f30xx devices, the adc feat ures two possible clock sources: ? the adc clock can be derived from the pll output. it can reach 72 mhz and can be divided by the following prescalers values: 1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, or 256. it is asynchronous to the ahb clock ? the adc clock can also be derived from the ahb clock of the adc bus interface, divided by a programmable factor (1, 2 or 4). when the programmable factor is 1, the ahb prescaler must be equal to '1'. ? sdadc stm32f37xx sdadc clock source is derive d from the system clock divided by a wide range of prescalers, ranging from 2 to 48. ? rtc in stm32f3 series, the rtc features three possible clock sources: ? the first one is based on the hse clock; a prescaler divides its frequency by 32 before going to the rtc ? the second one is the lse oscillator ? the third clock source is th e lsi rc with a value of 40 khz. ? timx the timers clock frequencies are automatic ally defined by hardware. there are two cases: ? if the apb prescaler equals 1, the timer clock frequencies are set to the same frequency as that of the apb domain ? otherwise, they are set to twice ( 2) the frequency of the apb domain. pll clock source a clock issued from the pll (pllclkx2) can be selected for timx (x = 1, 8 on the stm32f303xb/c, x = 1 on the stm32f303x6/8, x = 1, 15, 16, 17 on the stm32f302/301x6/8), x = 1,2,3,4,8,15,16,17,20 in the stm32f303xd/e. this configuration allows to feed timx with a frequency up to 144 mhz when the system clock source is the pll. in this configuration: ? on the stm32f303/302xb/c, ahb and apb2 prescalers are set to 1 i.e. ahb and apb2 clocks are not divided wit h respect to the system clock ? on the stm32f303/302/ 301x6/8 and stm32f302/ 303xd/e, ahb or apb2 subsystem clocks are not divided by more than 2 cumulatively with respect to the system clock. ? i2s in stm32f30xx devices, the i2s features 2 possible clock sources: ? the first one is the system clock ? the second one comes from the external clock provided on i2s_ckin pin. docid024110 rev 5 23/90 AN4228 peripheral migration 89 3.5 dma interface stm32f1 and stm32f3 series use the same fully compatible dma controller. the table below presents the correspondence bet ween the dma requests of the peripherals in stm32f1 series and stm32f3 series. the stm32f303/302xb/c has two dma controllers with 12 channels in total (as stm32f1), the stm32f302/301/303x6/8 has 1 dma controller with 7 channels table 12. dma request differences between stm32f3xx and stm32f1xx (1) peripheral dma request stm32f1xx stm32f30xx (2) stm32f37x adc2 adc2 na dma2_channel1 dma2_channel3 na adc3 adc3 dma2_channel5 dma2_channel5 na adc4 adc4 na dma2_channel2 dma2_channel4 na sdadc sdadc1 sdadc2 sdadc3 na na dma2_channel3 dma2_channel4 dma2_channel5 spi4 (3) spi4_rx spi4_tx na dma2_channel4 dma2_channel5 na tim6/dac1_ch1 tim7/dac1_ch2 dac1_channel1 dac1_channel2 dma2_channel3 dma2_channel4 dma2_channel3 dma1_channel3 dma2_channel4 dma1_channel4 dma2_channel3 dma1_channel3 dma1_channel4 dma2_channel4 tim18/dac2 dac2_channel1 dac2_channel2 na na dma2_channel5 dma1_channel5 uart4 uart4_rx uart4_tx dma2_channel3 dma2_channel5 dma2_channel3 dma2_channel5 na uart5 uart5_rx uart5_tx dma2_channel4 dma2_channel1 na na i2c3 (4) i2c3_rx i2c3_rx na dma1_channel2 dma1_channel1 na sdio sdio dma2_channel4 na na tim1 tim1_up tim1_ch1 tim1_ch2 tim1_ch3 tim1_ch4 tim1_trig tim1_com dma1_channel5 dma1_channel2 dma1_channel3 dma1_channel6 dma1_channel4 dma1_channel4 dma1_channel4 dma1_channel5 dma1_channel2 dma1_channel3 dma1_channel6 dma1_channel4 dma1_channel4 dma1_channel4 na peripheral migration AN4228 24/90 docid024110 rev 5 tim8 tim8_up tim8_ch1 tim8_ch2 tim8_ch3 tim8_ch4 tim8_trig tim8_com dma2_channel1 dma2_channel3 dma2_channel5 dma2_channel1 dma2_channel2 dma2_channel2 dma2_channel2 dma2_channel1 dma2_channel3 dma2_channel5 dma2_channel1 dma2_channel2 dma2_channel2 dma2_channel2 na tim5 tim5_up tim5_ch1 tim5_ch2 tim5_ch3 tim5_ch4 tim5_trig dma2_channel2 dma2_channel5 dma2_channel4 dma2_channel2 dma2_channel1 dma2_channel1 na dma2_channel2 dma2_channel5 dma2_channel4 dma2_channel2 dma2_channel1 dma2_channel1 tim16 tim16_up tim16_ch1 dma1_channel6 dma1_channel6 dma1_channel3 dma1_channel3 dma1_channel3 dma1_channel6 dma1_channel3 dma1_channel6 tim17 tim17_up tim17_ch1 dma1_channel7 dma1_channel7 dma1_channel1 dma1_channel1 dma1_channel1 dma1_channel7 dma1_channel1 dma1_channel7 tim19 tim19_up tim19_ch1 tim19_ch2 tim19_ch3 tim19_ch4 na na dma1_channel4 dma2_channel5 dma1_channel2 dma1_channel1 dma1_channel1 tim20 (3) tim20_up tim20_ch1 tim20_ch2 tim20_ch3 tim20_ch4 tim20_trig tim20_com na dma2_channel3 dma2_channel1 dma2_channel2 dma2_channel3 dma2_channel4 dma2_channel4 dma2_channel4 na 1. na = not applicable. 2. dma2 channels available only on stm32f303/302xb/c/d/e. 3. only on stm32f303/302xd/e 4. only on stm32f302/301x6/x8 and stm32f303/302xd/e. table 12. dma request differences between stm32f3xx and stm32f1xx (1) (continued) peripheral dma request stm32f1xx stm32f30xx (2) stm32f37x docid024110 rev 5 25/90 AN4228 peripheral migration 89 3.6 interrupt vectors table 13 presents the interrupt vectors in stm32f3 series versus stm32f1 series. the switch from cortex-m3 to cortex-m4 indu ces an increase of the number of vector interrupts. this leads to many differences between the two devices. table 13. interrupt vector differences between stm32f3 and stm32f1 series position stm32f1 stm32f30xx stm32f37xx 2 tamper tamp_stamp tamp_stamp 3 rtc rtc_wkup rtc_wkup 18 adc1_2 adc1_2 adc1 19 can1_tx / usb_hp_can_tx usb_hp/can_tx can_tx 20 can1_rx0 / usb_lp_can_rx0 usb_lp/can_rx0 can_rxd 21 can1_rx1 can1_rx1 can_rxi 22 can1_sce can1_sce can_sce 23 exti9_5 exti9_5 exti9_5 24 tim1_brk / tim1_brk _tim9 tim1_brk / tim15 tim15 25 tim1_up / tim1_up_tim10 tim1_up / tim16 tim16 26 tim1_trg_com / tim1_trg_com_tim11 tim1_trg_com / tim17 tim17 27 tim1_cc tim1_cc tim18_dac2 42 otg_fs_wkup / usbwakeup usb_wkup cec 43 tim8_brk / tim8_brk_tim12 (1) tim8_brk tim12 44 tim8_up / tim8_up_tim13 (1) tim8_up tim13 45 tim8_trg_com / tim8_trg_com_tim14 (1) tim8_trg_com tim14 46 tim8_cc tim8_cc reserved 47 adc3 adc3 reserved 48 fsmc reserved reserved 49 sdio reserved reserved 50 tim5 reserved tim5 52 uart4 uart4 reserved 53 uart5 uart5 reserved 59 dma2_channel4 / dma2_channel4_5 (1) dma2_ch4 dma2_ch4 peripheral migration AN4228 26/90 docid024110 rev 5 3.7 gpio interface the stm32f3 gpio peripheral embeds new features compared to stm32f1 series, below the main features: ? gpio mapped on ahb bus for better performance ? i/o pin multiplexer and mapping: pins are connected to on-chip peripherals/modules through a multiplexer that allows only one pe ripheral alternate function (af) connected to an i/o pin at a time. in this way, there can be no conflict between peripherals sharing the same i/o pin. ? more possibilities and featur es for i/o configuration the stm32f3 series gpio peripheral is a new design and thus the architecture, features and registers are different from the gpio peripheral in the stm32f1 series. any code 61 eth adc4 sdadc1 62 eth_wkup reserved sdadc2 63 can2_tx reserved sdadc3 64 can2_rx01 comp123 comp1_2 65 can2_rx1 comp456 reserved 66 can2_sce comp7 reserved 67 otg_fs reserved reserved 72 reserved i2c3_ev (only on stm32f302/301x6/x8) and stm32f303/302xd/e reserved 73 reserved i2c3_er (only on stm32f302/301x6/x8 and stm32f302/f303xd/e) reserved 76 reserved usb_wkup usb_wkup 77 reserved tim20_brk (only on stm32f303xd/e) reserved 78 reserved tim20_up (only on stm32f303xd/e) tim19 global interrupt 79 reserved tim20_trg_com (only on stm32f303xd/e) reserved 80 reserved tim20_cc (only on stm32f303xd/e) reserved 81 reserved fpu fpu 84 reserved spi4 (only on stm32f303xd/e) reserved 1. depending on the product line used. table 13. interrupt vector differences between stm32f3 and stm32f1 series (continued) position stm32f1 stm32f30xx stm32f37xx docid024110 rev 5 27/90 AN4228 peripheral migration 89 written for the stm32f1 series using the gpio needs to be rewritten to run on stm32f3 series. for more information about stm32f3 gpio pr ogramming and usage, please refer to the ?i/o pin multiplexer and mapping? section in the gpio chapter of the stm32f3xx reference manuals (rm0313 and rm0316). the table below presents the differences between gpios in the stm32f1 series and stm32f3 series. 3.7.1 alternate function mode stm32f1 series the configuration to use an i/o as an altern ate function depends on the peripheral mode used. for example, the usart tx pin should be configured as an alternate function push- pull, while the usart rx pin should be config ured as input floating or input pull-up. to optimize the number of peripheral i/o functions for different device packages (especially those with a low pin count), it is possible to remap some alternate functions to other pins by software. for example, the usart2_rx pin can be mapped on pa3 (default remap) or pd6 (by software remap). stm32f3 series whatever the peripheral mode used, the i/o must be configured as an alternate function, then the system can use the i/o in the proper way (input or output). table 14. gpio differences between stm32f1 and stm32f3 series gpio stm32f1 series stm32f3 series general purpose output pp od pp pp + pu pp + pd od od + pu od + pd alternate function output pp od pp pp + pu pp + pd od od + pu od + pd alternate function selection to optimize the number of peripheral i/o functions for different device packages, it is possible to re map some alternate functions to some other pins (software remap). highly flexible pin multiplexing allows no conflict between peripherals sharing the same i/o pin. max io toggle frequency 18 mhz 36 mhz peripheral migration AN4228 28/90 docid024110 rev 5 the i/o pins are connected to on-chip peripher als/modules through a mu ltiplexer that allows only one peripheral alternate function to be connected to an i/o pin at a time. in this way, there can be no conflict between peripherals sh aring the same i/o pin. each i/o pin has a multiplexer with 16 alternate function inputs (af0 to af15) that can be configured through the gpiox_afrl and gpiox_afrh registers: the peripheral alternate functions are mapped by configuring af0 to af15. in addition to this flexible i/o multiplexing architecture, each peripheral has alternate functions mapped on different i/o pins to optimize the number of peripheral i/o functions for different device packages. for example, the usart2_rx pin can be mapped on pa3 or pa15 pin. note: please refer to the ?alternate function ma pping? table in the stm32f3x datasheet for the detailed mapping of the system and the pe ripheral alternate function i/o pins. 1. configuration procedure ? configure the desired i/o as an altern ate function in the gpiox_moder register ? select the type, pull-up/pull-down and output speed via the gpiox_otyper, gpiox_pupdr and gpiox_ospeeder registers, respectively ? connect the i/o to the desired afx in the gpiox_afrl or gpiox_afrh register 3.8 exti source selection in stm32f1 devices, the selection of the ext i line source is performed through extix bits in afio_exticrx registers, while in stm32f3 series this selection is done through extix bits in syscfg_exticrx registers. only the mapping of the exticrx registers has been changed, without any changes to the meaning of the extix bits. however, the maxi mum range of extix bit values is 0b0101 as the last port is f (in stm32f1 series, the maximum value is 0b0110). 3.9 flash interface the table below presents the difference between the flash interface of stm32f1 series and stm32f3 series. table 15. flash differences between stm32f1 and stm32f3 series feature stm32f1 series stm32f3 series main/program memory granularity page size = 2 kbytes except for low and medium density page size = 1 kbyte page size = 2 kbytes system memory start address 0x1fff f000 0x1fff d800 end address 0x1fff f7ff 0x1fff f7ff flash interface programming procedure same for all product lines same as stm32f1 series for flash program and erase operations. different from stm32f1 series for option byte programming docid024110 rev 5 29/90 AN4228 peripheral migration 89 3.10 sar adc interface stm32f37xx adc interface is id entical to stm32f1xx, while a different adc interface is used in stm32f30xx devices. the table below presents the differences between the adc interface of stm32f1 series and stm32f30x lines; these differences are the following: ? new digital interface ? new architecture and new features read protection unprotection read protection disable rdp = 0xa55a level 0 no protection rdp = 0xaa protection read protection enable rdp != 0xa55a level 1 memory protection rdp != (level 2 & level 0) ? level 2: lvl 1 + debug disabled write protection protection by 4-kbyte block protection by a granularity of 2 pages user option bytes stop stop standby standby wdg wdg na ram_parity_check na vdda_monitor na nboot1 na sdadc12_vdd monitor (available only on stm32f37x) table 15. flash differences between stm32f1 and stm32f3 series (continued) feature stm32f1 series stm32f3 series table 16. adc differences between stm32f1 series and stm32f30x lines adc stm32f1 series stm32f30xxb/c stm32f302x6/8/ stm32f301x6/8 stm32f303x6/8 stm32f30xxd/e instances adc1 / adc2 / adc3 adc1 / adc2 / adc3 / adc4 adc1 adc1 / adc2 adc1 / adc2 / adc3 / adc4 maximum sampling frequency 1 msps 5.1 msps 5.1 msps 5.1 msps 5.1 msps number of channels up to 21 up to 39 + 7 internal up to 15 + 3 internal up to 21 + 4 internal up to 40 + 7 internal resolution 12 bits configurable to 12, 10, 8, and 6 bits configurable to 12, 10, 8, and 6 bits configurable to 12, 10, 8, and 6 bits configurable to 12, 10, 8, and 6 bits peripheral migration AN4228 30/90 docid024110 rev 5 note: on stm32f37xxx, the adc channels mapping is the same as in stm32f10xxx. conversion modes single / continuous / scan / discontinuous / dual mode single / continuous / scan / discontinuous / dual mode single / continuous / scan / discontinuous mode single / continuous / scan / discontinuous / dual mode single / continuous / scan / discontinuous / dual mode supply requirement 2.4 v to 3.6 v 2.0 to 3.6 v 2.0 to 3.6 v 2.0 to 3.6 v 2.0 to 3.6 v table 16. adc differences between stm32f1 series and stm32f30x lines (continued) adc stm32f1 series stm32f30xxb/c stm32f302x6/8/ stm32f301x6/8 stm32f303x6/8 stm32f30xxd/e table 17. adc channels mapping differences stm32f103xx stm32f303xb/c/d/e stm32f302/301x6/8 stm32f303x6/8 pa0 adc123_in0 adc1_in1 adc1_in1 adc1_in1 pa1 adc123_in1 adc1_in2 adc1_in2 adc1_in2 pa2 adc123_in2 adc1_in3 adc1_in3 adc1_in3 pa3 adc123_in3 adc1_in4 adc1_in4 adc1_in4 pa4 adc12_in4 adc2_in1 adc1_in5 adc2_in1 pa5 adc12_in5 adc2_in2 - adc2_in2 pc0 adc123_in10 adc12_in6 adc1_in6 adc12_in6 pc1 adc123_in11 adc12_in7 adc1_in7 adc12_in7 pc2 adc123_in12 adc12_in8 adc1_in8 adc12_in8 pc3 adc123_in13 adc12_in9 adc1_in9 adc12_in9 pc4 adc12_in14 adc2_in5 - adc2_in5 pc5 adc12_in15 adc2_in11 - adc2_in11 pa6 adc12_in6 adc2_in3 adc1_in10 adc2_in3 pb0 adc12_in8 adc3_in12 adc1_in11 adc1_in11 pb1 adc12_in9 adc3_in14 adc1_in12 adc1_in12 pb2 - adc2_in12 - adc2_in12 pb11 - adc12_in14 (1) 1. only on stm32f303/302xd/e. adc1_in14 - pb12 - adc2_in13 - adc2_in13 pb13 - adc3_in5 adc1_in13 adc1_in13 pb14 - adc4_in4 - adc2_in14 pb15 - adc4_in5 - adc2_in15 pa7 adc12_in7 adc2_in4 adc1_in15 adc2_in4 docid024110 rev 5 31/90 AN4228 peripheral migration 89 3.11 pwr interface in stm32f3 series the pwr controller presents some differences vs. stm32f1 series, these differences are summarized in the table below. however, the programming interface is unchanged. table 18. pwr differences between stm32f1 and stm32f3 series pwr stm32f1 series stm32f3 series power supplies ?v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through vdd pins. ?v ssa , v dda = 2.0 to 3.6 v: external analog power supplies for adc, reset blocks, rcs and pll. vdda and vssa must be connected to vdd and vss, respectively. ?v bat = 1.8 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when vdd is not present. ?v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through vdd pins. ?v ssa , v dda = 2.0 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll. v ssa must be connected to v ss . ?v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when vdd is not present. ?v sssd , v ddsdx = 2.0 to 3.6v: external analog power supplies for sdadcx peripherals and some gpios (stm32f37xx only). battery backup domain ? backup registers ?rtc ?lse ? pc13 to pc15 i/os ? backup registers ?rtc ?lse ? rcc backup domain control register wake-up sources standby mode ? wkup pin rising edge standby mode ? wkup1, wkup2 or wkup3 pin rising edge peripheral migration AN4228 32/90 docid024110 rev 5 3.12 real-time clo ck (rtc) interface the stm32f3 series embeds a new rtc peripheral versus the stm32f1 series. the architecture, features and programming interface are different. as a consequence, the stm32f3 series rtc programming procedures and registers are different from those of the stm32f1 series, so any code written for the stm32f1 series using the rtc needs to be rewritten to run on stm32f3 series. the stm32f3 series rtc provides best-in-class features: ? bcd timer/counter ? time-of-day clock/calendar featuring subsecond precision with programmable daylight saving compensation ? two programmable alarms ? digital calibration circuit ? time-stamp function for event saving ? accurate synchronization with an external clock using the subsecond shift feature. ? stm32f30xx/stm32f37xx feature 16 and 32 backup registers, respectively (64 and 128 bytes) which are reset when a tamper detection event occurs for more information about stm32f3?s rtc features, please refer to rtc chapter of stm32f30/31xx and stm32f37/38xx reference manuals (rm0316 and rm0313). for advanced information about the rtc programming, please refer to application note an3371 using the stm32 hw real-time clock (rtc) . 3.13 spi interface the stm32f3 series embeds a new spi peripheral versus the stm32f1 series. the architecture, features and programming interface are modified to introduce new capabilities. as a consequence, the stm32f3 series spi programming procedures and registers are similar to those of the stm32f1 series but with new features. the code written for the stm32f1 series using the spi needs little rework to run on stm32f3 series, if it did not use new capabilities. the stm32f3 series spi provides best-in-class added features: ? enhanced nss control - nss pulse mode (nssp) and ti mode ? programmable data frame length from 4-bit to 16-bit ? two 32-bit tx/rx fifo buffers with dma ca pability and data packing access for frames fitted into one byte (up to 8-bit) ? 8-bit or 16-bit crc calculation length for 8-bit and 16-bit data. furthermore, the spi peripheral, available in the stm32f3 series, fixes the crc limitation present in the stm32f1 series. for more information about stm32f3 spi features, please refer to spi chapter of stm32f30/31xx and stm32f37/38xx reference manuals (rm0316 and rm0313). docid024110 rev 5 33/90 AN4228 peripheral migration 89 3.14 i2c interface the stm32f3 series embeds a new i2c peripheral versus the stm32f1 series. the architecture, features and programming interface are different. as a consequence, the stm32f3 series i2c programming procedures and registers are different from those of the stm32f1 series, so any code written for the stm32f1 series using the i2c needs to be rewritten to run on stm32f3 series. the stm32f3 series i2c provides best-in-class new features: ? communication events managed by hardware. ? programmable analog and digital noise filters. ? independent clock source: hsi or sysclk. ? wake-up from stop mode. ? fast mode + (up to 1mhz) with 20ma i/o output current drive. ? 7-bit and 10-bit addressing mode, multiple 7-bit slave address support with configurable masks. ? address sequence automatic sending (bot h 7-bit and 10-bit) in master mode. ? automatic end of communication management in master mode. ? programmable hold and setup times. ? command and data acknowledge control. for more information about stm32f3 i2c f eatures, please refer to i2c chapter of stm32f30/31xx and stm32f37/38xx reference manuals (rm0316 and rm0313). peripheral migration AN4228 34/90 docid024110 rev 5 3.15 usart interface the stm32f3 series embeds a new usart peripheral versus the stm32f1 series. the architecture, features and prog ramming interface are modified to introdu ce new capabilities. as a consequence, the stm32f3 series usar t programming procedures and registers are modified from those of the stm32f1 series, so any code written for the stm32f1 series using the usart needs to be updated to run on stm32f3 series. the stm32f3 series usart provides best-in-class added features: ? a choice of independent clock sources allowing ? uart functionality and wake-up from low power modes, ? convenient baud-rate programming independently of the apb clock reprogramming. ? smartcard emulation capability: t=0 with auto retry and t=1 ? swappable tx/rx pin configuration ? binary data inversion ? tx/rx pin active level inversion ? transmit/receive enable acknowledge flags ? new interrupt sources with flags: ? address/character match ? block length detection and timeout detection ? timeout feature ? modbus communication ? overrun flag disable ? dma disable on reception error ? wake-up from stop mode ? auto baud rate detection capability ? driver enable signal (de) for rs485 mode for more information about stm32f3 usart features, please refer to usart chapter in the corresponding reference manual. docid024110 rev 5 35/90 AN4228 peripheral migration 89 3.16 cec interface the cec interface is available only on stm32f37xx devices. the stm32f3 series embeds a new cec peripheral versus the stm32f1 series. the architecture, features and prog ramming interface are modified to introdu ce new capabilities. as a consequence, the stm32f3 series cec programming procedures and registers are different from those of the stm32f1 series, so any code written for the stm32f1 series using the cec needs to be rewritten to run on stm32f3 series. the stm32f3 series cec provides best-in-class added features: ? 32 khz cec kernel with dual clock ?lse ? hsi/244 ? reception in listen mode ? rx tolerance margin: standard or extended ? arbitration (signal free time): sta ndard (by h/w) or aggressive (by s/w) ? arbitration lost detected flag/interrupt ? automatic transmission retry supported in case of arbitration lost ? multi-address configuration ? wake-up from stop mode ? receive error detection ? bit rising error (with stop reception) ? short bit period error ? long bit period error ? configurable error bit generation ? on bit rising error detection ? on long bit period error detection ? transmission under run detection ? reception overrun detection the following features present in the stm32f1 series are now handled by the new stm32f3 series cec features and thus are no more available. ? bit timing error mode & bit period error mode, by the new error handler ? configurable prescaler frequency divi der, by the cec fixed kernel clock for more information about stm32f3 cec features, please refer to cec chapter of stm32f37/38xx reference manual (rm0313). firmware migration using the library AN4228 36/90 docid024110 rev 5 4 firmware migration using the library this section describes how to migrate an application based on stm32f1xx standard peripherals library to the stm32f3xx standard peripherals library. the stm32f1xx and stm32f3xx libraries have the same architecture and are cmsis compliant; they use the same driver nami ng and the same apis for all compatible peripherals. only a few peripheral drivers need to be updated to migrate the application from an stm32f1 series to an stm32f3 series product. note: in the rest of this section (unless otherwis e specified), the term ?stm32f3xx library? is used to refer to the stm32f3xx standard peripherals library, and the term ?stm32f10x library? is used to refer to the stm32f10x standard peripherals library. stm32f3xx devices refers to stm32f30/3 1xxx devices and stm32f37/38xxx devices. 4.1 migration steps to update your application code to run on stm32f3xx library, follow the steps listed below: 1. update the toolchain startup files: a) project files: device connections and flash memory loader. these files are provided with the latest version of yo ur toolchain that supports stm32f3xx devices. for more information, please refer to your toolchain documentation. b) linker configuration and vector table location files: these files are developed following the cmsis standard and are included in the stm32f3xx library install package under the following directory: libraries\cmsis\de vice\st\stm32f3xx. 2. add stm32f3xx library source files to the application sources: a) replace the stm32f10x_conf.h file of your application by stm32f3xx_conf.h provided in stm32f3xx library. b) replace the existing stm32f10x_it.c/stm32f10x_it.h files in your application by stm32f3xx_it.c/stm32f3xx_it.h provided in stm32f3xx library. 3. update the part of your application co de that uses the pwr, gpio, flash, adc and rtc drivers. further details are provided in the next section. note: the stm32f3xx library comes with a rich set of examples (around 76 in total) demonstrating how to use the different peripherals. they are located under project\stm32f3xx_stdperiph_examples\. 4.2 rcc driver 4.2.1 system clock configuration as presented in section 3.4: reset and clock co ntroller (rcc) interface , the stm32f3 and stm32f1 series have the same clock sources and configuration procedures. however, there are some differences related to the product voltage range, pll configuration, maximum frequency and flash wait state config uration. thanks to the cmsis layer, these differences are hidden from the application code: only replace the system_stm32f10x.c file by system_stm32f3xx.c file. this file provides an implementation of systeminit() function docid024110 rev 5 37/90 AN4228 firmware migration using the library 89 used to configure the microcontroller system at start-up and before branching to the main() program. note: for stm32f3xx, you can use the clock configuration tool, stm32f3xx_clock_configuration.xls, to generate a customized systeminit() function depending on your application requirements. for more information, refer to an4152 ?clock configuration tool for stm32f30xx microcontrolle rs? and to an4132 clock configuration tool for stm32f37xx microcontrollers?. 4.2.2 peripheral acce ss configuration as presented in section 3.4: reset and clock co ntroller (rcc) interface , you need to call different functions to enable/disable the peripheral clock or enter/exit from reset mode. as an example, gpioa is mapped on ah b bus on stm32f3 series (apb2 bus on stm32f1 series). to enable its clock in the stm32f1 series, use _ahbperiphclockcmd(_ahbperiph_gpioa, enable) instead of: _apb2periphclockcmd(_apb2periph_gpioa, enable); refer to table 8 for the peripheral bus mapping changes between stm32f3 and stm32f1 series. 4.2.3 peripheral clock configuration some stm32f3xx peripherals support dual clock features. the table below summarizes the clock sources for these ips in comp arison with stm32f10x peripherals. table 19. stm32f10x and stm32f3xx clock source api correspondence peripherals source clock in stm32f10x source clock in stm32f3xx cec apb1 clock with prescaler ? hsi/244: by default ?lse ? apb clock: clock for the digital interface (used for register read /write access). this clock is equal to the apb2 clock. i2c apb1 clock i2c can be clocked with: ? system clock ?hsi spi/i2s system clock ? apb clock ? external clock for i2s clock source (1) 1. it is applicable only for stm32f30xx devices. usart ? usart1 can be clocked by pclk2 (72 mhz max) ? other usarts can be clocked by pclk1 (36 mhz max) usart can be clocked with: ? system clock ? lse clock ? hsi clock ? apb clock (pclk) firmware migration using the library AN4228 38/90 docid024110 rev 5 4.3 flash driver the table below shows the flash driver api correspondence between stm32f10x and stm32f3xx libraries. you can easily update your application code by replacing stm32f10x functions by the corresponding function in the stm32f3xx library. the api compatibility has been ma intained as much as possible. however legacy define statements are available within the flash driver in case api or parameter names change. table 20. stm32f10x and stm32f3xx flash driver api correspondence stm32f10x flash driver api stm32f3xx flash driver api interface configuration void flash_setlatency(uint32_t flash_latency); void flash_setlatency(uint32_t flash_latency); void flash_prefetchbuffercmd(uint32_t flash_prefetchbuffer); void flash_prefetchbuffercmd(functionalstate newstate); void flash_halfcycleaccesscmd(uint32_t flash_halfcycleaccess); void flash_halfcycleacce sscmd(functionalstate newstate); memory programming void flash_unlock(void); void flash_unlock(void); void flash_lock(void); void flash_lock(void); flash_status flash_e rasepage(uint32_t page_address); flash_status flash_erasepage(uint32_t page_address); flash_status flash_eraseallpages(void); flash_status flash_eraseallpages(void); flash_status flash_programword(uint32_t address, uint32_t data); flash_status flash_programword(uint32_t address, uint32_t data); flash_status flash_programhalfword(uint32_t address, uint16_t data); flash_status flash_programhalfword(uint32_t address, uint16_t data); docid024110 rev 5 39/90 AN4228 firmware migration using the library 89 option byte programming na void flash_ob_unlock(void); na void flash_ob_lock(void); flash_status flash_programoptionb ytedata(uint32_t address, uint8_t data); flash_status flash_programoptionbytedata(uint32_t address, uint8_t data); flash_status flash_enablewriteprotection(uint32_t flash_pages); flash_status flash_ob_enablewrp(uint32_t ob_wrp); flash_status flash_readoutprotection(functionalstate newstate); flash_status flash_ob_rdpconfig(uint8_t ob_rdp); flash_status flash_useroptionbyteconfig(uint16_t ob_iwdg, uint16_t ob_stop, uint16_t ob_stdby); flash_status flash_ob_userconfig(uint8_t ob_iwdg, uint8_t ob_stop, uint8_t ob_stdby); na flash_status flash_ob_launch(void); na flash_status flash_ob_writeuser(uint8_t ob_user); na flash_status flash_ob_bootconfig(uint8_t ob_boot1); na flash_status flash_ob_vddaconfig(uint8_t ob_vdda_analog); na flash_status flash_ob_sramparityconfig(uint8_t ob_sram_parity); uint32_t flash_getus eroptionbyte(void); uint8_t flash_ob_getuser(void); uint32_t flash_getwriteprotectionoptionbyte(void); uint16_t flash_ob_getwrp(void); flagstatus flash_getreadoutprotectionstatus(void); flagstatus flash_ob_getrdp(void); flash_status flash_eraseoptionbytes(void); flash_status flash_ob_erase(void); table 20. stm32f10x and stm32f3xx flash driver api correspondence (continued) stm32f10x flash driver api stm32f3xx flash driver api firmware migration using the library AN4228 40/90 docid024110 rev 5 4.4 crc driver the table below shows the crc driver api correspondence between stm32f10x and stm32f3xx libraries. interrupts and flags management flagstatus flash_get flagstatus(uint32_t flash_flag); flagstatus flash_getflagstatus(uint32_t flash_flag); void flash_clearflag(uint32_t flash_flag); void flash_clearflag(uint32_t flash_flag); flash_status flash_getstatus(void); flash_status flash_getstatus(void); flash_status flash_waitforlastoperation(uint32_t timeout); flash_status flash_waitforlastoperation(void); void flash_itconfig(uint32_t flash_it, functionalstate newstate); void flash_itconfig(uint32_t flash_it, functionalstate newstate); flagstatus flash_getprefetchbufferstatus(void); na table 20. stm32f10x and stm32f3xx flash driver api correspondence (continued) stm32f10x flash driver api stm32f3xx flash driver api color key: = new function = same function, but api was changed = function not available (na) table 21. stm32f10x and stm32f3xx crc driver api correspondence stm32f10x crc driver api stm32f3xx crc driver api configuration na void crc_deinit(void); void crc_resetdr(void); void crc_resetdr(void); na void crc_polynomialsizeselect(uint32_t crc_polsize); na void crc_reverseinputdataselect(uint32_t crc_reverseinputdata); na void crc_reverseoutputdatacmd(functionalstate newstate); na void crc_setpolynomial(uint32_t crc_pol); na void crc_setinitregister(uint32_t crc_initvalue); docid024110 rev 5 41/90 AN4228 firmware migration using the library 89 4.5 gpio configuration update this section explains how to update the conf iguration of the various gpio modes when porting the application code from stm32f1 to stm32f3 series. 4.5.1 output mode the example below shows how to configure an i/o in output mode (for example to drive a led) in stm32f1 series: gpio_initstructure.gpio_pin = gpio_pin_x; gpio_initstructure.gpio_speed = gpio_speed_xxmhz; /* 2, 10 or 50 mhz */ gpio_initstructure.gpio_mode = gpio_mode_out_pp; gpio_init(gpioy, &gpio_initstructure); in stm32f3 series, you have to update this code as follows: gpio_initstructure.gpio_pin = gpio_pin_x; gpio_initstructure.gpio_mode = gpio_mode_out; gpio_initstructure.gpio_otype = gpio_otype_pp; /*push-pull or open drain*/ gpio_initstructure.gpio_pupd = gpio_pupd_up; /*none, pull-up or pull-down*/ gpio_initstructure.gpio_speed = gpio_speed_xxmhz; /* 10, 2 or 50mhz */ gpio_init(gpioy, &gpio_initstructure); computation uint32_t crc_calccrc(uint32_t crc_data ); uint32_t crc_calccrc(uint32_t crc_data); na uint32_t crc_calccrc16bits(uint16_t crc_data); na uint32_t crc_calccrc8bits(uint8_t crc_data); uint32_t crc_calcblock crc(uint32_t pbuffer[], uint32_t bufferlength); uint32_t crc_calcblockcrc(uint32_t pbuffer[], uint32_t bufferlength); uint32_t crc_getcrc(void ); uint32_t crc_getcrc(void); idr access void crc_setidregister(uint8_t crc_idvalue); v oid crc_setidregister(uint8_t crc_idvalue); uint8_t crc_getidregister(void); uin t8_t crc_getidregister(void); table 21. stm32f10x and stm32f3xx crc driver api correspondence (continued) stm32f10x crc driver api stm32f3xx crc driver api color key: = new function = same function, but api was changed = function not available (na) firmware migration using the library AN4228 42/90 docid024110 rev 5 4.5.2 input mode the example below shows how to configure an i/ o in input mode (for example to be used as an exti line) in stm32f1 series: gpio_initstructure.gpio_pin = gpio_pin_x; gpio_initstructure.gpio_mode = gpio_mode_in_floating; gpio_init(gpioy, &gpio_initstructure); in stm32f3 series, you have to update this code as follows: gpio_initstructure.gpio_pin = gpio_pin_x; gpio_initstructure.gpio_mode = gpio_mode_in; gpio_initstructure.gpio_pupd = gpio_pupd_nopull; /* none, pull-up or pull- down */ gpio_init(gpioy, &gpio_initstructure); 4.5.3 analog mode the example below shows how to configure an i/o in analog mode (for example, an adc or dac channel) in stm32f1 series: gpio_initstructure.gpio_pin = gpio_pin_x; gpio_initstructure.gpio_mode = gpio_mode_ain; gpio_init(gpioy, &gpio_initstructure); in stm32f3 series, you have to update this code as follows: gpio_initstructure.gpio_pin = gpio_pin_x ; gpio_initstructure.gpio_mode = gpio_mode_an; gpio_initstructure.gpio_pupd = gpio_pupd_nopull ; gpio_init(gpioy, &gpio_initstructure); 4.5.4 alternate function mode stm32f1 series the configuration to use an i/o as an altern ate function depends on the peripheral mode used; for example, the usart tx pin should be configured as an alternate function push- pull while the usart rx pin should be configured as an input floating or an input pull-up. to optimize the number of peripheral i/o func tions for different device packages, it is possible, by software, to remap some alternat e functions to other pins. for example, the usart2_rx pin can be mapped on pa3 (default remap) or pd6 (by software remap). stm32f3 series whatever the peripheral mode used, the i/o must be configured as an alternate function, then the system can use the i/o in the proper way (input or output). the i/o pins are connected to on-board peripherals/modules through a multiplexer that allows only one peripheral alternate function to be connected to an i/o pin at a time. in this way, there can be no conflict between peripher als sharing the same i/o pin. each i/o pin docid024110 rev 5 43/90 AN4228 firmware migration using the library 89 has a multiplexer with sixteen alternate function inputs (af0 to af15) that can be configured through the gpio_pinafconfig () function: ? after reset, all i/os are connected to the system?s alternate function 0 (af0) ? the peripherals? alternate functions ar e mapped by configuring af0 to af15. in addition to this flexible i/o multiplexing architecture, each peripheral has alternate functions mapped onto different i/o pins to optimize the number of peripheral i/o functions for different device packages; for example, the usart2_rx pin can be mapped on pa3 or pa15 pin. the configuration procedure is the following: 1. connect the pin to the desired peripherals' alternate function (af) using gpio_pinafconfig() function 2. use gpio_init() function to configure the i/o pin: a) configure the desired pin in alternate function mode using ? gpio_initstructure->gpio_mode = gpio_mode_af; b) select the type, pull-up/pull-down and output speed via ? gpio_pupd, gpio_otype and gpio_speed members the example below shows how to remap usart2 tx/rx i/os on pd5/pd6 pins in stm32f1 series: /* enable apb2 interface clock for gpiod and afio (afio peripheral is used to configure the i/os software remapping) */ _apb2periphclockcmd(_apb2periph_gpiod | _apb2periph_afio, enable); /* enable usart2 i/os software remapping [(usart2_tx,usart2_rx):(pd5,pd6)] */ gpio_pinremapconfig(gpio_remap_usart2, enable); /* configure usart2_tx as alternate function push-pull */ gpio_initstructure.gpio_pin = gpio_pin_5; gpio_initstructure.gpio_mode = gpio_mode_af_pp; gpio_initstructure.gpio_speed = gpio_speed_50mhz; gpio_init(gpiod, &gpio_initstructure); /* configure usart2_rx as input floating */ gpio_initstructure.gpio_pin = gpio_pin_6; gpio_initstructure.gpio_mode = gpio_mode_in_floating; gpio_init(gpiod, &gpio_initstructure); in stm32f3 series, update this code as follows: /* enable gpioa's ahb interface clock */ _ahbperiphclockcmd(_ahbperiph_gpioa, enable); /* select usart2 i/os mapping on pa14/15 pins [(usart2_tx,usart2_rx):(pa.14,pa.15)] */ /* connect pa14 to usart2_tx */ gpio_pinafconfig(gpioa, gpio_pinsource14, gpio_af_2); /* connect pa15 to usart2_rx*/ gpio_pinafconfig(gpioa, gpio_pinsource15, gpio_af_2); /* configure usart2_tx and usart2_rx as alternate function */ gpio_initstructure.gpio_pin = gpio_pin_14 | gpio_pin_15; firmware migration using the library AN4228 44/90 docid024110 rev 5 gpio_initstructure.gpio_mode = gpio_mode_af; gpio_initstructure.gpio_speed = gpio_speed_50mhz; gpio_initstructure.gpio_otype = gpio_otype_pp; gpio_initstructure.gpio_pupd = gpio_pupd_up; gpio_init(gpioa, &gpio_initstructure); 4.6 exti line0 the example below shows how to configure the pa0 pin to be used as exti line0 in stm32f1 series: /* enable apb interface clock for gpioa and afio */ _apb2periphclockcmd(_apb2periph_gpioa | _apb2periph_afio, enable); /* configure pa0 pin in input mode */ gpio_initstructure.gpio_pin = gpio_pin_0; gpio_initstructure.gpio_mode = gpio_mode_in_floating; gpio_init(gpioa, &gpio_initstructure); /* connect exti line0 to pa0 pin */ gpio_extilineconfig(gpio_portsourcegpioa, gpio_pinsource0); /* configure exti line0 */ exti_initstructure.exti_line = exti_line0; exti_initstructure.exti_mode = exti_mode_interrupt; exti_initstructure.exti_trigger = exti_trigger_falling; exti_initstructure.exti_linecmd = enable; exti_init(&exti_initstructure); in stm32f3 series, the configuration of the exti line source pin is performed in the syscfg peripheral (instead of afio in stm32f1 series). as a result, the source code should be updated as follows: /* enable gpioa's ahb interface clock */ _ahbperiphclockcmd(_ahbperiph_gpioa, enable); /* enable syscfg's apb interface clock */ _apb2periphclockcmd(_apb2periph_syscfg, enable); /* configure pa0 pin in input mode */ gpio_initstructure.gpio_pin = gpio_pin_0; gpio_initstructure.gpio_mode = gpio_mode_in; gpio_initstructure.gpio_pupd = gpio_pupd_nopull; gpio_init(gpioa, &gpio_initstructure); /* connect exti line0 to pa0 pin */ syscfg_extilineconfig(exti_portsourcegpioa, exti_pinsource0); /* configure exti line0 */ docid024110 rev 5 45/90 AN4228 firmware migration using the library 89 exti_initstructure.exti_line = exti_line0; exti_initstructure.exti_mode = exti_mode_interrupt; exti_initstructure.exti_trigger = exti_trigger_falling; exti_initstructure.exti_linecmd = enable; exti_init(&exti_initstructure); 4.7 nvic interru pt configuration this section explains how to configure the nvic interrupts (irq). stm32f1 series in stm32f1 series, the nvic supports: ? up to 68 interrupts (68 ex. core it ? a programmable priority level of 0-15 for each interrupt (4 bits of interrupt priority are used). a higher level corresponds to a lower priority; level 0 is the highest interrupt priority. ? grouping of priority values into group priority and sub priority fields. ? dynamic changing of priority levels. the cortex-m3 exceptions are managed by cmsis functions: ? enabling and configuration of the preemption priority and sub priority of the selected irq channels according to the priority grouping configuration. stm32f3 series in stm32f3 series, the nvic supports: ? up to 66 interrupts ? 16 programmable priority levels. ? the priority level of an interrupt should not be changed after it is enabled. the cortex-m4 exceptions are managed by cmsis functions: ? enabling and configuration of the priority of the selected irq channels. the priority ranges between 0 and 15. lower priority values give a higher priority. the table below gives the misc driver api correspondence between stm32f10x and stm32f3xx libraries. table 22. stm32f10x and stm32f3xx misc driver api correspondence stm32f10x misc driver api stm32f3xx misc driver api void nvic_init(nvic_inittypedef* nvic_initstruct); void nvic_init(nvic_inittypedef* nvic_initstruct); void nvic_systemlpconfig(uint8_t lowpowermode, functionalstate newstate); void nvic_systemlpconfig(uint8_t lowpowermode, functionalstate newstate); void systick_clksourceconfig(uint32_t systick_clksource); void systick_clksourceconfig(uint32_t systick_clksource); firmware migration using the library AN4228 46/90 docid024110 rev 5 4.8 adc configuration the stm32f10x and stm32f37x adc peripherals are similar. the stm32f30xx devices feature a new adc. the table below describes the difference between stm32f10x functions and stm32f3xx libraries. nvic_prioritygroupconfig(uint32_t nvic_prioritygroup); nvic_prioritygroupconfig(uint32_t nvic_prioritygroup); void nvic_setvectortable(uint32_t nvic_vecttab, uint32_t offset); void nvic_setvectortable( uint32_t nvic_vecttab, uint32_t offset); table 22. stm32f10x and stm32f3xx misc driver api correspondence (continued) stm32f10x misc driver api stm32f3xx misc driver api docid024110 rev 5 47/90 AN4228 firmware migration using the library 89 table 23. stm32f10x and stm32f3xx adc driver api correspondence stm32f10x adc driver api stm32f37x adc driver api stm32f30x adc driver api initialization and configuration void adc_deinit(adc_typedef* adcx); void adc_deinit(adc_typedef* adcx); void adc_deinit(adc_typedef* adcx); void adc_init(adc_typedef* adcx, adc_inittypedef* adc_initstruct); void adc_init(adc_typedef* adcx, adc_inittypedef* adc_initstruct); void adc_init(adc_typedef* adcx, adc_inittypedef* adc_initstruct); void adc_structinit(adc_inittypedef * adc_initstruct); void adc_structinit(adc_inittypedef* adc_initstruct); void adc_structinit(adc_inittypedef* adc_initstruct); na na void adc_injectedinit(adc_typedef* adcx, adc_injectedinittypedef* adc_injectedinitstruct); na na void adc_injectedstructinit(adc_inject edinittypedef* adc_injectedinitstruct); na na void adc_commoninit(adc_typedef* adcx, adc_commoninittypedef* adc_commoninitstruct); na na void adc_commonstructinit(adc_com moninittypedef* adc_commoninitstruct); void adc_cmd(adc_typedef* adcx, functionalstate newstate); void adc_cmd(adc_typedef* adcx, functionalstate newstate); void adc_cmd(adc_typedef* adcx, functionalstate newstate); void adc_startcalibration(adc_type def* adcx); void adc_startcalibration(adc_typed ef* adcx); void adc_startcalibration(adc_typed ef* adcx); na na uint32_t adc_getcalibrationvalue(adc_ty pedef* adcx); na na void adc_setcalibrati onvalue(adc_ty pedef* adcx, uint32_t adc_calibration); firmware migration using the library AN4228 48/90 docid024110 rev 5 initialization and configuration na na void adc_selectcalibrationmode(adc_ typedef* adcx, uint32_t adc_calibrationmode); flagstatus adc_getcalibrationstatus(adc_ typedef* adcx); flagstatus adc_getcalibrationstatus(adc_ty pedef* adcx); flagstatus adc_getcalibrationstatus(adc_ty pedef* adcx); na na void adc_disablecmd(adc_typedef* adcx); na na flagstatus adc_getdisablecmdstatus(adc_ typedef* adcx); na na void adc_voltageregulatorcmd(adc_ typedef* adcx, functionalstate newstate); na na void adc_selectdifferentialmode(adc_ typedef* adcx, uint8_t adc_channel, functionalstate newstate); na na void adc_selectqueueofcontextmode( adc_typedef* adcx, functionalstate newstate); na na void adc_autodelaycmd(adc_typede f* adcx, functionalstate newstate); void adc_resetcalibration(adc_typ edef* adcx); void adc_resetcalibration(adc_type def* adcx); na table 23. stm32f10x and stm32f3xx adc driver api correspondence (continued) stm32f10x adc driver api stm32f37x adc driver api stm32f30x adc driver api docid024110 rev 5 49/90 AN4228 firmware migration using the library 89 analog watchdog configuration void adc_analogwatchdogcmd(adc _typedef* adcx, uint32_t adc_analogwatchdog); void adc_analogwatchdogcmd(adc_ typedef* adcx, uint32_t adc_analogwatchdog); void adc_analogwatchdogcmd(adc_ typedef* adcx, uint32_t adc_analogwatchdog); void adc_analogwatchdogthreshold sconfig(adc_typedef* adcx, uint16_t highthreshold, uint16_t lowthreshold); void adc_analogwatchdogthresholdsc onfig(adc_typedef* adcx, uint16_t highthreshold, uint16_t lowthreshold); void adc_analogwatchdog1thresholds config(adc_typedef* adcx, uint16_t highthreshold, uint16_t lowthreshold); void adc_analogwatchdog2thresholds config(adc_typedef* adcx, uint8_t highthreshold, uint8_t lowthreshold); void adc_analogwatchdog3thresholds config(adc_typedef* adcx, uint8_t highthreshold, uint8_t lowthreshold); void adc_analogwatchdogsinglecha nnelconfig(adc_typedef* adcx, uint8_t adc_channel); void adc_analogwatchdogsinglechan nelconfig(adc_typedef* adcx, uint8_t adc_channel); void adc_analogwatchdog1singlecha nnelconfig(adc_typedef* adcx, uint8_t adc_channel); void adc_analogwatchdog2singlecha nnelconfig(adc_typedef* adcx, uint8_t adc_channel); void adc_analogwatchdog3singlecha nnelconfig(adc_typedef* adcx, uint8_t adc_channel); table 23. stm32f10x and stm32f3xx adc driver api correspondence (continued) stm32f10x adc driver api stm32f37x adc driver api stm32f30x adc driver api firmware migration using the library AN4228 50/90 docid024110 rev 5 temperature sensor, vrefint and vbat management void adc_tempsensorvrefintcmd(fu nctionalstate newstate); void adc_tempsensorvrefintcmd(func tionalstate newstate); void adc_tempsensorcmd(adc_type def* adcx, functionalstate newstate); na na void adc_vrefintcmd(adc_typedef* adcx, functionalstate newstate); na na void adc_vbatcmd(adc_typedef* adcx, functionalstate newstate); table 23. stm32f10x and stm32f3xx adc driver api correspondence (continued) stm32f10x adc driver api stm32f37x adc driver api stm32f30x adc driver api docid024110 rev 5 51/90 AN4228 firmware migration using the library 89 regular channels void adc_regularchannelconfig(ad c_typedef* adcx, uint8_t adc_channel, uint8_t rank, uint8_t adc_sampletime); void adc_regularchannelconfig(adc_ typedef* adcx, uint8_t adc_channel, uint8_t rank, uint8_t adc_sampletime); void adc_regularchannelconfig(adc_ typedef* adcx, uint8_t adc_channel, uint8_t rank, uint8_t adc_sampletime); na na void adc_regularchannelsequencerle ngthconfig(adc_typedef* adcx, uint8_t sequencerlength); void adc_externaltrigconvcmd(adc _typedef* adcx, functionalstate newstate); void adc_externaltrigconvcmd(adc_ typedef* adcx, functionalstate newstate); void adc_externaltriggerconfig(adc_ typedef* adcx, uint16_t adc_externaltrigconvevent, uint16_t adc_externaltrigeventedge); void adc_softwarestartconv(adc_t ypedef* adcx); void adc_softwarestartconv(adc_typ edef* adcx); void adc_startconversion(adc_typed ef* adcx); flagstatus adc_getsoftwarestartconvstatu s(adc_typedef* adcx); flagstatus adc_getsoftwarestartconvstatus( adc_typedef* adcx); flagstatus adc_getstartconversionstatus(ad c_typedef* adcx); na na void adc_stopconversion(adc_typed ef* adcx); void adc_discmodechannelcountco nfig(adc_typedef* adcx, uint8_t number); void adc_discmodechannelcountconfi g(adc_typedef* adcx, uint8_t number); void adc_discmodechannelcountconfi g(adc_typedef* adcx, uint8_t number); table 23. stm32f10x and stm32f3xx adc driver api correspondence (continued) stm32f10x adc driver api stm32f37x adc driver api stm32f30x adc driver api firmware migration using the library AN4228 52/90 docid024110 rev 5 regular channels void adc_discmodecmd(adc_type def* adcx, functionalstate newstate); void adc_discmodecmd(adc_typede f* adcx, functionalstate newstate); void adc_discmodecmd(adc_typede f* adcx, functionalstate newstate); uint16_t adc_getconversionvalue(adc_ typedef* adcx); uint16_t adc_getconversionvalue(adc_ty pedef* adcx); uint16_t adc_getconversionvalue(adc_ty pedef* adcx); uint32_t ? adc_getdualmodeconversionv alue(void); | not supported by stm32f37xx uint32_t adc_getdualmodeconversionvalu e(adc_typedef* adcx); na na void adc_setchanneloffset1(adc_typ edef* adcx, uint8_t adc_channel, uint16_t offset); na na void adc_setchanneloffset2(adc_typ edef* adcx, uint8_t adc_channel, uint16_t offset); na na void adc_setchanneloffset3(adc_typ edef* adcx, uint8_t adc_channel, uint16_t offset); na na void adc_setchanneloffset4(adc_typ edef* adcx, uint8_t adc_channel, uint16_t offset); na na void adc_channeloffset1cmd(adc_ty pedef* adcx, functionalstate newstate); na na void adc_channeloffset2cmd(adc_ty pedef* adcx, functionalstate newstate); na na void adc_channeloffset3cmd(adc_ty pedef* adcx, functionalstate newstate); na na void adc_channeloffset4cmd(adc_ty pedef* adcx, functionalstate newstate); table 23. stm32f10x and stm32f3xx adc driver api correspondence (continued) stm32f10x adc driver api stm32f37x adc driver api stm32f30x adc driver api docid024110 rev 5 53/90 AN4228 firmware migration using the library 89 regular channels dma configuration void adc_dmacmd(adc_typedef* adcx, functionalstate newstate); void adc_dmacmd(adc_typedef* adcx, functionalstate newstate); void adc_dmacmd(adc_typedef* adcx, functionalstate newstate); na na void adc_dmaconfig(adc_typedef* adcx, uint32_t adc_dmamode); table 23. stm32f10x and stm32f3xx adc driver api correspondence (continued) stm32f10x adc driver api stm32f37x adc driver api stm32f30x adc driver api firmware migration using the library AN4228 54/90 docid024110 rev 5 injected channels configuration void adc_injectedchannelconfig(ad c_typedef* adcx, uint8_t adc_channel, uint8_t rank, uint8_t adc_sampletime); void adc_injectedchannelconfig(adc_ typedef* adcx, uint8_t adc_channel, uint8_t rank, uint8_t adc_sampletime); na void adc_injectedsequencerlengthc onfig(adc_typedef* adcx, uint8_t sequencerlength); void adc_injectedsequencerlengthcon fig(adc_typedef* adcx, uint8_t sequencerlength); na void adc_externaltriginjectedconvc onfig(adc_typedef* adcx, uint32_t adc_externaltriginjecconv); void adc_externaltriginjectedconvcon fig(adc_typedef* adcx, uint32_t adc_externaltriginjecconv); na void adc_softwarestartinjectedconv cmd(adc_typedef* adcx, functionalstate newstate); void adc_softwarestartinjectedconvc md(adc_typedef* adcx, functionalstate newstate); void adc_startinjectedconversion(adc _typedef* adcx); flagstatus adc_getsoftwarestartinjectedc onvcmdstatus(adc_typedef* adcx); flagstatus adc_getsoftwarestartinjectedcon vcmdstatus(adc_typedef* adcx); flagstatus adc_getstartinjectedconversionst atus(adc_typedef* adcx); adc_injectedchannelsampletim econfig(adc_typedef* adcx, uint8_t adc_injectedchannel, uint8_t adc_sampletime); na adc_injectedchannelsampletime config(adc_typedef* adcx, uint8_t adc_injectedchannel, uint8_t adc_sampletime); na na void adc_stopinjectedconversion(adc _typedef* adcx); adc_autoinjectedconvcmd(ad c_typedef* adcx, functionalstate newstate); adc_autoinjectedconvcmd(adc_ typedef* adcx, functionalstate newstate); adc_autoinjectedconvcmd(adc_ typedef* adcx, functionalstate newstate); void adc_injecteddiscmodecmd(ad c_typedef* adcx, functionalstate newstate); void adc_injecteddiscmodecmd(adc_ typedef* adcx, functionalstate newstate); void adc_injecteddiscmodecmd(adc_ typedef* adcx, functionalstate newstate); uint16_t adc_getinjectedconversionvalu e(adc_typedef* adcx, uint8_t adc_injectedchannel); uint16_t adc_getinjectedconversionvalue( adc_typedef* adcx, uint8_t adc_injectedchannel); uint16_t adc_getinjectedconversionvalue( adc_typedef* adcx, uint8_t adc_injectedchannel); table 23. stm32f10x and stm32f3xx adc driver api correspondence (continued) stm32f10x adc driver api stm32f37x adc driver api stm32f30x adc driver api docid024110 rev 5 55/90 AN4228 firmware migration using the library 89 adc dual mode configuration na na flagstatus adc_getcommonflagstatus(adc _typedef* adcx, uint32_t adc_flag); na na void adc_clearcommonflag(adc_typ edef* adcx, uint32_t adc_flag); interrupts and flags management void adc_itconfig(adc_typedef* adcx, uint32_t adc_it, functionalstate newstate); void adc_itconfig(adc_typedef* adcx, uint32_t adc_it, functionalstate newstate); void adc_itconfig(adc_typedef* adcx, uint32_t adc_it, functionalstate newstate); flagstatus adc_getflagstatus(adc_typed ef* adcx, uint8_t adc_flag); flagstatus adc_getflagstatus(adc_typedef * adcx, uint8_t adc_flag); flagstatus adc_getflagstatus(adc_typedef * adcx, uint8_t adc_flag); void adc_clearflag(adc_typedef* adcx, uint8_t adc_flag); void adc_clearflag(adc_typedef* adcx, uint8_t adc_flag); void adc_clearflag(adc_typedef* adcx, uint8_t adc_flag); itstatus adc_getitstatus(adc_typedef * adcx, uint16_t adc_it); itstatus adc_getitstatus(adc_typedef* adcx, uint16_t adc_it); itstatus adc_getitstatus(adc_typedef* adcx, uint16_t adc_it); void adc_clearitpendingbit(adc_ty pedef* adcx, uint16_t adc_it); void adc_clearitpendingbit(adc_typ edef* adcx, uint16_t adc_it); void adc_clearitpendingbit(adc_typ edef* adcx, uint16_t adc_it); flagstatus adc_getcalibrationstatus(adc_ typedef* adcx); flagstatus adc_getcalibrationstatus(adc_ty pedef* adcx); na flagstatus adc_getresetcalibrationstatus( adc_typedef* adcx); flagstatus adc_getresetcalibrationstatus(a dc_typedef* adcx); na table 23. stm32f10x and stm32f3xx adc driver api correspondence (continued) stm32f10x adc driver api stm32f37x adc driver api stm32f30x adc driver api color key: = new function = same function, but api was changed = function not available (na) firmware migration using the library AN4228 56/90 docid024110 rev 5 this section gives an example of how to po rt existing code from stm32f1 series to stm32f3 series. the example below shows how to configure the adc1 to convert continuously channel 14 in stm32f1 series: /* adcclk = pclk2/4 */ _adcclkconfig(_pclk2_div4); /* enable adc's apb interface clock */ _apb2periphclockcmd(_apb2periph_adc1, enable); /* configure adc1 to convert continously channel14 */ adc_initstructure.adc_mode = adc_mode_independent; adc_initstructure.adc_scanconvmode = enable; adc_initstructure.adc_continuousconvmode = enable; adc_initstructure.adc_externaltrigconv = adc_externaltrigconv_none; adc_initstructure.adc_dataalign = adc_dataalign_right; adc_initstructure.adc_nbrofchannel = 1; adc_init(adc1, &adc_initstructure); /* adc1 regular channel14 configuration */ adc_regularchannelconfig(adc1, adc_channel_14, 1, adc_sampletime_55cycles5); /* enable adc1's dma interface */ adc_dmacmd(adc1, enable); /* enable adc1 */ adc_cmd(adc1, enable); /* enable adc1 reset calibration register */ adc_resetcalibration(adc1); /* check the end of adc1 reset calibration register */ while(adc_getresetcalibrationstatus(adc1)); /* start adc1 calibration */ adc_startcalibration(adc1); /* check the end of adc1 calibration */ while(adc_getcalibrationstatus(adc1)); /* start adc1 software conversion */ adc_softwarestartconvcmd(adc1, enable); ... in f30 series, you have to update this code as follows: ... /* configure the adc clock */ docid024110 rev 5 57/90 AN4228 firmware migration using the library 89 rcc_adcclkconfig(rcc_adc12pllclk_div2); /* enable adc1 clock */ rcc_ahbperiphclockcmd(rcc_ahbperiph_adc12, enable); adc_structinit(&adc_initstructure); /* calibration procedure */ adc_voltageregulatorcmd(adc1, enable); adc_selectcalibrationmode(adc1, adc_calibrationmode_single); adc_startcalibration(adc1); while(adc_getcalibrationstatus(adc1) != reset ); calibration_value = adc_getcalibrationvalue(adc1); adc_commoninitstructure.adc_mode = adc_mode_independent; adc_commoninitstructure.adc_clock = adc_clock_asynclkmode; adc_commoninitstructure.adc_dmaaccessmode = adc_dmaaccessmode_disabled; adc_commoninitstructure.adc_dmamode = adc_dmamode_oneshot; adc_commoninitstructure.adc_twosamplingdelay = 0; adc_commoninit(adc1, &adc_commoninitstructure); adc_initstructure.adc_continuousconvmode = adc_continuousconvmode_enable; adc_initstructure.adc_resolution = adc_resolution_12b; adc_initstructure.adc_externaltrigconvevent = adc_externaltrigconvevent_0; adc_initstructure.adc_externaltrigeventedge = adc_externaltrigeventedge_none; adc_initstructure.adc_dataalign = adc_dataalign_right; adc_initstructure.adc_overrunmode = adc_overrunmode_disable; adc_initstructure.adc_autoinjmode = adc_autoinjec_disable; adc_initstructure.adc_nbrofregchannel = 1; adc_init(adc1, &adc_initstructure); /* adc1 regular channel14 configuration */ adc_regularchannelconfig(adc1, adc_channel_14, 1, adc_sampletime_7cycles5); /* enable adc1 */ adc_cmd(adc1, enable); /* wait for adrdy */ while(!adc_getflagstatus(adc1, adc_flag_rdy)); /* start adc1 software conversion */ firmware migration using the library AN4228 58/90 docid024110 rev 5 adc_startconversion(adc1); /* infinite loop */ while (1) { /* test eoc flag */ while(adc_getflagstatus(adc1, adc_flag_eoc) == reset); /* get adc1 converted data */ adc1convertedvalue =adc_getconversionvalue(adc1); } ... docid024110 rev 5 59/90 AN4228 firmware migration using the library 89 4.9 dac driver the table below describes the difference between stm32f10x functions and stm32f3xx libraries. table 24. stm32f10x and stm32f3xx dac driver api correspondence stm32f10x dac driver api stm32f3xx dac driver api configuration void dac_deinit(void); void dac_deinit(dac_typedef* dacx); void dac_init(uint32_t dac_channel, dac_inittypedef* dac_initstruct); void dac_init(dac_typedef* dacx, uint32_t dac_channel, dac_inittypedef* dac_initstruct); void dac_structinit(dac_inittypedef* dac_initstruct); void dac_structinit(dac_inittypedef* dac_initstruct); void dac_cmd(uint32_t dac_channel, functionalstate newstate); void dac_cmd(dac_typedef* dacx, uint32_t dac_channel, functionalstate newstate); void dac_softwaretriggercmd(uint32_t dac_channel, functionalstate newstate); void dac_softwaretriggercmd(dac_typedef* dacx, uint32_t dac_channel, functionalstate newstate); dac_dualsoftwaretriggercmd(functionalstate newstate); void dac_dualsoftwaretriggercmd(dac_typedef* dacx, functionalstate newstate); void dac_wavegenerationcmd(uint32_t dac_channel, uint32_t dac_wave, functionalstate newstate); void dac_wavegenerationcmd(dac_typedef* dacx, uint32_t dac_channel, uint32_t dac_wave, functionalstate newstate); void dac_setchannel1data(uint32_t dac_align, uint16_t data); void dac_setchannel1data(dac_typedef* dacx, uint32_t dac_align, uint16_t data); void dac_setchannel2data(uint32_t dac_align, uint16_t data); void dac_setchannel2data(dac_typedef* dacx, uint32_t dac_align, uint16_t data); void dac_setdualchanneldata(uint32_t dac_align, uint16_t da ta2, uint16_t data1); void dac_setdualchanneldata(dac_typedef* dacx, uint32_t dac_align, uint16_t data2, uint16_t data1); uint16_t dac_getdataoutputvalue(uint32_t dac_channel); uint16_t dac_getdatao utputvalue(dac_typedef* dacx, uint32_t dac_channel); na void dac_dualsoftwaretriggercmd(dac_typedef* dacx, functionalstate newstate) na void dac_wavegenerationcmd(dac_typedef* dacx, uint32_t dac_channel, uint32_t dac_wave, functionalstate newstate); dma management void dac_dmacmd(uint32_t dac_channel, functionalstate newstate); void dac_dmacmd(dac_typ edef* dacx, uint32_t dac_channel, functionalstate newstate); firmware migration using the library AN4228 60/90 docid024110 rev 5 4.10 pwr driver the table below presents the pwr driver api correspondence between stm32f10x and stm32f3xx libraries. you can easily update your application code by replacing stm32f10x functions by the corresponding function in the stm32f3xx library. interrupts and flags management void dac_itconfig(uint32_t dac_channel, uint32_t dac_it, functionalstate newstate); (1) void dac_itconfig(dac_t ypedef* dacx, uint32_t dac_channel, uint32_t dac_it, functionalstate newstate); flagstatus dac_getflagstatus(uint32_t dac_channel, uint32_t dac_flag); (1) flagstatus dac_getflagstatus(dac_typedef* dacx, uint32_t dac_channel, uint32_t dac_flag); void dac_clearflag(uint32_t dac_channel, uint32_t dac_flag); (1) void dac_clearflag(dac_typedef* dacx, uint32_t dac_channel, uint32_t dac_flag); itstatus dac_getitstatus(uint32_t dac_channel, uint32_t dac_it); (1) itstatus dac_getitstatus(dac_typedef* dacx, uint32_t dac_channel, uint32_t dac_it); void dac_clearitpendingbit(uint32_t dac_channel, uint32_t dac_it); (1) void dac_clearitpendingbit(dac_typedef* dacx, uint32_t dac_channel, uint32_t dac_it); 1. these functions exist only on stm32f10x_ld_vl, stm32f10x_md_vl, and stm32f10x_hd_vl devices. table 24. stm32f10x and stm32f3xx dac driver api correspondence (continued) stm32f10x dac driver api stm32f3xx dac driver api table 25. stm32f10x and stm32f3xx pwr driver api correspondence stm32f10x pwr driver api stm32f3xx pwr driver api interface configuration void pwr_deinit(void); void pwr_deinit(void); void pwr_backupaccesscmd(functionalstate newstate); void pwr_backupaccesscmd(functionalstate newstate); pvd void pwr_pvdlevelconfig(uint32_t pwr_pvdlevel); void pwr_pvdlevelconfig(uint32_t pwr_pvdlevel); void pwr_pvdcmd(functionalstate newstate); vo id pwr_pvdcmd(functionalstate newstate); wakeup void pwr_wakeuppincmd(functionalstate newstate); void pwr_wakeuppincmd(uint32_t pwr_wakeuppin, functionalstate newstate); (1) docid024110 rev 5 61/90 AN4228 firmware migration using the library 89 4.11 backup data registers in stm32f1 series, the backup data registers are managed through the bkp peripheral, while in stm32f3 series they are a part of the rtc peripheral (there is no bkp peripheral). the example below shows how to write to/read from backup data registers in stm32f1 series: uint16_t bkpdata = 0; ... /* enable apb2 interface clock for pwr and bkp */ _apb1periphclockcmd(_apb1periph_pwr | _apb1periph_bkp, enable); /* enable write access to backup domain */ pwr_backupaccesscmd(enable); /* write data to backup data register 1 */ power management na void pwr_entersleepmode(uint8_t pwr_sleepentry); void pwr_enterstopmode(uint32_t pwr_regulator, uint8_t pwr_stopentry); void pwr_enterstopmode(uint32_t pwr_regulator, uint8_t pwr_stopentry); void pwr_enterstandbymode(void); void pwr_enterstandbymode(void); flag management flagstatus pwr_getflagstatus(uint32_t pwr_flag); flagstatus pwr_getflagstatus(uint32_t pwr_flag); void pwr_clearflag(uint32_t pwr_flag); vo id pwr_clearflag(uint32_t pwr_flag); 1. additional wake-up pins are available on stm32f3 series. table 25. stm32f10x and stm32f3xx pwr driver api correspondence (continued) stm32f10x pwr driver api stm32f3xx pwr driver api color key: = new function = same function, but api was changed = function not available (na) firmware migration using the library AN4228 62/90 docid024110 rev 5 bkp_writebackupregister(bkp_dr1, 0x3210); /* read data from backup data register 1 */ bkpdata = bkp_readbackupregister(bkp_dr1); in stm32f3 series, you have to update this code as follows: uint16_t bkpdata = 0; ... /* pwr clock enable */ _apb1periphclockcmd(_apb1periph_pwr, enable); /* enable write access to rtc domain */ pwr_rtcaccesscmd(enable); /* write data to backup data register 1 */ rtc_writebackupregister(rtc_bkp_dr1, 0x3220); /* read data from backup data register 1 */ bkpdata = rtc_readbackupregister(rtc_bkp_dr1); the main changes in the source code in stm32f3 series versus stm32f1 series are described below: ? there is no bkp peripheral ? write to/read from backup data registers are performed through the rtc driver ? backup data registers na ming changed from bkp_ drx to rtc_bkp_drx, and numbering starts from 0 instead of 1. 4.12 cec application code you can easily update your cec application code by replacing stm32f10x functions by the corresponding function of the stm32f3xx library. the table below presents the cec driver api correspondence between stm32f10x and stm32f37x libraries. docid024110 rev 5 63/90 AN4228 firmware migration using the library 89 table 26. stm32f10x and stm32f37x cec driver api correspondence stm32f10x cec driver api stm32f37x cec driver api interface configuration void cec_deinit(void); void cec_deinit(void); void cec_init(cec_inittypedef* cec_initstruct); void cec_init(cec_inittypedef* cec_initstruct); na void cec_structinit(cec_inittypedef* cec_initstruct); void cec_cmd(functionalstate newstate); void cec_cmd(functionalstate newstate); na void cec_listenmodecmd(functionalstate newstate); void cec_ownaddressconfig(uint8_t cec_ownaddress); void cec_ownaddressconfig(uint8_t cec_ownaddress); na void cec_ownaddressclear(void); void cec_setprescaler(uint16_t cec_prescaler); na data transfers void cec_senddatabyte(uint8_t data); void cec_senddata(uint8_t data); uint8_t cec_receivedatabyte(void); uint8_t cec_receivedata(void); void cec_startofmessage(void); v oid cec_startofmessage(void); void cec_endofmessagecmd(functionalstate newstate); void cec_endofmessage(void); interrupt and flag management void cec_itconfig(functionalstate newstate) void cec_itconfig(uint16_t cec_it, functionalstate newstate); flagstatus cec_getflagstatus(uint32_t cec_flag); flagstatus cec_getflagstatus(uint16_t cec_flag); void cec_clearflag(uint32_t cec_flag) v oid cec_clearflag(uint32_t cec_flag); itstatus cec_getitstatus(uint8_t cec_it) i tstatus cec_getitstatus(uint16_t cec_it); void cec_clearitpendingbit(uint16_t cec_it) v oid cec_clearitpendingbit(uint16_t cec_it); color key: = new function = same function, but api was changed = function not available (na) firmware migration using the library AN4228 64/90 docid024110 rev 5 the main changes in the source code/procedure in stm32f3 series versus stm32f1 series are described below: ? dual clock source (refer to section for more details). ? no prescaler feature configuration. ? it supports more than one address (multiple addressing). ? each event flag has an associate enable control bit to generate the adequate interrupt. ? in the cec structure definition, se ven fields should be initialized. the example below shows how to configure the cec stm32f1 series: /* configure the cec peripheral */ cec_initstructure.cec_bittimingmode = cec_bittimingstdmode; cec_initstructure.cec_bitperiodmode = cec_bitperiodstdmode; cec_init(&cec_initstructure); in f37 series, you have to update this code as follows: /* configure cec */ cec_initstructure.cec_signalfreetime = cec_signalfreetime_standard; cec_initstructure.cec_rxtolerance = cec_rxtolerance_standard; cec_initstructure.cec_stopreception = cec_stopreception_off; cec_initstructure.cec_bitrisingerror = cec_bitrisingerror_off; cec_initstructure.cec_longbitperioderror = cec_longbitperioderror_off; cec_initstructure.cec_brdnogen = cec_brdnogen_off; cec_initstructure.cec_sftoption = cec_sftoption_off; cec_init(&cec_initstructure); 4.13 i2c driver stm32f3xx devices incorporate new i2c features. the table below presents the i2c driver api correspondence between stm32f10x a nd stm32f3xx libraries. update your application code by replacing stm32f10x functions by the corresponding functions of the stm32f3xx library. docid024110 rev 5 65/90 AN4228 firmware migration using the library 89 table 27. stm32f10x and stm32f3xx i2c driver api correspondence stm32f10x i2c driver api stm32f3xx i2c driver api initialization and configuration void i2c_deinit(i2c_typedef* i2cx); void i2c_deinit(i2c_typedef* i2cx); void i2c_init(i2c_typedef* i2cx, i2c_inittypedef* i2c_initstruct); void i2c_init(i2c_typedef* i2cx, i2c_inittypedef* i2c_initstruct); void i2c_structinit(i2c_inittypedef* i2c_initstruct); void i2c_structinit(i2c_inittypedef* i2c_initstruct); void i2c_cmd(i2c_typedef* i2cx, functionalstate newstate); void i2c_cmd(i2c_typedef* i2cx, functionalstate newstate); void i2c_softwareresetcmd(i2c_typedef* i2cx, functionalstate newstate); void i2c_softwareresetcmd(i2c_typedef* i2cx, functionalstate newstate); void i2c_itconfig(i2c_typedef* i2cx, uint16_t i2c_it, functionalstate newstate); void i2c_itconfig(i2c_typedef* i2cx, uint16_t i2c_it, functionalstate newstate); void i2c_stretchclockcmd(i2c_typedef* i2cx, functionalstate newstate); void i2c_stretchclockcmd(i2c_typedef* i2cx, functionalstate newstate); na void i2c_stopmodecmd(i2c_typedef* i2cx, functionalstate newstate); void i2c_dualaddresscmd(i2c_typedef* i2cx, functionalstate newstate); void i2c_dualaddresscmd(i2c_typedef* i2cx, functionalstate newstate); void i2c_ownaddress2config(i2c_typedef* i2cx, uint8_t address); void i2c_ownaddress2config(i2c_typedef* i2cx, uint16_t address, uint8_t mask); void i2c_generalcallcmd(i2c_typedef* i2cx, functionalstate newstate); void i2c_generalcallcmd(i2c_typedef* i2cx, functionalstate newstate); na void i2c_slavebytecontrolcmd(i2c_typedef* i2cx, functionalstate newstate); na void i2c_slaveaddressconfig(i2c_typedef* i2cx, uint16_t address); na void i2c_10bitaddressingmodecmd(i2c_typedef* i2cx, functionalstate newstate); void i2c_nackpositionconfig(i2c_typedef* i2cx, uint16_t i2c_nackposition); na void i2c_arpcmd(i2c_typedef* i2cx, functionalstate newstate); na firmware migration using the library AN4228 66/90 docid024110 rev 5 communications handling na void i2c_autoendcmd(i2c_typedef* i2cx, functionalstate newstate); na void i2c_reloadcmd(i2c_typedef* i2cx, functionalstate newstate); na void i2c_numberofbytesconfig(i2c_typedef* i2cx, uint8_t number_bytes); na void i2c_masterrequestconfig(i2c_typedef* i2cx, uint16_t i2c_direction); void i2c_generatestart(i2c_typedef* i2cx, functionalstate newstate); void i2c_generatestart(i2c_typedef* i2cx, functionalstate newstate); void i2c_generatestop(i2c_typedef* i2cx, functionalstate newstate); void i2c_generatestop(i2c_typedef* i2cx, functionalstate newstate); na void i2c_10bitaddressheadercmd(i2c_typedef* i2cx, functionalstate newstate); void i2c_acknowledgeconfig(i2c_typedef* i2cx, functionalstate newstate); void i2c_acknowledgeconfig(i2c_typedef* i2cx, functionalstate newstate); na uint8_t i2c_getaddressmat ched(i2c_typedef* i2cx); na uint16_t i2c_gettransferdirection(i2c_typedef* i2cx); na void i2c_transferhandling(i2c_typedef* i2cx, uint16_t address, uint8_t number_bytes, uint32_t reloadendmode, uint32_t startstopmode); errorstatus i2c_checkevent(i2c_typedef* i2cx, uint32_t i2c_event) na void i2c_send7bitaddress(i2c_typedef* i2cx, uint8_t address, ui nt8_t i2c_direction) na table 27. stm32f10x and stm32f3xx i2c driver api correspondence (continued) stm32f10x i2c driver api stm32f3xx i2c driver api docid024110 rev 5 67/90 AN4228 firmware migration using the library 89 smbus management void i2c_smbusalertconfig(i2c_typedef* i2cx, uint16_t i2c_smbusalert); void i2c_smbusalertcmd(i2c_typedef* i2cx, functionalstate newstate); na void i2c_clocktimeoutcmd(i2c_typedef* i2cx, functionalstate newstate); na void i2c_extendedclocktimeoutcmd(i2c_typedef* i2cx, functionalstate newstate); na void i2c_idleclocktimeoutcmd(i2c_typedef* i2cx, functionalstate newstate); na void i2c_timeoutaconfig(i2c_typedef* i2cx, uint16_t timeout); na void i2c_timeoutbconfig(i2c_typedef* i2cx, uint16_t timeout); void i2c_calculatepec(i2c_typedef* i2cx, functionalstate newstate); void i2c_calculatepec(i2c_typedef* i2cx, functionalstate newstate); na void i2c_pecrequestcmd(i2c_typedef* i2cx, functionalstate newstate); uint8_t i2c_getpec(i2c_typedef* i2cx); uint8_t i2c_getpec(i2c_typedef* i2cx); data transfers uint32_t i2c_readregister(i2c_typedef* i2cx, uint8_t i2c_register); uint32_t i2c_readregister(i2c_typedef* i2cx, uint8_t i2c_register); void i2c_senddata(i2c_typedef* i2cx, uint8_t data); void i2c_senddata(i2c_typedef* i2cx, uint8_t data); uint8_t i2c_receivedata(i2c_typedef* i2cx); ui nt8_t i2c_receivedata(i2c_typedef* i2cx); dma management void i2c_dmacmd(i2c_typedef* i2cx, functionalstate newstate); void i2c_dmacmd(i2c_typedef* i2cx, uint32_t i2c_dmareq, functionalstate newstate); void i2c_dmalasttransfercmd(i2c_typedef* i2cx, functionalstate newstate); na table 27. stm32f10x and stm32f3xx i2c driver api correspondence (continued) stm32f10x i2c driver api stm32f3xx i2c driver api firmware migration using the library AN4228 68/90 docid024110 rev 5 though some api functions are identical in stm32f1 and stm32f3 devices, in most cases the application code needs to be rewritten when migrating from stm32f1 to stm32f3. however, stmicroelectronics provides an ?i2c communication peripheral application library (cpal)?, which allows to move seamlessly fr om stm32f1 to stm32f3: the user needs to modify only few settings without any changes on the application code. for more details about stm32f1 i2c cpal, please refer to um1029. for stm32f3, the i2c cpal is provided within the standard peripherals library package. interrupts and flags management flagstatus i2c_getflagstatus(i2c_typedef* i2cx, uint32_t i2c_flag); flagstatus i2c_getflagstatus(i2c_typedef* i2cx, uint32_t i2c_flag); void i2c_clearflag(i2c_typedef* i2cx, uint32_t i2c_flag); void i2c_clearflag(i2c_typedef* i2cx, uint32_t i2c_flag); itstatus i2c_getitstatus(i2c_typedef* i2cx, uint32_t i2c_it); itstatus i2c_getitstatus(i2c_typedef* i2cx, uint32_t i2c_it); void i2c_clearitpendingbit(i2c_typedef* i2cx, uint32_t i2c_it); void i2c_clearitpendingbit(i2c_typedef* i2cx, uint32_t i2c_it); table 27. stm32f10x and stm32f3xx i2c driver api correspondence (continued) stm32f10x i2c driver api stm32f3xx i2c driver api color key: = new function = same function, but api was changed = function not available (na) docid024110 rev 5 69/90 AN4228 firmware migration using the library 89 4.14 spi driver the stm32f3xx spi includes some new features as compared with stm32f10x spi. table 28 presents the spi driver api correspondence between stm32f10x and stm32f3xx libraries. table 28. stm32f10x and stm32f3xx spi driver api correspondence stm32f10x spi driver api stm32f3xx spi driver api initialization and configuration void spi_i2s_deinit(spi_typedef* spix); v oid spi_i2s_deinit(spi_typedef* spix); void spi_init(spi_typedef * spix, spi_i nittypedef* spi_initstruct); void spi_init(spi_typedef * spix, spi_inittypedef* spi_initstruct); void i2s_init(spi_typedef * spix, i2s_inittypedef* i2s_initstruct); void i2s_init(spi_typedef * spix, i2s_inittypedef* i2s_initstruct); void spi_structinit(spi_inittypedef * spi_initstruct); void spi_structini t(spi_inittypedef* spi_initstruct); void i2s_structinit(i2s_inittypedef * i2s_initstruct); void i2s_structin it(i2s_inittypedef* i2s_initstruct); na void spi_timodecmd(spi_typedef* spix, functionalstate newstate); na void spi_nsspulsemodecm d(spi_typedef* spix, functionalstate newstate); void spi_cmd(spi_typedef * spix, functionalstate newstate); void spi_cmd(spi_typedef* spix, functionalstate newstate); void i2s_cmd(spi_typedef* spix, functionalstate newstate); void i2s_cmd(spi_typedef* spix, functionalstate newstate); void spi_datasizeconfig (spi_typedef* spix, uint16_t spi_datasize); void spi_datasizeconfig(spi_typedef* spix, uint16_t spi_datasize); na void spi_rxfifothresholdconfig(spi_typedef* spix, uint16_t spi_rxfifothreshold); na void spi_bidirectionallineconfig(spi_typedef* spix, uint16_t spi_direction); void spi_nssinternalsoftwa reconfig(spi_typedef* spix, uint16_t spi _nssinternalsoft); void spi_nssinternalsoftwareconfig(spi_typedef* spix, uint16_t spi_nssinternalsoft); na void i2s_fullduplexconfig (spi_typedef* i2sxext, i2s_inittypedef* i2s_initstruct); (1) void spi_ssoutputcmd (spi_typedef* spix, functionalstate newstate); void spi_ssoutputcmd( spi_typedef* spix, functionalstate newstate); data transfers void spi_i2s_senddata(spi_typedef* spix, uint16_t data); void spi_senddata8(spi_typedef* spix, uint8_t data); void spi_i2s_senddata16(spi_typedef* spix, uint16_t data); uint16_t spi_i2s_receivedata(spi_typedef* spix); uint8_t spi_receivedata8(spi_typedef* spix); uint16_t spi_i2s_receivedata16(spi_typedef* spix); firmware migration using the library AN4228 70/90 docid024110 rev 5 hardware crc calculation functions na void spi_crclengthconfig(spi_typedef* spix, uint16_t spi_crclength); void spi_transmitcrc(spi_typedef* spix) ; void spi_transmitcrc(spi_typedef* spix); void spi_calculatec rc(spi_typedef* spix, functionalstate newstate); void spi_calculatecrc(spi_typedef* spix, functionalstate newstate); uint16_t spi_getcrc(spi_t ypedef* spix, uint8_t spi_crc); uint16_t spi_getcrc(spi_typedef* spix, uint8_t spi_crc); uint16_t spi_getcrcpolynomial(spi_typedef* spix); uint16_t spi_getcrcpolynomial(spi_typedef* spix); dma transfers void spi_i2s_dmacmd( spi_typedef* spix, uint16_t spi_i2s_dmareq, functionalstate newstate); void spi_i2s_dmacmd( spi_typedef* spix, uint16_t spi_i2s_dmareq, functionalstate newstate); na void spi_lastdmatransfe rcmd(spi_typedef* spix, uint16_t spi_lastdmatransfer); table 28. stm32f10x and stm32f3xx spi driver api correspondence (continued) stm32f10x spi driver api stm32f3xx spi driver api docid024110 rev 5 71/90 AN4228 firmware migration using the library 89 4.15 usart driver the stm32f3xx usart includes enhancements in comparison with stm32f10x usart. table9. presents the usart driver api co rrespondence between stm32f10x and stm32f3xx libraries. interrupts and flags management void spi_i2s_itconfig(spi _typedef* spix, uint8_t spi_i2s_it, functionalstate newstate); void spi_i2s_itconfig(spi_typedef* spix, uint8_t spi_i2s_it, functionalstate newstate); na uint16_t spi_gettransmissionfifo status(spi_typedef* spix); na uint16_t spi_getreceptionfifostatus(spi_typedef* spix); flagstatus spi_i2s_getfl agstatus(spi_typedef* spix, uint16_t spi_i2s_flag); flagstatus spi_i2s_getflagstatus(spi_typedef* spix, uint16_t spi_i2s_flag); (2) void spi_i2s_clearfl ag(spi_typedef* spix, uint16_t spi_i2s_flag); void spi_i2s_clearitpe ndingbit(spi_typedef* spix, uint8_t spi_i2s_it); void spi_i2s_clearflag(spi_typedef* spix, uint16_t spi_i2s_flag); (2) itstatus spi_i2s_getitst atus(spi_typedef* spix, uint8_t spi_i2s_it); itstatus spi_i2s_getitstatus(spi_typedef* spix, uint8_t spi_i2s_it); (2) 1. it is applicable only for stm32f30xx devices. 2. one more flag in stm32f3xx (ti frame format error) c an generate an event in comparison with stm32f10x driver api. table 28. stm32f10x and stm32f3xx spi driver api correspondence (continued) stm32f10x spi driver api stm32f3xx spi driver api color key: = new function = same function, but api was changed = function not available (na) firmware migration using the library AN4228 72/90 docid024110 rev 5 table 29. stm32f10x and stm32f3xx usart driver api correspondence stm32f10x usart driver api stm32f3xx usart driver api initialization and configuration void usart_deinit(usart_typedef* usartx); void usart_deinit(usart_typedef* usartx); void usart_init(usar t_typedef* usartx, usart_inittypedef* usart_initstruct); void usart_init(usar t_typedef* usartx, usart_inittypedef* usart_initstruct); void usart_structinit (usart_inittypedef* usart_initstruct); void usart_structinit (usart_inittypedef* usart_initstruct); void usart_clockinit(usart_typedef* usartx, usart_clockinittypedef* usart_clockinitstruct); void usart_clockinit(u sart_typedef* usartx, usart_clockinittypedef* usart_clockinitstruct); void usart_clockstructinit(u sart_clockinittypedef* usart_clockinitstruct); void usart_clockstructinit(u sart_clockinittypedef* usart_clockinitstruct); void usart_cmd(usart_typedef* usartx, functionalstate newstate); void usart_cmd(usart_typedef* usartx, functionalstate newstate); na void usart_directionmodecmd(usart_typedef* usartx, uint32_t usart_directionmode, functionalstate newstate); void usart_setpresca ler(usart_typedef* usartx, uint8_t usart_prescaler); void usart_setpresca ler(usart_typedef* usartx, uint8_t usart_prescaler); void usart_oversampling8cmd(usart_typedef* usartx, functionalstate newstate); void usart_oversampling8cmd(usart_typedef* usartx, functionalstate newstate); void usart_onebitmethodcmd(usart_typedef* usartx, functionalstate newstate); void usart_onebitmethodcmd(usart_typedef* usartx, functionalstate newstate); na void usart_msbfirst cmd(usart_typedef* usartx, functionalstate newstate); na void usart_datainvcmd(usart_typedef* usartx, functionalstate newstate); na void usart_invpincmd(usart_typedef* usartx, uint32_t usart_invpin, functionalstate newstate); na void usart_swappincmd(usart_typedef* usartx, functionalstate newstate); na void usart_receivertimeoutcmd(usart_typedef* usartx, functionalstate newstate); na void usart_setreceivertimeout(usart_typedef* usartx, uint32_t usart_receivertimeout); docid024110 rev 5 73/90 AN4228 firmware migration using the library 89 stop mode na void usart_stopmodecmd(usart_typedef* usartx, functionalstate newstate); na void usart_stopmodewakeup sourceconfig(usart_t ypedef* usartx, uint32_t usart_wakeupsource); autobaudrate na void usart_autobaudrat ecmd(usart_typedef* usartx, functionalstate newstate); na void usart_autobaudrateco nfig(usart_typedef* usartx, uint32_t usart_autobaudrate); data transfers void usart_senddata(u sart_typedef* usartx, uint16_t data); void usart_senddata(u sart_typedef* usartx, uint16_t data); uint16_t usart_receivedata(usart_typedef* usartx); uint16_t usart_receivedata(usart_typedef* usartx); multi-processor communication void usart_setaddress(usart_typedef* usartx, uint8_t usart_address); void usart_setaddress(usart_typedef* usartx, uint8_t usart_address); na void usart_mutemodewakeupconfig(usart_typede f* usartx, uint32_t usart_wakeup); na void usart_mutemodecmd(usart_typedef* usartx, functionalstate newstate); na void usart_addressdetectionconfig(usart_typedef* usartx, uint32_t usart_addresslength); table 29. stm32f10x and stm32f3xx usart driver api correspondence (continued) stm32f10x usart driver api stm32f3xx usart driver api firmware migration using the library AN4228 74/90 docid024110 rev 5 lin mode void usart_linbreakdetectlengthconfig(usart_typ edef* usartx, uint32_t usart_linbreakdetectlength); void usart_linbreakdetectlengthconfig(usart_typ edef* usartx, uint32_t usart_linbreakdetectlength); void usart_lincmd(usart_typedef* usartx, functionalstate newstate); void usart_lincmd(usart_typedef* usartx, functionalstate newstate); half-duplex mode void usart_halfduplexcmd(usart_typedef* usartx, functionalstate newstate); void usart_halfduplexcmd(usart_typedef* usartx, functionalstate newstate); smart card mode void usart_smartcardcmd(usart_typedef* usartx, functionalstate newstate); void usart_smartcardcmd(usart_typedef* usartx, functionalstate newstate); void usart_smartcardnackcmd(usart_typedef* usartx, functionalstate newstate); void usart_smartcardnackcmd(usart_typedef* usartx, functionalstate newstate); void usart_setguardtime(usart_typedef* usartx, uint8_t usart_guardtime); void usart_setguardtime(usart_typedef* usartx, uint8_t usart_guardtime); na void usart_setautoretry count(usart_typedef* usartx, uint8_t usart_autocount); na void usart_setblocklength(usart_typedef* usartx, uint8_t usart_blocklength); irda mode void usart_irdaconfig(usart_typedef* usartx, uint32_t usart_irdamode); void usart_irdaconfig(usart_typedef* usartx, uint32_t usart_irdamode); void usart_irdacmd(usart_typedef* usartx, functionalstate newstate); void usart_irdacmd(usart_typedef* usartx, functionalstate newstate); rs485 mode na void usart_decmd(usart_typedef* usartx, functionalstate newstate); na void usart_depolarityconfig(usart_typedef* usartx, uint32_t usart_depolarity); na void usart_setdeassertiontime(usart_typedef* usartx, uint32_t usart_deassertiontime); na void usart_setdedeasserti ontime(usart_typedef* usartx, uint32_t usart_dedeassertiontime); table 29. stm32f10x and stm32f3xx usart driver api correspondence (continued) stm32f10x usart driver api stm32f3xx usart driver api docid024110 rev 5 75/90 AN4228 firmware migration using the library 89 dma transfers void usart_dmacmd(usar t_typedef* usartx, uint32_t usart_dmareq, functionalstate newstate); void usart_dmacmd(usar t_typedef* usartx, uint32_t usart_dmareq, functionalstate newstate); void usart_dmareceptionerrorconfig(usart_typed ef* usartx, uint32_t usart_dmaonerror); void usart_dmareceptionerrorconfig(usart_typed ef* usartx, uint32_t usart_dmaonerror); interrupts and flags management void usart_itconfig(u sart_typedef* usartx, uint16_t usart_it, functionalstate newstate); void usart_itconfig(usart_typedef* usartx, uint32_t usart_it, functionalstate newstate); na void usart_requestcmd(usart_typedef* usartx, uint32_t usart_request, functionalstate newstate); na void usart_overrundetectionconfig(usart_typedef* usartx, uint32_t usart_ovrdetection); flagstatus usart_getflagstatus(u sart_typedef* usartx, uint16_t usart_flag); flagstatus usart_getflagstatus(usart_typedef* usartx, uint32_t usart_flag); void usart_clearflag(usart_typedef* usartx, uint16_t usart_flag); void usart_clearflag(usart_typedef* usartx, uint32_t usart_flag); itstatus usart_getitstatus(usart_typedef* usartx, uint32_t usart_it); itstatus usart_getitstatus(usart_typedef* usartx, uint32_t usart_it); void usart_clearitpendi ngbit(usart_typedef* usartx, uint32_t usart_it); void usart_clearitpendi ngbit(usart_typedef* usartx, uint32_t usart_it); table 29. stm32f10x and stm32f3xx usart driver api correspondence (continued) stm32f10x usart driver api stm32f3xx usart driver api color key: = new function = same function, but api was changed = function not available (na) firmware migration using the library AN4228 76/90 docid024110 rev 5 4.16 iwdg driver existing iwdg available on stm32f10x and stm32f3xx devices have the same specifications, with window capa bility additional feature in stm32f3 series which detect over frequency on external oscillators. th e table below lists the iwdg driver apis. table 30. stm32f10x and stm32f3xx iwdg driver api correspondence stm32f10x iwdg driver api stm32f3xx iwdg driver api prescaler and counter configuration void iwdg_writeaccesscmd(uint16_t iwdg_writeaccess); void iwdg_writeaccesscmd(uint16_t iwdg_writeaccess); void iwdg_setprescaler(uint8_t iwdg_prescaler); void iwdg_setprescaler(uint8_t iwdg_prescaler); void iwdg_setreload(uint16_t reload); v oid iwdg_setreload(uint16_t reload); void iwdg_reloadcounter(void); void iwdg_reloadcounter(void); na void iwdg_setwindowvalue(uint16_t windowvalue); iwdg activation void iwdg_enable(void); void iwdg_enable(void); docid024110 rev 5 77/90 AN4228 firmware migration using the library 89 4.17 fmc driver stm32f303xd/e devices provide a flexible memory controller (fmc) supporting asynchronous and synchronous memories (sram, psram, nor and nand). existing fsmc available on stm32f10x and fmc avai lable on stm32f303xd/e devices have the same specifications. the table below shows the fsmc/fmc driver api correspondence between stm32f10x and stmf3xx libraries. flag management flagstatus iwdg_getflagstatus(uint16_t iwdg_flag); flagstatus iwdg_getflagstatus(uint16_t iwdg_flag); table 30. stm32f10x and stm32f3xx iwdg driver api correspondence (continued) stm32f10x iwdg driver api stm32f3xx iwdg driver api color key: = new function = same function, but api was changed = function not available (na) table 31. stm32f10x and stm32f303xd/e fmc driver api correspondence stm32f10x fsmc driver api stm32f303xd/e fmc driver api nor/sram contro ller functions void fsmc_norsramdeinit( uint32_t fsmc_bank); void fmc_norsramdeini t(uint32_t fmc_bank); void fsmc_norsraminit( fsmc_norsraminittypedef* fsmc_norsraminitstruct); void fmc_norsraminit(fmc_norsraminittypede f* fmc_norsraminitstruct); void fsmc_norsramstructinit( fsmc_norsraminittypedef* fsmc_norsraminitstruct); void fmc_norsramstructinit(fmc_norsraminitty pedef* fmc_norsraminitstruct); void fsmc_norsramcmd(uint32_t fsmc_bank, functionalstate newstate); void fmc_norsramcmd(uint32_t fmc_bank, functionalstate newstate); firmware migration using the library AN4228 78/90 docid024110 rev 5 nand controller functions void fsmc_nanddeinit(uint32_t fsmc_bank) ; void fmc_nanddeinit(uint32_t fmc_bank); void fsmc_nandinit(fsmc_nandinittypedef* fsmc_nandinitstruct); void fmc_nandinit(fmc_nandinittypedef* fmc_nandinitstruct); void fsmc_nandstructinit(fsmc_nandinittypedef* fsmc_nandinitstruct); void fmc_nandstructinit(fmc_nandinittypedef* fmc_nandinitstruct); void fsmc_nandcmd(uint32_t fsmc_bank, functionalstate newstate); void fmc_nandcmd(uint32_t fmc_bank, functionalstate newstate); void fsmc_nandecccmd(uint32_t fsmc_bank, functionalstate newstate); void fmc_nandecccmd(uint32_t fmc_bank, functionalstate newstate); uint32_t fsmc_getecc(uint32_t fsmc_bank); uint32_t fmc_getecc(uint32_t fmc_bank); pccard controller functions void fsmc_pccarddeinit(void); void fmc_pccarddeinit(void); void fsmc_pccardinit(fsmc_pccardinittypedef* fsmc_pccardinitstruct); void fmc_pccardinit(fmc_pccardinittypedef* fmc_pccardinitstruct); void fsmc_pccardstructinit(fsmc_pccardinittyped ef* fsmc_pccardinitstruct); void fmc_pccardstructinit(fmc_pccardinittyped ef* fmc_pccardinitstruct); void ? fsmc_pccardcmd(functionalstate newstate); void ? fmc_pccardcmd(functionalstate newstate); table 31. stm32f10x and stm32f303xd/e fmc driver api correspondence (continued) stm32f10x fsmc driver api stm32f303xd/e fmc driver api docid024110 rev 5 79/90 AN4228 firmware migration using the library 89 interrupts and flags management functions void fsmc_itconfig(uint 32_t fmc_bank,uint32_t fmc_it,functionalstate newstate); void fmc_itconfig(uint32_t fmc_bank uint32_t fmc_it, functionalstate newstate); flagstatus fsmc_get flagstatus(uint32_t fsmc_bank,uint32_t fsmc_flag); flagstatus fmc_getflagstatus(uint32_t fmc_bank,uint32_t fmc_flag); void fsmc_clearflag(uint32_t fsmc_bank,uint32_t fsmc_flag); void fmc_clearflag(uint32_t fmc_bank,uint32_t fmc_flag); itstatus fsmc_get itstatus(uint32_t fsmc_bank,uint32_t fsmc_it); itstatus fmc_getitstatus(uint32_t fmc_bank uint32_t fmc_it); void fsmc_clearitpendingbit(uint32_t fsmc_bank,uint32_t fsmc_it); void fmc_clearitpendingbit(uint32_t fmc_bank,uint32_t fmc_it); table 31. stm32f10x and stm32f303xd/e fmc driver api correspondence (continued) stm32f10x fsmc driver api stm32f303xd/e fmc driver api firmware migration using the library AN4228 80/90 docid024110 rev 5 4.18 tim driver existing tim available on stm32f10x and stm32f3xx devices have the same specifications, with additional features in stm32f3 series. the table below lists the tim driver apis. table 32. stm32f10x and stm32f3xx tim driver api correspondence stm32f10x tim driver api stm32f3xx tim driver api time base management void tim_deinit(tim_typedef* timx); void tim_deinit(tim_typedef* timx); void tim_timebaseinit (tim_typedef* timx, tim_timebaseinittypedef* tim_timebaseinitstruct); void tim_timebaseinit (tim_typedef* timx, tim_timebaseinittypedef* tim_timebaseinitstruct); void tim_timebasestructinit (tim_timebaseinittype def* tim_timebaseinitstruct); void tim_timebasestructinit(tim_timebaseinittypedef* tim_timebaseinitstruct); void tim_prescalerconfig(tim_typedef* timx, uint16_t prescaler, uint16_t tim_pscreloadmode); void tim_prescalerconfig(tim_typedef* timx, uint16_t prescaler, uint16_t tim_pscreloadmode); void tim_countermodeconfig(tim_typedef* timx, uint16_t tim_countermode); void tim_countermodeconfig(tim_typedef* timx, uint16_t tim_countermode); void tim_setcounter(tim_typedef* timx, uint16_t counter); void tim_setcounter(tim_typedef* timx, uint16_t counter); void tim_setautoreload(tim_typedef* timx, uint16_t autoreload); void tim_setautoreload(tim_typedef* timx, uint16_t autoreload); uint16_t tim_getcounter(tim_typedef* timx); uint16_t tim_getcounter(tim_typedef* timx); uint16_t tim_getprescaler(tim_typedef* timx); uint16_t tim_getprescaler(tim_typedef* timx); void tim_updatedisableconfig(tim_typedef* timx, functionalstate newstate); void tim_updatedisableco nfig(tim_typedef* timx, functionalstate newstate); void tim_updaterequestconfig(tim_typedef* timx, uint16_t tim_updatesource); void tim_updaterequestconfig(tim_typedef* timx, uint16_t tim_updatesource); na void tim_uifremap(tim_typedef* timx, functionalstate newstate); (1) void tim_arrpreloadconfig(tim_typedef* timx, functionalstate newstate); void tim_arrpreloadconfi g(tim_typedef* timx, functionalstate newstate); void tim_selectonepulsemode(tim_typedef* timx, uint16_t tim_opmode); void tim_selectonepulsemode(tim_typedef* timx, uint16_t tim_opmode); void tim_setclockdivision(tim_typedef* timx, uint16_t tim_ckd); void tim_setclockdivision(tim_typedef* timx, uint16_t tim_ckd); void tim_cmd(tim_typedef* timx, functionalstate newstate); void tim_cmd(tim_typedef* timx, functionalstate newstate); docid024110 rev 5 81/90 AN4228 firmware migration using the library 89 output compare management void tim_oc1init(tim_typedef* timx, tim_ocinittypedef* tim_ocinitstruct); void tim_oc1init(tim_typedef* timx, tim_ocinittypedef* tim_ocinitstruct); void tim_oc2init(tim_typedef* timx, tim_ocinittypedef* tim_ocinitstruct); void tim_oc2init(tim_typedef* timx, tim_ocinittypedef* tim_ocinitstruct); void tim_oc3init(tim_typedef* timx, tim_ocinittypedef* tim_ocinitstruct); void tim_oc3init(tim_typedef* timx, tim_ocinittypedef* tim_ocinitstruct); void tim_oc4init(tim_typedef* timx, tim_ocinittypedef* tim_ocinitstruct); void tim_oc4init(tim_typedef* timx, tim_ocinittypedef* tim_ocinitstruct); na void tim_oc5init(tim_typedef* timx, tim_ocinittypedef* tim_ocinitstruct); (1) na void tim_oc6init(tim_typedef* timx, tim_ocinittypedef* tim_ocinitstruct); (1) na void tim_selectgc5c1(tim_typedef* timx, functionalstate newstate); (1) na void tim_selectgc5c2(tim_typedef* timx, functionalstate newstate); (1) na void tim_selectgc5c3(tim_typedef* timx, functionalstate newstate); (1) void tim_ocstructinit(tim_ocinittypedef* tim_ocinitstruct); void tim_ocstructinit (tim_ocinittypedef* tim_ocinitstruct); na void tim_selectocxm(tim_typedef* timx, uint16_t tim_channel, uint32_t tim_ocmode); void tim_setcompare1( tim_typedef* timx, uint32_t compare1); void tim_setcompare1(tim_typedef* timx, uint32_t compare1); void tim_setcompare2( tim_typedef* timx, uint32_t compare2); void tim_setcompare2(tim_typedef* timx, uint32_t compare2); void tim_setcompare3( tim_typedef* timx, uint32_t compare3); void tim_setcompare3(tim_typedef* timx, uint32_t compare3); void tim_setcompare4( tim_typedef* timx, uint32_t compare4); void tim_setcompare4(tim_typedef* timx, uint32_t compare4); na void tim_setcompare5(tim_typedef* timx, uint32_t compare5); (1) na void tim_setcompare6(tim_typedef* timx, uint32_t compare6); (1) void tim_forcedoc1config(tim_typedef* timx, uint16_t tim_forcedaction); void tim_forcedoc1config(tim_typedef* timx, uint16_t tim_forcedaction); void tim_forcedoc2config(tim_typedef* timx, uint16_t tim_forcedaction); void tim_forcedoc2config(tim_typedef* timx, uint16_t tim_forcedaction); void tim_forcedoc3config(tim_typedef* timx, uint16_t tim_forcedaction); void tim_forcedoc3config(tim_typedef* timx, uint16_t tim_forcedaction); void tim_forcedoc4config(tim_typedef* timx, uint16_t tim_forcedaction); void tim_forcedoc4config(tim_typedef* timx, uint16_t tim_forcedaction); table 32. stm32f10x and stm32f3xx tim driver api correspondence (continued) stm32f10x tim driver api stm32f3xx tim driver api firmware migration using the library AN4228 82/90 docid024110 rev 5 output compare management na void tim_forcedoc5config(tim_typedef* timx, uint16_t tim_forcedaction); (1) na void tim_forcedoc6config(tim_typedef* timx, uint16_t tim_forcedaction); (1) void tim_oc1preloadconfig(tim_typedef* timx, uint16_t tim_ocpreload); void tim_oc1preloadconfig(tim_typedef* timx, uint16_t tim_ocpreload); void tim_oc2preloadconfig(tim_typedef* timx, uint16_t tim_ocpreload); void tim_oc2preloadconfig(tim_typedef* timx, uint16_t tim_ocpreload); void tim_oc3preloadconfig(tim_typedef* timx, uint16_t tim_ocpreload); void tim_oc3preloadconfig(tim_typedef* timx, uint16_t tim_ocpreload); void tim_oc4preloadconfig(tim_typedef* timx, uint16_t tim_ocpreload); void tim_oc4preloadconfig(tim_typedef* timx, uint16_t tim_ocpreload); na void tim_oc5preloadconfig(tim_typedef* timx, uint16_t tim_ocpreload); (1) na void tim_oc6preloadconfig(tim_typedef* timx, uint16_t tim_ocpreload); (1) void tim_oc1fastconfig(tim_typedef* timx, uint16_t tim_ocfast); void tim_oc1fastconfig(tim_typedef* timx, uint16_t tim_ocfast); void tim_oc2fastconfig(tim_typedef* timx, uint16_t tim_ocfast); void tim_oc2fastconfig(tim_typedef* timx, uint16_t tim_ocfast); void tim_oc3fastconfig(tim_typedef* timx, uint16_t tim_ocfast); void tim_oc3fastconfig(tim_typedef* timx, uint16_t tim_ocfast); void tim_oc4fastconfig(tim_typedef* timx, uint16_t tim_ocfast); void tim_oc4fastconfig(tim_typedef* timx, uint16_t tim_ocfast); void tim_clearoc1ref(tim_typedef* timx, uint16_t tim_occlear); void tim_clearoc1ref(tim_t ypedef* timx, uint16_t tim_occlear); void tim_clearoc2ref(tim_typedef* timx, uint16_t tim_occlear); void tim_clearoc2ref(tim_t ypedef* timx, uint16_t tim_occlear); void tim_clearoc3ref(tim_typedef* timx, uint16_t tim_occlear); void tim_clearoc3ref(tim_t ypedef* timx, uint16_t tim_occlear); void tim_clearoc4ref(tim_typedef* timx, uint16_t tim_occlear); void tim_clearoc4ref(tim_t ypedef* timx, uint16_t tim_occlear); na void tim_clearoc5ref(tim_t ypedef* timx, uint16_t tim_occlear); (1) na void tim_clearoc6ref(tim_t ypedef* timx, uint16_t tim_occlear); (1) na void tim_selectocrefclear(tim_typedef* timx, uint16_t tim_ocreferenceclear); (1) void tim_oc1polarityconfig(tim_typedef* timx, uint16_t tim_ocpolarity); void tim_oc1polaritycon fig(tim_typedef* timx, uint16_t tim_ocpolarity); void tim_oc1npolarityconfig(tim_typedef* timx, uint16_t tim_ocnpolarity); void tim_oc1npolarityconfig(tim_typedef* timx, uint16_t tim_ocnpolarity); table 32. stm32f10x and stm32f3xx tim driver api correspondence (continued) stm32f10x tim driver api stm32f3xx tim driver api docid024110 rev 5 83/90 AN4228 firmware migration using the library 89 output compare management void tim_oc2polarityconfig(tim_typedef* timx, uint16_t tim_ocpolarity); void tim_oc2polaritycon fig(tim_typedef* timx, uint16_t tim_ocpolarity); void tim_oc2npolarityconfig(tim_typedef* timx, uint16_t tim_ocnpolarity); void tim_oc2npolarityconfig(tim_typedef* timx, uint16_t tim_ocnpolarity); void tim_oc3polarityconfig(tim_typedef* timx, uint16_t tim_ocpolarity); void tim_oc3polaritycon fig(tim_typedef* timx, uint16_t tim_ocpolarity); void tim_oc3npolarityconfig(tim_typedef* timx, uint16_t tim_ocnpolarity); void tim_oc3npolarityconfig(tim_typedef* timx, uint16_t tim_ocnpolarity); void tim_oc4polarityconfig(tim_typedef* timx, uint16_t tim_ocpolarity); void tim_oc4polaritycon fig(tim_typedef* timx, uint16_t tim_ocpolarity); na void tim_oc5polaritycon fig(tim_typedef* timx, uint16_t tim_ocpolarity); na void tim_oc6polaritycon fig(tim_typedef* timx, uint16_t tim_ocpolarity); void tim_ccxcmd(tim_typedef* timx, uint16_t tim_channel, uint16_t tim_ccx); void tim_ccxcmd(tim_typedef* timx, uint16_t tim_channel, uint16_t tim_ccx); void tim_ccxncmd(tim_typedef* timx, uint16_t tim_channel, uint16_t tim_ccxn); void tim_ccxncmd(tim_typedef* timx, uint16_t tim_channel, uint16_t tim_ccxn); input capture management void tim_icinit(tim_typedef* timx, tim_icinittypedef* tim_icinitstruct); void tim_icinit(tim_typedef* timx, tim_icinittypedef* tim_icinitstruct); void tim_icstructinit(tim_icinittypedef* tim_icinitstruct); void tim_icstructinit(tim_icinittypedef* tim_icinitstruct); void tim_pwmiconfig(tim_typedef* timx, tim_icinittypedef* tim_icinitstruct); void tim_pwmiconfig(tim_typedef* timx, tim_icinittypedef* tim_icinitstruct); uint32_t tim_getcapt ure1(tim_typedef* timx); uint32_t tim_getcapture1 (tim_typedef* timx); uint32_t tim_getcapt ure2(tim_typedef* timx); uint32_t tim_getcapture2 (tim_typedef* timx); uint32_t tim_getcapt ure3(tim_typedef* timx); uint32_t tim_getcapture3 (tim_typedef* timx); uint32_t tim_getcapt ure4(tim_typedef* timx); uint32_t tim_getcapture4 (tim_typedef* timx); void tim_setic1prescale r(tim_typedef* timx, uint16_t tim_icpsc); void tim_setic1prescaler(tim_typedef* timx, uint16_t tim_icpsc); void tim_setic2prescale r(tim_typedef* timx, uint16_t tim_icpsc); void tim_setic2prescaler(tim_typedef* timx, uint16_t tim_icpsc); void tim_setic3prescale r(tim_typedef* timx, uint16_t tim_icpsc); void tim_setic3prescaler(tim_typedef* timx, uint16_t tim_icpsc); void tim_setic4prescale r(tim_typedef* timx, uint16_t tim_icpsc); void tim_setic4prescaler(tim_typedef* timx, uint16_t tim_icpsc); table 32. stm32f10x and stm32f3xx tim driver api correspondence (continued) stm32f10x tim driver api stm32f3xx tim driver api firmware migration using the library AN4228 84/90 docid024110 rev 5 advanced-control timers (tim 1 and tim8) specific features void tim_bdtrconfig(tim_typedef* timx, tim_bdtrinittypedef *tim_bdtrinitstruct); void tim_bdtrconfig(tim_typedef* timx, tim_bdtrinittypedef *tim_bdtrinitstruct); na void tim_break1config(tim_typedef* timx, uint32_t tim_break1polarity, uint 8_t tim_break1filter); (1) na void tim_break2config(tim_typedef* timx, uint32_t tim_break2polarity, uint 8_t tim_break2filter); (1) na void tim_break1cmd(tim_typedef* timx, functionalstate newstate); (1) na void tim_break2cmd(tim_typedef* timx, functionalstate newstate); (1) void tim_bdtrstructinit(tim_bdtrinittypedef* tim_bdtrinitstruct); void tim_bdtrstructinit (tim_bdtrinittypedef* tim_bdtrinitstruct); void tim_ctrlpwmoutputs(tim_typedef* timx, functionalstate newstate); void tim_ctrlpw moutputs(tim_typedef* timx, functionalstate newstate); void tim_selectcom(tim_typedef* timx, functionalstate newstate); void tim_selectcom(tim_typedef* timx, functionalstate newstate); void tim_ccpreloadcontrol(tim_typedef* timx, functionalstate newstate); void tim_ccpreloadcontro l(tim_typedef* timx, functionalstate newstate); interrupts, dma and flags management void tim_itconfig(tim_typedef* timx, uint16_t tim_it, functionalstate newstate); void tim_itconfig(tim_typed ef* timx, uint16_t tim_it, functionalstate newstate); void tim_generateevent(tim_typedef* timx, uint16_t tim_eventsource); void tim_generateevent(tim_typedef* timx, uint16_t tim_eventsource); flagstatus tim_getflagstatus(tim_typedef* timx, uint32_t tim_flag); flagstatus tim_getflagstatus(tim_typedef* timx, uint32_t tim_flag); void tim_clearflag(tim_typedef* timx, uint16_t tim_flag); void tim_clearflag(tim_t ypedef* timx, uint16_t tim_flag); itstatus tim_getitstatus(tim_typedef* timx, uint16_t tim_it); itstatus tim_getitstatus(ti m_typedef* timx, uint16_t tim_it); void tim_clearitpendingbit(tim_typedef* timx, uint16_t tim_it); void tim_clearitpendingbit(tim_typedef* timx, uint16_t tim_it); void tim_dmaconfig(tim_typedef* timx, uint16_t tim_dmabase, uint16_t tim_dmaburstlength); void tim_dmaconfig(tim_t ypedef* timx, uint16_t tim_dmabase, uint16_t tim_dmaburstlength); void tim_dmacmd(tim_typedef* timx, uint16_t tim_dmasour ce, functionalstate newstate); void tim_dmacmd(tim_typedef* timx, uint16_t tim_dmasource, functionalstate newstate); void tim_selectccdma(tim_typedef* timx, functionalstate newstate); void tim_selectccdma (tim_typedef* timx, functionalstate newstate); table 32. stm32f10x and stm32f3xx tim driver api correspondence (continued) stm32f10x tim driver api stm32f3xx tim driver api docid024110 rev 5 85/90 AN4228 firmware migration using the library 89 clocks management void tim_internalclockconfig(tim_typedef* timx); void tim_internalclockconfig(tim_typedef* timx); void tim_itrxexternalclockc onfig(tim_typedef* timx, uint16_t tim_inputtriggersource); void tim_itrxexternalclockconfig(tim_typedef* timx, uint16_t tim_inputtriggersource); void tim_tixexternalclockc onfig(tim_typedef* timx, uint16_t tim_tixexternalclksource, uint16_t tim_icpolarity, uint16_t icfilter); void tim_tixexternalclockc onfig(tim_typedef* timx, uint16_t tim_tixexternal clksource, uint16_t tim_icpolarity, ui nt16_t icfilter); void tim_etrclockmode1config(tim_typedef* timx, uint16_t tim_exttrgprescaler, uint16_t tim_exttrgpolarity, ui nt16_t exttrgfilter); void tim_etrclockmode1config(tim_typedef* timx, uint16_t tim_exttrgprescaler, uint16_t tim_exttrgpolarity, ui nt16_t exttrgfilter); void tim_etrclockmode2config(tim_typedef* timx, uint16_t tim_exttrgprescaler, uint16_t tim_exttrgpolarity, ui nt16_t exttrgfilter); void tim_etrclockmode2config(tim_typedef* timx, uint16_t tim_exttrgprescaler, uint16_t tim_exttrgpolarity, ui nt16_t exttrgfilter); synchronization management void tim_selectinputtrigger(tim_typedef* timx, uint16_t tim_inputtriggersource); void tim_selectinputtrigger(t im_typedef* timx, uint16_t tim_inputtriggersource); void tim_selectoutputtrigger(tim_typedef* timx, uint16_t tim_trgosource); void tim_selectoutputtr igger(tim_typedef* timx, uint16_t tim_trgosource); na void tim_selectoutputtrig ger2(tim_typedef* timx, uint32_t tim_trgo2source); (1) void tim_selectslavemode(tim_typedef* timx, uint32_t tim_slavemode); void tim_selectslavemode(tim_typedef* timx, uint32_t tim_slavemode); void tim_selectmasterslavemode(tim_typedef* timx, uint16_t tim_masterslavemode); void tim_selectmasterslav emode(tim_typedef* timx, uint16_t tim_masterslavemode); void tim_etrconfig(tim_typedef* timx, uint16_t tim_exttrgpr escaler, uint16_t tim_exttrgpolarity, ui nt16_t exttrgfilter); void tim_etrconfig(tim_typedef* timx, uint16_t tim_exttrgpre scaler, uint16_t tim_exttrgpolarity, uint16_t exttrgfilter); table 32. stm32f10x and stm32f3xx tim driver api correspondence (continued) stm32f10x tim driver api stm32f3xx tim driver api firmware migration using the library AN4228 86/90 docid024110 rev 5 specific interface management void tim_encoderinterfaceconfig(tim_typedef* timx, uint16_t tim_encodermode, uint16_t tim_ic1polarity, uint16_t tim_ic2polarity); void tim_encoderinterfaceconfig(tim_typedef* timx, uint16_t tim_encodermode, uint16_t tim_ic1polarity, uint16_t tim_ic2polarity); void tim_selecthallsensor(tim_typedef* timx, functionalstate newstate); void tim_selecthallsensor(tim_typedef* timx, functionalstate newstate); specific remapping management na void tim_remapconfig(tim_t ypedef* timx, uint16_t tim_remap); 1. those functions are applicable only for stm32f30xx devices. table 32. stm32f10x and stm32f3xx tim driver api correspondence (continued) stm32f10x tim driver api stm32f3xx tim driver api color key: = new function = same function, but api was changed = function not available (na) docid024110 rev 5 87/90 AN4228 firmware migration using the library 89 4.19 dbgmcu driver existing dbgmcu available on stm32f10x and stm32f3xx devices have the same specifications. the table belo w lists the dbgmcu driver apis. table 33. stm32f10x and stm32f3xx dbgmcu driver api correspondence stm32f10x dbgmcu driver api stm32f3xx dbgmcu driver api device and revision id management uint32_t dbgmcu_getrevid(void); uint32_t dbgmcu_getrevid(void); uint32_t dbgmcu_getdevid(void); uint32_t dbgmcu_getdevid(void); peripherals configuration void dbgmcu_config(uint32_t dbgmcu_periph, functionalstate newstate); void dbgmcu_config(uin t32_t dbgmcu_periph, functionalstate newstate); na void dbgmcu_apb1peri phconfig(uint32_t dbgmcu_periph, functionalstate newstate); na void dbgmcu_apb2peri phconfig(uint32_t dbgmcu_periph, functionalstate newstate); color key: = new function = same function, but api was changed = function not available (na) revision history AN4228 88/90 docid024110 rev 5 5 revision history table 34. document revision history date revision changes 19-feb-2013 1 initial release 20-mar-2014 2 updated table 2 , table 3 , table 7 , table 8 , table 9 , table 12 , table 13 , table 14 , table 15 , table 16 , table 18 and table 24 . added table 17: adc channels mapping differences . updated section 3.2: system architecture , section 3.4.3: peripheral clock configuration , section 3.15: usart interface and section 3.16: cec interface . updated figure 1 . 04-apr-2014 3 removed references to products with 16 kbytes of flash memory (stm32f301x4, stm32f302x4 and stm32f303x4). updated table 3 docid024110 rev 5 89/90 AN4228 revision history 89 28-jan-2015 4 extended the document applicabilit y to stm32f303xdxe devices. updated: ? table 2: stm32f103 and stm32f3xx line available packages ? the text after table 3: main pinout differences between stm32f10x and stm32f30x lines ? table 7: stm32 peripheral compatibility analysis stm32f1 versus stm32f3 series ? section 3.2: system architecture ? figure 1: system architecture for stm32f30x and stm32f3x8 lines ? table 8: ip bus mapping differences between stm32f3 and stm32f1 series ? section 3.4.1: system cl ock configuration ? section 3.4.3: peripheral clock configuration ? table 12: dma request differences between stm32f3xx and stm32f1xx ? table 13: interrupt vector differences between stm32f3 and stm32f1 series ? section 3.7.1: alternat e function mode ? table 16: adc differences between stm32f1 series and stm32f30x lines ? table 17: adc channels mapping differences ? table 20: stm32f10x and stm32f3xx flash driver api correspondence ? table 23: stm32f10x and stm32f3xx adc driver api correspondence ? table 24: stm32f10x and stm32f3xx dac driver api correspondence added ? section 4.17: fmc driver 05-mar-2015 5 updated: ? the number of adc channels for stm32f303x6/8 in table 16: adc differences between stm32f1 series and stm32f30x lines , ? pb1, pb2 and pb23 entries for stm32f303x6/8 in table 17: adc channels mapping differences . table 34. document revision history (continued) date revision changes AN4228 90/90 docid024110 rev 5 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved |
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