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stk12c68-5 (s md5962-94599) 64 kbit (8 k x 8) autostore nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-51026 rev. *a revised february 17, 2012 features 35 ns and 55 ns access times hands off automatic store on power down with external 68 f capacitor store to quantumtrap? nonvolatile elements is initiated by software, hardware, or autostore? on power down recall to sram initiated by software or power up unlimited read, writ e, and recall cycles 1,000,000 store cycl es to quantumtrap 100 year data retention to quantumtrap single 5 v + 10% operation military temperature 28-pin (300mil) cdip and 28-pad lcc packages functional description the cypress stk12c68-5 is a fast static ram with a nonvolatile element in each memory cell. the embedded nonvolatile elements incorporate quantumtrap technology producing the world?s most reliable nonvolatile memory. the sram provides unlimited r ead and write cycles, while independent nonvolatile data resides in the highly reliable quantumtrap cell. data transf ers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. a hardware store is initiated with the hsb pin. logic block diagram store/ recall control power control software detect static ram array 128 x 512 quantum trap 128 x 512 store recall column i/o column dec row decoder input buffers oe ce we hsb v cc v cap a 0 - a 12 a 0 a 1 a 2 a 3 a 4 a 10 a 5 a 6 a 7 a 8 a 9 a 11 a 12 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 2 of 18 pinouts pin definitions pin name alt io type description a 0 ?a 12 input address inputs . used to select one of the 8,192 bytes of the nvsram. dq 0 -dq 7 input or output bidirectional data io lines . used as input or output lines depending on operation. we w input write enable input, active low . when the chip is enabled and we is low, data on the i/o pins is written to the specific address location. ce e input chip enable input, active low . when low, selects the chip . when high, deselects the chip. oe g input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the i/o pins to tristate. v ss ground ground for the device . the device is connected to ground of the system. v cc power supply power supply inputs to the device . hsb input or output hardware store busy (hsb ) . when low, this output indicates a hardware store is in progress. when pulled low external to the chip , it initiates a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected (connection optional). v cap power supply autostore capacitor . supplies power to nvsram during power loss to store data from sram to nonvolatile elements. figure 1. pin diagram - 28-pin dip figure 2. pin diagram - 28-pin llc
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 3 of 18 contents device operation .............................................................. 4 sram read ....................................................................... 4 sram write ....................................................................... 4 autostore operation ........................................................ 4 autostore inhibit mode .................................................... 5 hardware store (hsb) operation ................................. 5 hardware recall (power up) ........................................ 5 software store ............................................................... 5 software recall ............................................................. 5 data protection ................................................................. 6 noise considerations ....................................................... 6 hardware protect .............................................................. 6 low average active power .............................................. 6 preventing store ............................................................... 6 best practices ................................................................... 7 maximum ratings ............................................................. 8 operating range .............................................................. 8 dc electrical characteristics .......................................... 8 data retention and endurance ....................................... 9 capacitance ...................................................................... 9 thermal resistance .......................................................... 9 ac test conditions .......................................................... 9 sram read cycle .................................................... 10 sram write cycle ..................................................... 11 autostore or power up recall .................................. 12 software controlled store/recall cycle ................ 13 switching waveform ...................................................... 14 part numbering nomenclature ...................................... 15 ordering information ...................................................... 16 acronyms ........................................................................ 17 document conventions ................................................. 17 units of measure ....................................................... 17 document history page ................................................ 18 sales, solutions, and legal information ...................... 18 worldwide sales and design s upport ......... .............. 18 products .................................................................... 18 psoc solutions ......................................................... 18
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 4 of 18 device operation the stk12c68-5 nvsram is made up of two functional components paired in the same physical cell. these are an sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferr ed to the nonvolatile cell (the store operation) or from the nonvolatile cell to sram (the recall operation). this unique architecture enables the storage and recall of all cells in parallel. during the store and recall operations, sram re ad and write operations are inhibited. the stk12c68-5 supports unlimited reads and writes similar to a typical sram. in addition, it provides unlimited recall operations from the nonvolatile cells and up to one million store operations. sram read the stk12c68-5 performs a read cycle whenever ce and oe are low while we and hsb are high. the address specified on pins a 0?12 determines the 8,192 data bytes accessed. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (read cycle 1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data outputs repeatedly respond to address changes within the t aa access time without the need for transitions on any control input pins, and remains valid until anot her address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed whenever ce and we are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must remain stable until either ce or we goes high at the end of the cycle. the data on the common i/o pins dq 0?7 are written into the memory if it has valid t sd , before the end of a we controlled write or before the end of an ce controlled write. keep oe high during the entire write cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the stk12c68-5 stores data to nvsram using one of three storage operations: 1. hardware store activated by hsb 2. software store activated by an address sequence 3. autostore on device power down autostore operation is a un ique feature of quantumtrap technology and is enabled by default on the stk12c68-5. during normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. figure 3 shows the proper connecti on of the storage capacitor (v cap ) for automatic store oper ation. a charge storage capacitor between 68 f and 220 f (+ 20%) rated at 6 v must be provided. the voltage on the v cap pin is driven to 5 v by a charge pump internal to the chip. a pull-up is placed on we to hold it inactive during power up. in system power mode, both v cc and v cap are connected to the +5 v power supply without the 68 ? f capacitor. in this mode, the autostore function of the stk12c68-5 operates on the stored system charge as power goes down. the user must, however, guarantee that v cc does not drop below 3.6 v during the 10 ms store cycle. to reduce unnecessary nonvolatile stores, autostore, and hardware store operations are ignored, unless at least one write operation has taken place since the most recent store or recall cycle. software initiated store cycles are performed regardless of whethe r a write operation has taken place. an optional pull-up resi stor is shown connected to hsb . the hsb signal is monitored by the system to detect if an autostore cycle is in progress. figure 3. autostore mode vcc v cap m h o k 0 1 f 8 6 5 % 0 2 + , v 6 m h o k 0 1 we hsb vss f 1 . 0 5 s s a p y b
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 5 of 18 figure 4. autostore inhibit mode if the power supply drops faster than 20 ? s/volt before v cc reaches v switch , then a 2.2 ? resistor must be connected between v cc and the system supply to avoid momentary excess of current between v cc and v cap . autostore inhibit mode if an automatic store on power loss is not required, then v cc is tied to ground and +5 v is applied to v cap ( figure 4 ). this is the autostore inhibit mode, wh ere the autostore function is disabled. if the stk12c68-5 is operated in this configuration, references to v cc are changed to v cap throughout this data sheet. in this mode, store operations are triggered through software control or the hsb pin. to enable or disable autostore using an i/o port pin see preventing store on page 6 . it is not permissible to change between these three options ?on the fly?. hardware store (hsb ) operation the stk12c68-5 provides the hsb pin for controlling and acknowledging the store operations. the hsb pin is used to request a hardware stor e cycle. when the hsb pin is driven low, the stk12c68-5 conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram takes place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is inter- nally driven low to indicate a busy condition, while the store (initiated by any means) is in progress. sram read and write operatio ns, that are in progress when hsb is driven low by any means, are given time to complete before the store operation is initiated. after hsb goes low, the stk12c68-5 continues sram operations for t delay . during t delay , multiple sram read operations take place. if a write is in progress when hsb is pulled low, it allows a time, t delay to complete. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. during any store operation, regardless of how it is initiated, the stk12c68-5 continues to drive the hsb pin low, releasing it only when the store is complete. after completing the store operation, the stk12c68-5 remains disabled until the hsb pin returns high. if hsb is not used, it is left unconnected. hardware recall (power up) during power-up or after any low-power condition (v cc < v reset ), an internal recall request is latched. when v cc once again exceeds the sense voltage of v switch , a recall cycle is automatically initiated and takes t hrecall to complete. if the stk12c68-5 is in a write state at the end of power-up recall, the sram data is corrupted. to help avoid this situation, a 10 k ? resistor is connected either between we and system v cc or between ce and system v cc . software store data is transferred from the sr am to the nonvolatile memory by a software address sequence. the stk12c68-5 software store cycle is initiated by executing sequential ce controlled read cycles from six specific address locations in exact order. during the store cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. when a store cycle is initiated, input and output are disabled until the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence. if they intervene, the sequence is aborted and no store or recall takes place. to initiate the software store cycle, the following read sequence is performed: 1. read address 0x0000, valid read 2. read address 0x1555, valid read 3. read address 0x0aaa, valid read 4. read address 0x1fff, valid read 5. read address 0x10f0, valid read 6. read address 0x0f0f, initiate store cycle the software sequence is clocked with ce controlled reads or oe controlled reads. when the sixth address in the sequence is entered, the store cycle commences and the chip is disabled. it is important that read cycles and not write cycles are used in the sequence. it is not necessary that oe is low for a valid sequence. after the t store cycle time is fulfilled, the sram is again activated for read and write operation. software recall data is transferred from the nonvolatile memory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of ce controlled read operations is performed: 1. read address 0x0000, valid read 2. read address 0x1555, valid read vcc v cap m h o k 0 1 m h o k 0 1 we hsb vss f 1 . 0 5 s s a p y b
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 6 of 18 3. read address 0x0aaa, valid read 4. read address 0x1fff, valid read 5. read address 0x10f0, valid read 6. read address 0x0f0e, initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared; then, the nonvolatile information is transferred into the sram cells. after the t recall cycle time, the sram is again ready for read and write operations. the recall operation does not alter the data in the nonvolatile elements. the nonvolatile data can be recalled an unlimited number of times. data protection the stk12c68-5 protects data from corruption during low-voltage conditions by inhibiting all externally initiated store and write operations. the low-voltage condition is detected when v cc is less than v switch . if the stk12c68-5 is in a write mode (both ce and we are low) at power up after a recall or after a store, the write is inhibited until a negative transition on ce or we is detected. this protects against inadvertent writes during power up or brown out condi- tions. noise considerations the stk12c68-5 is a high-speed memory. it must have a high frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss, using leads and traces that are as short as possible. as with all high-speed cmos ics, careful routing of power, ground, and signals reduce circuit noise. hardware protect the stk12c68-5 offers hardware protection against inadvertent store operation and sram writes during low-voltage conditions. when v cap stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 7 of 18 best practices nvsram products have been used effectively for over 15 years. while ease-of-use is one of t he product?s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: the nonvolatile cells in an nvsram are programmed on the test floor during final test and quality assurance. incoming inspection routines at custom er or contract manufacturer?s sites sometimes reprograms these values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. the end product?s firmware must not assume that an nv array is in a set programmed state. routines that check memory content values to determine fi rst time system configuration, cold or warm boot status, and so on must always program a unique nv pattern (for example, complex 4-byte pattern of 46 e6 49 53 hex or more random by tes) as part of the final system manufacturing test to ensure these system routines work consistently. power-up boot firmware routines must rewrite the nvsram into the desired state. while the nv sram is shipped in a preset state, best practice is to again rewrite the nvsram into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on). the v cap value specified in this datasheet includes a minimum and a maximum value size. the best practice is to meet this requirement and not exceed the maximum v cap value because the higher inrush currents may reduce the reliability of the internal pass transistor. customers who want to use a larger v cap value to make sure there is extra store charge must discuss their v cap size selection with cypress. table 1. hardware mode selection ce we hsb a12?a0 mode io power h x h x not selected output high z standby l h h x read sram output data active [3] l l h x write sram input data active x x l x nonvolatile store output high z i cc2 [1] l h h 0x0000 0x1555 0x0aaa 0x1fff 0x10f0 0x0f0f read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 [2, 3] l h h 0x0000 0x1555 0x0aaa 0x1fff 0x10f0 0x0f0e read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active [2, 3] notes 1. hsb store operation occurs only if an sram write is done since the last nonvolatile cycle. after th e store (if any) completes, the part goes into standby mode, inhibiting all operations until hsb rises. 2. the six consecutive addresses must be in the order listed. we must be high during all six consecutive ce controlled cycles to enable a nonvolatile cycle. 3. i/o state assumes oe < v il . activation of nonvolatile cycles does not depend on state of oe .
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 8 of 18 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c temperature under bias ........................... ?55 ?? c to +125 ? c voltage on input relative to gnd...................?0.5 v to 7.0 v voltage on input relative to v ss ......... ?0.6 v to v cc + 0.5 v voltage on dq 0-7 or hsb .................... ?0.5 v to v cc + 0.5 v power dissipation......................................................... 1.0 w dc output current (1 output at a time, 1s duration) .... 15 ma operating range range ambient temperature v cc military ?55 ? c to +125 ? c 4.5 v to 5.5 v dc electrical characteristics over the operating range (v cc = 4.5 v to 5.5 v) [4] parameter description test conditions min max unit i cc1 average v cc current t rc = 35 ns t rc = 55 ns dependent on output loading and cycle rate. values obtained without output loads. i out = 0 ma. ?75 55 ma ma i cc2 average v cc current during store all inputs do not care, v cc = max average current for duration t store ?3ma i cc3 average v cc current at t rc = 200 ns, 5 v, 25 c typical we > (v cc ? 0.2 v). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. ?10ma i cc4 average v cap current during autostore cycle all inputs do not care, v cc = max average current for duration t store ?2ma i sb1 [5] v cc standby current (standby, cycling ttl input levels) t rc = 35 ns, ce > v ih t rc = 55 ns, ce > v ih ?24 19 ma ma i sb2 [5] v cc standby current ce > (v cc ? 0.2 v). all others v in < 0.2 v or > (v cc ? 0.2 v). standby current level after nonvolatile cycle is complete. inputs are static. f = 0 mhz. ?2.5ma i ix input leakage current v cc = max, v ss < v in < v cc ?1 +1 ? a i oz off state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih or we < v il ?5 +5 ? a v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?4 ma 2.4 ? v v ol output low voltage i out = 8 ma ? 0.4 v v bl logic ?0? voltage on hsb output i out = 3 ma ? 0.4 v v cap storage capacitor between v cap pin and v ss , 6 v rated. 68 f + 20% nominal 54 260 f notes 4. v cc reference levels throughout this data sheet refer to v cc if that is where the power supply connection is made, or v cap if v cc is connected to ground. 5. ce > v ih does not produce standby current levels until any nonvolatile cycle in progress has timed out.
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 9 of 18 data retention and endurance parameter description min unit data r data retention 100 years nv c nonvolatile store operations 1,000 k capacitance in the following table, the capacitance parameters are listed. [6] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 0 to 3.0 v 8pf c out output capacitance 7pf thermal resistance in the following table, the thermal resistance parameters are listed. [6] parameter description test conditions 28-cdip 28-lcc unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. tbd tbd ? c/w ? jc thermal resistance (junction to case) tbd tbd ? c/w figure 7. ac test loads ac test conditions 5.0 v output 30 pf r1 963 ? r2 512 ? 5.0 v output 5 pf r1 963 ? r2 512 ? for tristate specs input pulse levels .................................................. 0 v to 3 v input rise and fall times (10% to 90%) ...................... < 5 ns input and output timing referenc e levels ......... ..............1.5 note 6. these parameters are guaranteed by design and are not tested.
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 10 of 18 ac switching characteristics sram read cycle parameter description 35 ns 55 ns unit min max min max cypress parameter alt t ace t elqv chip enable access time ? 35 ? 55 ns t rc [7] t avav, t eleh read cycle time 35 ? 55 ? ns t aa [8] t avqv address access time ? 35 ? 55 ns t doe t glqv output enable to data valid ? 15 ? 35 ns t oha [8] t axqx output hold after address change 5 ? 5 ? ns t lzce [9] t elqx chip enable to output active 5 ? 5 ? ns t hzce [9] t ehqz chip disable to output inactive ? 10 ? 12 ns t lzoe [9] t glqx output enable to output active 0 ? 0 ? ns t hzoe [9] t ghqz output disable to output inactive ? 10 ? 12 ns t pu [10] t elicch chip enable to power active 0 ? 0 ? ns t pd [10] t ehiccl chip disable to power standby ? 35 ? 55 ns switching waveforms figure 8. sram read cycle 1: address controlled [7, 8] figure 9. sram read cycle 2: ce and oe controlled [7] t rc t aa t oha address dq (data out) data valid address t rc ce t ace t lzce t pd t hzce oe t doe t lzoe t hzoe data valid active standby t pu dq (data out) icc notes 7. we and hsb must be high during sram read cycles. 8. device is continuously selected with ce and oe both low. 9. measured 200 mv from steady state output voltage. 10. these parameters are guaranteed by design and are not tested.
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 11 of 18 sram write cycle parameter description 35 ns 55 ns unit min max min max cypress parameter alt t wc t avav write cycle time 35 ? 55 ? ns t pwe t wlwh, t wleh write pulse width 25 ? 45 ? ns t sce t elwh, t eleh chip enable to end of write 25 ? 45 ? ns t sd t dvwh, t dveh data setup to end of write 12 ? 25 ? ns t hd t whdx, t ehdx data hold after end of write 0 ? 0 ? ns t aw t avwh, t aveh address setup to end of write 25 ? 45 ? ns t sa t avwl, t avel address setup to start of write 0 ? 0 ? ns t ha t whax, t ehax address hold after end of write 0 ? 0 ? ns t hzwe [11,12] t wlqz write enable to output disable ? 13 ? 15 ns t lzwe [11] t whqx output active after end of write 5 ? 5 ? ns switching waveforms figure 10. sram write cycle 1: we controlled [13, 14] figure 11. sram write cycle 2: ce controlled [13, 14] t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid notes 11. measured 200 mv from steady state output voltage. 12. if we is low when ce goes low, the outputs remain in the high impedance state. 13. hsb must be high during sram write cycles. 14. ce or we must be greater than v ih during address transitions.
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 12 of 18 autostore or power up recall parameter alt description stk12c68-5 unit min max t hrecall [17] t restore power up recall duration ? 550 ? s t store [18, 19, 20] t hlhz store cycle duration ? 10 ms t delay [15, 19] t hlqz , t blqz time allowed to complete sram cycle 1 ? ? s v switch low voltage trigger level 4.0 4.5 v v reset low voltage reset level ? 3.9 v t vccrise v cc rise time 150 ? ? s t vsbl [16] low voltage trigger (v switch ) to hsb low ? 300 ns switching waveform figure 12. autost ore/power up recall we notes 15. measured 200 mv from steady state output voltage. 16. hsb must be high during sram write cycles. 17. t hrecall starts from the time v cc rises above v switch . 18. ce and oe low for output behavior. 19. ce and oe low and we high for output behavior. 20. hsb is asserted low for 1us when v cap drops through v switch . if an sram write has not taken plac e since the last nonvolatile cycle, hsb is released and no store takes place.
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 13 of 18 software controlled store/recall cycle the software controlled store/recall cycle follows. [23] parameter alt description 35 ns 55 ns unit min max min max t rc [21] t avav store/recall initiation cycle time 35 ? 55 ? ns t sa [22] t avel address setup time 0 ? 0 ? ns t cw [22] t eleh clock pulse width 25 ? 30 ? ns t hace [22] t elax address hold time 20 ? 20 ? ns t recall recall duration ? 20 ? 20 ? s switching waveform figure 13. ce controlled software store/recall cycle [23] t rc t rc t sa t sce t hace t store / t recall data valid data valid 6 # s s e r d d a 1 # s s e r d d a high impedance address ce oe dq (data) notes 21. ce and oe low for output behavior. 22. the software sequence is clocked on the falling edge of ce without involving oe (double clocking aborts the sequence). 23. the six consecutive addresses must be read in the order listed in table 1 on page 7 . we must be high during all six consecutive cycles.
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 14 of 18 hardware store cycle parameter alt description stk12c68-5 unit min max t store [25, 26] t hlhz store cycle duration ? 10 ms t dhsb [26, 24] t recover, t hhqx hardware store high to inhibit off ? 700 ns t phsb t hlhx hardware store pulse width 15 ? ns t hlbl hardware store low to store busy ? 300 ns switching waveform figure 14. hardware store cycle note 24. t dhsb is only applicable after t store is complete. 25. measured 200 mv from steady state output voltage. 26. ce and oe low for output behavior.
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 15 of 18 speed: 35 - 35 ns 55 - 55 ns package: c = ceramic 28-pin 300 mil dip (gold lead finish) part numbering nomenclature stk12c68 - 5 c 35 m temperature range: m - military (?55 c to 125 c) k l = ceramic 28-pin llc = ceramic 28-pin 300 mil dip (solder dip finish) retention / endurance 5 = military (10 years or 10 5 cycles) case outline x = ceramic 28-pin 300 mil dip y = ceramic 28-pin llc device class indicator - class m smd5962 - 94599 01 mx x lead finish a = solder dip lead finish device type: 01 = 55 ns 03 = 35 ns c = gold lead dip finish x = lead finish ?a? or ?c? is acceptable
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 16 of 18 ordering information speed (ns) ordering code package diagram package type operating range 35 stk12c68-5c35m 001-51695 28-pin cdip (300 mil) military stk12c68-5k35m 001-51695 28-pin cdip (300 mil) stk12c68-5l35m 001-51696 28-pin lcc (350 mil) 55 stk12c68-5c55m 001-51695 28-pin cdip (300 mil) stk12c68-5k55m 001-51695 28-pin cdip (300 mil) stk12c68-5l55m 001-51696 28-pin lcc (350 mil) the above table contains final information. contact your local cypress sales representative for availability of these parts package diagrams figure 15. 28-pin (300-mil) side braze dil (001-51695) 001-51695 *a
stk12c68-5 (smd5962-94599) document number: 001-51026 rev. *a page 17 of 18 acronyms document conventions units of measure figure 16. 28-pad (350-mil) lcc (001-51696) package diagrams (continued) 001-51696 *a acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output nvsram nonvolatile static random access memory oe output enable sram static random access memory ttl transistor-transistor logic we write enable symbol unit of measure c degrees celsius k ? kilohm ? a microampere ma milliampere ? f microfarad ? s microsecond ms millisecond ns nanosecond pf picofarad v volt ? ohm w watt
document number: 001-51026 rev. *a revised february 17, 2012 page 18 of 18 autostore and quantumtrap are registered trademarks of cypress semiconductor corporation. all products and company names mentio ned in this document may be the trademarks of their respective holders. stk12c68-5 (smd5962-94599) ? cypress semiconductor corporation, 2009-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document title: stk12c68-5 (smd5962-94599), 64 kbit (8 k x 8) autostore nvsram document number: 001-51026 rev ecn no. orig. of change submission date description of change ** 2666844 gvch/pyrs 03/02/09 new datasheet *a 3528539 gvch 02/17/2012 added acronyms, docume nt conventions, and table of contents. updated package diagrams 001-51695 (from rev ** to *a) and 001-51696 (from rev ** to *a). completing sunset review.

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