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all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. doc . v er s io n : 0. 6 tota l pa g es : 49 da te : 20 0 8/ 3/ 2 5 note: the content of this specification is subject to change. ? 2008 au optronics all rights reserved, do not copy. model name: a027cw01 v0 product specification 2.7 color tft-lcd module < > preliminary specification < > final specification www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 1 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. record of revision version revise date page content 0.0 2006/08/28 dr aft 0.1 2006/11/24 6 23,24 vcom dc typical value updated application circuit updated 0.2 2006/12/11 33,34 update the transmittance 3,38 update the outline dimension 0.3 2006/12/15 49 update the application circuit 0.4 2006/12/27 38 update the outline dimension 0.5 2008/3/7 34 revise viewing angle 0.6 2008/3/25 38 update the outline dimension www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 2 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. contents: a. physical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p3 b. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p4 c. optical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p33 d. reliability test items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p35 e. packing form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p36 f. outline dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p37 g. application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 3 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. a. physical specifications no. item specification remark 1 display resolution (dot) 480(w) 234(h) 2 active area (mm) 58.56 (w) 33.228 (h) 3 screen size (inch) 2.65 (diagonal) 4 dot pitch (mm) 0.122 (w) 0.142 (h) 5 color configuration r. g. b. delta 6 overall dimension (mm) 63.10 (w) 42 (h) 1.635 (d) 7 weight (g) 9.1 8 panel surface treatment ag www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 4 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or t r ansformed to any other forms without permission from au optronics corp. b. electrical specifications 1. pin assignment pin n o symbol i/o description remark 1 vcom i common electrode driving voltage 2 nc -- nc 3 vgl po negative low power supply for gate driver output: -12.5v 4 c4p c pins to connect capacitance for power circuitry 5 c4m c pins to connect capacitance for power circuitry 6 vgh po positive power supply for gate driver output: +12.5v 7 frp o frame polarity output for vcom 8 vcac c define the amplitude of the vcom swing 9 vint3 p intermediate voltage for charge pump 10 c3p c pins to connect capacitance for power circuitry 11 c3m c pins to connect capacitance for power circuitry 12 vint2 p intermediate voltage for charge pump 13 c2p c pins to connect capacitance for power circuitry 14 c2m c pins to connect capacitance for power circuitry 15 vint1 p intermediate voltage for charge pump 16 c1p c pins to connect capacitance for power circuitry 17 c1m c pins to connect capacitance for power circuitry 18 pgnd p charge pump power gnd 19 pvdd p charge pump power vdd 20 drv po gate signal for the power transistor of the boost converter 21 led anode i for led anode voltage 22 gnd p digital gnd 23 fb p main boost regulator feedback input 24 avdd p analog power supply 25 gnd p digital gnd 26 vcc p digital power supply 27 cs i serial communication chip select 28 sda i/o serial communication data input/output 29 scl i serial communication clock input 30 hsync i horizontal sync input 31 vsync i vertical sync input 32 dclk i clock input: 33 d7 i data input: msb www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 5 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 34 d6 i data input: 35 d5 i data input: 36 d4 i data input: 37 d3 i data input: 38 d2 i data input: 39 d1 i data input: 40 d0 i data input: lsb i: input; o: output. vi: voltage input vo: voltage output p:power. i/o input/output c: capacitor pin. po: power out. note: definition of scanning direction. refer to figure as below 2. absolute maximum ratings item symbol condition min. max. unit remark v cc gnd=0 -0.5 7.0 v digital power supply av dd av ss =0 -0.5 7.0 v analog power supply power voltage pv dd pv ss =0 -0.5 7.0 v charge pump power supply input signal voltage data - -0.3 3.6 v input signal voltage vcom -2.9 5.2 v vcom dc voltage operating temperature topa - 0 60 ambient temperature storage temperature tstg - -25 70 ambient temperature www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 6 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or t ransformed to any other forms without permission from au optronics corp. 3. e lectrical characteristics a. t ypical operating conditions (gnd=avss=0v) item symb ol min. typ. max. unit remark v cc 2.7 3.3 3.6 v digital power supply av dd 3.0 3.3 3.6 v analog power supply power voltage pv dd 3.0 3.3 3.6 v charge pump power supply h level v oh vcc-0.4 - vcc v output signal voltage l level v ol gnd - gnd+0.4 v h level v ih 0.7xv cc - v cc v input signal voltage l level v il gnd - 0.3v cc v v cac 5.4 5.8 6.4 v vcom voltage v cdc 0.25 0.95 1.65 v drv output voltage v drv 0 - v cc v analog stand by current ist - - 100 ua dclk is stopped note 1: a build-in power on reset circuit for pv dd and v cc is provided within the integrated lcd driver ic. the lcd module is in power save mode in default, and standby releasing is required after v cc powe r on through serial control. pleaser refer to the register stb setting for detail. b. c urrent characteristics (gnd=avss=0v) parameter symbol condition min. typ. max. unit remark input current for v cc i vcc (pin 26) v cc =3.3v 2 5 m a input current for pv dd i pvdd (pin 19) pv dd = 3.3v 10 20 ma f dclk =24.54mhz (ups052) other registers are default setting h level ioh - 400 - ua output current l level iol - -400 - ua analog stand by current i ast av dd =3.3v - 50 200 ua digital stand by current i dst v cc =3.3v - 50 200 ua dclk is stopped drv output current i drv v cc = 3.0v drv = 0.7v - - 10 ma www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 7 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, o r transformed to any other forms without permission from au optronics corp. 4. ac timing a. digital signal ac characteristic p a rameter symbol condition min. typ. max. unit. 9.7mhz (ups051 mode) - 103 - 24.54 mhz (ups052 320, yuv640 mode) - 40 - dclk cycle time tcph 27 mhz (ups052 320, ccir656, yuv 720 mode) - 37 - ns 9.7mhz (ups051 mode) - 4.6 - 24.54 mhz (ups052 320, yuv640 mode) - 1.8 - dclk raising/falling time tslew (30 ? 70%) 27 mhz (ups052 320, ccir656, yuv 720 mode) - 1.6 - ns dclk duty cycle tcwh/tcwl 40 50 60 %tcph data set-up time tdsu 12 - - data hold time tdhd 12 - - ns 1 2 dclk din tcph tcwh tcwl 70% 30% 70% 70% last // / / last data 2n d data first data tdsu 70% 30% tdhd 70% 30% t s lew tdsu tdsu www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 8 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. b. ups051 timing conditions parameter sym bol min. typ. max. unit. remark dclk frequency 1/t dclk 8 9.7 12 mhz period t h 580 616 649 dclk display period t hdisp 480 dclk back porch t hbp 84 100 115 dclk front porch t hfp 0 3 6 - dclk hsync pulse width t hsw 1 2 0 50 dclk note 1 odd period even t v note 4 262.5 note 4 t h odd display period even t vdisp 240 t h odd 11 18 24 back porch even t vbp 10. 5 17.5 23.5 t h odd 0 4.5 - front porch even t vfp 0 5 - t h odd vsync pulse width even t vsw 1 - - dclk note 2, 3, 5, 6 data set-up time t ds 12 ns data hold time t dh 12 ns note 1: ups051 horizontal back porch time (t hbp ) is adjustable by setting register ddl; requirement of minimum back porch time and minimum front porch time must be satisfied. note 2: ups051 vertical back porch time (t vbp ) is adjustable by setting register hdl; requirement of minimum back porch time and minimum front porch time must be satisfied. note 3: both interlace and non-interlace mode can be accepted. note 4: the min and max value of vsync period is related to hsync period and vs back porch. note 5: this chip support both interlace & non-interlace mode. note 6: please keep frame over 50 hz to get the better display quality. www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 9 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. hsync dclk data invalid data 1 2 3 4 477 478 479 480 invalid data ups051 input horizontal signal t hsw t hbp t ds t dh t dclk t hdisp t hfp t h www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 10 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. ups051 input vertical signal vsync hsync data invalid data invalid data line 1 line 2 line 3 line 239 line 240 t v t vsw t vbp t vdisp t vfp even field vsync hsync data invalid data invalid data line 1 line 2 line 3 line 239 line 240 t v t vsw t vbp t vdisp t vfp odd field www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 11 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, o r transformed to any other forms without permission from au optronics corp. c. ups052 timing conditions c - 1. ups052 (320 mode 24.545mhz) timing specifications parameter s ymbol min. typ. max. unit. remark dclk frequency 1/t dclk 16 24.55 27 mhz period t h 1 472 1560 1644 dclk display period t hdisp 1 280 dclk back porch t hbp 2 20 252 283 dclk front porch t hfp 0 - - dclk hsync pulse width t hsw 1 - - dclk odd period even t v note 1 262.5 note 1 t h odd display period even t vdisp 2 40 t h odd 11 18 24 back porch even t vbp 1 0.5 17.5 23.5 t h odd 0 4.5 - front porch even t vfp 0 5 - t h odd vsync pulse width even t vsw 1 - - dclk note 2, 3 note 1: the min and max value of vsync period is related to hsync period and vs back porch. note 2: this chip support both interlace & non-interlace mode. note 3: please keep frame over 50 hz to get the better display quality. c - 2. ups052 (360 mode 27mhz) timing specifications parameter s ymbol min. typ. max. unit. remark dclk frequency 1/t dclk 16 27 27 mhz period t h 1 620 1716 1809 dclk display period t hdisp 1 440 dclk back porch t hbp 2 20 252 283 dclk front porch t hfp 0 - - dclk hsync pulse width t hsw 1 - - dclk odd period even t v note 1 262.5 note 1 t h odd display period even t vdisp 2 40 t h odd 11 18 24 back porch even t vbp 1 0.5 17.5 23.5 t h odd 0 4.5 - front porch even t vfp 0 - - t h odd vsync pulse width even t vsw 1 - - dclk note 2, 3 note 1: the min and max value of vsync period is related to hsync period and vs back porch. note 2: this chip support both interlace & non-interlace mode. note 3: please keep frame over 50 hz to get the better display quality. www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 12 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. hsync dclk data invalid data r0 g0 b0 invalid data ups052 input horizontal signal t hsw t hbp t ds t dh t dclk t hdisp t hfp t h r1 g1 b1 vsync t hsw dummy note: please send 00h as blanking data. www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 13 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. ups052 input vertical signal vsync hsync data invalid data invalid data line 1 line 2 line 3 line 239 line 240 t v t vsw t vbp t vdisp t vfp even field vsync hsync data invalid data invalid data line 1 line 2 line 3 line 239 line 240 t v t vsw t vbp t vdisp t vfp odd field www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 14 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, o r transformed to any other forms without permission from au optronics corp. d. ccir656 timing conditions d - 1. ccir656 timing specifications parameter s ymbol min. typ. max. unit. remark dclk frequency 1/t dclk 16 27 27 mhz period t h 1 620 1716 1809 dclk display period t hdisp 1 440 dclk back porch t hbp 2 41 273 304 dclk front porch t hfp 4 4 4 dclk hsync pulse width t hsw 1 - - dclk odd period even t v note 1 262.5 note 1 t h odd display period even t vdisp 2 40 t h odd 11 18 24 back porch even t vbp 1 0.5 17.5 23.5 t h odd 0 4.5 - front porch even t vfp 0 5 - t h odd vsync pulse width even t vsw 1 - - dclk note 2 note 1: the min and max value of vsync period is related to hsync period and vs back porch. note 2: please keep frame over 50 hz to get the better display quality. c cir656 data input format d[7..0] dclk (27mhz) ffh 00h 00h xy (sav) cb0 y0 cr0 y1 cb 718 y718 cr 718 y719 ffh 00h 00h invalid data invalid data xy (eav) 720 ccir valid data www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 15 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, o r transformed to any other forms without permission from au optronics corp. d- 2. ccir656 decoding ff 00 00 xy signals are involved with hsync, vsync and field x y encode following bits: f=field select v=indicate vertical blanking h=1 if eav else 0 for sav p3-p0=protection bits p3=v h p2=f h p1=f v p0=f v h represents the exclusive-or function. control is provided through ?end of video? (eav) and ?start of video? (sav) timing references. horizontal blanking section consists of repeating pattern 80 10 80 10 xy d7(msb) d6 d5 d4 d3 d2 d1 d0(lsb) 1 f v h p3 p2 p1 p0 d- 3. ccir656 to rgb conversion r=1.164 (y-16) +1.596(cr-128) g =1 .164 (y-16) -0.813(cr-128)-0.392(cb-128) b=1.164 (y-16) +2.017(cb-128) where y: 16~235 cr: 16~240 cb: 16~240 d- 4. ccir656 vertical timing format (ntsc) line number f v h (eav) h ( s av) 1-3 1 1 1 0 4-22 0 1 1 0 23-262 0 0 1 0 263-265 0 1 1 0 266-285 1 1 1 0 286-525 1 0 1 0 blanking field 1 active vi deo blanking field 2 active video line 1(v=1) line 23(v=0) line 263(v=1) line 286(v=0) line 525(v=0) line 3 line 266 line 4 filed 1 (f=0) odd filed 2 (f=1) even h = 1 eav h = 0 sav www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 16 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. f h v 1 even field eav blanking 0 odd field sav active video e. yuv timing e - 1. yuv 640 timing specifications parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 16 24.545 27 mhz period t h 1472 1560 1644 dclk display period t hdisp 1280 dclk back porch t hbp 220 252 283 dclk front porch t hfp 0 - - dclk hsync pulse width t hsw 1 - - dclk odd period even t v note 1 262.5 note 1 t h odd display period even t vdisp 240 t h odd 11 18 24 back porch even t vbp 10.5 17.5 23.5 t h odd 0 4.5 - front porch even t vfp 0 5 - t h odd vsync pulse width even t vsw 1 - - dclk note 2 note 1: the min and max value of vsync period is related to hsync period and vs back porch. note 2: please keep frame over 50 hz to get the better display quality. www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 17 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. e - 2. yuv 720 timing specifications parameter symbol min. typ. max. unit. remark dclk frequency 1/t dclk 16 27 27 mhz period t h 1620 1716 1809 dclk display period t hdisp 1440 dclk back porch t hbp 220 252 283 dclk front porch t hfp 0 24 - dclk hsync pulse width t hsw 1 20 50 dclk odd period even t v note 1 262.5 note 1 t h odd display period even t vdisp 240 t h odd 11 18 24 back porch even t vbp 10.5 17.5 23.5 t h odd 0 4.5 - front porch even t vfp 0 5 - t h odd vsync pulse width even t vsw 1 3 200 dclk note 2 note 1: the min and max value of vsync period is related to hsync period and vs back porch. note 2: please keep frame over 50 hz to get the better display quality. www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 18 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. hsync dclk data invalid data cb0 invalid data yuv mode a (24.5 mhz) input horizontal signal (sel = 011) t hsw t hbp t dclk t hdisp t hfp t h y0 cr0 y1 y3 cr638 y639 cr2 cb2 y2 hsync dclk data invalid data cr0 invalid data yuv mode b (24.5 mhz) input horizontal signal (sel = 101) t hsw t hbp t dclk t hdisp t hfp t h y0 cb0 y1 y3 cb63 y639 cb2 cr2 y2 www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 19 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. hsync dclk data invalid data cb0 invalid data yuv mode a (27 mhz) input horizontal signal (sel = 100) t hsw t hbp t dclk t hdisp t hfp t h y0 cr0 y1 y3 cr718 y719 cr2 cb2 y2 hsync dclk data invalid data cr0 invalid data yuv mode b (27mhz) input horizontal signal (sel = 110) t hsw t hbp t dclk t hdisp t hfp t h y0 cb0 y1 y3 cb71 y719 cb2 cr2 y2 www.datasheet.co.kr datasheet pdf - http://www..net/
version : 0.4 page : 20 / 49 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, o r transformed to any other forms without permission from au optronics corp. 5 . charge pump structure note: fb_p and fb_n are for one led solution. pvdd nt39010 power supply application notes c1p c1m cp1 power setting power setting charge pump c2p c2m cp2 power setting power setting vgh c4 internal avdd adjustable and regulator avdd c7 power generator for vgh c3 c 3p c3m c6 cp3 power setting power setting power setting vgl charge pump (vghx-1) vcac c5 vcac voltage select c4p c4m cp4 power setting power setting vint3 vint1 c2 vint2 c1 vcomdc vcomdc c8 frp frp power setting iled= 20 ma drv vcc vled ( 5.5~10v ) fb (default= 0.6 v) pwm driving output pwm power input l c rfb fb_p normally open fb_n 25ma www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. pgnd scl gnd d3 c3p c3p vsy nc vdd3v3 vint1 vcc led_anode d6 c2m c3m vint2 d0 c1p sda avdd c1p c4m gnd vint2 vgl pgnd drv pvdd d5 c4m vcc c4p dclk frp c2p vint3 vcac d7 fb vint1 vdd3v3 c3m d4 d1 c1m pvdd c4p c1m d2 vcom cs vcom vint3 vcac frp hsy nc avdd c2p c2m vgl vgh vgh j3 con40 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 c64 1uf /10v c69 1uf /10v c65 1uf /10v c409 1uf /16v l11 120 ohm c70 1uf /10v l10 120 ohm c68 1uf /10v c421 1uf /16v c407 1uf /16v c411 1uf /16v c410 1uf /16v c414 1uf /16v c415 1uf /25v c406 1uf 16/v c408 1uf /16v c420 4.7uf/16v c413 1uf /25v l15 120 ohm pgnd 3.3v 3.3v 3.3v c2m c3m pvdd c3p avdd vcc c4p c2p vcc c4m c1m c1p frp vcom vgl scl gnd d3 c3p vgh vsy nc vcc led_anode d6 c2m c3m d0 c1p sda avdd c4m gnd vint2 vgl pgnd drv pvdd d5 dclk frp c2p vint3 vcac d7 fb vint1 d4 d1 c4p c1m d2 cs vcom hsy nc vcac vint2 vint1 vint3 vgh l13 120 ohm c67 1uf /10v l10 120 ohm c68 1uf /10v c64 1uf /10v c69 1uf 10v c65 1uf /10v c421 1uf /10v(x7r) c422 4.7uf/10v c409 1uf 16v l11 120 ohm c412 1uf /16v c70 1uf /10v c411 1uf 16v c410 1uf /16v c406 1uf /16v c408 1uf /16v c407 1uf /16v j3 con40 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 c413 1uf /25v l15 120 ohm c415 1uf /25v c414 1uf /16v 6. reference circuit internal avdd + internal vcom dc application circuit www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. external avdd + internal vcom dc application circuit www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. d0 d1 d2 d3 d4 d5 d7 d6 dclk vsync hsync scl sda cs vcc gnd avdd fb gnd led_anode drv pvdd pgnd c1m c1p vint1 vint2 vint3 c2m c3m c2p c3p vcac frp vgh c4m c4p vgl vcom c1m c1p c2m c3m c4m c4p c3p c2p vint1 vint2 vint3 vgh vgl vcac vcc frp vcom avdd vdd3v3 pvdd vcc vdd3v3 j3 con40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 c406 1uf/16v c407 1uf/16v c408 1uf/16v c409 1uf/16v c415 1uf/25v c410 1uf/16v c411 1uf/16v c421 1uf/16v c413 1uf/25v c414 1uf/16v c416 4.7u/16v r205 6.8k r207 1.5k r206 10k 1 3 2 l11 120 ohm l10 120 ohm l15 120 ohm c65 1uf/10v c70 1uf/10v c64 1uf/10v c69 1uf/10v c68 1uf/10v internal avdd + external vcom dc application circuit www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. d0 d1 d2 d3 d4 d5 d7 d6 dclk vsync hsync scl sda cs vcc gnd avdd fb gnd led_anode drv pvdd pgnd c1m c1p vint1 vint2 vint3 c2m c3m c2p c3p vcac frp vgh c4m c4p vgl vcom c1m c1p c2m c3m c4m c4p c3p c2p vint1 vint2 vint3 vgh vgl vcac vcc frp vcom vdd3v3 pvdd vcc vdd3v3 avdd vdd3v3 j3 con40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 c406 1uf/16v c407 1uf/16v c408 1uf/16v c409 1uf/16v c415 1uf/25v c410 1uf/16v c411 1uf/16v c421 1uf/16v c413 1uf/25v c414 1uf/16v c416 4.7u/16v r205 6.8k r207 1.5k r206 10k 1 3 2 l11 120 ohm l10 120 ohm l15 120 ohm c65 1uf/10v c70 1uf/10v c64 1uf/10v c69 1uf/10v l13 120 ohm c67 1uf/10v c68 1uf/10v external avdd + external vcom dc application circuit www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or t r ansformed to any other forms without permission from au optronics corp. 7. serial interface & register table a. serial interface format item symbol conditions min typical max unit t s0 scl to cs 120 ns data setup time t s1 scl to sda 120 ns t h0 scl to cs 120 ns data hold time t h1 scl to sda 120 ns t w1l scl pulse width 120 ns t w1h scl pulse width 120 ns pulse width t w2 cs pulse width 1000 ns b. the configuration of serial data at sda terminal is at below msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register address r/w data note: r/w = ?0? write mode r/w = ?1? read mode b1 ? write mode waveform b2 ? read mode waveform scl cs t h1 t s0 50% t w1l t h1h sda t s1 t h0 t w1l t w1h t w2 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d4 d3 d2 d1 d0 d15 d13 d14 d12 d10 ?0? d9 d7 d8 d6 d4 d5 d3 d2 d0 d1 d15 d13 d14 d12 d10 ?1? d9 d7 d8 d6 d4 d5 d3 d2 d0 d1 write mode read mode www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. c. register parameters address r/w content no d15 d14 d13 d12 d11 d[10:8] d7 d6 d5 d4 d3 d2 d1 d0 r0 0 0 0 0 w x x x x x grb stb shdb shcb r1 0 0 1 0 w x x x reserved reserved pfon reserved r2 0 1 0 0 w x x x x x fpol vset u/d shl r3 0 1 1 0 w x x x x palm pal sel r4 1 0 0 0 w x x x x ddl r5 1 0 1 0 w x x x oea hdl r6 1 1 0 0 w x x x x x x vcsl r7 1 1 1 0 w x x x x reserved vlnc avgy reserved t0 0 0 0 1 w x reserved pdty fbv2 fbv1 fbv0 t1 0 0 1 1 w x x avg reserved t352 const t2 0 1 0 1 w x x vdcen vcomdc t3 0 1 1 1 w x x bradj t4 1 0 0 1 w x x x x x x reserved wnsel t5 1 0 1 1 w x sat hue t6 1 1 0 1 r x reserved note 1: please keep all the reserved register at ? default value ? to avoid abnormal display. not e 2: register t6 is read only. c1 - default register settings no d15 d14 d13 d12 d11 d[10 : 8] d7 d6 d5 d4 d3 d2 d1 d0 r0 0 0 0 0 r/w x x x x x 1 1 0 1 r1 0 0 1 0 r/w x x x 0 0 0 0 0 1 r2 0 1 0 0 r/w x x x x x 0 0 1 1 r3 0 1 1 0 r/w x x x x 0 0 0 0 1 r4 1 0 0 0 r/w x x x x 0 0 0 0 0 r5 1 0 1 0 r/w x x x 0 0 0 0 0 0 r6 1 1 0 0 r/w x x x x x x 1 1 0 r7 1 1 1 0 r/w x x x x 0 0 0 1 1 t0 0 0 0 1 r/w x 0 0 0 0 0 1 0 0 t1 0 0 1 1 r/w x x 0 0 0 1 0 0 0 t2 0 1 0 1 r/w x x 0 1 0 0 0 0 0 t3 0 1 1 1 r/w x x 1 0 0 0 0 0 0 t4 1 0 0 1 r/w x x x x x x 0 0 0 t5 1 0 1 1 r/w x 1 0 0 0 1 0 0 0 t6 1 1 0 1 r x reserved ?x? => don?t care. d. detail register description d1. register r0 address bit description default bit3 (grb) global reset. bit2 (stb) standby mode setting. bit1 (shdb) dc-dc converter shutdown setting. 0000 [3..0] bit0 (shcb) charge pump shutdown setting. 1101b bit3 grb function 0 the controller is resets, the charge pump and dcdc is off. www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. reset all register to default value. 1 normal operation. (default) bit2 stb function 0 t-con, source driver and dc-dc converter are off. all outputs are high-z. 1 normal operation. (default) bit1 shdb function 0 dc-dc converter is off. (default) 1 dc-dc converter is on. dc-dc controls by stb and power on/off sequence. bit0 shcb function 0 charge pump converter is off. 1 charge pump converter is on. (default) charge pump controls by stb and power on/off sequence. d2. register r1: address bit description default reserved reserved reserved reserved bit1 (pfon) pre-filter setting. 0010 [5..0] reserved reserved 00_0001b bit1 pre-filter setting. 0 pre-filter off (default) 1 pre-filter on d3. register r2: address bit description default bit3 (fpol) frp source driver polarity inversion polarity inversion selection. bit2 (vset) selects between internal or external references for gamma correction. (for test only, please keep this bit l) bit1 (u/d) vertical shift direction selection. 0100 [3..0] bit0 (shl) horizontal shift direction selection. 0011b bit3 fpol function 0 frp=0 when positive polarity frp=1 when negative polarity (default) 1 frp=1 when positive polarity frp=0 when negative polarity bit1 ud function 0 scan down: first line=g241 g239 ? g2 last line=g0. 1 scan up: first line=g0 g2 ? g239 last line=g241. (default) www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. bit0 shl function 0 shift left; first data=s640 s639 ? s2 last data=s1. 1 shift right: first data=s1 s2 ? s639 last data=s640. (default) d4. register r3: address bit description default bit4 (palm) pal 1/6, pal1/6,8 selection. bit3 (pal) pal/ntsc selection. 0110 [4..0] bit2-0 (sel) input data format selection. 0_0001b bit4 palm function 0 pal 1/6,8 input format. (280 active line). (default) 1 pal1/6 input format. (288 active line). bit3 pal function 0 ntsc input format (240 active line). (default) 1 pal input format. bit2-0 sel function 000 ups051 path, special data format: ddx. 001 ups052 320rgb 24.54mhz data format. (default) 010 ups052 360rgb 27mhz data format. 011 yuv mode a 640y 320crcb 24.54mhz data format. 100 yuv mode a 720y 360crcb 27mhz data format. 101 yuv mode b 640y 320crcb 24.54mhz data format. 110 yuv mode b 720y 360crcb 27mhz data format. 111 ccir 656 720y 360crcb 27mhz data format. d5. register r4: address bit description default 1000 [4..0] bit4-0 (ddl) horizontal data start delay selection. 0_0000b d4 d3 d2 d1 d0 value unit 0 0 0 0 0 +0 (default) 0 0 0 0 1 +1 0 0 0 1 0 +2 0 0 0 1 1 +3 0 0 1 0 0 +4 0 0 1 0 1 +5 0 0 1 1 0 +6 0 0 1 1 1 +7 0 1 0 0 0 +8 0 1 0 0 1 +9 0 1 0 1 0 +10 0 1 0 1 1 +11 dclk 0 1 1 0 0 +12 0 1 1 0 1 +13 0 1 1 1 0 +14 dclk www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, o r transformed to any other forms without permission from au optronics corp. 0 1 1 1 1 +15 1 0 0 0 0 -1 1 0 0 0 1 -2 1 0 0 1 0 -3 1 0 0 1 1 -4 1 0 1 0 0 -5 1 0 1 0 1 -6 1 0 1 1 0 -7 1 0 1 1 1 -8 1 1 0 0 0 -9 1 1 0 0 1 -10 1 1 0 1 0 -11 1 1 0 1 1 -12 1 1 1 0 0 -13 1 1 1 0 1 -14 1 1 1 1 0 -15 1 1 1 1 1 -16 d6. register r5: address bit description default bit5-4 (oea) odd even advance selection. 1010 [5..0] bit3-0 (hdl) vertical delay selection. 00_0000b bit5-4 oea function 00 display start @hdl delay for odd and even field (default) 01 display start @hdl delay for odd field and @hdl+1 for even field 1x display start @hdl+1 delay for odd field and @hdl+1 for even field bit3-0 hdl function hdl3 hdl2 hdl1 hdl0 value unit 0 0 0 0 +0 (default) 0 0 0 1 +1 0 0 1 0 +2 0 0 1 1 +3 0 1 0 0 +4 0 1 0 1 +5 0 1 1 0 +6 0 1 1 1 +7 1 0 0 0 +8 1 0 0 1 -1 1 0 1 0 -2 1 0 1 1 -3 1 1 0 0 -4 1 1 0 1 -5 1 1 1 0 -6 1 1 1 1 -7 h d7. register r6: address bit description default 1100 [2..0] bit2-0 (vcom_ac) vcac level adjustment. step 0.2v/lsb. 110b www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, o r transformed to any other forms without permission from au optronics corp. vcsl2 vcsl1 vcsl0 vcac level unit 0 0 0 6.2 0 0 1 6.4 0 1 0 5.0 0 1 1 5.2 1 0 0 5.4 1 0 1 5.6 1 1 0 5.8 (default) 1 1 1 6.0 v d8. register r7: address bit description default reserved reserved reserved reserved bit2 (vlnc) yuv vertical line function bit1 (avgy) average yuv interface luminance y setting 1110 [4..0] reserved reserved 0 _0011 bit2 yuv vertical line function 0 vertical line are 240 (default) 1 vertical line are 234 ntsc: 240 lines scaling to 234-skip 6 lines. (1/40) pal: 288 lines scaling to 234-skip 54 lines (3/16) @ palm = ?h? 280 lines scaling to 234-skip 46 lines (1/6) @ palm = ?l? bit1 average yuv interface luminance y setting 0 only used odd y sample for yuv conversion 1 used odd and even y sample for yuc conversion (default) d9. register t0: address bit description default reserved reserved bit3-4 (pdty) pwm duty control for dc to dc converter 0001 [7..0] bit2-0 (fbv) fb voltage adjust 0000_0100b www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. bit3-4 pwm duty control for dc to dc converter 00 75 %(default) 01 55 % 10 60 % 11 65 % bit2-0 fb voltage adjust 000 0.4v 001 0.45v 010 0.5v 011 0.55v 100 0.6v (default) 101 0.65v 110 0.7v 111 0.75v d10. register t1: address bit description default bit6 (avg) data alignment to scaling down function select reserved reserved bit4 (t352) select ups052 path and input data format for 352 rgb 0011 [6..0] bit3-0 (const) rgb contrast level adjustment 000_1000b bit6 data alignment to scaling down function select 0 data alignment by dmda settling (default) 1 data alignment with averaged and input data. (r1, (g1+3g2)/4, (3b2+b3)/4??.) bit4 select ups052 path and input data format for 352 rgb 0 sel setting timing (default) 1 sel setting don?t care, input data for 352 rgb (27mhz) bit3-0 rgb contrast level adjustment 0x0 0 0x8 1.00 (default) 0xf 1.875 d11. register t2: address bit description default bit6 (vdcen) setting frp output to add dc level 0101 [6..0] bit5-0 (vcom dc) vcom dc level adjustment ( P 16mv/bit) 010_0000b bit6 setting frp output to add dc level 0 external vcom dc (default) 1 internal vcom dc bit5-0 vcom dc level adjustment 0x00 0.188v 0x20 0.7v (default) www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 0x2c 1.196v d12. register t3: address bit description default 0111 [6..0] bit6-0 (bradj) brightness level adjustment (4/bit) 100_0000b bit6 brightness level adjustment 0x00 -256 0x40 0 (default) 0x7f +256 d13. register t4: address bit description default reserved reserved 1001 [2..0] bit1-0 (wnsel) wide and narrow display select 000b bit1-0 wide and narrow display select 00 normal display (default) 01 narrow display 10 wide display 11 normal display d14. register t5: address bit description default bit7-4 (sat) yuv saturation constant adjustment (0.125/bit) 1011 [7..0] bit3-0 (hue) yuv hue adjustment (5deg/bit) 1000_1000b bit7-4 yuv saturation constant adjustment 0x0 0 0x8 1.00 (default) 0xf 1.875 bit3-0 yuv hue adjustment (5deg/bit) 0x0 -40 ? 0x8 0 ? (default) 0xf 35 ? note: register t5 is for yuv only. www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, o r transformed to any other forms without permission from au optronics corp. c. optical specification (note 1,note 2, note 3 ) item symbol condition min. typ. max. unit remark rise tr - 20 30 ms response time fall tf =0 - 30 40 ms note 4, 6 transmittance y l =0 - 9.5 - % note 8 contrast ratio cr at optimized viewing angle 150 300 - note 5, 6 top 30 35 - bottom 10 15 - left 40 45 - viewing angle right cr R 10 40 45 - deg . note 6, 7 note 1. ambient temperature =25 . note 2. to be measured in the dark room. note 3.to be measured on the center area of panel with a field angle of 1 by topcon luminance meter bm-7. note 4. definition of response time: the output signals of photo detector are measured when the input signals are changed from ?black? to ?white?(falling time) and from ?white? to ?black?(rising time), respectively. the response time is defined as the time interval between the 10% and 90% of amplitudes. refer to figure as below. note 5. definition of contrast ratio: contrast ratio is calculated with the following formula. photo detector output when lcd is at ?white? state photo detector output when lcd is at ?black? state note 6. white vi=v i5 +1.5v black vi=v i50 2.0v s i g n a l ( r e l a t i v e v a l u e ) "black" tr tf "white" "white" 0% 1 0% 90% 100% contrast ratio (cr) = www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. ? ? means that the analog input signal swings in phase with com signal. ? + ? means that the analog input signal swings out of phase with com signal. v i50 : the analog input voltage when transmission is 50% the 100% transmission is defined as the transmission of lcd panel when all the input terminals of module are electrically opened. note 7. definition of viewing angle: refer to figure as below. note 8. measured at the center area of the panel when all the input terminals of lcd panel are electrically opened. www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. d. reliability test items: no. test items conditions remark 1 high temperature storage ta= 70 240hrs 2 low temperature storage ta= -25 240hrs 3 high temperature operation ta= 60 240hrs 4 low temperature operation ta= 0 240hrs 5 high temperature and high humidity ta= 60 . 90% rh 240hrs operation 6 heat shock -25 ~80 /50 cycle 2hrs/cycle non-operation 7 electrostatic discharge 200v,200pf(0 ), once for each terminal non-operation 8 vibration (with carton) random vibration: 0.015g 2 /hz from 5~200hz ? 6db/octave from 200~500hz iec 68-34 9 drop (with carton) height: 60cm 1 corner, 3 edges , 6 surfaces note: ta: ambient temperature. www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. e. packing form www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, o r transformed to any other forms without permission from au optronics corp. f. outline dimension www.datasheet.co.kr datasheet pdf - http://www..net/
stb no dclk 1 2 3 4 5 6 dclk vsync valid data don?t care don?t care valid data din normal output normal output normal output s1~s480 g1~g240 charge pump enable frp enable 7 normal output 00h 3fh 1 2 3 4 5 6 7 8 9 1 11 00h all rights strictly reserved. any portion of this prper shall not be reproduced, copied, o r transformed to any other forms without permission from au optronics corp. g. application notes 1. stand-by timing figure 1: stand-by timing diagram note 1:during no dclk, hsync and vsync can be stopped. but in all other cases hsync and vsync m ust be active. note 2: external signal: dclk, vsync, din (d0 ~ d7), stb (by register) internal signal: dc/dc enable s1 ~ s480 (source driver output signal), frp enable g1 ~ g240 (gate driver output signal) and charge pump enable. dc/dc enable www.datasheet.co.kr datasheet pdf - http://www..net/
pv dd av dd min: 16 ms don?t care valid data normal output 1 2 3 4 5 6 7 8 9 10 11 00h vsync charge pump enable normal display frp enable din dc/dc enable source output gate output serial command max: 16 ms dclk max < 20 ms 7 frames 2 frames all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 2. power on sequence note 1: external signal: v cc, pv dd, av dd , dclk, vsync, din (d0 ~ d7), stb (by register) internal signal: dc/dc enable s1 ~ s480 (source driver output signal), frp enable, g1 ~ g240 (gate driver output signal) and charge pump enable. v cc www.datasheet.co.kr datasheet pdf - http://www..net/
pv dd av dd stb dc/dc enable dclk vsync valid data don?t care din normal output s1~s480 g1~g240 charge pump enable frp enable 1 2 3 4 5 6 7 normal output 00h 3fh 8 7 frames 3 frames 4 frames all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 3. power off sequence note 1: external signal: v cc, pv dd, av dd , dclk, vsync, din (d0 ~ d7), stb (by register) internal signal: dc/dc enable s1 ~ s480 (source driver output signal), frp enable, g1 ~ g240 (gate driver output signal) and charge pump enable. v cc www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 4. recommend ups051 (9.7 mhz) power on/off setting power on power off 1 frame input register r0 dclk / hsync / vsync 7 frames dclk / hsync / vsync vcc/pv dd /av dd min: 16 ms max: 20 msec signal input register r3 00h set to ups051 mode 0fh r0 turn on dcdc/charge pump/ tcon data input normal operation don ? t care 08h turn off tcon / charge pump / tcon vcc/pv dd /av dd don ? t care normal operation data input 9 frames www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, o r transformed to any other forms without permission from au optronics corp. 5. recommend ups052 320rgb mode (24.54 mhz) power on/off setting power on power off input register r0 dclk / hsync / vsync dclk / hsync / vsync vcc/pv dd /av dd max: 20 msec register r3 01h set to ups052 320 mode 0fh r0 data input normal operation don ? t care 08h vcc/pv dd /av dd don ? t care normal operation turn on dcdc/charge pump/ tcon turn off tcon / charge pump / tcon signal input d ata input 1 frame 7 frames min: 16 ms 9 frames www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, o r transformed to any other forms without permission from au optronics corp. 6. recommend ups052 360rgb mode (27mhz) power on/off setting power on power off input register r0 dclk / hsync / vsync dclk / hsync / vsync vcc/pv dd /av dd max: 20 msec register set to ups052 360 mode r0 data input normal operation don ? t care vcc/pv dd /av dd don ? t care normal operation turn on dcdc/charge pump/ tcon turn off tcon / charge pump / tcon signal input d ata input 1 frame 7 frames m in: 16 ms 9 frames r3 02h 0fh 08h www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 7. recommend yuv mode a 640y 320crcb (24.54 mhz) power on/off setting power on power off input register r0 dclk / hsync / vsync dclk / hsync / vsync vcc/pv dd /av dd max: 20 msec register set to yuv 640 a mode r0 data input normal operation don ? t care vcc/pv dd /av dd don ? t care normal operation turn on dcdc/charge pump/ tcon turn off tcon / charge pump / tcon signal input data input 1 frame 7 frames min: 16 ms 9 frames r3 03h 0fh 08h www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 8. recommend yuv mode a 720y 360crcb (27 mhz) power on/off setting power on power off input register r0 dclk / hsync / vsync dclk / hsync / vsync vcc/pv dd /av dd max: 20 msec register r3 04h set to yuv 720 a mode 0fh r0 data input normal operation don ? t care 08h vcc/pv dd /av dd don ? t care normal operation turn on dcdc/charge pump/ tcon turn off tcon / charge pump / tcon signal input data input 1 frame 7 frames min: 16 ms 9 frames www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 9. recommend yuv mode b 640y 320crcb (24.54 mhz) power on/off setting power on power off input register r0 dclk / hsync / vsync dclk / hsync / vsync vcc/pv dd /av dd max: 20 msec register r3 05h set to yuv 640 b mode 0fh r0 data input normal operatio n don ? t care 08h vcc/pv dd /av dd don ? t care normal operation turn on dcdc/charge pump/ tcon turn off tcon / charge pump / tcon signal input data input 1 frame 7 frames min: 16ms 9 frames www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 10. recommend yuv mode b 720y 320crcb (27 mhz) power on/off setting power on power off input register r0 dclk / hsync / vsync dclk / hsync / vsync vcc/pv dd /av dd max: 20 msec register r3 06h set to yuv 720 b mode 0fh r0 data input normal operation don ? t care 08h vcc/pv dd /av dd don ? t care normal operation turn on dcdc/charge pump/ tcon turn off tcon / charge pump / tcon signal input data input 1 frame 7 frames min : 16 ms 9 frames www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, o r transformed to any other forms without permission from au optronics corp. 11. recommend ccir656 mode (27 mhz) power on/off setting power on power off input register r0 dclk / hsync / vsync dclk / hsync / vsync vcc/pv dd /av dd max: 20 msec register r3 07h set to ccir656 mode 0fh r0 data input normal operation don ? t care 08h vcc/pv dd /av dd don ? t care normal operation turn on dcdc/charge pump/ tcon turn off tcon / charge pump / tcon signal input d ata input 1 frame 7 frames min: 16 ms 9 frames www.datasheet.co.kr datasheet pdf - http://www..net/
all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 12. recommend internal led booster circuit the internal led circuit is drawn as follows. the value of r200 and c100 needs to be modified for led characteristics. un-compatible rc value will cause back light noise resulting ripple in image. for one led solution, we often set r200 to be 30k as well as c100 to be 0.01uf(10v).for two leds solution, r200 is 18k and c100 is 0.01uf(10v). furthermore, led current is decided by vfb/r208. regarding to the range of vfb, please refer to p.30 and p.31 (t0 register description). www.datasheet.co.kr datasheet pdf - http://www..net/

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