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automotive power data sheet rev. 1.1, 2014-02-01 TLE9266QX driver sbc family body system ic with int egrated voltage regulators, power management functions, hs-can and lin transceiver. featuring multiple high-side and low-si de switches including wake inputs. system basis chip
data sheet 2 rev. 1.1, 2014-02-01 TLE9266QX table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 hints for unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 hints for alternate pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 system features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 block description state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.1 sbc init mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.2 sbc normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.3 sbc stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.4 sbc sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.5 sbc restart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.6 sbc fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.7 sbc development mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 cyclic sense and cyclic wake feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2.1 timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2.2 timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2.3 cyclic sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2.3.1 configuration and start of cyclic sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.3.2 cyclic sense in low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.4 cyclic wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 supervision features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 voltage regulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 voltage regulator 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 high-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.2.1 over- and under voltage switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.2.2 over-current detection and switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.2.3 open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.2.4 hsx operation in different sbc modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.2.5 pwm and timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table of contents
TLE9266QX table of contents data sheet 3 rev. 1.1, 2014-02-01 9low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2.1 over- and under voltage detection and switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2.2 over-current detection and switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10 high-speed can transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.2 high-speed can functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.2.1 can off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.2.2 can normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.2.3 can receive only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.2.4 can wake capable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.2.5 txd time-out feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2.6 bus dominant clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2.7 vcan under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11 lin transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.1.1 lin specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.2.1 lin off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.2.2 lin normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.2.3 lin receive only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.2.4 lin wake capable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.2.5 txd time - out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.2.6 bus dominant clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.2.7 under-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.2.8 slope selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.2.9 flash programming via lin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12 wake and voltage monitoring inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.2.1 wake input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.2.2 alternate measurement function with wk1 and wk2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.2.2.1 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.2.2.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13 interrupt function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.1 block and functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14 fail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.1 block and functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 15 supervision functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 15.1 reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 15.1.1 reset output description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 15.1.2 soft reset description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
data sheet 4 rev. 1.1, 2014-02-01 TLE9266QX table of contents 15.2 window watchdog function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 15.2.1 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15.2.2 watchdog settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 15.2.3 watchdog during sbc stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 15.2.4 watchdog start in sbc stop mode due to bus wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 15.3 vs power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 15.4 under voltage vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 15.5 over voltage vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 15.6 vcc1 under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 15.7 vcc1 fail & short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 15.8 vcc2 fail & short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 15.9 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 15.10 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 16 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 16.1 spi description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 16.2 failure signalization in the spi data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 16.3 spi programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 16.4 spi bit mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 16.5 spi control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 16.5.1 general control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 16.6 spi status information registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 16.6.1 general status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 16.6.2 family and product information register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 16.7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 17 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 17.1 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 17.2 esd and emc tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 17.3 thermal behavior of package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 18 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 24 19 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
pg-vqfn-48-31 type package marking TLE9266QX pg-vqfn-48-31 TLE9266QX data sheet 5 rev. 1.1, 2014-02-01 driver sbc family TLE9266QX 1overview features ? very low quiescent current cons umption in stop- and sleep mode ? periodic cyclic sense in normal-, stop- and sleep mode ? periodic cyclic wake in normal- and stop mode ? low-drop voltage regulator 5v, 250ma ? low-drop voltage regulator 5v, 100ma, robust against short to vs ? high-speed can transceiver iso11898-2/5 ? lin transceiver lin 2.2, j2602-2 ? two low-side outputs for relay drive with active zener clamping ? two high-side output 2 ? typ., four high-side outputs 7 ? typ., e.g. for led lighting, cyclic sensing, etc. ? four independent pwm generators and two on/off timers ? three universal high-voltage wake inputs for voltage level monitoring with cyclic sense functionality ? alternate high-voltage measurement func tion, e.g. for batt ery voltage sensing ? one universal low-voltage wake input for voltag e level monitoring with cyclic sense functionality ? sync input for external cyclic sense control via microcontroller ? reset output and fail output ? over temperature and short circuit protection feature ? wide input voltage and temperature range ? green product (rohs co mpliant) & aec qualified description the TLE9266QX is a monolithic integrated circuit in an exposed pad vqfn-48 (7mm x 7mm) power package. the device is designed for various can-lin automotive body applications as a main supp ly for the microcontroller and as an interface for a can and lin bus network to support these applications, the s ystem basis chip (sbc) provides the main functions, such as a 5v low- dropout voltage regulator (ldo) for mi crocontroller supply, a 5v low-dropout voltage regulator with short circuit protection against supply voltage vs fo r e.g. sensor supply, hs-can tran sceiver and lin transceiver for data transmission, low- and high-side switches providing protec tive functions, and a 16-bit serial peripheral interface (spi) to control and monitor the device. also implemente d are a window watchdog circuit with a reset feature, a fail output and an under voltage reset feature. the device offers low-power modes in order to support applications that are permanently connected to the battery. a wake up from the low-po wer mode is possible via a message on the buses, via the bi-level sensitive monitoring/wake-up inputs as well as via cyclic wake. the device is designed to withstand the severe conditions of automotive applications.
data sheet 6 rev. 1.1, 2014-02-01 TLE9266QX block diagram 2 block diagram figure 1 block diagram v cc 1 v cc 2 spi interrupt control sbc state machine sdi sdo clk csn vcc1 vcc2 can cell lin cell window watchdog wk txd_lin rx d_ lin lin txd_can rxd_can vcan canh canl wk1 reset generator int gnd wake register vs v s wk wk3 wk wk2 low side ls 1 ls 2 high side hs1 hs2 hs3 hs4 hs5 test fail safe ro hs6 fo wk wk 4 / sync
TLE9266QX pin configuration data sheet 7 rev. 1.1, 2014-02-01 3 pin configuration 3.1 pin assignment figure 2 tle9266 pin configuration TLE9266QX/-2qx pg-vqfn-48 1 gnd 2 n. c. 3 ls1 4 ls2 5 n. c. 6 hs1 7 hs2 8 hs3 9 hs4 10 hs5 11 hs6 12 n. c. n.c. 48 n.c. 47 n.c. 46 n.c. 45 n.c. 44 n.c. 43 13 vs 14 vs 15 vs 16 n.c. 17 vcc1 18 vcc2 19 n.c. 20 gnd 21 fo 22 wk 1 23 wk 2 24 wk 3 25 wk4/sync 26 test 27 clk 28 sdi 29 sdo 30 csn 31 int 32 ro 33 txdlin 34 rxdlin 35 txdcan 36 rxdcan lin 42 gnd 41 canh 40 canl 39 gnd 38 vcan 37
data sheet 8 rev. 1.1, 2014-02-01 TLE9266QX pin configuration 3.2 pin definitions and functions pin symbol function 1gnd ground; 2n.c. not connected; 3ls1 low-side output 1; 4ls2 low-side output 2; 5n.c. not connected; 6hs1 high-side output 1; typ. 2 ? 7hs2 high-side output 2; typ. 2 ? . 8hs3 high-side output 3; typ. 7 ? 9hs4 high-side output 4; typ. 7 ? 10 hs5 high-side output 5; typ. 7 ? 11 hs6 high-side output 6; typ. 7 ? 12 n.c not connected; 13 vs supply voltage; connected to battery voltage with reverse protection diode and filter against emc 14 vs supply voltage; connected to battery voltage with reverse protection diode and filter against emc 15 vs supply voltage; connected to battery voltage with reverse protection diode and filter against emc 16 n.c. not connected; 17 vcc1 voltage regulator output 1; 18 vcc2 voltage regulator output 2; 19 n.c. not connected 20 gnd gnd; 21 fo fail output; 22 wk1 wake input 1; 23 wk2 wake input 2; 24 wk3 wake input 3; 25 wk4/sync wake input 4 (low-voltage) / synchronization input for cyclic sense / cyclic wake; 26 test test pin; 27 clk spi clock input; 28 sdi spi data input; into sbc (=mosi) 29 sdo spi data output; out of sbc (=miso) 30 csn spi chip select not input; 31 int interrupt output; 32 ro reset output; 33 txdlin transmit lin; 34 rxdlin receive lin; 35 txdcan transmit can;
TLE9266QX pin configuration data sheet 9 rev. 1.1, 2014-02-01 note: all vs pins must be connected on the pcb; all gnd pins as well as the cooling ta p must be also connected on the pcb 3.3 hints for unused pins it must be ensured that the correct configurations are also selected via spi, e.g. when connecting wkx to gnd, then the respective wk pin must be disabled as wake source and the correct pull-up/ -down configuration must be selected: ? wk1/2/3/4: connect to gnd and configure correctly ? ls1/2: leave open ? hsx: leave open ? ro / fo: leave open ? int: leave open ? vcan: connect to vcc1 ? canh/canl: leave open ? lin: leave open ? test: leave open for normal operation. connect to vcc1 to enter sbc development mode 36 rxdcan receive can; 37 vcan supply input; for internal hs-can cell 38 gnd gnd; 39 canl can low bus pin; 40 canh can high bus pin; 41 gnd ground; 42 lin lin bus; bus line for the lin interface, according to iso. 9141 and lin specification 2.2 as well as sae j2602-2. 43 n.c. not connected; 44 n.c. not connected; 45 n.c. not connected; 46 n.c. not connected; 47 n.c. not connected; 48 n.c. not connected; cooling tab gnd cooling tab - exposed die pad ; for cooling purposes only, do not use as an electrical ground. 1) 1) the exposed die pad at the bottom of th e package allows better power dissipation of heat from the sbc via the pcb. the exposed die pad is not connected to any active part of the ic an can be left fl oating or it can be connected to gnd (recommended) for the best emc performance. pin symbol function
data sheet 10 rev. 1.1, 2014-02-01 TLE9266QX pin configuration 3.4 hints for alternate pin functions in case of alternate pin functions, it must be ensured th at the correct configurations are also selected via spi, in case it is not done automatically. please consult the re spective chapter. in addition, following topics shall be considered: ? wk4 / sync pin: the pin can be either used as a low-vo ltage wake pin or as a cont rol pin for cyclic sense / cyclic wake, the respective functi on can be selected via the spi bit wk4_sync . see also chapter 12.2.1 . ? wk1..2: the pins can be either used as hv wake / voltage monitoring inputs or for a voltage measurement function. the respective function can be selected via the spi bit wk_meas . in the later case, the wk1..2 pins shall not be used / assigned for any wake detection nor cyclic sense functionality because any level changes at the pins will be ignored. see also chapter 12.2.2 .
TLE9266QX general product characteristics data sheet 11 rev. 1.1, 2014-02-01 4 general product characteristics 4.1 absolute maximum ratings table 1 absolute maximum ratings 1) t j = -40 c to +150 c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. voltages supply voltage v s, max -0.3 ? 28 v ? p_4.1.1 supply voltage v s, max -0.3 ? 40 v load dump, max. 400 ms p_4.1.2 voltage regulator 1 output v cc1, max -0.3 ? 5.5 v ? p_4.1.3 voltage regulator 2 output v cc2, max -0.3 ? v s + 0.3 v ? p_4.1.4 wake inputs 1...3 v wk, max -0.3 ? 40 v ? p_4.1.5 high-side 1...6 v hs, max -0.3 ? v s + 0.3 v ? p_4.1.6 low-side 1...2, fo v ls, max -0.3 ? 40 v dc value only p_4.1.7 lin, canh, canl v bus, max -27 ? 40 v ? p_4.1.8 logic input / output voltage, test pin, wk4/sync v io, max -0.3 ? v cc1 + 0.3 v ? p_4.1.9 vcan input voltage v vcan, max -0.3 ? 5.5 v ? p_4.1.10 currents wake inputs 1..2 i wk1,2, max -500 500 a 2) 2) applies only if wk1 and wk2 are configur ed as alternative hv-measurement function p_4.1.11 temperatures junction temperature t j -40 ? 150 c ? p_4.1.12 storage temperature t stg -55 ? 150 c ? p_4.1.13 esd susceptibility esd resistivity all pins v esd -2 ? 2 kv hbm 3) 3) esd susceptibility, human body model ?hbm? according to ansi/esd a/jedec js-001 (1.5k ? , 100pf) p_4.1.14 esd resistivity canh, canl, lin vs. gnd v esd -8 ? 8 kv hbm 4) 3) 4) esd ?gun? resistivity 6kv information according to iec61000-4-2 ?gun test? (330 ? , 150pf) is shown in application information in chapter 17.2 p_4.1.15 esd resistivity vs. gnd v esd -500 ? 500 v cdm 5) 5) esd susceptibility, charged device model ?cdm? according to eia/jesd22-c101 or esda stm5.3.1, p_4.1.18 esd resistivity pin 1, 12,13,24,25,36,37,48 (corner pins) vs. gnd v esd1,12,13,24 ,25,36,37,48 -750 ? 750 v cdm 5) p_4.1.19
data sheet 12 rev. 1.1, 2014-02-01 TLE9266QX general product characteristics notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. 4.2 functional range note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. device behavior outside of specified functional range: ?28v < v s,func < 40v: device will still be functional including the state machine; the specified electrical characteristics might not be ensured anymore. the regulators vcc1/2 are working properly; however, a thermal shutdown might occur due to high power dissipation. hsx switches might be turned off depending on vs_ov configurations.; the absolute maximum ratings are not violated, however the device operat ion at high junction temperatures for long periods might reduce the operating life time; ?18v < v s,lin <28v: the lin transceiver is still functional. however, the communication might fail due to out-of- spec operation; ? v can < 4.75v: the undervoltage bit vcan_uv will be set in the spi register bus_ctrl and the transmitter will be disabled as long as the uv condition is present; ?5.25v < v can < 5.50v: can transceiver still functional. however, the communi cation might fail due to out-of- spec operation; ?5.5v < v s < 28v: parameter specification applies; ? v por,f < v s < 5.5v: device will be still be functional; the specif ied electrical characterist ics might not be ensured anymore. the lin transmitter will be disabled if v,uvd,f is re ached; hsx switches might be turned off depending on vs_uv configurations . the voltage regulators will ente r the low-drop op eration mode. a vcc1_uv reset could be triggered depending on the vrtx settings table 2 functional range parameter symbol values unit note / test condition number min. typ. max. supply voltage v s,func v por ?28v 1) v por see section chapter 15.10 1) including power-on reset, over- and under voltage protection p_4.2.1 lin supply voltage v s,lin 6?18v 2) 2) parameter specification according to lin 2.2 standard p_4.2.2 can supply voltage v can 4.75 ? 5.25 v ? p_4.2.3 spi frequency f spi ??4mhzsee chapter 16.7 for f spi,max p_4.2.4 junction temperature t j -40 ? 150 c ? p_4.2.5
TLE9266QX general product characteristics data sheet 13 rev. 1.1, 2014-02-01 4.3 thermal resistance table 3 thermal resistance 1) 1) not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. junction to soldering point r thjsp ? 6 ? k/w exposed pad p_4.3.1 junction to ambient r thja ?33?k/w 2) 2) according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board for 1.5w. board: 76.2x114.3x1.5mm3 with 2 inner copper layers (35m thick), with thermal via array under the exposed pad contacting t he first inner copper layer and 300mm2 cooling area on t he bottom layer (70m). p_4.3.2
data sheet 14 rev. 1.1, 2014-02-01 TLE9266QX general product characteristics 4.4 current consumption table 4 current consumption 1) parameter symbol values unit note / test condition number min. typ. max. sbc normal mode normal mode current consumption i normal ?3.56mavcc2 on (no load); can, lin, hsx, lsx = off p_4.4.1 sbc stop mode stop mode current consumption i stop,25 ? 40 53 a vcc2, hsx = off; can, lin, wkx not wake capable. p_4.4.2 stop mode current consumption i stop,85 ?5070a t j = 85c 2) ; vcc2, hsx = off; can, lin, wkx not wake capable. p_4.4.3 sbc sleep mode sleep mode current consumption i sleep,25 ? 14 22 a vcc2, hsx = off; can, lin, wkx not wake capable p_4.4.7 sleep mode current consumption i sleep,85 ?2535a t j = 85c 2) ; vcc2, hsx = off; can, lin, wkx not wake capable p_4.4.8 feature incremental current consumption current consumption for can module, recessive state i can,rec ? 3 5.5 ma sbc normal mode; can normal mode; vcc2 connected to vcan; vtxdcan = vcc1; no rl on can p_4.4.18 current consumption for can module, dominant state i can,dom ?56.5ma 2) sbc normal mode; can normal mode; vcc2 connected to vcan; vtxdcan = gnd; no rl on can p_4.4.19 current consumption for can module, receive only mode i can,rcvonly ?1.351.50ma 2) sbc stop mode; can receive only mode; vcc2 connected to vcan; vtxdcan = vcc1; no rl on can p_4.4.20 current consumption for lin module, recessive state i lin,rec ? 0.5 1.5 ma sbc normal mode; lin normal mode; vtxdlin = vcc1; no rl on lin p_4.4.22
TLE9266QX general product characteristics data sheet 15 rev. 1.1, 2014-02-01 note: to achieve the target low-quiescent current consumptio n the user must make sure to set the pull-up or pull- down current sources for the wkx pins accordingly or to disable them. current consumption for lin module, dominant state i lin,dom ?1.22.0ma 2) sbc normal mode; lin normal mode; vtxdlin = gnd; no rl on lin p_4.4.23 current consumption for lin module, receive only mode i lin,rcvonly ?0.51.1ma 2) sbc stop mode; lin receive only mode; vtxdlin = vcc1; no rl on lin p_4.4.24 current consumption for wk1..3 wake capability i wake,wkx,25 ?57.5a 3) sbc sleep mode; wk1..3 wake capable; lin,can = off p_4.4.15 current consumption for lin wake capability i wake,lin,25 ?34asbc sleep mode; lin wake capable; wk1..3, can = off p_4.4.16 current consumption for can wake capability i wake,can,25 ?56a 2) sbc sleep mode; can wake capable; wk1..3, lin = off p_4.4.17 current consumption for vcc2 in sbc stop mode i stop,vcc2,25 ? 2026asbc stop mode; vcc2 = on (no load); lin, can, wk1..3 = off p_4.4.28 current consumption for vcc2 in sbc stop mode i stop,vcc2,85 ?2228a 2) sbc stop mode; t j = 85c; vcc2 = on (no load); lin, can, wk1..3 = off p_4.4.29 current consumption for cyclic sense function i stop,c25 ?2026a 4) sbc stop mode; p_4.4.32 1) the current consumption values are specified with t j = 25c, v s = 13.5v, no load on vcc1 and test = 0v (unless otherwise specified). current consumpti on adders of features in sbc stop mode also apply for sbc sleep mode (unless otherwise specified). 2) specified by design; not subject to production test. 3) no pull-up or pull-down configuration selected. the current consumption in sbc stop mode cannot be reduced by disabling the wk1..3 as wake sources because the curr ent is needed for the voltage level monitoring. 4) hs2 used for cyclic sense, timer 2, 20m s period, 0.1ms on-time, no load on hs2. in general the current consumption adder for cyclic sens e in sbc stop mode can be calculated with below equation: i stop,cs = 18a + (700a *t on /t per ) table 4 current consumption 1) (cont?d) parameter symbol values unit note / test condition number min. typ. max.
data sheet 16 rev. 1.1, 2014-02-01 TLE9266QX system features 5 system features this chapter describes the system fe atures and behavior of the TLE9266QX: ? state machine ? sbc mode control ? state of supply and peripherals ? system functions such as cyclic sens e, cyclic wake or pwm control of hs ? supervision and diagnosis functions the system basis chip is controlled via a 16-bit sp i interface. a detailed description can be found in chapter 16 .the configuration as well as the diagnosis is ha ndled via the spi. the spi mapping of the TLE9266QX is compatible to other devi ces of the tle92xx family.
data sheet 17 rev. 1.1, 2014-02-01 TLE9266QX system features 5.1 block description state machine the different sbc modes are selected vi a spi by setting the respective sbc mode bits in the register m_s_ctrl . the sbc mode bits are cleared when going through sbc restart mode and thus always show the current sbc mode. figure 3 state diagram showing the sbc operating modes sbc init mode (long open window) vcc1 on vcc2 off wd conf fo inact can inact lin inact sbc normal mode vcc1 on vcc2 on/off wd conf sbc restart mode vcc1 on/ ramping vcc2 off reset act. can woken / off sbc sleep mode vcc1 off vcc2 on/off wd off can wake capable /off lin wake capable /off sbc stop mode vcc1 on vcc2 on/off wd fixed/off can wake capab./ rcv only/off wd failure (up to 14 times) wake up event spi cmd spi cmd spi cmd any spi command wd trig first battery connection condition / event sbc action fo unchanged vcc1 undervoltage fo act/inact fo act/inact fo act/inact lin woken / off automatic 7th t sd2, 15th watchdog failure sbc fail-safe mode (3) vcc1 off vcc2 off hs/ls off can wake capable lin wake capable fo active tsd2 (1) (up to 6 times) wake up event vcc1 short to gnd sbc_reset can config. lin config. reset is released, start with long open window (1) in case of a tsd2 event, vcc1 will be disabled for 1s (with ro pulled low) and stay during restart mode. (2) can/lin receive only mode is selectable via spi before going into sbc stop mode (3) this mode will be maintained for 1s, i.e. the default wake sources are disabled during this time. (2) lin wake capab./ rcv only/off (2)
data sheet 18 rev. 1.1, 2014-02-01 TLE9266QX system features 5.1.1 sbc init mode the sbc starts up in sbc in it mode after crossing the v por,r threshold and the window watchdog will start with a long open window. the sbc waits for the microcontroller to finish its startup and init ialization sequence. from this transition mode, the sbc can be switched via spi command to the main operating mode - sbc normal mode. any spi command will bring the sbc to sbc normal mode. wake-up events are ignor ed during sbc init mode and will therefor e be lost. note: for a safe start-up, it is recommended to send firs t a spi command that triggers the watchdog and sets the watchdog configuration. the watchdog triggering is achieved by writing to the watchdog register wd_ctrl . after powering up, the watchdog must be triggered within the long-open window t lw to avoid a watchdog failure reset. note: in case of slow supply voltage ramps at power up the spi flags vcc1_uv and failure will not be updated and fo will not be triggered as long as vcc1 is below the v rt1,r threshold. however, the ro pin will be pulled low and will stay low for at least t rd1 . the sbc fail-safe mode will be entered if the vcc1 output voltage has not crossed the v cc1,sc after the filter time t vcc1,sc . 5.1.2 sbc normal mode the sbc normal mode is the standard operating mode fo r the sbc. all configurations have to be done in sbc normal mode before enteri ng a low-power mode. a wake-up event on ca n, lin and wkx will create an interrupt on pin int - however, no change of sbc mode will occur. the configuration options are listed below: ? vcc1 is active ? vcc2 can be switched on or off (default = off) ? can is configurable (off, wa ke capable, receive only, on) ? lin is configurable (off, wa ke capable, receive only, on) ? outputs can be switched on or off (default = off) ? wake pins show the input level ? cyclic sense and cyclic wake can be selected 5.1.3 sbc stop mode the sbc stop mode is the first level technique to reduce the overall current consumption. in this mode, vcc1 is still active and supplying the microcon troller, which can enter a power down mode. the vcc2 supply as well as the hsx outputs can be configured to stay enabled. the settings have to be done before entering sbc stop mode. a wake-up event on can, li n and wkx will create an interrupt on pin int - however, no change of sbc mode will occur. the configuration options are listed below: ? vcc1 is on ? vcc2 can be on or off ? can can be selected for ?receive only mode? and to be wake capable (interrupt) or off ? lin can be selected for ?receive only mode? and to be wake capable (interrupt) or off ? wk pins show the input level and can be selected to be wake capable (interrupt) ? hs1...6 can be switched on or can be controlled by pwm ? ls driver are off ? cyclic sense can be done with hs1...6 and timer 1 or timer 2; ? cyclic wake is selectable in sb c stop mode with timer 1 or timer 2; ? watchdog can be disabled via spi or is automatically disabled if ivcc1< i wd_off (see chapter 15.2.3 ) note: if switches are enabled during sleep mode, e.g. hsx on with or without pwm, then the sbc current consumption will increase ( chapter 4.4 ).
data sheet 19 rev. 1.1, 2014-02-01 TLE9266QX system features note: it is not possible to switch directly from sbc stop mode to sbc sleep mode. doing so will also set the spi_fail flag and will bring the sbc into sbc restart mode. 5.1.4 sbc sleep mode the sbc sleep mode is the second level technique to reduce the current overall consumption to a minimum needed to react on wake-up events or for the sbc to perfor m autonomous actions (e.g. cyclic sense). in this mode, vcc1 is off and not supplying the microcontroller anymor e.the vcc2 supply as well as the hsx outputs can be configured to stay enabled. the setti ngs have to be done before entering sbc sleep mode. a wake-up event on can, lin or wkx will bring the device via sbc restart mo de into sbc normal mode again and signal the wake source. the configuration options are listed below: ? vcc1 is off ? vcc2 can be switched on or off ? can can be selected to be wake capable or off ? lin can be selected to be wake capable or off ? wk pins can be selected to be wake capable ? hs1...6 can be switched on or can be controlled by pwm ? ls drivers are off ? cyclic sense can be done with hs1...6 and timer 1 and timer 2 ? the watchdog is off it is not possible to switch off all wake so urces in sbc sleep mode. doing so will set the spi_fail flag and will bring the sbc into sbc restart mode. all settings must be done before entering sbc sleep mode. note: if switches are enabled during sleep mode, e.g. hsx on with or without pwm, then the sbc current consumption will increase 5.1.5 sbc restart mode there are multiple reasons to enter the sbc restart mode . the purpose of the sbc rest art mode is to reset the microcontroller: ? in case of under voltage on vcc1 in sbc normal and in sbc stop mode, ? due to incorrect watchdog triggering (for the firs t 14 times, then sbc fail- safe mode is entered), ? due to an overall thermal shutdown (tsd2) event (the first 6 times within one minute - see also chapter 15.9 ). sbc restart mode will be maintained for 1s in this case to avoid thermal toggling, ? in case of a wake-up event from sbc sleep mode, this tr ansition is used to ramp up vcc1 after wake in a defined way. from sbc restart mode, the sbc goes au tomatically to sbc normal mode, i.e the mode is left automatically by the sbc without any microcon troller influence. the sbc mode bits are cleared. the reset output (ro) is pulled low when entering restart mode and is released at the tr ansition to normal mode a fter the reset delay time ( t rd1 ). the watchdog timer will start with a long open window starting from the moment of the risi ng edge of ro. however, the watchdog period setting in the register wd_ctrl remains unchanged. leaving the sbc restart mode will not result in ch anging / deactivating the fail output. the configuration options are listed below: ? vcc1 is on or ramping up, ? vcc2 will be disabled if it was activa ted before, ? can and lin transceivers are ?woken? in case of a wa ke-up event in sbc sleep mode or sbc fail-safe mode, wake capable when they were on or in ?receive only? before restart mode, or off if they were off before the sbc restart mode (see also chapter chapter 10 and chapter 11 and register bus_ctrl ), ? the hs1...6 will be disabled if they were acti vated before, ? ls switches are switched off automatically,
data sheet 20 rev. 1.1, 2014-02-01 TLE9266QX system features ? ro is pulled low during sbc restart mode ? the spi communication is ignored by the sbc, i.e. it is not interpreted, note: in case of a tsd2 event, vcc1 is switched off and the device remains in sbc re start mode for 1s to allow cooling down of the chip. afterwards the reset is released and sbc normal mode is entered. the tsd2 counter will be increased if the tsd event occurred wit hin one minute. in case of a wd failure event, the sbc restart mode is also entered and the wd_fail counter is increased up to 14x. 5.1.6 sbc fail-safe mode the fail-safe mode is automatically reached after 7 ti mes over temperature (tsd2) within 1 minute, after 15 watchdog fails, or if vcc1 is shor ted to gnd. in this case, the de fault wake sources (see register wk_ctrl_1 and bus_ctrl ) are activated, the wake-up events are cleared in the register wk_stat , and all output drivers and both voltage regulator are switched off. this mode will be maintained for at least 1s to avoid any fast toggling behavior. all wake sources will be di sabled during this time. leaving t he sbc fail-safe mode will not result in deactivation of the fail output pin. the followi ng functions are influenced during fail-safe mode: ? fo is activated ? vcc1 is off ? vcc2 is off ? can is wake capable ? lin is wake capable ? hs1...6 are off ? ls driver are off ? wk1...3 pins are wake capable, wk4 is disabled ? cyclic sense and cyclic wake is disabled, stat ic sense is active with default filter time note: after 7 tsd2 within 1 min. the sbc goes to sbc fail-sa fe mode. the time is counted starting from the first tsd2 event. if the minute passed and less than 7 tsd2 events occurred, then the first event is discarded table 5 reasons for restart - state of spi status bits after return to normal mode sbc mode event dev_stat tsd2 wd_fail vcc1_uv vcc1_sc normal watchdog failure 01 xxx 0001...1110 x 0 normal tsd2 01 001...110 xxxx x 0 normal vcc1 under voltage reset 01 xxx xxxx 1 0 stop mode watchdog failure 01 xxx 0001...1110 x 0 stop mode tsd2 01 001...110 xxxx x 0 stop mode vcc1 under voltage reset 01 xxx xxxx 1 0 sleep mode wake-up event 10 xxx xxxx x 0 fail-safe wake-up event 01 see ?reasons for fail-safe, table 6 ? table 6 reasons for fail-safe - state of spi status bits after return to normal mode sbc mode event dev_stat tsd2 wd_fail vcc1_uv vcc1_sc normal 15 x watchdog failure 01 xxx 1111 x 0 normal 7 x tsd2 01 111 xxxx x 0 normal vcc1 short to gnd 01 xxx xxxx 1 1 stop mode 15 x watchdog failure 01 xxx 1111 x 0 stop mode 7 x tsd2 01 111 xxxx x 0 stop mode vcc1 short to gnd 01 xxx xxxx 1 1
data sheet 21 rev. 1.1, 2014-02-01 TLE9266QX system features and the minute is considered to be counted from the second even t and so on. a wake -up event will lead via sbc restart mode to sbc normal mode. the tsd2 re gister will show ?7? to si gnal that fail-safe was reached due to 7 tsd2 events. the tsd2 register can then be cleared by spi, i.e. it is not cleared automatically. with the next tsd2 event the device will go to restart m ode, and show tsd2 = ?1? regardless if the tsd2 register was cleared before the event. the counter will start new. note: after 15 watchdog failures the sbc goes to sbc fail- safe mode. a wake-up event will lead via sbc restart mode to sbc normal mode. the wd_f ail register will show ?15? to sign al that sbc fail-safe mode was reached due to 15x watchdog failure. the wd_fail regist er is cleared by a correct watchdog trigger or can be cleared by spi. with the next watchdog failure the device will go to sbc restart mode, and show wd_fail = ?1? regardless if the wd_fail register was cleared before the event. the counter will start new. 5.1.7 sbc development mode the sbc development mode is used during development phase of the module, especially for software development. the mode is reached by setting the test pin to high. in this mode, the watchdog does not need to be triggered. no reset is triggered because of watchdog failure, sbc fail-safe mode is not reached after 15 watchdog fails. if the test pin is set from high to low during oper ation, then the watchdog starts with a long open window. independent from the sbc development mode, there is the possibility by testing the fo output, i.e. if setting the fo pin to low will create the inten ded behavior within the system. the fo output can be enabled by the microcontroller by setting the fo_on spi bit.
data sheet 22 rev. 1.1, 2014-02-01 TLE9266QX system features 5.2 cyclic sense and cyclic wake feature both features are intended to reduce the qui escent current of the device and application. in the cyclic sense configuration, one or more high-side drivers are switched on periodically (controlled by a timer) and supplies an external circuitry e.g. switches and/or resistor array, wh ich is connected to one or more wake inputs (see figure 4 ). any edge change of the wkx input signal causes a wake. the behavior of the wk4 pin is the same as the wk1..3 pins even though it is a 5v-pin only. depending on the sbc mode, either the int is pulled low (sbc normal mode and sbc stop mode) or th e sbc is enabling the vcc1 (after sbc sleep mode). cyclic wake means that a timer is enabled as an inte rnal wake source (in sbc normal and sbc stop mode) and causes periodic interrup t at the timer overflow. two timers are integrated and can be us ed for cyclic sense and/or cyclic wake. the timers can be mapped to the dedicated hs outputs by spi (via hs_ctrl1 ...3). both timers have the same configuration options but can be configured independently. in addition, cyclic sense can also be controlled via th e sync pin. in this case the wk4/sync pin needs to be configured by setting the bit wk4_sync (default = ?0?). see also chapter 12 for more information regarding the cyclic sense configuration of sync and the wkx pins. 5.2.1 timer 1 the timer 1 is typically used to wake-up the microcontro ller periodically or to do cyclic sense on the wake inputs with assigned hs switches (= cyclic sense). following periods and on-times can be selected via the register timer1_ctrl : ? period: 10ms / 20ms / 50ms / 100ms / 200ms / 1s / 2s / controllable via sync ? on-time: 0.1ms / 0.3ms / 1.0ms / 10ms / 20ms / controllable via sync / off at high or low 5.2.2 timer 2 the timer 2 is identical to timer 1 but can be operated co mpletely independently, e.g. timer1 is used for cyclic sense and timer2 is used for cyclic wake. following periods and on-times can be selected via the register timer2_ctrl : ? period: 10ms / 20ms / 50ms / 100ms / 200ms / 1s / 2s / controllable via sync ? on-time: 0.1ms / 0.3ms / 1.0ms / 10ms / 20ms / controllable via sync / off at high or low 5.2.3 cyclic sense the principle of the cyclic sense function is shown in figure 4 in a simplified block diagram. as mentioned, the sync pin can also be used to control the cyclic sense function. the first sample of the wk input value (high or low) is taken as the reference for the next cycle. a wake from sbc sleep mode or an interrupt in sbc stop- or normal mode via wk pin can therefore only happen with the second cycle (on-time) and onwards. during cyclic sense, wk_lvl_stat is updated and only with the samples voltage levels of the wkx pins in sbc normal and sbc stop mode. if sync is selected to control the cyclic sense or cyc lic wake timing, then the wk4/sync pin is automatically configured with a pull down ( wk4_pupd = ?01?) but register values will be kept. when sync is selected to stop the on-time, then the def ault filter time (see wk_flt_ctrl ) is selected. note: when sync is selected in cyclic sense for either starting the period or the end of the on-time it is recommended to also select sync for the other paramet er, i.e. ending the on-time or starting the period.
data sheet 23 rev. 1.1, 2014-02-01 TLE9266QX system features figure 4 cyclic sense working principle including sync control 5.2.3.1 configuration and start of cyclic sense the correct sequence to configure the cyclic sense is shown in figure 5 . the settings ?off / low? and ?off / high? define the voltage level of the re spective hs driver before the start of the cyclic sense. the intention of this selection is to avoid an unintentional wake due to a voltage level change at the start of the cyclic sense. cyclic sense (=timerx) will start as so on as the respective on-time has b een selected indepen dently from the assignment of the hs and filter configurat ion. the selection of config c/d (see chapter 12.2.1 ) must therefore be done before starting the timer. the corr ect configuration sequence is as follows: ? mapping of a timer or sync input to the respective hsx outputs ? configuring the respective filter timing, i.e. assigning the respective wk pin for cyclic sense ? configuring the timer period and on-time note: it is not possible to select sync (on, off or both) for cyclic sense / cyclic wake when wk4 is enabled. in this case the timer is not started and the spi_fail bit is set. so first th e pin must be configured to sync via the bit wk4_sync before starting cyclic wake / cyclic sense. hs1...6 high side from uc hs x wk x sync sbc state machine switching circuitry gnd wk 1..3 wk_flt_ctrl hs_ctrl timer_ctrl period / on- tim e signals to uc int
data sheet 24 rev. 1.1, 2014-02-01 TLE9266QX system features figure 5 cyclic sense: configuration and sequence the first wk input value (high or low) is taken as the reference for the next cycle. a wake from sbc sleep mode or an interrupt in sbc stop- or normal mode via wk pi n can therefore only happen with the second cycle (on- time). a wake-up event due to cyc lic sense in sbc mode will set the bit wk1_wu, wk2_wu, wk3_wu or wk4_wu. to ensure that no change of the wk input level was missed during the settle time of the first cyclic sense cycle the level can be checked at the wkx bit. the functionality of the sampling and the different scenarios is depicted in figure 6 to figure 8 . a edge change on a wk pin is only sensed and signalled after the filter time of the respective on-time. cyclic sense configuration sequence assign timerx / sync to selected hs switch in hs_ctrl_x enable wkx as wake source with configured timer in wk_flt_ctrl cyclic sense starts / ends by setting / clearing on-time timer1 / sync, timer2 / sync select timer period / sync and desired on-time in timerx_ctrl wk1, wk2, wk3, (wk4) with above selected timer 10, 20, 50, 100 , 200ms, 1s, 2s, sync low /high off, 0.1, 0.3, 1.0, 10, 20ms, sync
data sheet 25 rev. 1.1, 2014-02-01 TLE9266QX system features figure 6 wake input timing figure 7 start of cyclic sense, hs ?off? before cycle sense start settle time filter time t fwk1 on-time period settle time hs switch t wk level filter time t fw k1 wake event t hs switch wk level switch open switch closed sample points first sample taken as reference change of level leads to wake 1k 20k no change in level hs start of cyclic sense application exam ple for the tim ing
data sheet 26 rev. 1.1, 2014-02-01 TLE9266QX system features figure 8 start of cyclic sense, hs ?on? before cycle sense start 5.2.3.2 cyclic sense in low-power mode if cyclic sense is intended for sbc stop or sbc sleep mo de mode, it is necessary to activate the cyclic sense in sbc normal mode before going to the low-power mode. a wake-up event due to cyclic sense will set the bit wk1_wu, wk2_wu, wk3_wu or wk4_wu. in sbc stop m ode the wake-up event will trigger an interrupt, in sbc sleep mode the wake-up event will send the devi ce via sbc restart mode to sbc normal mode. before returning to sbc sleep mode, the wake status register wk_stat needs to be cleared. trying to go to sbc sleep mode with uncleared wake flags, such as wkx_wu the sbc will directly wake-up from sbc sleep mode by going via sbc restart mode to sbc normal m ode, a reset is issued. the wkx_wu bi t is seen as source for the wake. this is implemented in order not to loos e an wake-up event during the transition. note: cyclic sense remains active even if the respective hs switch is disabled due to a failure. therefore, it is recommended not to enter sbc sleep mode with only cyclic sense activated as awake source. wk_cyclic_start_hs_on.vsd settle time filter time t fwk1 on-time period settle time hs switch t wk level filter time t fwk1 hs on cyclic sense wkx bit 0 1 1. sample taken as reference 2. sample wake possible switch closed switch open after first sample, wake can be done with a change of level
data sheet 27 rev. 1.1, 2014-02-01 TLE9266QX system features 5.2.4 cyclic wake for the cyclic wake feature one or bo th timers are configured as internal wake-up so urce and will periodically trigger an interrup t in sbc normal and sbc stop mode. the correct sequence to configure the cyclic wake is shown in figure 9 . the sequence is as follows: ? enable timer1 and/or timer2 as a wake-up source in the register wk_ctrl_1 . ? configure the respective peri od of timer1 and/or timer2 figure 9 cyclic wake: configuration and sequence as in cyclic sense, the cyclic wake function will start as soon as the on-time is configured. an in terrupt is generated for every start of the on-time except for the very first time when the timer is started. note: the timer on-time has no function during cyclic wake operation except for starting the cyclic wake function. note: it is not possible to select sync (on, off or both) for cyclic sense / cyclic wake when wk4 is enabled. in this case the timer is not started and the spi_fail bit is set. so first th e pin must be configured to sync via the bit wk4_sync before starting cyclic wake / cyclic sense. 5.3 supervision features the device offers various supervision features to support functional safety requirements. please see chapter 15 for more information. cyclic wake configuration sequence cyclic wake starts / ends by setting / clearing on-time int is pulled low of evey rising edge of on-time except for the first one select timer period / sync and desired on-time in timerx_ctrl 10, 20, 50, 100 , 200ms, 1s, 2s, sync low /high off, 0.1, 0.3, 1.0, 10, 20ms, sync select timer1 and/or timer2 as a wake source in wk_ctrl_1 no interrupt will be generated , if the timer is not enabled as a wake source
data sheet 28 rev. 1.1, 2014-02-01 TLE9266QX voltage regulator 1 6 voltage regulator 1 6.1 block description figure 10 module block diagram functional features ? 5 v low-drop voltage regulator ? under voltage monitoring with adjust able reset level, vcc1 failure and vcc1 short circuit detection ( v rt1/2/3/4 , v cc1,fail , v cc1,sc ). please refer to chapter 15.6 and chapter 15.7 for more information. ? short circuit detection and switch off with under volt age fail threshold, device enters sbc fail-safe mode ? 470nf ceramic capacitor at voltage output for stability, with esr < 3 ? @ f = 10khz, to achieve the voltage regulator control lo op stability based on the safe phase margin (bode diagram). ? output current capability up to i vcc1 ,lim . 6.2 functional description the voltage regulator 1 (=vcc1) is ?on? in sbc normal mode and is disabled in sbc sleep mode. to reduce the current consumption of the sbc (see chapter 4.4 ), the vcc1 output voltage is supplied by a low-power regulator (see also p_6.3.18) in sbc stop mo de with a reduced voltage output accuracy ( v cc1,out4 ). the output current of vcc1 is limited at i vcc1 ,lim . gnd bandgap reference charge pump vs state machine vcc1 inh vref overtemperat ure shutdown
TLE9266QX voltage regulator 1 data sheet 29 rev. 1.1, 2014-02-01 6.3 electrical characteristics note: please see chapter 15.7 for the power-up blanking time and short circuit protection. table 7 electrical characteristics t j = -40 c to +150 c; v s = 5.5 v to 28 v; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. output voltage including line and load regulation v cc1,out1 4.9 5.0 5.1 v 1ma < i vcc1 < 150ma; sbc normal mode p_6.3.1 output voltage including line and load regulation v cc1,out2 4.85 5.0 5.15 v 150ma < i vcc1 < 250ma; sbc normal mode p_6.3.2 output voltage including line and load regulation v cc1,out4 4.8 5.0 5.2 v 0ma < i vcc1 < 15ma; sbc stop mode p_6.3.4 output drop v cc1,d1 ? ? 400 mv i vcc1 = 50ma v s =5v p_6.3.5 output drop v cc1,d2 ? ? 500 mv i vcc1 = 150ma v s =5v p_6.3.6 output drop v cc1,d3 ? ? 500 mv 1) ivcc1 = 100ma vs =4.5v 1) specified by design; not subject to production test. p_6.3.7 output drop v cc1,d4 ? ? 600 mv 1) ivcc1 = 150ma vs =4.5v p_6.3.8 active peak threshold vcc1 i peak_vcc1,r 7.0 9.7 15.0 ma 1) i vcc1 rising p_6.3.18 over current limitation i vcc1,lim 250 ? 1100 ma current flowing out of pin, vcc1 = 0v p_6.3.9
data sheet 30 rev. 1.1, 2014-02-01 TLE9266QX voltage regulator 1 figure 11 vcc1 pass device on-resistance during low-drop operation
TLE9266QX voltage regulator 2 data sheet 31 rev. 1.1, 2014-02-01 7 voltage regulator 2 7.1 block description figure 12 module block diagram functional features ? 5 v low-drop voltage regulator ? under voltage monitoring with vcc2 failu re and vcc2 short circuit detection ( v cc2,fail , v cc2,sc ). please refer to chapter 15.8 for more information ? vcc2 switch off after entering sbc restart mode. switch-off is latched, ldo must be enabled via spi after shutdown. ? over temperature protection ? short-circuit robustness against supply voltage vs ? 470 nf ceramic capacitor at output voltage for stability, with esr < 3 ? @ f = 10khz, to achieve the voltage regulator control loop stab ility based on the safe phase margin (bode diagram). ? output current capability up to i vcc2 ,lim . gnd bandgap reference charge pump vs state machine vcc2 inh vref overtemperature shutdown
data sheet 32 rev. 1.1, 2014-02-01 TLE9266QX voltage regulator 2 7.2 functional description in sbc normal mode vcc2 can be switched on or off via spi. in sbc stop- or sleep mode, the vcc2 has to be switched on or off befor e entering the respective sbc mode. to reduce the current consumption of the sbc in sbc stop- and sleep mode (see chapter 4.4 ), the current consumption of the vcc2 regula tor is also reduced with a reduced voltage output accuracy ( v cc2,out2 ). the output current of vcc1 is limited at i vcc2 ,lim.
TLE9266QX voltage regulator 2 data sheet 33 rev. 1.1, 2014-02-01 7.3 electrical characteristics note: please see chapter 15.8 for power-up blanking time and short circuit protection. figure 13 vcc2 pass device on-resistance during low-drop operation table 8 electrical characteristics t j = -40 c to +150 c; v s = 5.5 v to 28 v; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. output voltage including line and load regulation v cc2,out1 4.85 5.0 5.15 v 1ma < i vcc2 < 100ma; sbc normal mode p_7.3.1 output voltage including line and load regulation v cc2,out2 4.8 5.0 5.2 v 0ma < i vcc2 < 15ma; sbc stop and sleep p_7.3.2 output drop v cc2,d2 ? ? 500 mv i vcc2 = 100ma; v s = 5v p_7.3.3 over current limitation i vcc2,lim 100 ? 500 ma current flowing out of pin, vcc2 = 0v p_7.3.4
data sheet 34 rev. 1.1, 2014-02-01 TLE9266QX high-side switch 8 high-side switch 8.1 block description figure 14 high-side module block diagram functional features ? over-voltage and under-voltage switch off - configurable via spi ? over-current detection and switch off ? open-load detection in on-state ? pwm capability with internal timer configurable via spi ? supports cyclic se nse features - see chapter 5.2.3 ? switch recovery after removal of ov or uv condition configurable via spi ? hs1...2 have a typical ron of 2 ? and hs3...6 have a typical ron of 7 ? ? the over-current and open-load dete ction of hs1...2 can be configured via spi depending on the external load hs gate control overcurrent detection open load (on) vs hsx control inputs status / monitoring outputs
TLE9266QX high-side switch data sheet 35 rev. 1.1, 2014-02-01 8.2 functional description the high-side switches can be used for control of leds, as supply of the wake inputs and for other loads. the high-side outputs can be controlled either directly via spi by ( hs_ctrl1 , hs_ctrl2 , hs_ctrl3 ) or by the integrated pwm timers. hs1 and hs2 feature two different open load and over curr ent detection thresholds. this allows to adapt the system to different loads. the selection between th e two configurations can be done via the spi bits hs1_sel and hs2_sel in the register hs_ctrl1 . the higher thresholds are activated by configuring the respective switch with the low on-resistance r on,hs11 and vice versa. the high-side drivers can be kept on also in sbc stop- and sbc sleep mode and also during a long open window, i.e. no successful watchdog trigger is required to turn on the drivers (as compared to the low-side switches). the configuration of the high-side driv ers (permanent on, pwm, cyclic sens e, etc.) must be done in sbc normal mode. when entering sbc restart mode the hsx outputs are disabled. 8.2.1 over- and under voltage switch-off all hs drivers in on-state are switched off in case of over voltage on vs ( v ovd,r ). if the voltage drops below the over voltage threshold the hs drivers are activated agai n. the feature can be disabled by setting the spi bit hs_ov _sd_en . the hs drivers are switched off in case of under voltage on vs ( v uvd,f ). if the voltage rises above the under voltage threshold the hs drivers are acti vated again. the feature can be di sabled by setting the spi bit hs_uv _sd_en . so after release of under voltage or over voltage conditio n the hs switch goes back to programmed state in which it was configured via spi. this beh avior is only valid if the bit hs_ov_uv _rec is set to ?1?. otherwise the switches will stay off (configuration registers hs_ctrlx will be cleared). the over voltage and under voltage is signaled in the bits vs_ov and vs_uv , no other error bits are set. 8.2.2 over-current det ection and switch-off if the load current exceeds the short ci rcuit shutdown current for a time longer then the short circuit shutdown filter time the output is switched off. the over current condition and the switch off is signaled with the respective hsx_oc_ot bit in the register hs_oc_ot_stat . the hsx configuration is then reset to 000 by the sbc. to activate the high-side switch again the hsx configuration has to be set to on (001) or be programmed to a timer function. it is recommended to clear the over-current bit before activa tion the high-side switch, as the bits are not cleared automatically by the sbc. 8.2.3 open-load detection open load detection on the high-side outputs is done during on-state of the output. if the current in the activated output falls below then open-load detection current, the op en load is detected and sign aled via the respective bit hs1_ol, hs2_ol, hs3_ol, hs4_ol, hs5_ol, hs6_ol in the register hs_ol_stat . the high-hide output stays activated. if the open load condition disappears the open load bit in the spi can be cleared. the bits are not cleared automatically by the sbc. 8.2.4 hsx operation in different sbc modes ? in sbc normal mode the output stage is fully functional. prot ection functions as over current detection and open load detection are available. ? using the hsx outputs for the cyclic sense featur e during sbc stop- and sbc sleep mode the open-load detection functionality is disabled fo r power consumption reasons. short circuit shut down as well as over
data sheet 36 rev. 1.1, 2014-02-01 TLE9266QX high-side switch voltage and under voltage shutdown is available. the device is not woken because of short circuit shutdown of a hs output 1) . only the respective hs will be disabled. ? the hsx output can also be enabled for sbc stop- and sbc sleep mode as well as controlled by the pwmx generator. the hsx outputs must be configured in sbc normal mode before entering a low-power mode. ? the hsx outputs are switched off during sbc restart- or sbc fail-safe mode. they can be enabled via spi if the failure condition is removed. 8.2.5 pwm and timer function four 8-bit pwm generators are dedicated to generate a pw m signal on the hs outputs, e.g. for brightness adjustment or compensation of supply voltage fluctuat ion. the pwm generators are mapped to the dedicated hs outputs, and the duty cycle can be independently configured with a 8-bit resolution via spi ( pwm1_ctrl ... pwm4_ctrl ). two different frequencies (150hz, 300hz) can be selected independently for every pwm generator in the register pwm_freq_ctrl . in addition, the hsx outputs can also be used for cyclic sensing via a the timer or sync control (see chapter 5.2 ) and the timers can be used for the cyclic wake function. below assignment is possible: hs1... hs6 : ?timer 1 ?timer 2 ?pwm 1 ?pwm 2 ?pwm 3 ?pwm 4 note: the min. on-time during pwm is lim ited by the actual ton and toff time of the respective hs switch, e.g. the pwm setting ?0000 0001? could not be realized. in addition, the minimum pwm setting for reliable detecti on of over-current and open-load measurement is 5 digits for a period of 300hz and 3 digits for a period of 150hz. 1) a shutdown of an hsx output for the above described reasons could lead to an unintended wake-up. this must be checked in the respective status r egister if it was the case.
TLE9266QX high-side switch data sheet 37 rev. 1.1, 2014-02-01 8.3 electrical characteristics table 9 target specifications t j = -40 c to +150 c; v s = 5.5 v to 28 v; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. output hs1, hs2 static drain-source on resistance hs1...2 r on,hs11 ?2? ? 1) ids=60ma, t j < 25c, spi setting p_8.3.1 static drain-source on resistance hs1...2 r on,hs12 ?4.25.0 ? 1) ids=60ma, t j < 150c, p_8.3.2 output slew rate (rising) sr raise,hs1 0.6 ? 2.8 v/s 2) 20 to 80% v s = 6 to 18v r l =220 ? p_8.3.3 output slew rate (falling) sr fall,hs1 -2.8 ? -0.6 v/s 2) 80 to 20% v s = 6 to18v r l =220 ? p_8.3.4 switch-on time hs1...2 t on,hs1 3 ? 70 s csn = high to 0.8* v s ; r l =220 ? v s = 6 to 18v p_8.3.5 switch-off time hs1...2 t off,hs1 3 ? 70 s csn = high to 0.2* v s ; r l =220 ? v s = 6 to 18v p_8.3.6 short circuit shutdown current 1 i sd1,hs1 150 215 330 ma spi setting v s = 6 to 28v p_8.3.7 short circuit shutdown current 2 i sd2,hs1 260 375 490 ma spi setting v s = 6 to 28v p_8.3.8 short circuit shutdown filter time t sd,hs1 ?64?s 3) 4) p_8.3.9 open load detection current 1 i ol1,hs1 0.4 ? 4 ma spi setting v s = 6 to 28v p_8.3.10 open load detection current 2 i ol2,hs1 6 ? 13.5 ma spi setting v s = 6 to 28v p_8.3.11 open load detection filter time t ol,hs1 ?64?s 3) 4) p_8.3.12
data sheet 38 rev. 1.1, 2014-02-01 TLE9266QX high-side switch note: the slew rate values might be determined by the external component s if the component values are large. note: there is a timing offset of max. 20s (typ.) to control the high-side switc hes due to internal signal transmission. this offset is already includ ed in the specified turn-on and -off times. output hs3, hs4, hs5, hs6 static drain-source on resistance hs3...6 r on,h21 ?7? ? ids=60ma, t j < 25c p_8.3.13 static drain-source on resistance hs3...6 r on,hs22 ? 11.5 16 ? ids=60ma, t j < 150c p_8.3.14 output slew rate (rising) sr raise,hs2 0.6 ? 2.8 v/s 2) 20 to 80% v s = 6 to 18v r l =220 ? p_8.3.15 output slew rate (falling) sr fall,hs2 -2.8 ? -0.6 v/s 2) 80 to 20% v s = 6 to 18v r l =220 ? p_8.3.16 switch-on time hs3...6 t on,hs2 3 ? 70 s csn = high to 0.8* v s ; r l =220 ? v s = 6 to 18v p_8.3.17 switch-off time hs3...6 t off,hs2 3 ? 70 s csn = high to 0.2* v s ; r l =220 ? v s = 6 to 18v p_8.3.18 short circuit shutdown current i sd1,hs2 150 215 330 ma v s = 6 to 20v v s = 6 to 28v p_8.3.19 short circuit shutdown filter time t sd,hs2 ?64?s 3) 4) p_8.3.20 open load detection current i ol,hs2 0.4 ? 4 ma v s = 6 to 28v p_8.3.21 open load detection filter time t ol,hs2 ?64?s 3) 4) p_8.3.22 1) in case the low over current and open load threshold is select ed (hsx_sel = 0) for the respective hs1 or hs2 output, then the static drain-source on resistance values of p_8.3.13/14 apply for this configuration. 2) not subject to production test, specified by design. 3) not subject to production test, tolerance defined by internal oscillator tolerance. 4) the minimum pwm setting for reliable detection of over-c urrent and open-load measurement is 5digits for a period of 300hz and 3 digits for a period of 150hz table 9 target specifications (cont?d) t j = -40 c to +150 c; v s = 5.5 v to 28 v; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
TLE9266QX low-side switch data sheet 39 rev. 1.1, 2014-02-01 9 low-side switch 9.1 block description figure 15 module block diagram functional features ? multi purpose low-side switch ? intended mainly for relay driver ? integrated clamping for inductive loads ? over-current shutdown, signaled via spi ? switch-on via spi ? switch recovery after removal of ov or uv condition - configurable via spi ? over- and under voltage shutdown -configurable via spi 9.2 functional description the general purpose low-side switches are mainly inte nded for on-board relay control, e.g. for power window control. the outputs feature an active output z ener clamping for demagnetization of the relay coil. the low-side drivers can only be active during sbc normal mode and will automatically be switched off when going to sbc sleep- or sbc stop mode or due to failures (tsd1, wd fail or vcc1_uv). the lsx outputs will not be turned on automatically when going back to sbc normal mode. diagnosis registers will be kept until they are actively clea red by the microcontroller. for safety reasons, the below described protection functions are implemented. gate control overcurrent / overtemperature detection lsx gnd control inputs clamp
data sheet 40 rev. 1.1, 2014-02-01 TLE9266QX low-side switch note: the drivers cannot be turned on in a long open wa tchdog window, i.e. they can only be turned on after a first successful watchdog trigger or in sbc software development mode. 9.2.1 over- and under voltag e detection and switch-off the lsx drivers and the respective loads can be protected against supply over voltage ( v ovd,r ) and supply under voltage ( v uvd,f ) conditions. the over voltage shutdown f eature can be disabled by setting the bit ls_ov _sd_en . the under voltage shutdown feature can be disabled respectively by setting the bit ls_uv _sd_en . depending of the bit ls_ov_uv _rec the lsx outputs stay disabled ( ls_ov_uv _rec = 0, i.e. the configuration register will be cleared)) or are enabled again a fter crossing the respecti ve vs threshold again. over voltage and under voltage conditions are si gnaled and latched in the spi status bits vs_ov and vs_uv . no other error bits are set. 9.2.2 over-current detection and switch-off if the load current exceeds the short circuit shutdown current for a time longer then the short-circuit shutdown filter time t ocf the respective lsx output is switched off. the over-current condition and switch off is si gnaled with the respective bit in the registers ls_ctrl and ls_oc_ot_stat . it is recommended to clear the over current bi t before re-activation of the low-side switch, as the bits are not cleared automatically by the sbc.
TLE9266QX low-side switch data sheet 41 rev. 1.1, 2014-02-01 9.3 electrical characteristics table 10 electrical characteristics low-side switch t j = -40 c to +150 c; v s = 5.5 v to 28 v; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. ls1, ls2 static drain - source on resistance r on,ls ?6.58 ? v s > 5.5 v, ids=100ma, t j = 150c p_9.3.1 static drain - source on resistance r on,ls ?4 ? t j = 25c p_9.3.2 switch-on time t on,ls 5 25 100 s csn=high to 0.2* v s r l = 220 ? ; v s = 6 to 20v p_9.3.3 switch-off time t off,ls 5 25 100 s csn=high to 0.8* v s ; r l = 220 ? ; v s = 6v to 20v p_9.3.4 zener clamp voltage v az 40 50 60 v ids=100ma p_9.3.5 clamping energy (repetitive) e clamp,re p 2.5 ? ? mj 1) 1.000.000 cycles 1) not subject to production test, specified by design. p_9.3.6 clamping energy (single), cold e clamp,sin gle,c 10 ? ? mj 1) 1 cycle, t start = 25c p_9.3.7 clamping energy (single), hot e clamp, single,c 7??mj 1) 1 cycle, t start = 85c p_9.3.8 over current shut down threshold over current threshold i octh 250 500 ma ? p_9.3.9 over current filter time t ocf ?64?s 2) 2) not subject to production test; tolerance defined by internal oscillator tolerance. p_9.3.10
data sheet 42 rev. 1.1, 2014-02-01 TLE9266QX high-speed can transceiver 10 high-speed can transceiver 10.1 block description figure 16 functional block diagram 10.2 high-speed can functional description the controller area network (can) transceiver part of th e sbc provides high-speed (hs) differential mode data transmission (up to 1 mbaud) and reception in automotive and industrial applications. it works as an interface between the can protocol controller and the physical bus lines compatible to iso 11898-2 and 11898-5 as well as sae j2284. the can transceiver offers low-power modes to reduce current consumption. this supports networks with partially powered down nodes. to support software diagnostic fu nctions, a can receive-only mode is implemented. it is designed to provide excellent passive behavior when the transceiver is switched off (mixed networks, clamp15/30 applications). a wake-up from the can wake capable mode is possible via a message on the bus. thus, the microcontroller can be powered down or idled and will be woken up by the can bus activities. the can transceiver is designed to withstand the severe conditions of automotive applications and to support 12 v applications. txd can output stage driver temp.- protection canh canl + timeout rxd can receiver mux v cc 1 spi mode control to spi diagnostic vcan v cc1 r td wake receiver vs vcan
data sheet 43 rev. 1.1, 2014-02-01 TLE9266QX high-speed can transceiver 10.2.1 can off mode the can off mode is the default mode after power-up of the sbc. it is available in all sbc modes and is intended to completely stop can activities or when can communication is not needed. the canh/l bus interface acts as a high impedance input with a very sm all leakage current. in can off mo de, a wake-up event on the bus will be ignored. 10.2.2 can normal mode the can transceiver is enabled via spi in sbc norma l mode. can normal mode is designed for normal data transmission/reception within the hs can network. the mode is available in sbc normal mode. the bus biasing is set to 0.5x vcan. transmission the signal from the microcontroller is applied to the txdcan input of the sbc. t he bus driver switches the canh/l output stages to transfer this input signal to the can bus lines. enabling sequence the can transceiver requires an enabling time t can,en before a message can be sent on the bus. this means that the txdcan signal can only be pulled low after the enab ling time. if this is not ensured, then the txdcan needs to be set back to high (=recessive) until the enabling time is completed. only the next dominant bit will be transmitted on the bus. figure 17 shows different scenarios and explanations for can enabling. figure 17 can transceiver enabling sequence reduced electromagnetic emission to reduce electromagnetic emissions (eme), the bu s driver controls canh/l slopes symmetrically. reception analog can bus signals are converted into digital si gnals at rxd via the differential input receiver. t v candi f f t can, en t v t xdcan t can mode can no rmal can off can , en t recessive txd level required bevor start of transmission t can, en not ensured , no tr ansmission on bus can , en t correct sequence , bus is enabled after t can, en t can, en not ensured , no transmission on bus recessive txd level required dominant recessive (v canh -v ) canh
data sheet 44 rev. 1.1, 2014-02-01 TLE9266QX high-speed can transceiver 10.2.3 can receive only mode in can receive only mode (rxd only), the driver stage is de-act ivated but reception is still operational. this mode is accessible by an spi command in normal mode a nd in stop mode. the bus biasing is set to vcan/2. note: the transceiver is still properly working in receive only mode even if vcan is not available because of an independent receiver supply. 10.2.4 can wake capable mode this mode can be used in sbc stop-, sleep-, restart- and sbc normal mode by programming via spi and it is used to monitor bus activities. it is automatically acce ssed in sbc fail-safe mode. a wake-up signal on the bus results in a change of behavior of the sbc, as described in table 11 . as a signalization to the microcontroller, the rxd_can pin is set low and will stay low until the can tr ansceiver is changed to any other mode or until the sbc mode is changed to sbc sleep-, stop- or fail-safe mode (automatic rearming - see also below). after a wake-up event, the transceiver can be switched via spi to can normal mode for communication. both bus pins canh/l are connected to gnd via the input resistors. a wake-up pattern is signaled on the bus by two consecutive dominant bus levels for at least t wake1 (filtering time t > t wake1 ). however the time between two consecutive dominant pulses must be less than t wake2 . figure 18 wup detection following the definition in iso 11898-5 ini bias off 1 bias off 2 bias off 3 bias on 4 bias on wait bias off bus recessive > t wake1 bus dominant > t wake1 optional: t wake2 expired bus recessive > t wake1 bus dominant > t wake1 bus recessive > t wake1 bus dominant > t wake1 optional: t wake2 expired t silence expired and device in low-power mode t silence expired and device in low-power mode entering can normal or can recive only entering low-power mode , when selective wake-up funktion is disabled or not supported
data sheet 45 rev. 1.1, 2014-02-01 TLE9266QX high-speed can transceiver rearming the transceiver for wake capability after a bus wake-up event, the tran sceiver is woken. however, the can transceiver mode bits will still show wake capable (=?01?) so that th e rxd signal will be pulled low. there are tw o possibilities how the can transceiver?s wake capable mode is enabled again after a wake-up event: ? the can transceiver mode must be toggled, i.e. s witched from wake capable mode to can normal mode, can receive only mode or ca n off, before switching to can wake capable mode again. ? rearming is done automatically when the sbc is chan ged to sbc stop-, sbc sleep- , or sbc fail-safe mode to ensure wake -up capability. wake-up in sbc stop- and sbc normal mode in sbc stop mode, if a wake-up is detected, it is signaled by the int output and in the wk_stat spi register. it is also signaled by rxdcan put to low. the same app lies for the sbc normal mode. the microcontroller should set the device from sbc stop mode to sbc normal mode, there is no automatic transition to normal mode. for functional safety reas ons, the watchdog will be automatically enabled in sbc stop mode after a bus wake-up event in case it was disabled before (only if wd_en_ wk_bus = 1). wake-up in sbc sleep mode wake-up is possible via a can message (filtering time t > t wk,bus ). the wake-up automatically transfers the sbc into the sbc restart mode and from there to normal mode the corresponding rxd pins in set to low. the microcontroller is able to detect the low signal on rxd and to read the wake source out of the wk_stat register via spi. no interrupt is generated when coming out of sleep mode. the microcontroller can now for example switch the can transceiver into can norm al mode via spi to start communication. 10.2.5 txd time-out feature if the txd signal is dominant for a time t > t txd_can_to , the txd time-out function deactivates the transmission of the signal at the bus. this is implemen ted to prevent the bus from being blocked permanently due to an error. the can transceiver is switched to receive only mo de. the failure is stored in the spi flag can_fail . the can transmitter stage is activated again after the dom inant time-out condition is removed. the level on the txd pin must be recessive for at least one clock cycle (1/ f clksbc ) to consider the dominant time-out condition is removed. once this condition is fulfilled, th e can transceiver requir es an enabling time t can,en before a dominant bit can be sent on the bus again (see also figure 17 ). table 11 action due to can bus wake up sbc mode sbc mode after wake vcc1 int rxd normal mode normal mode on low low stop mode stop mode on low low sleep mode restart mode ramping up high low restart mode restart mode on high low fail-safe mode restart mode ramping up high low
data sheet 46 rev. 1.1, 2014-02-01 TLE9266QX high-speed can transceiver 10.2.6 bus dominant clamping if the hs can bus signal is dominant for a time t > t bus_can_to , a bus dominant clamping is detected and the spi bit can_fail is set. 10.2.7 vcan under voltage the voltage at the can supply pin is monitored in ca n normal mode. in case of vcan under voltage a signalization via spi bit vcan_uv is triggered and the TLE9266QX disabl es the transmitter stage. if the power supply reaches a higher level than the under voltage detection threshold (vcan > vcan_uv ), then the transmitter is enabled again. once this cond ition is fulfilled, the can transceiver requires an enabling time t can,en before a dominant bit can be sent on the bus again (see also figure 17 ). a transceiver mode ch ange will only occur if the power supply v s drops below the power on reset level. vcan_uv comparator is enabled in sbc normal mode if can_1 = ?1?. note: in order to enable the sending on the can bus ag ain after a vcan under voltage event txd needs to be high (=send recessive bit) firs t before sending a dominant bit. note: please see also bus_stat for an application hint on the vcan_uv behavior during can receive only mode.
data sheet 47 rev. 1.1, 2014-02-01 TLE9266QX high-speed can transceiver 10.3 electrical characteristics table 12 electrical characteristics t j = -40 c to +150 c; v s = 5.5 v to 28 v; 4.75 v < v can < 5.25 v; r l = 60 ? ; can normal mode; all voltages with respect to ground, positive current flo wing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. can supply voltage can supply under voltage detection threshold v can_uv,f 4.5 ? 4.75 v can normal mode; vcan falling; p_10.3.1 can bus receiver differential receiver threshold voltage, recessive to dominant edge v diff,rd_n ?0.800.90v v diff = v canh - v canl ; -12v v cm (can) +12 v; can normal mode p_10.3.2 differential receiver threshold voltage, dominant to recessive edge v diff,dr_n 0.50 0.60 ? v v diff = v canh - v canl ; -12v v cm (can) +12 v; can normal mode p_10.3.3 common mode range cmr -12 ? 12 v ? p_10.3.4 canh, canl input resistance r in 20 40 50 k ? can normal / wake capable mode; recessive state p_10.3.6 differential in put resistance r diff 40 80 100 k ? can normal / wake capable mode; recessive state p_10.3.7 input resistance deviation between canh and canl ? r i -3 ? 3 % 3) recessive state p_10.3.38 input capacitance canh, canl versus gnd c in ?2040pf 3) vtxd = 5v p_10.3.39 differential input capacitance c diff ?1020pf 3) vtxd = 5v p_10.3.40 wake-up receiver threshold voltage, recessive to dominant edge v diff, rd_w ? 0.8 1.15 v -12v v cm (can) +12 v; can wake capable mode p_10.3.8 wake-up receiver threshold voltage, dominant to recessive edge v diff, dr_w 0.4 0.7 ? v -12v v cm (can) +12 v; can wake capable mode p_10.3.9
data sheet 48 rev. 1.1, 2014-02-01 TLE9266QX high-speed can transceiver can bus transmitter canh/canl recessive output voltage v canl/h 2.0 ? 3.0 v can normal mode; vtxd = v cc1 ; no load p_10.3.11 canh/canl recessive output voltage (can wake capable mode) v canl/h_lp -0.1 ? 0.1 v can wake capable mode; v txd = v cc1 ; no load p_10.3.43 canh, canl recessive output voltage difference v diff = v canh - v canl (can normal mode) v diff_r_n -500 ? 50 mv can normal mode v txd = v cc1 ; no load p_10.3.12 canh, canl recessive output voltage difference v diff = v canh - v canl (can wake capable mode) v diff_r_w -500 ? 50 mv can wake capable mode; v txd = v cc1 ; no load p_10.3.41 canl dominant output voltage v canl 0.5 ? 2.25 v can normal mode; v txd = 0 v; v can = 5 v; 50 ? r l 65 ? p_10.3.13 canh dominant output voltage v canh 2.75 ? 4.5 v can normal mode; v txd = 0 v; v can = 5 v; 50 ? r l 65 ? p_10.3.14 canh, canl dominant output voltage difference v diff = v canh - v canl v diff_d_n 1.5 ? 3.0 v can normal mode; v txd = 0 v; v can = 5 v; 50 ? r l 65 ? p_10.3.16 driver symmetry v sym = v canh + v canl v sym 4.5 ? 5.5 v 1) can normal mode; v txd = 0 v / 5 v; v can = 5 v; c split = 4.7nf; 50 ? r l 60 ? p_10.3.42 canh short circuit current i canhsc -100 -80 -50 ma can normal mode; v canhshort = 0 v p_10.3.17 table 12 electrical characteristics (cont?d) t j = -40 c to +150 c; v s = 5.5 v to 28 v; 4.75 v < v can < 5.25 v; r l = 60 ? ; can normal mode; all voltages with respect to ground, positive current flo wing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
data sheet 49 rev. 1.1, 2014-02-01 TLE9266QX high-speed can transceiver canl short circuit current i canlsc 50 80 100 ma can normal mode v canlshort = 18 v p_10.3.18 leakage current (unpowered device) i canh,lk i canl,lk ?57.5a v s = v can =0v; 0v < v canh,l 5v; 2) rtest = 0 / 47 k ? p_10.3.19 receiver output rxd high level output voltage v rxd,h 0.8 v cc1 ??vcan normal mode i rxd(can) = -2 ma; p_10.3.20 low level output voltage v rxd,l ? ? 0.2 v cc1 vcan normal mode i rxd(can) = 2 ma; p_10.3.21 transmission input txd high level input voltage threshold v txd,h ? ? 0.7 v cc1 vcan normal mode recessive state p_10.3.22 low level input voltage threshold v txd,l 0.3 v cc1 ??vcan normal mode dominant state p_10.3.23 txd input hysteresis v txd,hys ? 0.12 v cc1 ?mv 3) p_10.3.24 txd pull-up resistance r txd 20 40 80 k ? ? p_10.3.25 can transceiver enabling time t can,en ?10?s 5) csn = high to first valid transmitted txd dominant p_10.3.37 dynamic can-transceiver characteristics min. dominant time for bus wake-up t wake1 0.5 3 5 s -12v v cm (can) +12 v; can wake capable mode p_10.3.26 wake-up time-out, recessive bus t wake2 0.5 ? 10 ms 5) can wake capable mode p_10.3.36 wup wake-up reaction time t wu_wup ??100s 3)4)5) wake-up reaction time after a valid wup on can bus; p_10.3.44 table 12 electrical characteristics (cont?d) t j = -40 c to +150 c; v s = 5.5 v to 28 v; 4.75 v < v can < 5.25 v; r l = 60 ? ; can normal mode; all voltages with respect to ground, positive current flo wing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
data sheet 50 rev. 1.1, 2014-02-01 TLE9266QX high-speed can transceiver propagation delay txd-to-rxd low (recessive to dominant) t d(l),tr ? 150 255 ns 1) can normal mode cl = 100 pf; rl = 60 ? ; vcan = 5 v; c rxd = 15 pf p_10.3.27 propagation delay txd-to-rxd high (dominant to recessive) t d(h),tr ? 150 255 ns 1) can normal mode cl = 100 pf; rl = 60 ? ; vcan = 5 v; c rxd = 15 pf p_10.3.28 propagation delay txd low to bus dominant t d(l),t ? 50 140 ns can normal mode c l = 100pf; r l = 60 ? ; v can = 5 v; p_10.3.29 propagation delay txd high to bus recessive t d(h),t ? 50 140 ns can normal mode c l = 100 pf; r l = 60 ? ; v can = 5 v; p_10.3.30 propagation delay bus dominant to rxd low t d(l),r ? 100 115 ns can normal mode c l = 100pf; r l = 60 ? ; v can = 5 v; c rxd = 15 pf p_10.3.31 propagation delay bus recessive to rxd high t d(h),r ? 100 115 ns can normal mode c l = 100pf; r l = 60 ? v can = 5 v; c rxd = 15 pf p_10.3.32 propagation delay symmetry td(h),tr - td(l),tr t d,tr,sym ?50 ? 100 ns 1) can normal mode cl = 100pf; rl = 60 ? vcan = 5 v; c rxd = 15 pf p_10.3.45 txd permanent dominant time-out t txd_can_to ?4?ms 5) can normal mode p_10.3.33 bus permanent dominant time-out t bus_can_to ?4?ms 5) can normal mode p_10.3.34 table 12 electrical characteristics (cont?d) t j = -40 c to +150 c; v s = 5.5 v to 28 v; 4.75 v < v can < 5.25 v; r l = 60 ? ; can normal mode; all voltages with respect to ground, positive current flo wing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
data sheet 51 rev. 1.1, 2014-02-01 TLE9266QX high-speed can transceiver figure 19 timing diagrams for dynamic characteristics 1) f txd = 250 khz rectangular signal, duty cycle = 50%; 2) rtest between vs/vcan and 0v (gnd); 3) wake-up is signalized via int pin activation in sbc stop mo de and via vcc1 ramping up with wake from sbc sleep mode; 4) time starts with end of last dominant phase of wup; 5) not subject to production test, tolerance defined by internal oscillator tolerance; t d(l), r t v can di f f t d(l ),t r t d(h), r t d(h), t r t d(l),t t gnd v txd v cc1 t d(h ),t v diff, rd_n v diff, dr_n t gnd 0.2 x v cc1 0.8 x v cc1 v rxd v cc1 (v canh -v ) canh
data sheet 52 rev. 1.1, 2014-02-01 TLE9266QX lin transceiver 11 lin transceiver 11.1 block description figure 20 block diagram 11.1.1 lin specifications the lin network is standardized by international regula tions. the TLE9266QX is compliant to the specification lin 2.2 (also covers lin2.2a) and backward compatible to previous lin specifications lin2.1, lin 2.0 or lin 1.3. the device is also complia nt to the physical layer standard sae-j2 602-2. the sae-j2 602-2 standard differs from the lin 2.2 standard mainly by the lower data rate (10.4 kbit/s). driver temp.- protection current limit output stage txd input receiver rxdlin lin txdlin v s r bus filter timeout lin block.vsd r tx d vcc1 to spi diagnostic spi mode control vcc1 wake receiver vs
TLE9266QX lin transceiver data sheet 53 rev. 1.1, 2014-02-01 11.2 functional description the lin bus is a single wire, bi-direc tional bus, used for in-vehicle networks. the lin transceiver implemented inside the TLE9266QX is the interface between the microcontroller and the physical lin bus. the digital output data from the microcontroller are driven to the lin bus via the txd input pin on the TLE9266QX. the transmit data stream on the txd input is converted to a lin bus signal with optimized slew rate to minimize the eme level of the lin network. the rxd output sends back the information from the lin bus to the microcontroller. the receiver has an integrated filter network to suppress noise on the lin bus and to increase the emi (electro magnetic immunity) level of the transceiver. two logical states are possible on the lin bus according to the lin specification 2.2. in dominant state, the voltage on the lin bus is set close to the gnd level. in recessive state, the voltage on the lin bus is set close to the supply voltage v s . by setting the txd input of the TLE9266QX to low the transceiver generates a dominant level on the li n interface pin. the rxd output reads back the signal on the lin bus and indicates a dominant lin bus signal with a logical low to the microcontroller. setting the txd pin to high the transceiver TLE9266QX sets the lin interface pin lin to th e recessive level, at the sa me time the recessive level on the lin bus is indicated by a logical ?high? on the rxd output. every lin network consists of a master node and one or more slave nodes. to configure the TLE9266QX for master node applications, a resistor in the range of 1 k ? and a reverse diode must be connected between the lin bus and the power supply v s . 11.2.1 lin off mode the lin off mode is the default mode after power-up of th e sbc. it is available in a ll sbc modes and is intended to completely stop lin activities or when lin communication is not needed. in lin off mode, a wake-up event on the bus will be ignored.
data sheet 54 rev. 1.1, 2014-02-01 TLE9266QX lin transceiver 11.2.2 lin normal mode the lin transceiver is enabled via spi in sbc normal mode. lin normal mode is designed for normal data transmission/reception within the lin network. the mode is available in sbc normal mode and in sbc software development mode. transmission the signal from the microcontroller is applied to the txdlin input of the sbc. the bus driver switches the lin output stage to transfer this input signal to the lin bus line. enabling sequence the lin transceiver requires an enabling time t lin,en before a message can be sent on the bus. this means that the txdlin signal can only be pulled low after the enablin g time. if this is not ensu red, then the txdlin needs to be set back to high (=recessive ) until the enabling time is complete d. only the next dominant bit will be transmitted on the bus. figure 21 shows different scenarios and explanations for can enabling. figure 21 lin transceiver enabling sequence reduced electromagnetic emission to reduce electromagnetic emissions (eme), the bus driv er controls lin slopes symm etrically. the configuration of the different slopes is described in chapter 11.2.8 . reception analog lin bus signals are converted into digital signals at rxd via the differential input receiver. 11.2.3 lin receive only mode in lin receive only mode (rxd only), the driver stage is de-act ivated but reception is still possible. this mode is accessible by an spi command and is available in sbc normal- and sbc stop mode. t v li n_ bus t li n, en t v txdlin t lin m ode li n no rmal li n o f f li n ,en t li n, en t recessive txd level required bevor start of tr ansmission t lin, en not ensured , no transm ission on bus cor rect sequence , bus is enabled after t lin, en t lin, en not ensured , no transm ission on bus recessive txd level required recessive dominant
TLE9266QX lin transceiver data sheet 55 rev. 1.1, 2014-02-01 11.2.4 lin wake capable mode this mode can be used in sbc stop, sleep, restart an d normal mode by programming via spi and it is used to monitor bus activities. it is automatic ally accessed in sbc fail-safe mode . a valid wake-up signal on the bus (must be a change from dominant to recessive on the lin bus with a filtering time t > t wk,bus ) results in different behavior of the sbc, as described in below table 22 . as a signalization to the microcontroller, the rxd_lin pin is set low and will stay low until the li n transceiver is changed to any other mo de or until the sb c mode is changed to sbc sleep-, stop- or fail-safe mode (automatic rear ming - see also below). after the wake-up event the transceiver needs be switched to lin normal mode for communication. rearming the transceiver for wake capability after a bus wake-up event, the tran sceiver is woken. however, the reserved transceiver mode bits will still show wake capable (=?01?) so that th e rxd signal will be pulled low. ther e are two possibilities how the lin transceiver?s wake capable mode is enabled again after a wake-up event: ? the lin transceiver mode must be to ggled, i.e. switched to lin normal mode, lin receive only mode or lin off, before switching to li n wake capable mode again. ? rearming is done automatically when the sbc is chan ged to sbc stop-, sbc sleep- , or sbc fail-safe mode to ensure wake -up capability. wake-up in sbc stop- and sbc normal mode in sbc stop mode, if a wake-up is detected, it is signaled by the int output and in the wk_stat spi register. it is also signaled by rxdlin put to low. the same ap plies for the sbc normal mode. the microcontroller should set the device to sbc normal mode, there is no automati c transition to normal mode. for functional safety reas ons, the watchdog will be automatically enabled in sbc stop mode after a bus wake-up event in case it was disabled before (only if wd_en_ wk_bus = 1). wake-up in sbc sleep mode wake-up is possible via a lin message (filtering time t > t wk,bus ). the wake-up automatically transfers the sbc into the sbc restart mode and from there to normal mode the corresponding rxd pins in set to low. the microcontroller is able to detect the low signal on rxd and to read the wake source out of the wk_stat register via spi. no interrupt is generated when coming out of sleep mode. the microcontroller can now switch the lin transceiver into lin normal mode via spi to start communication. table 13 action due to a lin bus wake up sbc mode sbc mode after wake vcc1 int rxd normal mode normal mode on low low stop mode stop mode on low low sleep mode restart mode ramping up high low restart mode restart mode on high low fail-safe mode restart mode ramping up high low
data sheet 56 rev. 1.1, 2014-02-01 TLE9266QX lin transceiver 11.2.5 txd time - out if the txd signal is dominant for the time t > t txd_lin_to , the txd time-out function de activates the lin transmitter output stage temporarily. the transceive r remains in recessive state. the txd time-out functions prevents the lin bus from being blocked by a permanent low signal on the txd pin, caused by a failure. the failure is stored in the spi flag lin_fail . the lin transmitter stage is activated again after the dominant time-out c ondition is removed. the level on the txd must be recessive for at least one clock cycle (1/ f clksbc ) to consider the dominant time-out condition is removed. once this conditio n is fulfilled, the can transc eiver requires an enabling time t lin,en before a dominant bit can be sent on the bus again (see also figure 21 & figure 22 ). figure 22 txd time-out function 11.2.6 bus dominant clamping if the lin bus signal is dominant for a time t > t bus_lin_to , a bus dominant clamping is detected and the spi bit lin_fail is set. 11.2.7 under-voltage detection in case the supply voltage vs is dropping below the vs under-voltage detection threshold ( v s < v uvd ), the TLE9266QX disables the output and receiver stages. if the power supply vs reaches a higher level than the vs under voltage detection threshold (vs >v uvd ), the transmitter stage is enabled again. once this condition is fulfilled, the lin transceiver requires an enabling time t lin,en before a dominant bit can be sent on the bus again (see also figure 21 ). a transceiver mode change will only occur if the power supply v s drops below the power on reset level. txd lin t torec t timeout normal communication normal communication txd time-out due to microcontroller error release after txd time-out recovery of the microcontroller error t t
TLE9266QX lin transceiver data sheet 57 rev. 1.1, 2014-02-01 11.2.8 slope selection the lin transceiver offers a lin low-slope mode for 10.4 kbaud communication and a lin normal-slope mode for 20 kbaud communication. the only difference is the behavior of the transmitter. in lin low-slope mode, the transmitter uses a lower slew rate to further reduce th e eme compared to normal-slo pe mode. this complies with sae j2602 requirements. by default, the device works in lin normal-slope mode. the selection of lin low-slope mode is done by an spi word and will become effectiv e as soon as csn goes ?high?. the selection is accessible in sbc normal mode only. 11.2.9 flash progr amming via lin the device allows lin flash programm ing, e.g. of another li n slave with a communication of up to 115 kbaud. this feature is enabled by de-activating the slope control mechanism via a spi command (bit lin_flash) and will become effective as soon as csn goes ?high?. the spi bit can be set in sbc normal mode. note: it is recommended to perform flash programming only at nominal supply voltage v s = 13.5v.
data sheet 58 rev. 1.1, 2014-02-01 TLE9266QX lin transceiver 11.3 electrical characteristics table 14 electrical characteristics v s = 6 v to 18 v, t j = -40 c to +150 c, r l =500 ? , all voltages with respect to gr ound, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. receiver output (rxd pin) high level output voltage v rxd,h 0.8 v cc ??v i rxd = -1.6 ma; v bus = v s p_11.3.1 low level output voltage v rxd,l ? ? 0.2 v cc v i rxd = 1.6 ma v bus = 0 v p_11.3.2 transmission input (txd pin) high level input voltage v txd,h 0.7 v cc ? ? v recessive state p_11.3.3 txd input hysteresis v txd,hys ?0.12 v cc ?mv 1) p_11.3.4 low level input voltage v txd,l ? ? 0.3 v cc v dominant state p_11.3.5 txd pull-up resistance r txd 20 40 80 k ? v txd = 0 v p_11.3.6 lin bus receiver (lin pin) receiver threshold voltage, recessive to dominant edge v bus,rd 0.4 v s 0.45 v s ?v v bus,rec < v bus < 27 v p_11.3.7 receiver dominant state v bus,dom ? ? 0.4 v s v lin 2.2 param. 17 p_11.3.8 receiver threshold voltage, dominant to recessive edge v bus,dr ?0.55 v s 0.60 v s v v bus,rec < v bus < 27 v p_11.3.9 receiver recessive state v bus,rec 0.6 v s ? ? v lin 2.2 param 18 p_11.3.10 receiver center voltage v bus,c 0.475 v s 0.5 v s 0.525 v s v lin 2.2 param 19 p_11.3.11 receiver hysteresis v bus,hys 0.07 v s 0.1 v s 0.175 v s v v bus,hys = v bus,dr - v bus,rd lin 2.2 param 20 p_11.3.12 wake-up threshold voltage v bus,wk 0.40 v s 0.5 v s 0.6 v s v ? p_11.3.13 dominant time for bus wake-up t wk,bus 30 ? 150 s ? p_11.3.14 lin bus transmitter (lin pin) bus serial diode voltage drop v serdiode 0.4 0.7 1.0 v 1) vtxd = vcc1; lin 2.2 param 21 p_11.3.15 bus recessive output voltage v bus,ro 0.8 v s ? v s v v txd = high level p_11.3.16 bus short circuit current i bus,sc 40 100 150 ma v bus = 13.5 v; lin 2.2 param 12 p_11.3.20
TLE9266QX lin transceiver data sheet 59 rev. 1.1, 2014-02-01 leakage current loss of ground i bus,lk1 -1000 -450 0 a v s = 0 v; v bus = -12 v; lin 2.2 param 15 p_11.3.21 leakage current loss of battery i bus,lk2 ??20a v s = 0 v; v bus = 18 v; lin 2.2 param 16 p_11.3.22 leakage current i bus,lk3 -1??ma v s = 18 v; v bus = 0 v; lin 2.2 param 13 p_11.3.23 leakage current driver off i bus,lk4 ??20a v s = 8 v; v bus = 18 v; lin 2.2 param 14 p_11.3.24 bus pull-up resistance r bus 20 30 47 k ? normal mode lin 2.2 param 26 p_11.3.25 lin input capacitance c bus 20 25 pf 1) p_11.3.26 receiver propagation delay bus dominant to rxd low t d(l),r ? 16s v cc = 5 v; c rxd = 20 pf; lin 2.2 param 31 p_11.3.27 receiver propagation delay bus recessive to rxd high t d(h),r ? 16s v cc = 5 v; c rxd = 20 pf; lin 2.2 param 31 p_11.3.28 receiver delay symmetry t sym,r -2?2s t sym,r = t d(l),r - t d(h),r ; lin 2.2 param 32 p_11.3.29 lin transceiver enabling time t lin,en ?10?s 2) csn = high to first valid transmitted txd dominant p_11.3.39 bus dominant time out t bus_lin _to ?20?ms 1)2) p_11.3.30 txd dominant time out t txd_lin _to ?20?ms 1)2) v txd = 0 v p_11.3.31 txd dominant time out recovery time t torec ?10?s 1)2) p_11.3.32 duty cycle d1 (for worst case at 20 kbit/s) lin 2.2 normal slope d1 0.396 ? ? 3) th rec (max) = 0.744 v s ; th dom (max) = 0.581 v s ; v s = 7.0 ? 18 v; t bit = 50 s; d1 = t bus_rec(min) /2 t bit ; lin 2.2 param 27 p_11.3.33 duty cycle d2 (for worst case at 20 kbit/s) lin 2.2 normal slope d2 ? ? 0.581 3) th rec (min.) = 0.422 v s ; th dom (min.) = 0.284 v s ; v s = 7.6 ? 18 v; t bit = 50 s; d2 = t bus_rec(max) /2 t bit ; lin 2.2 param 28 p_11.3.34 table 14 electrical characteristics (cont?d) v s = 6 v to 18 v, t j = -40 c to +150 c, r l =500 ? , all voltages with respect to gr ound, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
data sheet 60 rev. 1.1, 2014-02-01 TLE9266QX lin transceiver figure 23 simplified test circuit for dynamic characteristics duty cycle d3 (for worst case at 10.4 kbit/s) sae j2602 low slope d3 0.417 ? ? 3) th rec (max) = 0.778 v s; th dom (max) = 0.616 v s ; v s = 7.0 ? 18 v; t bit = 96 s; d3 = t bus_rec(min) /2 t bit ; lin 2.2 param 29 p_11.3.35 duty cycle d4 (for worst case at 10.4 kbit/s) sae j2602 low slope d4 ? ? 0.590 3) threc(min.) = 0.389 vs; thdom(min.) = 0.251 vs; vs = 7.6 ? 18 v; tbit = 96 s; d4 = tbus_rec(max)/2 tbit; lin 2.2 param 30 p_11.3.36 1) not subject to production test, specified by design. 2) not subject to production test, tolerance defined by internal oscillator tolerance 3) bus load conditions concerning lin spec 2.1 c lin , r lin = 1 nf, 1 k ? / 6.8 nf, 660 ? / 10 nf, 500 ? table 14 electrical characteristics (cont?d) v s = 6 v to 18 v, t j = -40 c to +150 c, r l =500 ? , all voltages with respect to gr ound, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. gnd lin 100 nf v s c lin txd wk r lin rxd c rxd d lin
TLE9266QX lin transceiver data sheet 61 rev. 1.1, 2014-02-01 figure 24 timing diagram for dynamic characteristics t bit t bit t bit t bus _dom (max ) t bus_rec (min ) thresholds of receiving node 1 thresholds of receiving node 2 th rec (max) th dom (max) th rec(min ) th dom(min ) t bus _dom (min ) t bus_ rec(max ) t d(l ),r (1) t d(h),r(1) t d(h),r(2) t (l ),r (2) v sup (transceiver supply of transmitting node ) txd ( input to transmitting node ) rxd ( output of r eceiving node 1) rxd (output of receiving node 2) duty cycle 1 = t bus_ rec(min ) / (2 x t bit ) duty cycle 2 = t bus_ rec(max ) / (2 x t bit )
data sheet 62 rev. 1.1, 2014-02-01 TLE9266QX wake and voltage monitoring inputs 12 wake and voltage monitoring inputs 12.1 block description figure 25 wake input block diagram features ? three high-voltage inputs (w k1...3) with vs/2 threshold voltage ? alternate measurement function for high-voltage sensing via wk1 and wk2 ? one 5v input with vcc/2 threshold voltage configurable as wk4 or sync input ? selectable sync input for external control of cycli c sense / cyclic wake, e.g. via microcontroller ? wake-up capability fo r power saving modes ? level-sensitive wake feature low to high and high to low ? in sbc normal- and sbc stop mode the level of the wk pin can be read via spi even if the respective wk is not enabled as a wake source. ? pull-up and pull-down current sources, configurable via spi ? selectable configuration for cyclic wake / cyclic sense ? cyclic sense working with timer1, timer2 ? cyclic sense can be selected to conne ct to any high-side switch (hs1...6) monx_input_circuit_ext.vsd + - t fwkx wkx vs logic i pd_wk i pu_wk
TLE9266QX wake and voltage monitoring inputs data sheet 63 rev. 1.1, 2014-02-01 12.2 functional description the sbc can wake up by a voltage level change at the wa ke inputs. the wk input pins are level sensitive input. this means that both transitions, high to low and low to high, result in a wake-u p. the switching threshold is designed for vs/2 for wk1...3 and vcc1/2 for wk4. the wk input filtering time (16 s or 64 s) can be selected via spi ( wk1_flt ...4). the wake-up capability for each wk pin can be enabled or disabled vi a spi command in the wk_ctrl_2 register. when setting the bit wk1_en, wk2_en, wk3_ en or wk4_en to 1, the device wakes up from sbc sleep mode with a high to low or low to high transition on the se lected wk input. an interrupt will be generated in sbc stop mo de and in sbc normal mode. from sbc fa il-safe mode the device will always go to sbc restart mode with a high to low or low to high transition. the wake source for a wake via a wkx pin can always be read in the register wk_stat at the bits wk1_wu, wk2_wu, wk3_wu, and wk4_wu. the actual voltage level of the wk pin (low or high ) can always be read in sbc normal and sbc stop mode in the register wk_lvl_stat . during cyclic sense, the register show the sampled levels of the respective wk pin. wk4 is not a default wake source to avoid an unin tentional wake if the pin is configured as sync. by selecting the sync input, the cyclic sense function can be controlled extern ally via the microcontroller. it can be configured (spi registers timer1_ctrl and hs_ctrl1 ...3) to control either the period, or the on-time or both parameters (see also chapter 5.2 ). note: it is not possible to select sync (on, off or both) for cyclic sense / cyclic wake when wk4 is enabled. in this case the timer is not started and the spi_fail bit is set. so first the pin must be configured to sync via the bit wk4_sync before starting cyclic wake / cyclic sense. 12.2.1 wake input configuration the wk inputs can be configured independently via the spi register wk_pupd_ctrl note: if there is no pull-up or pull-down configured on th e wk input, then the respective input should be tied to gnd or vs on board to avoid unintended floating and waking of the pin. during sbc sleep mode, the configurations ?01?, ?10? and ?11? are not available for wk4. the pull-up/down configurations of wk4 are supplied by vcc1, which is di sabled during sbc sleep mode. this must be considered by the application. note: to avoid an unintentional wake-up at wk4, it is recommended to define the level of wk4 with an external pull-up/down circuitry if possible. table 15 pull-up / pull-down resistor wkx_pupd_1 wkx_pupd _0 output current 00no resistor 0 1 pull-down 1 0 pull-up 1 1 automatic switching if a high level is detected t he pull-up is activated, if low level is detected the pull down is activated.
data sheet 64 rev. 1.1, 2014-02-01 TLE9266QX wake and voltage monitoring inputs the filter time configuration of each wk input is done via the spi register wk_flt_ctrl . the user can choose between static sensing and cyclic sensing with an as signed hs switch or cyclic wake respectively. configurations c or d are intended for cyclic sense config uration. with the filter se ttings, the respective timer needs to be assigned to one or more hs output, which s upplies an external circuit connected to the wkx pin, e.g. hs1 controlled by timer 2 (hs1 = 010) and connecte d to wk3 via an switch circuitry - see also chapter 5.2 . if sync is selected to control the cyclic sense or cyc lic wake timing, then the wk4/sync pin is automatically configured with a pull down ( wk4_pupd = ?01?) but register values will be kept. when sync is selected to stop the on-time, then the def ault filter time (see wk_flt_ctrl ) is selected. 12.2.2 alternate measurement function with wk1 and wk2 12.2.2.1 block description this function provides the possibility to measure a volta ge, e.g. the unbuffered battery voltage, with the protected wk1 high-voltage input. the measured voltage is routed out at wk2. it allows for example a voltage compensation for led lighting by changing the duty cycle of the hi gh-side outputs according to the supply voltage. a simple voltage divider needs to be placed ex ternally to provide the correct voltage level to the microcontroller a/d converter input. the function is available in sbc normal mode and it is disabled in all other modes to allow a low-quiescent current operation.the meas urement function can be used instead of the wk1 and wk2 wake and level signalling capability. the benefits of the function is that the signal is meas ured by a hv-input pin and that there is no current flowing through the resistor divider during low-power modes. the functionality is shown in a simplified applicat ion diagram in figure 4 . 12.2.2.2 functional description this measurement function is by default disabled. in this case, wk1 and wk2 have the regular wake and voltage level signalization functionality. the switch s1 is open for this configuration (see figure 4 ). the measurement function can be enabled via the spi bit wk_meas . if wk_meas is set to ?1?, then the measurement function is enabled and switch s1 is closed in sbc normal mode. s1 is open in all other sbc modes. in this function th e pull-up and down currents of wk1 and wk2 are disabled and the internal wk1 and wk2 signals are gated. in ad dition, the settings for wk1 and wk2 in the registers wk_pupd_ctrl , wk_flt_ctrl and wk_ctrl_2 are ignored but changing these setting is not prevented. the registers wk_stat and wk_lvl_stat are not updated with respect to the inputs wk1 and wk2. however, if only wk1 or wk2 are set as wake sour ces and a sbc sleep mode command is sent, then the spi_fail flag will be set and the sbc will be changed into sbc restart mode. see below ta ble for further details. table 16 wake filter time wkx_flt_1 wkx_flt_0 filter time 0 0 config a 16s filter time, no cyclic sense 0 1 config b 64s filter time, no cyclic sense 1 0 config c timer 1, 16s filter time. period, on-time and settle time configurable in register timer1_ctrl 1 1 config d timer 2, 16s filter time. period, on-time and settle time configurable in register timer2_ctrl
TLE9266QX wake and voltage monitoring inputs data sheet 65 rev. 1.1, 2014-02-01 note: there is a diode in series to the switch s1 (not shown in the figure 4 ), which will influence the temperature behavior of the switch. table 17 differences between normal wk function and measurement function affected settings/modules for wk1 and wk2 inputs wk_meas = 0 wk_meas = 1 s1 configuration ?open? ?closed? in sbc normal mode, ?open? in all other sbc modes internal wk1 & wk2 signal processing default wake and level signaling function, wk_stat , wk_lvl_stat are updated accordingly ?wk1...2 inputs are gated internally, wk_stat , wk_lvl_stat are not updated wk1_en , wk2_en wake up via wk1 and wk2 possible if bits are set setting the bits is ignored and not prevented. if only wk1_en , wk2_en are set while trying to go to sbc sleep mode, then the spi_fail flag will be set and the sbc will be changed into sbc restart mode. wk_pupd_ctrl normal configuration is possible no pull-up or pull-down enabled wk_flt_ctrl normal configuration is possible setti ng the bits is ignored and not prevented
data sheet 66 rev. 1.1, 2014-02-01 TLE9266QX wake and voltage monitoring inputs 12.3 electrical characteristics table 18 electrical characteristics t j = -40 c to +150 c; v s = 5.5 v to 28 v; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. wk1...wk3 input pin characteristics wake-up/monitoring threshold voltage v wkth 0.4*v s 0.5*v s 0.6*v s v without external serial resistor r s (with r s :dv = i pd/pu * r s ); p_12.3.1 threshold hysteresis v wkth,hys 0.02*v s 0.06*v s 0.12*v s v 1) without external serial resistor rs (with rs:dv = ipd/pu * rs); 1) not subject to production test; specified by design p_12.3.2 wk pin pull-up current i pu_wk -20 -10 -3 a v wk_in = 0,6*v s p_12.3.3 wk pin pull-down current i pd_wk 31020av wk_in = 0.4*v s p_12.3.4 input leakage current i lk,l -2 2 a 0 v < v wk_in < 40v p_12.3.5 drop voltage across s1 switch v drop,s1 ? 1000 ? mv 1) drop voltage between wk1 and wk2 when enabled for voltage measurement; i wk1 = 500a; t j = 25c p_12.3.13 timing wake-up filter time t fwk1 -16-s 2) spi setting 2) not subject to production test, tolerance defined by internal oscillator tolerance p_12.3.6 wake-up filter time t fwk2 -64-s 2) spi setting p_12.3.7 wk4/sync wk4/sync threshold voltage v wk4th 1.5 ? 3.5 v 3) sbc normal- and sbc stop mode; without external serial resistor r s (with r s :dv = i pd/pu * r s ); 3) the parameter applies only for sbc normal and stop mode, the lower threshold is lower in sbc sleep mode p_12.3.10 hysteresis of wk4/sync input voltage v wk4,hys ?0.8?v 1) p_12.3.11 pull-down resistance at pin wk4/sync r sync 20 40 80 k ? 4) v sync = 1v 4) only applies if pin is configur ed as sync. if configured as wk 4 then settings in spi register wk_pupd_ctrl will apply. the pull-up resistor has the same value as the pull-down resistor. p_12.3.12
TLE9266QX wake and voltage monitoring inputs data sheet 67 rev. 1.1, 2014-02-01 figure 26 typical characteristics of s1 drop voltage (between wk1 & wk2) vs. temperature for different s1 currents
data sheet 68 rev. 1.1, 2014-02-01 TLE9266QX interrupt function 13 interrupt function 13.1 block and functional description figure 27 interrupt block diagram as shown in figure 27 int is designed as a push/pull output stage. an interrupt is triggere d and int is pulled low (active low) for t int in sbc normal- and sbc stop mode in case of a wake-up event via: ?lin ?can ? wk1...4 ? cyclic wake (timer1 and timer2) ? tripping the i wd_off threshold on vcc1 in sbc stop mode an interrupt is only triggered if the respective function is also enabled as a wake source in wk_ctrl_2 . no interrupt is generated for a failure detection, e. g. for hsx failure. when the sbc is in stop mode and an interrupt is triggered, then the mode is not left automatically. if the device is in sbc stop mode with ivcc1 > i wd_off and the watchdog is not disabl ed, then an interrupt is also generated if ivcc1 > i wd_off . the intention is to signal the microcontr oller that the watchdog has restarted and needs to be triggered again. the wake signalization of an i wd_off threshold crossing can be disabled by clearing the bit wd_stm_ wk_en in wk_ctrl_1 . the spi register wk_stat is updated at every falling edge of the int pulse. all wake-up events are stored in this register until the register is read and cleared via spi command. a second spi read after reading out the wk_stat register is optional but recommended to verify th at the wake-up event is not present anymore. the interrupt behavior is shown in figure 28 . interrupt block.vsd interrupt logic int time out v cc1
data sheet 69 rev. 1.1, 2014-02-01 TLE9266QX interrupt function figure 28 interrupt signalization behavior interrupt_behavior.vsd int wk1 wk2 t int t intd update of wk_stat register spi read & clear update of wk_stat register wk_stat contents scenario 1 wk1 no wk wk2 no wk optional spi read & clear wk_stat contents scenario 2 wk 1 + wk2 no wk no spi read command sent
data sheet 70 rev. 1.1, 2014-02-01 TLE9266QX interrupt function 13.2 electrical characteristics table 19 interrupt output v s = 6 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol values unit note / test condition number min. typ. max. interrupt output; pin int int high output voltage v int,h 0.8 v cc1 ??v i int = -1 ma; int = off p_13.2.1 int low output voltage v int,l ? ? 0.2 v cc1 v i int = 1 ma; int = on p_13.2.2 int pulse width t int ? 100 ? s 1) 1) not subject to production test, tolerance defined by internal oscillator tolerance. p_13.2.3 int pulse minimum delay time t intd ? 100 ? s 1) between consecutive pulses p_13.2.4
data sheet 71 rev. 1.1, 2014-02-01 TLE9266QX fail output 14 fail output 14.1 block and functional description figure 29 fail output block diagram the fail output consists of a failure logic block and a low-side switch. in ca se of failure the fo output is activated (pulled to low) and the spi bit failure in the register dev_stat is set. the fail output is activated due to following failure conditions: failure conditions ? one watchdog trigger failure ? vcc1 under voltage ? thermal shutdown tsd2 ? sdi stuck at ?high? or ?low? in order to deactivate the fail output the failure conditions (e.g . tsd2, ...) must not be present anymore and the bit failure needs to be cleared via spi command. in case of watchdog fail, the deactiv ation of the fail output is only allowed after a successful wd trigger, which will automatically clear the wd_fail bits. note: the fail output pin is triggered for any of the above described failure and not only for failures leading to the sbc fail-safe mode. it is also possible to activate the fo pin manually via the spi bit fo_on , e.g. for verification purposes. the fo output can also be disabled again by cl earing this bit as long as none of the above described failure conditions are present. in this case, the fo will stay activated until the fa ilure is not present anymore. note: the failure bit will not be updated in the spi register dev_stat if fo_on is set because it is not considered as a failure. fail output block.vsd failure logic fo
data sheet 72 rev. 1.1, 2014-02-01 TLE9266QX fail output 14.2 electrical characteristics table 20 interrupt output v s = 6 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol values unit note / test condition number min. typ. max. fail output; pin fo fo low output voltage (active) v fo,l ?0.10.2v i fo = 1ma p_14.2.1 fo high output current (inactive) i fo,h 0? 2a v fo = 28v p_14.2.2
data sheet 73 rev. 1.1, 2014-02-01 TLE9266QX supervision functions 15 supervision functions 15.1 reset function figure 30 reset block diagram 15.1.1 reset output description the reset output pin ro provides a reset information to the microcontroller, for example, in the event that the output voltage has fallen below the under voltage threshold v rt1/2/3/4 . in case of a reset ev ent, the reset output ro is pulled to low after the filter time t rf and stays low as long as the reset event is present including a reset delay time t rd1 . when connecting the sbc to battery voltage, the reset signal remains low initially. when the output voltage v cc1 has reached the default reset threshold v rt1,f , the reset output ro is rele ased to high after the reset delay time t rd1 . a reset can also occur due to a watchdog trigger failure. the reset threshold can be adjusted via spi. the thresholds have a larger tolerance in sbc stop mode. the ro pin has an integrated pull-up resistor. in case reset is triggered, it will be pulled low for v cc1 1v and for vs v por,f . 15.1.2 soft reset description it is also possible to trigger a soft reset via an spi command in order to bring the sbc into a defined state in case of failures. in this case the microcontroller must send a spi command and set the mode bits to ?11? in the m_s_ctrl register. as soon as this command becomes valid, the sbc is set back to sbc init mode and all spi registers are set to their default values (see spi chapter 16.5 and chapter 16.6 ). there is no reset (ro) triggered when the soft reset is executed. note: the device must be in sbc normal mode when sending this command 15.2 window watchdog function the watchdog is used to monitor the software execution of the microcontroller and to trigger a reset if the microcontroller stops serving the watchdog due to a lock up in the software. in case of the window watchdog, the microcontroller must trigger the watchdog in a certain time frame, the so called open window, of the selected timeout period. reset logic incl. filter & delay ro v c c 1
TLE9266QX supervision functions data sheet 74 rev. 1.1, 2014-02-01 the watchdog timing is programmed via spi command. as soon as the watch dog is programmed, the timer starts with the new setting and the watchdog must be served. please refer to table 21 to match the sbc modes with the respective watchdog modes. the long open window ( t lw ) allows the microcontroller to run its initialization sequences and then to trigger the watchdog via the spi. the watchdog is served (=triggered) by spi with a write access to the watchdog register. in case of a watchdog reset, sbc restart mode is entere d and ro is pulled low. the sbc transitions automatically to normal mode after the reset delay time t rd1 and ro is deactivated (pulled high) and the watchdog immediately starts with a long open window. in sbc software development mode, no reset is generated due to watchdog failure, the watchdog is off. 15.2.1 window watchdog the watchdog is triggered by sending a valid spi-write command to the watchdog configuration spi register wd_ctrl . the wd-trigger command is executed when the csn input becomes high. a correct watchdog trigger results in starting the window watchdog by a closed window with a width of typically 60% of the selected window watchdog timer period. the closed window is followed by an open window. the ratio between open and closed window as well as the tolerance of the oscillator defines the ?safe trigger area? of the programmed window watchdog time (see figure 31 ). the safe trigger area is therefore between 72% and 120% of the selected window watchdog timer period. this pe riod, selected via the window watchdog timing bit field ( wd_timer ), is in the range of 10 ms to 1000 ms. a correct watchdog service immediately resu lts in starting the next closed window. should the trigger signal meet the closed window, a watc hdog reset is created by sett ing the reset output ro low and the sbc switches to sbc restart mode. table 21 watchdog functionality by sbc modes sbc mode watchdog mode remarks init mode start after init mode watchdog starts with long open window normal mode wd programmable; ? stop mode watchdog is fixed watchdog off depending on setting and current on vcc1 sleep mode off sbc does not remain the set-up. restart mode off sbc will start with lo ng open window when entering normal mode.
data sheet 75 rev. 1.1, 2014-02-01 TLE9266QX supervision functions figure 31 window watchdog definitions 15.2.2 watchdog settings the settings of the watchdog can be changed during the operation of the watchdog. the change is done with a spi programming into the watchdog configuration bits. the new setting is programmed together with a valid watchdog trigger according to the old settings. the time r with the new settings st arts with this spi command. the following watchdog settings are available ? wd setting 1: 10ms ? wd setting 2: 20ms ? wd setting 3: 50ms ? wd setting 4: 100ms ? wd setting 5: 200ms ? wd setting 6: 500ms ? wd setting 7: 1000ms note: after a watchdog trigger failure, the wd_fail counter is increase d. this counter is cleared automatically after a successful watchdog trigger or when enterin g sbc software developm ent mode. sbc fail-safe mode is entered after 15 sequential watchdog fails. 15.2.3 watchdog durin g sbc stop mode in sbc stop mode the watchdog can be disabled. there are 2 options that can be selected via spi. ? watchdog is off in sbc stop mode ( wd_stm_ en_0 = 1, wd_stm_ en_1 = 1) ? watchdog is off if i vcc1 < i wd_off ( wd_stm_ en_0 = 0 and/or wd_stm_ en_1 = 0) for wd_stm_en_x = 0, the watchdog will automatically start if i vcc1 > i wd_off . in this case, the watchdog will start again with a long open window. should the current decrease again below the i wd_off threshold, then the watchdog is again disabled. in case the watchdog is enabled in sbc stop mode, then the watchdog settings can?t be changed. a trial to do this will result the diagnosis bit spi_fail to be set. it would also enable the watchdog again in case the watchdog was enabled. for safety reasons, there is a special sequence to be followed in order to disable the watchdog. if this sequence is not ensured th en also the bit wd_stm_ en_1 will be cleared and the sequence has to be st arted again. closed window open window t / [t wdper ] safe trigger area w d1 _per .vsd window watchdog timer period (wd_timer) t wd x 0.72 t wd x 1.20 uncertainty uncertainty t wd x 0.48 t wd x 1.80 t wd x 0.60
TLE9266QX supervision functions data sheet 76 rev. 1.1, 2014-02-01 this is shown in figure 32 . as soon as the sbc is set to sbc no rmal mode, then the bits wd_stm_en_1 and wd_stm_ en_0 are cleared and this sequence must be followed again to switch off the watchdog. returning to sbc normal mode and/or triggering th e watchdog in sbc stop mode will al so enable the watchdog again, which will start with a long open window. figure 32 window watchdog disabling sequence 15.2.4 watchdog start in sbc st op mode due to bus wake in sbc stop mode the watchdog can be disabled. in additi on a feature is available which will start the watchdog with any bus wake during sbc stop mode. t he feature is enabled by setting the bit wd_en_ wk_bus = 1 (= default value after por). the bit can only be changed in sbc normal mode and needs to be programmed before entering sbc stop mode and it is not reset by the sbc. the sequence described in figure 33 needs to be followed to disable the wd. with the function enabled the watchd og will start again with any wake on ca n or lin. the wake on can and lin will generate an interrupt and th e rxd pin for lin or can is pulled to low. with that microcon troller is informed that the watchdog is started independently if the vcc1 load current is below the i wd_off threshold or not. the watchdog starts with a long open window. the watchdog can be triggered in sbc stop mode or the sbc can be switched to sbc normal mode. to disable the watchdog again, the sbc needs to be switched to sbc normal mode and the sequence needs to be sent again. correct wwd disabling sequence set bit wd_stm_en_1 = 1 wwd_disabling_sequence.vsd set bit wd_stm_en_0 = 1 with next wd trigger wwd is switched off sequence errors ? missing to set bit wd_stm_en_0 with the next watchdog trigger after having set wd_stm_en_1 ? staying in normal mode change to sbc stop mode before subsequent wd trigger will enable the wwd : ? switching back to sbc normal mode ? triggering the watchdog
data sheet 77 rev. 1.1, 2014-02-01 TLE9266QX supervision functions figure 33 watchdog disabling sequence (with wake via bus) 15.3 vs power-on reset the vs power-on reset ( v por,f ) will generate an internal reset to the device. it can be detected via spi. in case vs < v por,f , the sbc is switched off and will restart in init mode at the next vs rising. 15.4 under voltage vs if the supply voltage vs reaches the under voltage threshold ( v uvd,f ) the sbc preforms the following measures: ? hs1...6 are switched off depending on the spi setting (only if spi bit hs_uv _sd_en is set to ?0?) ? lin is switched to high impedance (can is not disabled) ? ls1 and ls2 are switched off depending on the spi setting (only if spi bit ls_uv _sd_en is set to ?0?) ? spi bit vs_uv is set and can be read/cleared via spi, no other error bits are set in case the drivers are switched off, the respective spi bits are cleared and must be turned on again by setting the respective spi bits. it is recommended to clear the vs_uv bit but it is not requir ed to enable the switches again. note: in case the spi bits ls_ov_uv _rec and hs_ov_uv _rec are set to ?1?, the output drivers (lsx, and hsx) resume the previous state once the vs under-voltage condition is removed. note: there is no vs monitoring available in sbc stop mode - due to current consumption saving requirements. however, vs_uv monitoring is enabled as soon as one peripheral (e.g. hs, lin, can, vcc2) is turned on. correct wd disabling sequence set bits wd_en_wk_bus = 1 (1) & wd_stm_en_1 = 1 set bit wd_stm_en_0 = 1 with next wd trigger wwd is switched off sequence errors ? missing to set bit wd_stm_en_0 with the next watchdog trigger after having set wd_stm_en_1 ? staying in normal mode change to sbc stop mode before subsequent wd trigger will enable the wwd : ? switching back to sbc normal mode ? triggering the watchdog ? wake on can ? wake on lin (1) this bit must not be set at the same time with wd_stm_en. it can also be set earlier
TLE9266QX supervision functions data sheet 78 rev. 1.1, 2014-02-01 15.5 over voltage vs if the supply voltage vs reaches the over voltage threshold ( v ovd,r ) the sbc does the following measures: ? hs1...6 are switched off depending on the spi setting (only if spi bit hs_ov _sd_en is set to ?0?) ? ls1 and ls2 are switched off depending on the spi setting (only if spi bit ls_ov_uv _rec is set to ?0?) ? spi bit vs_ov is set and can be read/cleared via spi in case the drivers are switched off, the respective spi bits are cleared and must be turned on again by setting the respective spi bits. it is recommended to clear the vs_ov bit but it is not requir ed to enable the switches again. note: in case the spi bit ls_ov_uv _rec is set to ?1?, the output drivers (hsx, and lsx) resume the previous state once the vs over-voltage condition is removed. note: there is no vs monitoring available in sbc stop mode - due to current consumption saving requirements. however, vs_uv monitoring is enabled as soon as one peripheral (e.g. hs, lin, can, vcc2) is turned on. 15.6 vcc1 under voltage as described in chapter 15.1 , when the v cc1 output voltage reaches the under voltage threshold (v rtx ), a reset will be triggered (ro pulled ?low?) and the sbc will enter sbc restart mode. note: the vcc1_uv bit is not set in sbc sleep mode as vcc1 is switched off in this case. 15.7 vcc1 fail & short circuit there are two additional protecti on features implemented for v cc1 : ? short circuit detection: if v cc1 is not above the v cc1,sc within t vcc1,sc after turning on v cc1 or falls below v cc1,sc for more than t vcc1,sc , then the spi bit vcc1_sc bit is set. v cc1 is turned off and sbc fail-safe mode is entered. the sbc can be activated ag ain via wake on can, lin, wk1-3 ? vcc1 failure: in case vcc1 will drop below the threshold v cc1,fail for t > t vcc1,fail , the spi bit vcc1_fail is set and can be only cleared via spi ? the thresholds of v cc1,sc and v cc1,fail are identical note: neither the vcc1_sc nor the vcc1_fail flag is set during power up of vcc1 , i.e. it is blanked out. 15.8 vcc2 fail & short circuit ? short circuit detection: in case vcc2 is not above v cc2,sc within t vcc2,sc after turning on v cc2 or falls below v cc2,sc for more than t vcc2,sc , then the spi bit vcc2_sc _ot bit is set, and vcc2 is turned off. the filter time (=blanking time) also applies when vcc2 is switched on. vcc2 can be activated again via spi. it is not necessary to clear the spi failure bit but it is recommended. ? vcc2 failure: in case vcc2 will drop below the v cc2,fail threshold for t > t vcc2,fail , then the spi bit vcc2_fail is set and can be only cleared via spi ? the threshold of v cc2,sc and v cc2,fail are identical note: neither vcc2_sc _ot nor vcc2_fail flag is set during tu rn-on or turn-off up of v cc2. note: if vcc2 is enabled during sbc sleep m ode and the voltage will decrease below the v cc2,fail threshold, then the vcc2_fail bit will be set.
data sheet 79 rev. 1.1, 2014-02-01 TLE9266QX supervision functions 15.9 thermal protection the thermal protection mechanis m is designed in a way that vcc1 will stay active as long as possible in case of high temperature. following thermal protection features are available and signaled via spi: ? thermal pre warning: only the spi bit tpw is set when the threshold t jpw is reached. no other actions are taken. ? over temperature protection: ? over temperature shut down with 2 levels of priority (tsd1 and tsd2). ? if one output stage or driver (hs1...hs6, ls1... 2, lin, can, vcc2) reaches the tsd1 temperature threshold t jtsd1 , then it is switched off individually as a firs t-level protection measure, the respective control bits are reset, the tsd1 bit and the respective oc_ot bit is set. th e other output stages are not affected if their tsd1 threshol d is not exceeded. once the ot condition is not present anymore, the re spective peripherals are not automatically enabled (except for can & lin - see below) but must be switched on by setting the respective spi registers. it is not required to clear the tsd1 flag and the oc_ot flags (where applicable) to turn on the respective driver but it is recommended. ? lin and can transceivers: the drivers are automatically switched on again if the ot condition is not present anymore. the user should rese t the bus_fail bits via spi. ? in case vcc1 reaches the t jtsd2 temperature threshold, then the sbc is switched off for 1s and the tsd2 bit is set. then the sbc restart mode is entered. if 7x tsd2 restarts occur within one minute, then the device is sent to sbc fail-safe mo de with the default wake sources lin, can, wk1...wk3 are enabled. the time is counted starting from the first tsd2 ev ent. if the minute passed and less than 7 tsd2 events occurred, then the first event is discarded and the minu te is considered to be counted from the second event and so on. ? once the respective bits (tpw, tsd1, tsd2) are set, they can be cleared via spi if the condition is not present anymore. note: in case of an tsd1 event for one high-side switch or for one low-side switch, then all high-sides or low-sides are switched off respectively and the ot bits are set for all high-side or low-side switches. note: once a tsd2 event it detected and he sbc is switch ed off for 1s, then also the reset output is pulled low to bring the sbc into a defined state. note: if the tsd2 counter is different than ?000? when entering sbc stop mode or sbc sleep mode, then there will be a period of not more than on e minute (depending when the last tsd2 event occurred) of higher current consumption before the specified low-power current consumption is resumed.
TLE9266QX supervision functions data sheet 80 rev. 1.1, 2014-02-01 15.10 electrical characteristics table 22 electrical characteristics v s = 5.5 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol values unit note / test condition number min. typ. max. vcc1 monitoring, reset generator; pin ro reset threshold voltage rt1,f v rt1,f 4.45 4.60 4.70 v default setting; vcc1 falling p_15.10.1 reset threshold voltage stop rt1,f v rt1st,f 4.40 4.60 4.75 v default setting; sbc stop mode; vcc1 falling p_15.10.40 reset threshold voltage rt2,f v rt2,f 4.05 4.20 4.30 v spi option; vcc1 falling p_15.10.3 reset threshold voltage stop rt2,f v rt2st,f 4.00 4.20 4.35 v spi option; sbc stop mode; vcc1 falling p_15.10.42 reset threshold voltage rt3,f v rt3,f 3.65 3.80 3.90 v spi option; vs 4v; vcc1 falling p_15.10.5 reset threshold voltage stop rt3,f v rt3st,f 3.60 3.80 3.95 v spi option; sbc stop mode; vs 4v; vcc1 falling p_15.10.44 reset threshold voltage rt4,f v rt4,f 3.15 3.40 3.50 v spi option; vs 4v; vcc1 falling p_15.10.7 reset threshold voltage stop rt4,f v r0t4st,f 3.10 3.40 3.55 v spi option; sbc stop mode; vs 4v; vcc1 falling p_15.10.46 reset threshold hysteresis v rt,hys 20 100 200 mv sbc normal mode p_15.10.9 vcc1 short to gnd threshold voltage v cc1,sc ??2v? p_15.10.10 vcc1 short to gnd filter time t vcc1,sc ?4 ms 2) p_15.10.11 vcc1 fail threshold voltage v cc1,fail ??2v? p_15.10.12 vcc1 fail filter time t vcc1,fail ?2?s 3) p_15.10.13 reset low output voltage v ro,l ?0.20.4v i ro = 1 ma for v cc1 1 v p_15.10.14 reset high output voltage v ro,h 0.8 x v cc1 ? v cc1 + 0.3 v v i ro = -20a p_15.10.15 reset pull-up resistor r ro 10 20 40 k ? v ro = 0 v p_15.10.16
data sheet 81 rev. 1.1, 2014-02-01 TLE9266QX supervision functions reset filter time t rf 41026s 2) vcc1 < vrt1x to ro = l p_15.10.17 reset delay time t rd1 1.5 2 2.5 ms 1) 2) p_15.10.18 vcc2 monitoring vcc2 short to gnd threshold voltage v cc2,sc ??2v? p_15.10.19 vcc2 short to gnd filter time t vcc2,sc ?4 ms 2) p_15.10.20 vcc2 fail threshold voltage v cc2,fail ??2v? p_15.10.21 vcc2 fail filter time t vcc2,fail ?2?s 3) p_15.10.22 watchdog generator long open window t lw ? 200 ? ms 2) p_15.10.23 switch-off current for wd in stop mode i wd_off 0.80 5 ma ? p_15.10.24 internal oscillator f clksbc 0.8 1.0 1.2 mhz ? p_15.10.25 power-on reset, over / under voltage protection vs power-on reset rising v por,r ? 4.5 v vs increasing p_15.10.26 vs power-on reset falling v por,f ? 4v v vs decreasing p_15.10.27 vs over voltage detection threshold v ovd,r 19.5 22 v rising p_15.10.28 vs under voltage detection threshold v uvd,f 4.8 5.5 v falling p_15.10.29 test test high-input voltage threshold v test,h ? ? 0.7 x v cc1 v ? p_15.10.30 test low-input voltage threshold v test,l 0.3 x v cc1 ? ? v ? p_15.10.31 hysteresis of test input voltage v test,hys ? 0.12 x v cc1 ?v 3) p_15.10.32 pull-down resistance at pin test r test 2.5 5 10 k ? v test = 0.2 x v cc1 p_15.10.33 test input filter time t rf ?64?s 2) p_15.10.34 table 22 electrical characteristics (cont?d) v s = 5.5 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol values unit note / test condition number min. typ. max.
TLE9266QX supervision functions data sheet 82 rev. 1.1, 2014-02-01 over temperature shutdown 3) thermal pre-warning on temperature t jpw 125 145 165 c 3) p_15.10.35 thermal shutdown tsd1 t jtsd1 165 185 200 c 3) p_15.10.36 thermal shutdown tsd2 t jtsd2 165 185 200 c 3) p_15.10.37 deactivation time after thermal shutdown tsd2 t tsd2 ?1?s 2) p_15.10.38 1) the reset delay time will start when vcc1 crosses above the selected vrtx threshold 2) not subject to production test, tolerance defined by internal oscillator tolerance. 3) not subject to production test; specified by design. table 22 electrical characteristics (cont?d) v s = 5.5 v to 28 v; t j = -40 c to +150 c; sbc normal mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. parameter symbol values unit note / test condition number min. typ. max.
data sheet 83 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface 16 serial peripheral interface 16.1 spi description the 16-bit wide control input word is read via the data in put sdi, which is synchroniz ed with the clock input clk provided by the microcontroller. the output word appears synchronous ly at the data output sdo (see figure 34 ). the transmission cycle begins when the chip is selected by the input csn (chip select not), low active. after the csn input returns from low to high, the word that has been read is interpreted according to the content. the sdo output switches to tri-state status (high impe dance) at this point, thereby releasing the sdo bus for other use. the state of sdi is shifted into the i nput register with every fa lling edge on clk. the stat e of sdo is shifted out of the output register after every rising edge on cl k. the spi of the sbc is not daisy chain capable. figure 34 spi data transfer timing (note the reversed order of lsb and msb shown in this figure compared to the register description) 0 0 + 1 2 3 4 5 6 7 8 9 10 15 1 + 0 1 2 3 4 5 6 11 12 13 14 7 8 9 10 15 csn high to low: sdo is enabled (low impedance ). status information transferred to output shift register csn low to high: sdo is disabled. data from shift register is transferred to output functions sdi: will accept data on the falling edge of clk signal sdo: will change state on the rising edge of clk signal actual status 11 12 13 14 actual data new data new status sdo sdi csn clk time time time time err err - 0 + 1 + csn high to low: sdo is enabled. status information transferred to output shift register min. csn high -time to be ensured error flag
TLE9266QX serial peripheral interface data sheet 84 rev. 1.1, 2014-02-01 16.2 failure signalization in the spi data output when the microcontroller sends a wrong spi command, then the sbc ignores the information. in case of invalid spi commands the diagnosis bit ? spi_fail ? is set and the complete spi writ e command is ignored (no partial interpretation). the bit can be only reset by actively clearing this bit via spi command. invalid spi commands leading to the spi_fail bit being set are listed below: ? illegal state transitions: - going from sbc stop- to sbc sleep mode. in this case the sbc enters in addition the sbc restart mode; - attempt to go directly from sbc init mode to sbc stop- or sleep mode with the first spi command. sbc normal mode will be entered instead; ? attempting to change the watchdog settings, pwm settings and hs/ls configuration se ttings or to write to any other control registers during sbc stop mode; only wd triggering, returning to sbc normal mode , and read & clear commands are valid spi commands in sbc stop mode. ? attempt to go to sbc sleep mode when no wake sources are set (i.e.all bits in the bus_ctrl and wk_ctrl_2 registers are cleared). in this case the spi_fail bit is set and the sbc enters sbc restart mode. note: at least one wake source must be activated in order to avoid a deadlock situation in sbc sleep mode, i.e. the sbc would not be able to wake up anymore. no signalization or failure handling is done for the attempt to go to sbc stop mode when all bits in the registers bus_ctrl and wk_ctrl_2 are cleared because the microcontroller can leave this mode via spi. ? when trying to enter sbc sleep mode: if the only wake source is cyclic sense with a timer and this timer is off, then the sbc will imme diately enter restart mode ? attempt to enter sbc sleep mode if wk_meas is set to ?1? and wk1_en or wk2_en are set as the only wake sources. also in this case the spi_fail bit is set and the sbc enters sbc restart mode. ? trying to turn on ls1..2 during a long open window. ? setting a longer or equal on-time than th e timer period of the respective timer. ? enabling wk4 as a wake source when sync is selected. ? trying to select sync for the on - or off time of ti mer1...2 while wk4_sync = '0' will generate a spi_fail and the spi write command is ignored. signalization of the err flag (high active) in the spi data output (see figure 34 ): in addition, the number of received i nput clocks is supervised to be 0- or 16 clock cycles and the input / control word is discarded in case of a mismatch. the error lo gic also recognizes if clk was high during csn edges. both errors - 0 bit and 16 bit clk mismatch or clk high during csn edges - are flagged in the following spi output by a high at the data output (sdo pin, bit err) before the first rising edge of the clock is received. note: after exiting sbc fail-safe mode, the err flag might no t be set correctly due to the failure condition. in this case the flag should be ignored. note: it is possible to quickly check for the err flag without sending any data bits. i.e. only the csn is pulled low and sdo is observed - no spi clocks are sent in this case
data sheet 85 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface 16.3 spi programming for the TLE9266QX, 7 bits are used for the address sele ction (bit6...0). bit 7 is used to decide between read only and read & clear for the status bits, and betw een write and read only for configuration bits. for the actual configuration and status inform ation, 8 data bits (bit15...8) are used. writing, clearing and reading is done byte wise. the sp i status bits are not cleared automatically and must be cleared by the microcontrolle r, e.g. if the tsd2 was se t due to over temp erature. the configuration bits will be partially automatically cleared by th e sbc - please refer to the individu al register description for detailed information. during sbc restart mode the spi communicati on is ignored by the sbc, i. e. it is no t interpreted. for the status registers , the requested information is given in the same spi command in do. for the control registers , also the status of the respective bit is sh own in the same spi command, but if the setting is changed this is only shown with the next spi command (it is only valid after csn high). the status information is given with ea ch spi command e.g. watchdog trigger in the status information field. each bit shows if there is a status information set to 1 in one of the status register bits. the register wk_lvl_stat is not included in the status info rmation field. this is listed in table 23 . for example if bit 0 in the status information field is set to 1, one or more bits of the register 100001 ( sup_stat ) is set to 1. then this register needs to be read in a seco nd spi command. the bit in th e status register will be set to 0 when all bits in the register 100001 are set back to 0 (see also figure 35 ) table 23 status information field bit in status information field corresponding address bit status register description 0 100 0001 sup_stat : supply status -vs fa il, vccx fail, por 1 100 0010 therm_stat : thermal protection status 2 100 0011 dev_stat : device status - mode before wake, wd fail, spi fail, failure 3 100 0100 bus_stat : bus failure status: can, lin, 4 100 0110 wk_stat : wake source status 5 101 0010 ls_oc_ot_stat : low-side over load status 6 101 0100 hs_oc_ot_stat : high-side over load status 7 101 0101 hs_ol_stat : high-side open load status
TLE9266QX serial peripheral interface data sheet 86 rev. 1.1, 2014-02-01 figure 35 spi operation mode (note the reversed order of lsb and msb shown in this figure) 16.4 spi bit mapping , figure 36 show the mapping of the registers and , figure 37 show the spi bits of the respective registers. the control registers ?000 0001? to ?001 1110? are read/write re gister. depending on bit 7 the bits are only read (setting bit 7 to ?0?) or also written (setting bit 7 to ?1?). the new setting of the bit after write can be seen with a new read / write command. the registers ?100 0001? to ?111 1110? are status registers and can be read or read with clearing the bit (if possible) depending on bit 7. to clear a data byte of on e of the status registers bit 7 must be set to 1. the registers wk_lvl_stat , fam_prod_stat , are an exception as they show the actual voltage level at the respective wk pin (low/high), or a fixed family/pr oduct id respectively and can thus not be cleared. when changing to a different sbc mode, certain configur ations bits will be cleared automatically: ? the sbc mode bits are updated to the actual status, e.g. when returning to sbc normal mode ? when changing to a low-power mode (stop/sleep), the di agnosis bits of the switches and transceivers are not cleared. ? the lsx outputs will be swit ched off when going from sbc normal to sbc sleep- or sbc stop mode and will not turn on automatically when going back to sbc normal mode. the same applies when going into sbc fail- safe mode or sbc restart mode. ? hsx will stay on when going to sbc sleep-/stop mode (configuration can only be done in sbc normal mode). diagnosis is active (oc, ol, ot). in case of a failu re the switch is turned off and no wake-up is issued ? the configuration bits for hsx and vcc2 are cleared in sbc restart mode 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 data bits di address bits x x x x x x x x r/w 0 1 2 3 4 5 7 6 8 9 10 11 12 13 15 14 data bits do status information field x x x x x x x x register content of selected address lsb msb time lsb is sent first in spi message
data sheet 87 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface figure 36 TLE9266QX spi register mapping 0 0 0 0 0 1 0 hw_ctrl 15 14 13 12 11 10 8 9 7 6 5 4 3 2 0 1 7 address bits [bits 6...0] for register selection 8 data bits [bits 15...8] for configuration & status information spi_register_mapping_tle9266.vsd lsb msb 0 0 0 0 0 0 1 m_s_ctrl reg. type rw 0 0 0 0 0 1 1 wd_ctrl rw 0 0 0 0 1 0 0 bus_ctrl rw 0 0 0 0 1 1 0 wk_ctrl_1 rw 0 0 0 1 0 0 0 wk_pupd_ctrl rw 0 0 0 1 0 0 1 wk_flt_ctrl rw 0 0 0 1 1 0 0 timer1_ctrl rw 0 0 1 0 0 0 0 sw_sd_ctrl rw 0 0 1 0 0 1 0 ls_ctrl rw 0 0 1 0 1 0 0 hs_ctrl_1 rw 0 0 1 0 1 0 1 hs_ctrl_2 rw 0 0 1 1 0 0 0 pwm1_ctrl rw 0 0 1 1 0 0 1 pwm2_ctrl rw 0 0 1 1 0 1 0 pwm3_ctrl rw 0 0 1 1 0 1 1 pwm4_ctrl rw control registers status registers 1 0 0 0 0 0 1 sup_stat rc 1 0 0 0 0 1 0 therm_stat rc 1 0 0 0 0 1 1 dev_stat rc 1 0 0 0 1 0 0 bus_stat rc 1 0 0 0 1 1 0 wk_stat rc 1 0 0 1 0 0 0 wk_lvl_stat r 1 0 1 0 0 1 0 ls_oc_ot _stat rc 1 0 1 0 1 0 0 hs_oc_ot_stat rc 1 0 1 0 1 0 1 hs_ol_stat rc 0 0 1 0 1 1 0 hs_ctrl_3 rw 0 0 0 1 1 0 1 timer2_ctrl rw 0 0 0 0 1 1 1 wk_ctrl_2 rw rw 0 0 1 1 1 0 0 pwm_freq_ctrl rw 1 1 1 1 1 1 0 fam_prod_stat r 0 0 1 1 1 1 0 sys_stat_ctrl rw
TLE9266QX serial peripheral interface data sheet 88 rev. 1.1, 2014-02-01 figure 37 tle9266 spi bit mapping
data sheet 89 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface 16.5 spi control registers read-/write operation (see chapter 16.3 ): ? the ?por / soft reset valu e? defines the register content after por or sbc reset. ? the ?restart value? defines the register content after sbc restart mode, where ?x? means the bit is unchanged. ? spi control bits are in general not cleared or changed automatically. this must be done by the microcontroller via spi. programming. exceptions to this behavior are st ated at the respective register description and the respective bit type is marked with a ?h? meaning that the sbc is able to change the register content. ? reading a register is done byte wise by setting the spi bit 7 to ?0? (= read only). ? writing to a register is done byte wise by setting the spi bit 7 to ?1?. 16.5.1 general control registers note: trying to enter sbc sleep mode wi thout any of the wake sources enabl ed will result in entering sbc restart mode and triggering a reset. note: after entering sbc restart mode, the mode bits will be automatically set to sbc normal mode. the vcc2_on bits will be automatically set to off after entering sbc restart mode and after oc/ot. note: it is not possible to change from stop to sleep m ode via spi command. see also the state machine chapter m_s_ctrl mode- and supply control (address 000 0001 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 00xx b 76543210 mode_1 mode_0 reserved vcc2_on_1 vcc2_on_0 reserved vcc1_rt_1 vcc1_rt_0 r rwh rwh r rwh rwh r rw rw field bits type description mode 7:6 rwh sbc mode control 00 b sbc normal mode (default value) 01 b sbc sleep mode 10 b sbc stop mode 11 b sbc reset: soft reset is exec uted (ro is not triggered) reserved 5r reserved, always reads as 0 vcc2_on 4:3 rwh vcc2 mode control 00 b vcc2 off 01 b vcc2 on in normal mode 10 b vcc2 on in normal and stop mode 11 b vcc2 always on (incl. sleep mode) reserved 2r reserved, always reads as 0 vcc1_rt 1:0 rw vcc1 reset threshold control 00 b vrt1 selected (highest threshold - default value) 01 b vrt2 selected 10 b vrt3 selected 11 b vrt4 selected
TLE9266QX serial peripheral interface data sheet 90 rev. 1.1, 2014-02-01 note: the bit is cleared by the sbc after sbc restart mode. clearing the bi t via spi or via sbc restart mode will not disable the fo ou tput, if the failure condition is still present. see also chapter 14 for fo activation and deactivation. hw_ctrl mode- and supply control (address 000 0010 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 0000 b 76543210 reserved reserved fo_on reserved reserved reserved reserved reserved r rrrwhrrrrr field bits type description reserved 7:6 r reserved, always reads as 0 fo_on 5rwh failure output activation 0 b fo not activated by software, fo can be activated by defined failures 1 b fo activated by software (via spi) reserved 4:0 r reserved, always reads as 0
data sheet 91 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface note: the watchdog is only deactivated in sbc stop mo de when following sequence is ensured: 1.) set bit wd_stm_ en_1 in the register wk_ctrl_1 to ?1?; 2.) set bit wd_stm_ en_0 in the register wd_ctrl to ?1? with the next watchdog trigger. if the sequence is not ensured or the watchdog is triggered when the wd is off, then the wd will not be stopped or will be enabled again re spectively. when returning to sbc normal mode, the bits wd_stm_en_x are cleared. see also chapter 15.2.3 . note: see chapter 15.2.4 for more information on the effect of the bit wd_en_wk_bus. wd_ctrl window watchdog control (address 000 0011 b ) por / soft reset value: 0001 0000 b ; restart value: 000x 0xxx b 76543210 reserved wd_stm_ en_0 reserved wd_en_ wk_bus reserved wd_timer_2 wd_timer_1 wd_timer_0 r r rwh r rw r rw rw rw field bits type description reserved 7r reserved, always reads as 0 wd_stm_ en_0 6rwh watchdog activation during stop mode 0 b watchdog is active in stop mo de as long as ivcc1 > iwd_off 1 b watchdog is deactivated in sbc stop mode reserved 5r reserved, always reads as 0 wd_en_ wk_bus 4rwh watchdog enable after bus (can/lin) wake in sbc stop mode 0 b watchdog will not start after a can/lin wake 1 b watchdog starts with a long open window after can/lin wake reserved 3r reserved, always reads as 0 wd_timer 2:0 rw window watchdog timer period 000 b 10ms (por and restart value) 001 b 20ms 010 b 50ms 011 b 100ms 100 b 200ms 101 b 500ms 110 b 1000ms 111 b reserved
TLE9266QX serial peripheral interface data sheet 92 rev. 1.1, 2014-02-01 note: changes in the bits lin_flash and lin_lsm will be effective immediately once csn goes to ?1?.? note: the reset values for the lin and can transceivers are marked with ?y? because they will vary depending on the cause of change - see below. note: in case either can or lin transceivers are configured to ?11? or ?10? while going to sbc sleep mode, they will be automatically set to wake ca pable (?01?). if configured to ?11? when going to sbc stop mode they will be automatically set to wake capable. the spi bits will be changed to wake capable . if configured to ?10? when going to sbc stop mode they will be stay in receive only mode. if they had been configured to wake capable or off then th e mode will remain unch anged.the receive only mode has to be selected by the user before entering sbc stop mode. note: behavior after sbc restart mode: if the transceivers had been configured to normal mode, or receive only mode, or wake capable then the mo de will be changed to wake capabl e or respectively remain wake capable. if they had been o ff before sbc restart mode, then they will remain off. bus_ctrl bus control (address 000 0100 b ) por / soft reset value: 0010 0000 b ; restart value: xxxy y0yy b 76543210 lin_flash lin_lsm lin_txd_to lin_1 lin_0 reserved can_1 can_0 r rw rw rw rwh rwh r rwh rwh field bits type description lin_flash 7rw lin flash programming mode 0 b slope control mechanism active 1 b deactivation of slope contro l for baud rates up to 115kbaud lin_lsm 6rw lin low-slope mode selection 0 b lin normal-mode is activated 1 b lin low-slope mode (10.4kbaud) activated lin_txd_ to 5rw lin txd time-out control 0 b txd time-out feature disabled 1 b txd time-out feature enabled (default value) lin 4:3 rwh lin-module mode 00 b lin off 01 b lin is wake capable 10 b lin receive only mode 11 b lin normal mode reserved 2r reserved, always reads as 0 can 1:0 rwh hs-can module modes 00 b can off 01 b can is wake capable 10 b can receive only mode 11 b can normal mode
data sheet 93 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface note: the watchdog is only deactivated in sbc stop mo de when following sequence is ensured: 1.) set bit wd_stm_ en_1 in the register wk_ctrl_1 to ?1?; 2.) set bit wd_stm_ en_0 in the register wd_ctrl to ?1? with the next watchdog trigger. if the sequence is not ensured or the watchdog is triggered when the wd is off, then the wd will not be stopped or will be enabled again re spectively. when returning to sbc normal mode, the bits wd_stm_en_x are cleared. see also chapter 15.2.3. note: failure handling mechanism: wh en the device goes to sbc fail-safe mode due to a failure (tsd2, wd- failure,...), then the wake registers bus_ctrl and wk_ctrl_2 are reset to following values (=wake sources) ?0000 1001? and ?000x 0111? in order to ensure that the device can be woken again. the selection for wk4_sync is unchanged in this case. note: an interrupt will be trigge red in sbc stop mode if wd_stm_ wk_en is set and if the current on vcc1 crosses above the i wd_off threshold. even though the bit wd_stm_ wk_en is set, an interrupt will only be triggered if the bits ?wd_stm_en_x? are set to ?0?. wk_ctrl_1 internal wake input control (address 000 0110 b ) por / soft reset value: 0000 1000 b ; restart value: xx00 x000 b 76543210 timer2_wk_ en timer1_wk_ en reserved reserved wd_stm_wk _en wd_stm_ en_1 reserved reserved r rw rw r r rw rwh r r field bits type description timer2_wk _en 7rw timer2 wake source control 0 b timer2 wake disabled 1 b timer2 is enabled as a wake source timer1_wk _en 6rw timer1 wake source control 0 b timer1 wake disabled 1 b timer1 is enabled as a wake source reserved 5:4 r reserved, always reads as 0 wd_stm_ wk_en 3rw watchdog activation interrupt in stop mode 0 b watchdog wake via int in sbc stop mode disabled 1 b watchdog wake via int in stop mode is enabled (default value) wd_stm_ en_1 2rwh watchdog activation during sbc stop mode 0 b watchdog is active in stop mo de as long as ivcc1 > iwd_off 1 b watchdog is deactivated in sbc stop mode reserved 1:0 r reserved, always reads as 0
TLE9266QX serial peripheral interface data sheet 94 rev. 1.1, 2014-02-01 note: wk_meas is by defa ult configured for standard wk functionality (wk1 and wk2) , i.e. the bits wk1_en and wk2_en are ignored in this case. if the bit is set to ?1? then the measurement function is enabled during sbc normal mode. note: wk4 is the default select ion. this means it has priority over the sync settings. note: the wake sources lin and can are selected in the register bus_ctrl by setting the respective bits to ?wake capable? note: failure handling mechanism: wh en the device goes to sbc fail-safe mode due to a failure (tsd2, wd- failure,...), then the wake regi sters bus_ctrl and wk_ctrl_2 are reset to following values (=wake sources) ?0000 1001? and ?000x 0111? in order to ensu re that the device can be woken again. the selection for wk4_sync is unchanged in this case. wk_ctrl_2 external wake source control (address 000 0111 b ) por / soft reset value: 0000 0111 b ; restart value: 00xx xxxx b 76543210 reserved reserved wk_meas wk4_sync wk4_en wk3_en wk2_en wk1_en r r r rw rw rw rw rw rw field bits type description reserved 7:6 r reserved, always reads as 0 wk_meas 5rw wk / measurement selection 0 b wk functionality enabled for wk1 and wk2 1 b measurement functionality enabled; wk1 & wk2 are disable as wake sources, i.e. bits wk1/2_en bits are ignored wk4_sync 4rw wk4 / sync selection 0 b wk4 active (default value) 1 b sync active wk4_en 3rw wk4 wake source control 0 b wk4 wake disabled (default value) 1 b wk4 is enabled as a wake source wk3_en 2rw wk3 wake source control 0 b wk3 wake disabled 1 b wk3 is enabled as a wake source (default value) wk2_en 1rw wk2 wake source control 0 b wk2 wake disabled 1 b wk2 is enabled as a wake source (default value) wk1_en 0rw wk1 wake source control 0 b wk1 wake disabled 1 b wk1 is enabled as a wake source (default value)
data sheet 95 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface note: if wk4 is used as sync, the settings from r egister wk_pu_pd_ctrl for wk4 are ignored and the pull- down configuration is used to avoid uninte ntional activation of a hs by sync. the configurations pull-up/down or automatic switching are not available for wk4 in sbc sleep mode. see also chapter 12.2.1 . wk_pupd_ctrl wake input level control (address 000 1000 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 wk4_pupd_1 wk4_pupd_0 wk3_pupd_1 wk3_pupd_0 wk2_pupd_1 wk2_pupd_0 wk1_pupd_1 wk1_pupd_0 r rw rw rw rw rw rw rw rw field bits type description wk4_pupd 7:6 rw wk4 pull-up / pull-do wn configuration 00 b no pull-up / pull-down selected 01 b pull-down resistor selected 10 b pull-up resistor selected 11 b automatic switching to pull-up or pull-down wk3_pupd 5:4 rw wk3 pull-up / pull-do wn configuration 00 b no pull-up / pull-down selected 01 b pull-down resistor selected 10 b pull-up resistor selected 11 b automatic switching to pull-up or pull-down wk2_pupd 3:2 rw wk2 pull-up / pull-do wn configuration 00 b no pull-up / pull-down selected 01 b pull-down resistor selected 10 b pull-up resistor selected 11 b automatic switching to pull-up or pull-down wk1_pupd 1:0 rw wk1 pull-up / pull-do wn configuration 00 b no pull-up / pull-down selected 01 b pull-down resistor selected 10 b pull-up resistor selected 11 b automatic switching to pull-up or pull-down
TLE9266QX serial peripheral interface data sheet 96 rev. 1.1, 2014-02-01 note: when selecting a filter time configuration, the user mu st make sure to also assign the respective timer to at least one hs switch during cyclic sense operation wk_flt_ctrl wake input filter time control (address 000 1001 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 wk4_flt_1 wk4_flt_0 wk3_flt_1 wk3_flt_0 wk2_flt_1 wk2_flt_0 wk1_flt_1 wk1_flt_0 r rw rw rw rw rw rw rw rw field bits type description wk4_flt 7:6 rw wk4 filtering time configuration 00 b configuration a: filter with 16s filter time (static sensing) 01 b configuration b: filter with 64 s filter time (static sensing) 10 b configuration c: filter is enable d after a settle time defined by timer on-time and a filter time of 16s (cyclic sensing), timer1 11 b configuration d: filter is enabled after a settle time defined by timer on-time and a filter time of 16s (cyclic sensing), timer2 wk3_flt 5:4 rw wk3 filtering time configuration 00 b configuration a: filter with 16s filter time (static sensing) 01 b configuration b: filter with 64 s filter time (static sensing) 10 b configuration c: filter is enable d after a settle time defined by timer on-time and a filter time of 16s (cyclic sensing), timer1 11 b configuration d: filter is enable d after a settle time defined by timer on-time and a filter time of 16s (cyclic sensing), timer2 wk2_flt 3:2 rw wk2 filtering time configuration 00 b configuration a: filter with 16s filter time (static sensing) 01 b configuration b: filter with 64 s filter time (static sensing) 10 b configuration c: filter is enable d after a settle time defined by timer on-time and a filter time of 16s (cyclic sensing), timer1 11 b configuration d: filter is enable d after a settle time defined by timer on-time and a filter time of 16s (cyclic sensing), timer2 wk1_flt 1:0 rw wk1 filtering time configuration 00 b configuration a: filter with 16s filter time (static sensing) 01 b configuration b: filter with 64 s filter time (static sensing) 10 b configuration c: filter is enable d after a settle time defined by timer on-time and a filter time of 16s (cyclic sensing), timer1 11 b configuration d: filter is enabled after a settle time defined by timer on-time and a filter time of 16s (cyclic sensing), timer2
data sheet 97 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface note: for cyclic wake or cyclic sense, a timer must be first assigned and is then automatically activated as soon as the on-time is configured. note: if cyclic sense is selected and the hs switches are cleared during sbc restart mode, then also the timer settings (period and on-time) are cleared to avoid incorrect switch detection. timer1_ctrl timer1 control and selection (address 000 1100 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 0000 b 76543210 reserved timer1_ on_2 timer1_ on_1 timer1_ on_0 reserved timer1_ per_2 timer1_ per_1 timer1_ per_0 r r rwh rwh rwh r rwh rwh rwh field bits type description reserved 7r reserved, always reads as 0 timer1_ on 6:4 rwh timer1 on-time configuration 000 b off / low (timer not running, hsx output is low) 001 b 0.1ms on-time / 0.08ms settle time 010 b 0.3ms on-time / 0.27ms settle time 011 b 1.0ms on-time / 0.8ms settle time 100 b 10ms on-time / 0.8ms settle time 101 b 20ms on-time / 0.8ms settle time 110 b off / high (timer not ru nning, hsx output is high) 111 b sync controlled --> off (cyclic sense / cyclic wake end), 0.08ms settle time reserved 3r reserved, always reads as 0 timer1_ per 2:0 rwh timer1 period configuration 000 b 10ms 001 b 20ms 010 b 50ms 011 b 100ms 100 b 200ms 101 b 1s 110 b 2s 111 b sync controlled --> on (cyclic sense / cyclic wake start)
TLE9266QX serial peripheral interface data sheet 98 rev. 1.1, 2014-02-01 note: for cyclic wake or cyclic sense, a timer must be first assigned and is then automatically activated as soon as the on-time is configured. note: if cyclic sense is selected and the hs switches are cleared during sbc restart mode, then also the timer settings (period and on-time) are cleared to avoid incorrect switch detection. timer2_ctrl timer2 control and selection (address 000 1101 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 0000 b 76543210 reserved timer2_ on_2 timer2_ on_1 timer2_ on_0 reserved timer2_ per_2 timer2_ per_1 timer2_ per_0 r r rwh rwh rwh r rwh rwh rwh field bits type description reserved 7r reserved, always reads as 0 timer2_ on 6:4 rwh timer2 on-time configuration 000 b off / low (timer not running, hsx output is low) 001 b 0.1ms on-time / 0.08ms settle time 010 b 0.3ms on-time / 0.27ms settle time 011 b 1.0ms on-time / 0.8ms settle time 100 b 10ms on-time / 0.8ms settle time 101 b 20ms on-time / 0.8ms settle time 110 b off / high (timer not ru nning, hsx output is high) 111 b sync controlled --> off (cyclic sense / cyclic wake end), 0.08ms settle time reserved 3r reserved, always reads as 0 timer2_ per 2:0 rwh timer2 period configuration 000 b 10ms 001 b 20ms 010 b 50ms 011 b 100ms 100 b 200ms 101 b 1s 110 b 2s 111 b sync controlled --> on (cyclic sense / cyclic wake start)
data sheet 99 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface sw_sd_ctrl switch shutdown control (address 001 0000 b ) por / soft reset value: 0000 0000 b ; restart value: 0xxx 0xxx b 76543210 reserved hs_ov_sd _en hs_uv _sd_en hs_ov_uv _rec reserved ls_ov _sd_en ls_uv _sd_en ls_ov_uv _rec r r rw rw rw r rw rw rw field bits type description reserved 7r reserved, always reads as 0 hs_ov _sd_en 6rw shutdown disabling of hs1...6 in case of vs ov 0 b shutdown enabled in case of vs ov 1 b shutdown disabled in case of vs ov hs_uv _sd_en 5rw shutdown disabling of hs1...6 in case of vs uv 0 b shutdown enabled in case of vs uv 1 b shutdown disabled in case of vs uv hs_ov_uv _rec 4rw switch recovery after remo val of vs ov/uv for hs1...6 0 b switch recovery is disabled 1 b previous state before vs ov/uv is enabled after ov/uv condition is removed reserved 3r reserved, always reads as 0 ls_ov _sd_en 2rw shutdown disabling of ls1...2 in case of vs ov 0 b shutdown enabled in case of vs ov 1 b shutdown disabled in case of vs ov ls_uv _sd_en 1rw shutdown disabling of ls1...2 in case of vs uv 0 b shutdown enabled in case of vs uv 1 b shutdown disabled in case of vs uv ls_ov_uv _rec 0rw switch recovery after remo val of vs ov/uv for ls1...2 0 b switch recovery is disabled 1 b previous state before vs ov/uv is enabled after ov/uv condition is removed
TLE9266QX serial peripheral interface data sheet 100 rev. 1.1, 2014-02-01 note: the bits for the switches are also reset in case of overcurrent and overtemperature. note: the switches will also stay off and the respective spi bits are clear ed for tsd2 and for vs_ov or vs_uv unless the respective recovery bit is set.in addition, th e lsx bits are cleared as soon as sbc normal mode is left. the bits cannot be set if th e watchdog timer is in a long open window. ls_ctrl low-side switch control (address 001 0010 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 0000 b 76543210 reserved reserved reserved reserved reserved reserved ls2 ls1 r rrrrrrrwhrwh field bits type description reserved 7:2 r reserved, always reads as 0 ls2 1rwh ls2 control 0 b ls2 output is ?off? 1 b ls2 output is switched on ls1 0rwh ls1 control 0 b ls1 output is ?off? 1 b ls1 output is switched on
data sheet 101 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface note: the bits hs1_sel and hs2_sel also reconfigure the r ds_on of hs1/2 to achieve the respective over current and open load settings selection, i. e. the switch is configured with the higher r ds_on (p_8.3.13) when the lower thresholds for open-load (p_8.3.10) and over current (p_8.3.7) are needed and vice versa. note: the bits for the switches are also reset in case of overcurrent and overtemperature as well as for under/over voltage in case the switch recovery bit is not set. hs_ctrl1 high-side switch control 1 (address 001 0100 b ) por / soft reset value: 0000 0000 b ; restart value: x000 x000 b 76543210 hs2_sel hs2_2 hs2_1 hs2_0 hs1_sel hs1_2 hs1_1 hs1_0 r rw rwh rwh rwh rw rwh rwh rwh field bits type description hs2_sel 7rw hs2 open load & over current detection configuration 0 b small open load detection threshold (0.4ma - 4ma) and small over current threshold are selected 1 b large open load detection threshold (6ma - 13ma) and large over current threshold are selected hs2 6:4 rwh hs2 configuration 000 b off 001 b on 010 b controlled by timer1 / sync 011 b controlled by timer2 / sync 100 b controlled by pwm1 101 b controlled by pwm2 110 b controlled by pwm3 111 b controlled by pwm4 hs1_sel 3rw hs1 open load & over curr ent detection configuration 0 b small open load detection threshold (0.4ma - 4ma) and small over current threshold are selected 1 b large open load detection threshold (6ma - 13ma) and large over current threshold are selected hs1 2:0 rwh hs1 configuration 000 b off 001 b on 010 b controlled by timer1 / sync 011 b controlled by timer2 / sync 100 b controlled by pwm1 101 b controlled by pwm2 110 b controlled by pwm3 111 b controlled by pwm4
TLE9266QX serial peripheral interface data sheet 102 rev. 1.1, 2014-02-01 note: the bits for the switches are also reset in case of overcurrent and overtemperature as well as for under/over voltage in case the switch recovery bit is not set. hs_ctrl2 high-side switch control 2 (address 001 0101 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 0000 b 76543210 reserved hs4_2 hs4_1 hs4_0 reserved hs3_2 hs3_1 hs3_0 r r rwh rwh rwh r rwh rwh rwh field bits type description reserved 7r reserved, always reads as 0 hs4 6:4 rwh hs4 configuration 000 b off 001 b on 010 b controlled by timer1 / sync 011 b controlled by timer2 / sync 100 b controlled by pwm1 101 b controlled by pwm2 110 b controlled by pwm3 111 b controlled by pwm4 reserved 3r reserved, always reads as 0 hs3 2:0 rwh hs3 configuration 000 b off 001 b on 010 b controlled by timer1 / sync 011 b controlled by timer2 / sync 100 b controlled by pwm1 101 b controlled by pwm2 110 b controlled by pwm3 111 b controlled by pwm4
data sheet 103 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface note: the bits for the switches are also reset in case of overcurrent and overtemperature as well as for under/over voltage in case the switch recovery bit is not set. hs_ctrl3 high-side switch control 3 (address 001 0110 b ) por / soft reset value: 0000 0000 b ; restart value: 0000 0000 b 76543210 reserved hs6_2 hs6_1 hs6_0 reserved hs5_2 hs5_1 hs5_0 r r rwh rwh rwh r rwh rwh rwh field bits type description reserved 7r reserved, always reads as 0 hs6 6:4 rwh hs6 configuration 000 b off 001 b on 010 b controlled bytimer1 / sync 011 b controlled by timer2 / sync 100 b controlled by pwm1 101 b controlled by pwm2 110 b controlled by pwm3 111 b controlled by pwm4 reserved 3r reserved, always reads as 0 hs5 2:0 rwh hs5 configuration 000 b off 001 b on 010 b controlled bytimer1 / sync 011 b controlled by timer2 / sync 100 b controlled by pwm1 101 b controlled by pwm2 110 b controlled by pwm3 111 b controlled by pwm4
TLE9266QX serial peripheral interface data sheet 104 rev. 1.1, 2014-02-01 note: the min. on-time during pwm is lim ited by the actual ton and toff time of the respective hs switch, e.g. the pwm setting ?000 0001? could not be realized. note: the min. on-time during pwm is lim ited by the actual ton and toff time of the respective hs switch, e.g. the pwm setting ?000 0001? could not be realized. pwm1_ctrl pwm1 configuration control (address 001 1000 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 pwm1_dc_7 pwm1_dc_6 pwm1_dc_5 pwm1_dc_4 pwm1_dc_3 pwm1_dc_2 pwm1_dc_1 pwm1_dc_0 r rw rw rw rw rw rw rw rw field bits type description pwm1_dc 7:0 rw pwm1 duty cycle (bit0=lsb; bit7=msb) 0000 0000 b 100% off xxxx xxxx b x% on 1111 1111 b 100% on pwm2_ctrl pwm2 configuration control (address 001 1001 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 pwm2_dc_7 pwm2_dc_6 pwm2_dc_5 pwm2_dc_4 pwm2_dc_3 pwm2_dc_2 pwm2_dc_1 pwm2_dc_0 r rw rw rw rw rw rw rw rw field bits type description pwm2_dc 7:0 rw pwm2 duty cycle (bit0=lsb; bit7=msb) 0000 0000 b 100% off xxxx xxxx b x% on 1111 1111 b 100% on
data sheet 105 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface note: the min. on-time during pwm is lim ited by the actual ton and toff time of the respective hs switch, e.g. the pwm setting ?000 0001? could not be realized. note: the min. on-time during pwm is lim ited by the actual ton and toff time of the respective hs switch, e.g. the pwm setting ?000 0001? could not be realized. pwm3_ctrl pwm3 configuration control (address 001 1010 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 pwm3_dc_7 pwm3_dc_6 pwm3_dc_5 pwm3_dc_4 pwm3_dc_3 pwm3_dc_2 pwm3_dc_1 pwm3_dc_0 r rw rw rw rw rw rw rw rw field bits type description pwm3_dc 7:0 rw pwm3 duty cycle (bit0=lsb; bit7=msb) 0000 0000 b 100% off xxxx xxxx b x% on 1111 1111 b 100% on pwm4_ctrl pwm4 configuration control (address 001 1011 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 pwm4_dc_7 pwm4_dc_6 pwm4_dc_5 pwm4_dc_4 pwm4_dc_3 pwm4_dc_2 pwm4_dc_1 pwm4_dc_0 r rw rw rw rw rw rw rw rw field bits type description pwm4_dc 7:0 rw pwm4 duty cycle (bit0=lsb; bit7=msb) 0000 0000 b 100% off xxxx xxxx b x% on 1111 1111 b 100% on
TLE9266QX serial peripheral interface data sheet 106 rev. 1.1, 2014-02-01 note: this byte is intended for storing system configurations of the ecu by the microcontroller and is only accessible in sbc normal mode. the byte is not acce ssible by the sbc and is also not cleared after sbc fail-safe- or sbc restart mode. it allows the microcontro ller to quickly store sys tem configuration without loosing the data. the data is stored as long as the sbc is supplied and no por was issued. pwm_freq_ctrl pwm frequency configuration control (address 001 1100 b ) por / soft reset value: 0000 0000 b ; restart value: 0x0x 0x0x b 76543210 reserved pwm4_freq reserved pwm3_freq reserved pwm2_freq reserved pwm1_freq r rrwrrwrrwrrw field bits type description reserved 7r reserved, always reads as 0 pwm4_ freq 6rw pwm4 frequency selection 0 b 150hz configuration 1 b 300hz configuration reserved 5r reserved, always reads as 0 pwm3_ freq 4rw pwm3 frequency selection 0 b 150hz configuration 1 b 300hz configuration reserved 3r reserved, always reads as 0 pwm2_ freq 2rw pwm2 frequency selection 0 b 150hz configuration 1 b 300hz configuration reserved 1r reserved, always reads as 0 pwm1_ freq 0rw pwm1 frequency selection 0 b 150hz configuration 1 b 300hz configuration sys_status_ctrl system status control (address 001 1110 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 sys_stat_7 sys_stat_6 sys_stat_5 sys_stat_4 sys_stat_3 sys_stat_2 sys_stat_1 sys_stat_0 r rw rw rw rw rw rw rw rw field bits type description sys_stat 7:0 rw system status control byte (bit0=lsb; bit7=msb) dedicated byte for system co nfiguration, access only by microcontroller
data sheet 107 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface 16.6 spi status information registers read-/write operation (see chapter 16.3 ): ? reading a register is done byte wise by setting the spi bit 7 to ?0? (= read only) ? clearing a register is done byte wise by setting the spi bit 7 to ?1? ? spi status registers are not cleared or changed auto matically. this must be done by the microcontroller via spi command 16.6.1 general status registers note: during sbc sleep mode, the bits vcc1_sc, vcc1 _fail, and vcc1_uv will not be set when vcc1 is off sup_stat supply voltage fail status (address 100 0001 b ) por / soft reset value: 1000 0000 b ; restart value: xxxx xxxx b 76543210 por vs_uv vs_ov vcc2_sc_ot vcc2_fail vcc1_sc vcc1_fail vcc1_uv r rc rc rc rc rc rc rc rc field bits type description por 7rc power-on reset detection 0 b no por 1 b por occurred vs_uv 6rc vs under-voltage detection 0 b no vs-uv 1 b vs-uv detected vs_ov 5rc vs over-voltage detection 0 b no vs-ov 1 b vs-ov detected vcc2_sc _ot 4rc vcc2 short to gnd (<2v for t>4ms after switch on) or over temperature detection 0 b no short, no over temperature 1 b vcc2 short to gnd or over temperature detected vcc2_fail 3rc vcc2 failure detection (<2v for t>2s, any time) 0 b no vcc2 fail 1 b vcc2 fail detected vcc1_sc 2rc vcc1 short to gnd detection (<2v for t>4ms after switch on) 0 b no short 1 b vcc1 short to gnd detected vcc1_fail 1rc vcc1 failure detection (<2v for t>2s, any time) 0 b no vcc1 fail 1 b vcc1 fail detected vcc1_uv 0rc vcc1 uv-detection (due to v rtx reset) 0 b no vcc1 uv detection 1 b vcc1 uv-fail detected
TLE9266QX serial peripheral interface data sheet 108 rev. 1.1, 2014-02-01 note: the default value of the por bit is set after power-o n reset. however it will be cl eared after a sbc soft reset command. note: tsd1 and tsd2 are not reset automatically, even if the temperature pre warning or tsd1 ot condition is not present anymore. also tsd2 is not reset after 7xts d2 to signal to the microcontroller that the device was in fail-safe m ode. it must be cleared by the microcontroller or it will be changed if a new tsd2 event occurs again. then the tsd2 register will show ?001?. tsd2 is only reset if <7x tsd2 events occurred within one minute. see also chapter 5.1.6 therm_stat thermal protection status (address 100 0010 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 reserved reserved reserved tsd2_2 tsd2_1 tsd2_0 tsd1 tpw r r r r rcrcrcrcrc field bits type description reserved 7:5 r reserved, always reads as 0 tsd2 4:2 rc number of tsd2 thermal shut-down events which caused a restart 000 b no tsd2 event 001 b 1xtsd2 event, which caused a restart xxx b .... 111 b 7xtsd2 event (within 1 minute), leading to sbc fail-safe mode tsd1 1rc thermal shut-down detection tsd1 threshold 0 b no tsd1 fail 1 b tsd1 ot detected tpw 0rc thermal pre warning 0 b no thermal pre warning 1 b thermal pre warning detected
data sheet 109 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface note: the bits dev_stat show the status of the device before it went through rest art. either the device came from regular sbc sleep mode or a failure (wd fail, tsd2 fail, vcc_uv fail) occurr ed (where it could have also have been sent to sleep and then to restart). note: the spi_fail bit is cleared only by spi command note: the wd_fail counter is increased whenever a watc hdog failure occurred. the counter is reset after a successful trigger or when software development is reached, i.e. test = 1; wd_fail register will show ?15? to signal that sbc fail-safe mode was reached due to 15x watchdog failure. also wd_fail is not reset automatically to signal the watchdog failure and that the fail-safe mode was entered after15x wd_fail. see also chapter 5.1.6 . the wd_fail register is cl eared by a correct watchdog trigger or can be cleared by spi. dev_stat device information status (address 100 0011 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 dev_stat_1 dev_stat_0 wd_fail_3 wd_fail _2 wd_fail_1 wd_fail_0 spi_fail failure r rc rc rc rc rc rc rc rc field bits type description dev_stat 7:6 rc device status before sbc restart mode 00 b cleared (register must be actively cleared) 01 b restart due to failure (w d fail, tsd2, vcc1_uv); also after a wake from sbc fail-safe mode; also due to illegal command from stop to sleep or normal to sleep if no wake source is activated; 10 b sbc sleep mode; also if wake sources were still not cleared when going to sbc sleep mode; 11 b reserved wd_fail 5:2 rc number of wd-fail events (max. 15 allowed before sbc fail-safe mode is entered) 0000 b no wd fail 0001 b 1x wd fail xxx1 b .... 1111 b 15 wd fails, causing sbc to enter sbc fail-safe mode spi_fail 1rc spi fail information 0 b no spi fail 1 b invalid spi command detected failure 0rc activation of fail output fo 0 b no failure 1 b failure occurred
TLE9266QX serial peripheral interface data sheet 110 rev. 1.1, 2014-02-01 note: vcan_uv comparator is enabled in sbc norma l mode if can_1 = ?1?. note: application hint fo r can receive only mode : when the sbc is changed from sbc normal to stop mode and back to normal while the can is in receive only mode, then the vcan_uv bit will be set unintentionally even if no vcan-uv condition is present. clearing of the bit before setting the can to normal mo de is recommended to ensure that no uv occurred. bus_stat bus communication status (address 100 0100 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 reserved lin_fail_1 lin_fail_0 reserved reserved can_fail_1 can_fail_0 vcan_uv r rrcrcr rrcrcrc field bits type description reserved 7r reserved, always reads as 0 lin_fail 6:5 rc lin failure status 00 b no error 01 b lin tsd shutdown 10 b lin_txd_dom: txd dominant time out for more than 20ms 11 b lin_bus_dom: bus dominant time out for more than 20ms reserved 4:3 r reserved, always reads as 0 can_fail 2:1 rc can failure status 00 b no error 01 b can tsd shutdown 10 b can_txd_dom: txd dominant ti me out for more than 20ms 11 b can_bus_dom: bus dominant time out for more than 20ms vcan_uv 0rc under voltage can bus supply 0 b normal operation 1 b can supply under voltage detected. transmitter disabled
data sheet 111 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface note: wd_st_wu is set and signalled as a wake-up event as soon as the load current on vcc1 has exceeded the i wd_off threshold. then the watchdog is started with a long open window if the watchdog was not disabled before going to sbc stop mode. the wake-up event signalization can be disabled by clearing the bit wd_stm_ wk_en . wk_stat wake-up source and information status (address 100 0110 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 wd_stm_wu lin_wu can_wu timer_wu wk4_wu wk3_wu wk2_wu wk1_wu r rw rc rc rc rc rc rc rc field bits type description wd_stm _wu 7rc watch-dog wake up during sbc stop mode 0 b no wake up 1 b wake up lin_wu 6rc wake up via lin bus 0 b no wake up 1 b wake up can_wu 5rc wake up via can bus 0 b no wake up 1 b wake up timer_wu 4rc wake up via timerx 0 b no wake up 1 b wake up wk4_wu 3rc wake up via wk4 0 b no wake up 1 b wake up wk3_wu 2rc wake up via wk3 0 b no wake up 1 b wake up wk2_wu 1rc wake up via wk2 0 b no wake up 1 b wake up wk1_wu 0rc wake up via wk1 0 b no wake up 1 b wake up
TLE9266QX serial peripheral interface data sheet 112 rev. 1.1, 2014-02-01 note: in cyclic sense or cyclic wake mode, the registers contain the sampled level, i.e. the registers are updated after every sampling. note: at the moment the sync function is conf igured then the level of wk4 is stored. wk_lvl_stat wk input level (address 100 1000 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 test_lvl reserved reserved reserved wk4_lvl wk3_lvl wk2_lvl wk1_lvl r rrrrrrrr field bits type description test_lvl 7r status of test pin 0 b low level (=0) 1 b high level (=1) reserved 6:4 r reserved, always reads as 0 wk4_lvl 3r status of wk4 0 b low level (=0) 1 b high level (=1) wk3_lvl 2r status of wk3 0 b low level (=0) 1 b high level (=1) wk2_lvl 1r status of wk2 0 b low level (=0) 1 b high level (=1) wk1_lvl 0r status of wk1 0 b low level (=0) 1 b high level (=1)
data sheet 113 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface note: both ls switches will be shut do wn and both bits will be set in case of an over temper ature even t of one switch. ls_oc_ot_stat low-side switch overload status (address 101 0010 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 reserved reserved reserved reserved reserved reserved ls2_oc_ot ls1_oc_ot r rrrrrrrcrc field bits type description reserved 7:2 r reserved, always reads as 0 ls2_oc_ ot 1rc over-current & over-temperature detection ls2 0 b no oc 1 b oc detected ls1_oc_ ot 0rc over-current & over-temperature detection ls1 0 b no oc 1 b oc detected hs_oc_ot_stat high-side switch overload status (address 101 0100 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 reserved reserved hs6_oc_ot hs5_oc_ot hs4_oc_ot hs3_oc_ot hs2_oc_ot hs1_oc_ot r r r rc rc rc rc rc rc field bits type description reserved 7:6 r reserved, always reads as 0 hs6_oc_ot 5rc over-current & over-temperature detection hs6 0 b no oc or ot 1 b oc or ot detected hs5_oc_ot 4rc over-current & over-temperature detection hs5 0 b no oc or ot 1 b oc or ot detected hs4_oc_ot 3rc over-current & over-temperature detection hs4 0 b no oc or ot 1 b oc or ot detected hs3_oc_ot 2rc over-current & over-temperature detection hs3 0 b no oc or ot 1 b oc or ot detected hs2_oc_ot 1rc over-current & over-temperature detection hs2 0 b no oc or ot 1 b oc or ot detected
TLE9266QX serial peripheral interface data sheet 114 rev. 1.1, 2014-02-01 note: all hs switches will be shut down and all bits will be set in case of an over temper ature event of one switch. hs1_oc_ot 0rc over-current & over-temperature detection hs1 0 b no oc or ot 1 b oc or ot detected hs_ol_stat high-side switch open-load status (address 101 0101 b ) por / soft reset value: 0000 0000 b ; restart value: xxxx xxxx b 76543210 reserved reserved hs6_ol hs5_ol hs4_ol hs3_ol hs2_ol hs1_ol r r r rc rc rc rc rc rc field bits type description reserved 7:6 r reserved, always reads as 0 hs6_ol 5rc open-load detection hs6 0 b no ol 1 b ol detected hs5_ol 4rc open-load detection hs5 0 b no ol 1 b ol detected hs4_ol 3rc open-load detection hs4 0 b no ol 1 b ol detected hs3_ol 2rc open-load detection hs3 0 b no ol 1 b ol detected hs2_ol 1rc open-load detection hs2 0 b no ol 1 b ol detected hs1_ol 0rc open-load detection hs1 0 b no ol 1 b ol detected field bits type description
data sheet 115 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface 16.6.2 family and produc t information register note: the actual default register va lue after por, soft reset or restar t of prod will depend on the respective product. therefore the value ?y? is specified. fam_prod_stat swk data0 register (address 111 1110 b ) por / soft reset value: 0001 yyyy b ; restart value: 0001 yyyy b 76543210 fam_3 fam_2 fam_1 fam_0 pr od_3 prod_2 prod_1 prod_0 r rrrrrrrr field bits type description fam 7:4 r sbc family identifier (bit4=lsb; bit7=msb) 0 0 0 1 b driver sbc family prod 3:0 r sbc product identifier (bit0=lsb; bit3=msb) 0 0 1 0 b tle9266 0 0 1 1 b tle9266-2 (inverted low-side functionality) 0 1 0 0 b tle9267 (selective wake feature = swk) 0 1 0 1 b tle9267-2 (swk, inverted low-side functionality)
TLE9266QX serial peripheral interface data sheet 116 rev. 1.1, 2014-02-01 16.7 electrical characteristics table 24 electrical characteristics: power stage v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. spi frequency maximum spi frequency f spi,max ??4.0mhz 1) p_16.7.1 spi interface; logic inputs sdi, clk and csn h-input voltage threshold v ih ? ? 0.7* v cc1 v ? p_16.7.2 l-input voltage threshold v il 0.3* v cc1 ? ? v ? p_16.7.3 hysteresis of input voltage v ihy ?0.12* v cc1 ?v 1) p_16.7.4 pull-up resistance at pin csn r icsn 20 40 80 k ? v csn = 0.7 x v cc1 p_16.7.5 pull-down resistance at pin sdi and clk r iclk/sdi 20 40 80 k ? v sdi/clk = 0.2 x v cc1 p_16.7.6 input capacitance at pin csn, sdi or clk c i ?10?pf 1) p_16.7.7 logic output sdo h-output voltage level v sdoh v cc1 - 0.4 v cc1 - 0.2 ?v i doh = -1.6 ma p_16.7.8 l-output voltage level v sdol ?0.20.4v i dol = 1.6 ma p_16.7.9 tri-state leakage current i sdolk -10 ? 10 a v csn = v cc1 ; 0 v < v do < v cc1 p_16.7.10 tri-state input capacitance c sdo ?1015pf 1) p_16.7.11 data input timing 1) clock period t pclk 250 ? ? ns ? p_16.7.12 clock high time t clkh 125 ? ? ns ? p_16.7.13 clock low time t clkl 125 ? ? ns ? p_16.7.14 clock low before csn low t bef 125 ? ? ns ? p_16.7.15 csn setup time t lead 250 ? ? ns ? p_16.7.16 clk setup time t lag 250 ? ? ns ? p_16.7.17 clock low after csn high t beh 125 ? ? ns ? p_16.7.18 sdi set-up time t disu 100 ? ? ns ? p_16.7.19 sdi hold time t diho 50 ? ? ns ? p_16.7.20 input signal rise time at pin sdi, clk and csn t rin ? ? 50 ns ? p_16.7.21 input signal fall time at pin sdi, clk and csn t fin ? ? 50 ns ? p_16.7.22 delay time for mode changes 2) t del,mode ??4s? p_16.7.23
data sheet 117 rev. 1.1, 2014-02-01 TLE9266QX serial peripheral interface figure 38 spi timing diagram note: numbers in drawing correlate to the last 2 digits of the number field in the elec trical characteristics table. minimum csn high time t csn(high) 3??s? p_16.7.24 data output timing 1) sdo rise time t rsdo ?3080ns c l = 100 pf p_16.7.25 sdo fall time t fsdo ?3080ns c l = 100 pf p_16.7.26 sdo enable time t ensdo ? ? 50 ns low impedance p_16.7.27 sdo disable time t dissdo ? ? 50 ns high impedance p_16.7.28 sdo valid time t vasdo ??50ns c l = 100 pf p_16.7.29 1) not subject to production test; specified by design 2) applies to all mode changes triggered via spi commands. no t subject to production test; tolerance defined by internal oscillator tolerance table 24 electrical characteristics: power stage (cont?d) v s = 5.5 v to 28 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. csn clk sdi sdo 14 13 not defined lsb msb flag lsb msb 16 27 29 19 17 28 24 20 15 18
TLE9266QX application information data sheet 118 rev. 1.1, 2014-02-01 17 application information 17.1 application diagram note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 39 simplified application diagram c 1 c 2 d 3 r 1 c 6 vs lin s 3 vbat c 9 r 2 canh c 8 r 3 canl r 5 v ss v dd csn clk sdi sdo c txd lin rxd lin txd can rxd can int csn clk sdo sdi txd lin rxd lin txd can rxd can fo vc c 1 c 4 v cc 1 c 5 wk1 hs1 vs reset int ro vcan gnd q1 v cc gnd ic1 v s logic state machine v s t1 c 3 canh canl can cell vbat vbat vs tle9266/67 v s vcc2 wk4 / sync sync v cc 2 q2 lin lin cell ls 1 ls 2 v s hs2 hs3 v s hs4 v s hs5 v s hs6 lh c 7 v cc 2 m wk3 wk2 r 4 s 2 r 6 s 1 r 9 r 7 r 8 hall1 hall2 q1 q2 q1 q2 d 1 d 2 c 12 r 10 d 4 other loads , e. g. sensor , opamp , ... v s c 11 r 11 d 5 c 14 c 10 c 13
data sheet 119 rev. 1.1, 2014-02-01 TLE9266QX application information note: this is a very simplified example of an application ci rcuit and bill of material. the function must be verified in the actual application. table 25 bill of material for figure 39 ref. typical value purpose / comment capacitances c1 68f buffering capacitor to cut off battery spikes, depending on application c2 100nf emc, blocking capacitor c3 10f low esr as required by app lication, min. 470nf for stability c4 10f low esr as required by app lication, min. 470nf for stability c5 100nf ceramic spike filterin g, improve stability of supply c6 1nf / oem dependent lin master termination c7 100nf emc improvement, blocking capacitor c8 4.7nf / oem dependent sp lit termination stability c9 10nf as required by applicatio n, for off-board connections c10 47pf as required by application, mandatory for off-board connections; place close to pin c11 47pf as required by application, mandatory for off-board connections; place close to pin c12 33nf as required by application, mandatory for off-board connections, especially when used in high-ohmic configurat ion or for hs3...6; place close to connector c13 33nf as required by application, mandatory for off-board connections, especially when used in high-ohmic configurat ion or for hs3...6; place close to connector c14 47nf as required by application, mandator y for off-board connections, place close to connector resistances r1 1k ? / oem dependent lin master termination (if configured as a lin master) r2 60 ? / oem dependent can bus termination r3 60 ? / oem dependent can bus termination r4 10k ? wetting current of the switch, as required by application r5 10k ? limit the wk pin current, e.g. for iso pulses r6 10k ? limit the wk pin current, e.g. for iso pulses r7 10k ? wetting current of the switch, as required by application r8 10k ? wetting current of the switch, as required by application r9 10k ? limit the wk pin current, e.g. for iso pulses r10 depending on led config. led current limitation, as required by application r11 depending on led config. led current limitation, as required by application relay relay e.g. ftr-p4cn012w1 relay for mo tor control, controlled by ls1/2 active components d1 e.g. bas 3010a reverse polarity protection d2 e.g. bas 3010a reverse polarity protection
TLE9266QX application information data sheet 120 rev. 1.1, 2014-02-01 figure 40 simplified application diagram with the alternate measurement function via wk1 and wk2 note: this is a very simplified example of an applicatio n circuit. the function must be verified in the real application.wk1 must be connected to signal to be measured and wk2 is the output to the microcontroller supervision function. the maximum current into wk 1 must be <500a. the minimum current into wk1 should be >5a to ensure proper operation. d3 e.g. bas70 requested by lin standard; reverse polarity protection of network d4 led as required by application, configure series resistor accordingly d5 led as required by application, configure series resistor accordingly t1 e.g. bcr191w high active fo control c e.g. xc2xxx microcontroller table 25 bill of material for figure 39 (cont?d) ref. typical value purpose / comment c 1 e.g. 470uf c 2 v ss v dd csn clk sdi sdo c txd lin rxd lin txd can rxd can int csn clk sdo sdi txd lin rxd lin txd can rxd can vcc1 c 4 v cc1 c 5 wk1 vs reset int ro gnd v s logic state machine vbat vbat vs tle9266/67 wk4 / sync sync wk2 r 1 adc_x vbat_uc d 1 d 2 e.g.10k c 4 10n vbat_uc r 2 r 3 max. 500ua iso pulse protection s 1 note: max. wk1 input current limited to 500a to ensure accuracy and proper operation ;
data sheet 121 rev. 1.1, 2014-02-01 TLE9266QX application information 17.2 esd and emc tests tests for esd robustness according to iec61000-4-2 ?gun test? (150pf, 330 ? ) have been performed. the results and test condition are available in a te st report. the values for the test are listed in table 26 . emc and esd susceptibility tests accord ing to sae j2962-2 (2010) have been performed. tested by external test house (ul llc, test report nr. 2012-787 & 2013-238) table 26 esd ?gun test? performed test r esult unit remarks esd at pin canh, canl, lin, vs 1) , wk1..3 1) , hsx 1) , vcc2 1) versus gnd 1) esd test ?gun test? is specified with external componen ts for pins vs, wk1..3, hsx and vcc2. see the application diagram in chapter 17.1 for more information. >6 kv 2) positive pulse 2) esd susceptibility ?esd gun? according lin emc 1.3 test s pecification, section 4.3 (iec 61000-4-2). tested by external test house (ibee zwickau, emc test report nr. 02-13-13) esd at pin canh, canl, lin, vs 1) , wk1..3 1) , hsx 1) , vcc2 1) versus gnd < -6 kv 2) negative pulse
TLE9266QX application information data sheet 122 rev. 1.1, 2014-02-01 17.3 thermal behavior of package figure 41 thermal resistance (rth j-a ) vs. cooling area
data sheet 123 rev. 1.1, 2014-02-01 TLE9266QX application information figure 42 board setup board setup is defined according to jesd 51-2,-5,-7. board: 76.2x114.3x1.5m m3 with 2 inner copper layers (35m thick), with thermal via array under the exposed pad contacting the first inner copper layer and 300mm 2 cooling area on the bottom layer (70m). pcb (top view) pcb (bottom view) detail solderarea 1 , 5 mm 1 , 5 mm 70m modelled (traces) 35m, 90% metalization* 35m, 90% metalization* 70m / 5% metalization + cooling area *: means percentual cu metalization on each layer cross section (jedec 1s0p) with cooling area cross section (jedec 2s2p) with cooling area
TLE9266QX package outlines data sheet 124 rev. 1.1, 2014-02-01 18 package outlines figure 43 pg-vqfn-48-31 note: for assembly recommendations please also refer to the documents ?recommendations for board assembly (vqfn and iqfn)? and ?vqfn48 layou t hints? on the infineon website ( www.infineon.com ). green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). 0.9 max. seating plane index marking 0.4 x 45 (0.65) index marking 13 12 24 25 48 1 (5.2) 37 36 7 0. 0.03 1 a 6.8 6.8 0.1 48x 0.08 (0.2) 0.05 max. 1) vertical burr 0.03 max. all sides c 7 0.1 b 11 x 0.5 = 5.5 0.5 0.5 11 x 0.5 = 5.5 0.5 0.07 0.15 0.05 (6) (6) (5.2) 0.23 (0.35) m 0.05 0.10 0.05 48x 0.1 a b c pg-vqfn-48-29, -31-po v01 +0.03 1) for further info rmation on alternative pa ckages, please visit our website: http://www.infineon.com/packages . dimensions in mm
data sheet 125 rev. 1.1, 2014-02-01 TLE9266QX revision history 19 revision history revision date changes rev. 1.1 changes vs. rev 1.0 : v1.1 2014-02-01 - voltage regulators 1 & 2: updated block diagrams figure 10 & figure 12 and corrected axis format of figure 13 ; - high-side switches: updated block diagram figure 14 , added description for the ron configuration to achieve selection of different open- load and over-current thresholds in chapter 8.2 and with footnote 1) in chapter 8.3 (numbering of other footnotes increased sequentially); - low-side switches: updated block diagram figure 15 ; - serial peripheral interface: added note in hs_ctrl_1 register explaining that hsx_sel bit is reconfiguring the r ds_on to achieve selection of respective open- load and over-current threshold; - application information: updated figure 42 showing cooling area of cross section in same color as bottom view; v1.0 2013-07-01 initial release
edition 2014-02-01 published by infineon technologies ag 81726 munich, germany ? 2014 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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