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fedl610q476-02 issue date jul. 31, 2014 ml610q474/ML610Q475/ml610q476 8-bit microcontroller with a built-in lcd driver general description this lsi is a high performance cmos 8-bit microcontroller equipped with an 8-bit cpu nx-u8/100 and integrated with peripheral functions such as the uart, melody driver, analog compartor, and lcd driver. the cpu nx-u8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel processing. additionally, it adopts the low-/high-speed dual clock system, standby mode, and process that prohibits leak current at high temperatures, and is most suitable for battery-driven applications. mtp version can rewrite programs on-board, which can contribute to reduction in product development tat. the flash memory incorporated into this mtp version implements the mask rom-equivalent low-voltage operation (1.25v or higher) and low-power consumption (typically 4.5ua at low-speed operation), enabling volume production by the mtp version. features ? cpu - 8-bit risc cpu (cpu name: nx-u8/100) - instruction system: 16-bit length instruction - instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on - on-chip debug function - minimum instruction execution time 30.5 s (@ 32.768 khz system clock) 2 s (@ 500 khz system clock) 0.5 s (@ 2 mhz system clock) ? internal memory - internal 16kbyte flash memory (8k x 16 bits) (including unusable 1k byte test area) - internal 1kbyte ram (1024 x 8 bits) ? interrupt controller - 1 non-maskable interrupt source: internal source: 1 (watchdog timer) - 22 maskable interrupt sources: internal source: 12 (timer0, timer1, timer 2, timer 3, timer c, timer d, uart0, tbc128hz, tbc32hz, tbc16hz, tbc2hz, analog comparator) external source: 10 (p00, p01, p02, p03, p50, p51, p52, p53, p54, p56) (one interrupt request is generated from p50 to p54, p56 interrupt sources.) ? time base counter - low-speed time base counter x 1 channel frequency compensation (compensation range: approx. -488ppm to +488ppm. compensation accuracy: approx. 0.48ppm) - high-speed time base counter x 1 channel ? watchdog timer - non-maskable interrupt and reset - free running - overflow period: 4 types selectable (125ms, 500ms, 2s, 8s)
fedl610q476-02 ml610q474/ML610Q475/ml610q476 2/28 ? timers - 8 bits x 6 channels [also available is 16-bit x 3 configuration (using timers 0-1, 2-3, or c-d) ] - clock frequency measurement function mode (16-bit configuration using timers 2 and 3 x 1 channel only) - the timer c and timer d are controlled by the external trigger. - the timer c and timer d are used for the one-shot timer mode. ? capture - time base capture x 2 channels (4096 hz to 32 hz) ? uart - txd/rxd 1 channel - bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits - positive logic/negative logic selectable - built-in baud rate generator ? melody driver - scale: 29 types (melody sound frequency: 508 hz to 32.768 khz) - tone length: 63 types - tempo: 15 types - buzzer output mode (4 output modes, 8 frequencies, 16 duty levels) ? analog comparator - operating voltage: v dd =1.8v 3.6v - common mode input voltage: 0.2v vdd 0.2v - input offset voltage: 30mv(max) - interrupt allow edge selection and sampling selection - the rc discharged type a/d convertor is configured with the timers c and d. - the temperature measurement function using built-in temperature sensor. temperature measurement range: -20c to +70c - the reference voltage can be switched between cmpp0, cmpm0, temperature sensor and the internal 0.7v voltage source. ? general-purpose ports - input-only port: 4 channels (including secondary functions) - output-only port ml610q474: 10 channels (including secondary functions) ML610Q475: 6 channels (including secondary functions) ml610q476: 2 channels (including secondary functions) - input/output port: 10 channels (including secondary functions) ? lcd driver - number of segments ml610q474: up to 135 dots (select among 27 segments x 5 commons, 28 segments x 4 commons, 29 segments x 3 commons, and 30 segments x 2 commons) ML610Q475: up to 155 dots (select among 31 segments x 5 commons, 32 segments x 4 commons, 33 segments x 3 commons, and 34 segments x 2 commons) ml610q476: up to 175 dots (select among 35 segments x 5 commons, 36 segments x 4 commons, 37 segments x 3 commons, and 38 segments x 2 commons) - 1/1 to 1/5 duty - 1/2 or 1/3 bias (built-in bias generation circuit) - frame frequency selectable (approx. 64 hz, 73 hz, 85 hz, and 102 hz) - bias voltage multiplying clock selectable (8 types) - lcd drive stop mode, lcd display mode, all lcds on mode, and all lcds off mode selectable
fedl610q476-02 ml610q474/ML610Q475/ml610q476 3/28 ? reset - reset through the reset_n pin - power-on reset generation when powered on - reset by the watchdog timer (wdt) overflow - reset by the low-speed oscillation stop detection (available by a mask option) ? clock - low-speed clock (operation of this lsi is not guaranteed under a condition with no supply of low-speed crystal oscillation clock) crystal oscillation (32.768 khz) - high-speed clock built-in rc oscillation (500 khz, 2 mhz) ? power management - halt mode: suspends the instruction execution by cpu (peripheral circuits are in operating states) - stop mode: stops the low-speed oscillation and high-speed oscillation (operations of cpu and peripheral circuits are stopped.) - high-speed clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) - block control function: completely stops the operation of any function block circuit that is not used (resets registers and stops clock) - when lsclk is selected for system clock, the power consumption can be reduced by using halver circuit. ? guaranteed operation range ? operating temperature: -20c to +70c ? operating voltage: v dd = 1.25v to 3.6v (2.4v to 3.6v used halver circuit) ? product name ? s upported function lcd bias - chip (die) - 1/2 1/3 low-speed oscillation stop detect reset operating temperature product availability ml610q474- wa yes yes available by a mask option is possible -20c to +70c yes ML610Q475- wa yes yes available by a mask option is possible -20c to +70c yes ml610q476- wa yes yes available by a mask option is possible -20c to +70c yes lcd bias -80-pin plastic tqfp - 1/2 1/3 low-speed oscillation stop detect reset operating temperature product availability ml610q474- tb yes yes available by a mask option is possible -20c to +70c - ML610Q475- tb yes yes available by a mask option is possible -20c to +70c - ml610q476- tb yes yes available by a mask option is possible -20c to +70c - xxx: rom code number q: mtp version wa: chip (die) tb: tqfp
fedl610q476-02 ml610q474/ML610Q475/ml610q476 4/28 block diagram block diagram of ml610q474/ML610Q475/ml610q476 * secondary function or tertiary function (*1) select among 27 segments x 5 commons, 28 segments x 4 commons, 29 segments x 3 commons, and 30 segments x 2 commons with the register (*2) select among 31 segments x 5 commons, 32 segments x 4 commons, 33 segments x 3 commons, and 34 segments x 2 commons with the register (*3) select among 35 segments x 5 commons, 36 segments x 4 commons, 37 segments x 3 commons, and 38 segments x 2 commons with the register figure 1 ml610q474/ML610Q475/ml610q476 block diagram program memory (flash) 16kbyte ram 1k byte interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 wdt int 6 8bit timer 6 capture 2 gpio int 5 data-bus test0 reset_n osc xt0 xt1 lsclk* power v ddx lcd driver lcd bias v l1 , v l2 , v l3 c1 , c2 reset & test alu epsw1 ? 3 psw elr1 ? ? ? 15 v pp v dd v ss display register 190bit com0 to com4 ( *1 )( *2 )( *3 ) seg0 to seg29 (ml610q474) (*1) seg0 to seg33 (ML610Q475) (*2) seg0 to seg37 ( ml610q476 ) ( *3 ) p00 to p03 p20 , p21 p42 to p45 p60 to p67 (ml610q474) p60 to p63 (ML610Q475) uart int 1 rxd0* txd0* analog comparator cmpp0* cmpm0* int 1 p50 to p54 , p56 ch1 , ch2 v ddl v hf melody/ buzzer int 1 md0*
fedl610q476-02 ml610q474/ML610Q475/ml610q476 5/28 pin configuration ml610q474 chip pad layout & dimension p00 1 p01 2 p02 3 p03 4 p56 5 p54 6 p44 7 p45 8 v dd 9 v ss 10 v ddl 11 ch1 12 ch2 13 v hf 14 xt0 15 xt1 16 v ddx 17 reset_n 18 test0 19 20 c1 21 c2 22 v l1 23 v l2 24 v l3 25 com0 26 com1 27 com2/seg0 28 com3/seg1 29 com4/seg2 30 seg3 31 seg4 32 seg5 33 seg6 34 seg7 35 seg8 36 seg9 37 seg10 52 seg25 51 seg24 50 seg23 49 seg22 48 seg21 47 seg20 46 seg19 45 seg18 44 seg17 43 seg16 42 seg15 41 seg14 40 seg13 39 seg12 38 seg11 56 seg29 55 seg28 54 seg27 53 seg26 p60 64 p61 63 p62 62 p63 61 p64 60 p65 59 p66 58 p67 57 p20 72 v ss 71 p43 70 p42 69 p50 68 p51 67 p52 66 p53 65 v pp 74 p21 73 2.23mm 2.1mm x y chip size: 2.23mm 2.10mm pad count: 74 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: vss level. figure 5 ml610q474 chip pin layout & dimension
fedl610q476-02 ml610q474/ML610Q475/ml610q476 6/28 ML610Q475 chip pad layout & dimension p00 1 p01 2 p02 3 p03 4 p56 5 p54 6 p44 7 p45 8 v dd 9 v ss 10 v ddl 11 ch1 12 ch2 13 v hf 14 xt0 15 xt1 16 v ddx 17 reset_n 18 test0 19 20 c1 21 c2 22 v l1 23 v l2 24 v l3 25 com0 26 com1 27 com2/seg0 28 com3/seg1 29 com4/seg2 30 seg3 31 seg4 32 seg5 33 seg6 34 seg7 35 seg8 36 seg9 37 seg10 52 seg25 51 seg24 50 seg23 49 seg22 48 seg21 47 seg20 46 seg19 45 seg18 44 seg17 43 seg16 42 seg15 41 seg14 40 seg13 39 seg12 38 seg11 56 seg29 55 seg28 54 seg27 53 seg26 p60 64 p61 63 p62 62 p63 61 seg33 60 seg32 59 seg31 58 seg30 57 p20 72 v ss 71 p43 70 p42 69 p50 68 p51 67 p52 66 p53 65 v pp 74 p21 73 2.23mm 2.1mm x y chip size: 2.23mm 2.10mm pad count: 74 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 6 ML610Q475 chip pin layout & dimension
fedl610q476-02 ml610q474/ML610Q475/ml610q476 7/28 ml610q476 chip pad layout & dimension p00 1 p01 2 p02 3 p03 4 p56 5 p54 6 p44 7 p45 8 v dd 9 v ss 10 v ddl 11 ch1 12 ch2 13 v hf 14 xt0 15 xt1 16 v ddx 17 reset_n 18 test0 19 20 c1 21 c2 22 v l1 23 v l2 24 v l3 25 com0 26 com1 27 com2/seg0 28 com3/seg1 29 com4/seg2 30 seg3 31 seg4 32 seg5 33 seg6 34 seg7 35 seg8 36 seg9 37 seg10 52 seg25 51 seg24 50 seg23 49 seg22 48 seg21 47 seg20 46 seg19 45 seg18 44 seg17 43 seg16 42 seg15 41 seg14 40 seg13 39 seg12 38 seg11 56 seg29 55 seg28 54 seg27 53 seg26 seg37 64 seg36 63 seg35 62 seg34 61 seg33 60 seg32 59 seg31 58 seg30 57 p20 72 v ss 71 p43 70 p42 69 p50 68 p51 67 p52 66 p53 65 v pp 74 p21 73 2.23mm 2.1mm x y chip size: 2.23mm 2.10mm pad count: 74 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 7 ml610q476 chip pin layout & dimension
fedl610q476-02 ml610q474/ML610Q475/ml610q476 8/28 pad coordinates ml610q474/ML610Q475/ml 610q476 pad coordinates table 1 ml610q474/ML610Q475/ml610q476 pad coordinates chip center: x=0,y=0 ml610q474/5/6 ml610q474/5/6 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 1 p00 -705 -944 44 seg17 330 944 2 p01 -625 -944 45 seg18 250 944 3 p02 -545 -944 46 seg19 170 944 4 p03 -465 -944 47 seg20 90 944 5 p56 -385 -944 48 seg21 10 944 6 p54 -305 -944 49 seg22 -70 944 7 p44 -225 -944 50 seg23 -150 944 8 p45 -145 -944 51 seg24 -230 944 9 v dd -65 -944 52 seg25 -310 944 10 v ss 15 -944 53 seg26 -390 944 11 v ddl 95 -944 54 seg27 -470 944 12 ch1 175 -944 55 seg28 -550 944 13 ch2 255 -944 56 seg29 -630 944 14 v hf 335 -944 p67 (*1) 15 xt0 415 -944 57 seg30 (*2) (*3) -1009 835 16 xt1 575 -944 p66 (*1) 17 v ddx 655 -944 58 seg31 (*2) (*3) -1009 755 18 reset_n 735 -944 p65 (*1) 19 test0 815 -944 59 seg32 (*2) (*3) -1009 675 20 c1 1009 -650 p64 (*1) 21 c2 1009 -570 60 seg33 (*2) (*3) -1009 595 22 v l1 1009 -490 p63 (*1) (*2) 23 v l2 1009 -410 61 seg34 (*3) -1009 515 24 v l3 1009 -330 p62 (*1) (*2) 25 com0 1009 -240 62 seg35 (*3) -1009 435 26 com1 1009 -160 p61 (*1) (*2) 27 com2/seg0 1009 -80 63 seg36 (*3) -1009 355 28 com3/seg1 1009 0 p60 (*1) (*2) 29 com4/seg2 1009 80 64 seg37 (*3) -1009 275 30 seg3 1009 160 65 p53 -1009 175 31 seg4 1009 240 66 p52 -1009 95 32 seg5 1009 320 67 p51 -1009 15 33 seg6 1009 400 68 p50 -1009 -65 34 seg7 1009 480 69 p42 -1009 -145 35 seg8 1009 560 70 p43 -1009 -225 36 seg9 1009 640 71 v ss -1009 -305 37 seg10 1009 720 72 p20 -1009 -385 38 seg11 810 944 73 p21 -1009 -465 39 seg12 730 944 74 v pp -1009 -545 40 seg13 650 944 41 seg14 570 944 42 seg15 490 944 43 seg16 410 944 (*1) pad for ml610q474 . (*2) pad for ML610Q475. (*3) pad for ml610q476.
fedl610q476-02 ml610q474/ML610Q475/ml610q476 9/28 pin list primary function secondary function pin no. pad no. pin name i/o function pin name i/o function 11, 76 10,71 vss ? negative power supply pin ? ? ? 10 9 v dd ? positive power supply pin ? ? ? 15 14 v hf ? power supply pin for halver circuit (internally generated) ? ? ? 12 11 v ddl ? power supply pin for internal logic (internally generated) ? ? ? 18 17 v ddx ? power supply pin for low-speed oscillation (internally generated) ? ? ? 79 74 v pp ? power supply pin for flash rom ? ? ? 24 22 v l1 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*1) ? ? ? 25 23 v l2 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*1) ? ? ? 26 24 v l3 ? power supply pin for lcd bias (internally generated) ? ? ? 22 20 c1 ? capacitor connection pin for lcd bias generation ? ? ? 23 21 c2 ? capacitor connection pin for lcd bias generation ? ? ? 13 12 ch1 ? capacitor connection pin for halver circuit ? ? ? 14 13 ch2 ? capacitor connection pin for halver circuit ? ? ? 20 19 test0 i/o test pin ? ? ? 19 18 reset_n i reset input pin ? ? ? 16 15 xt0 i low-speed clock oscillation pin ? ? ? 17 16 xt1 o low-speed clock oscillation pin ? ? ? 2 1 p00/exi0/ cap0/tprun0 i input port, external interrupt, capture 0 input timer c/timer d external trigger input ? ? ? 3 2 p01/exi1/ cap1/tprun1 i input port, external interrupt, capture 1 input timer c/timer d external trigger input ? ? ? 4 3 p02/exi2/ rxd0/tprun2 i input port, external interrupt, uart0 received data timer c/timerd external trigger input ? ? ? 5 4 p03/exi3/ tprun3 i input port, external interrupt timer c/timer d external trigger input ? ? ? 77 72 p20/led0 o output port lsclk o low-speed clock output 78 73 p21/led1 o output port outclk o high-speed clock output 74 69 p42 i/o input/output port rxd0 i uart data input 75 70 p43 i/o input/output port txd0 o uart data output 8 p44/t02dck/ tcdrun i/o input/output port, timer 0/timer 2/timer c external clock input timer c/timer d external trigger input ? ? ? 9 8 p45/t13dck/ tcdrun i/o input/output port, timer 1/timer 3/timer d external clock input timer c/timer d external trigger input ? ? ? 73 68 p50/exi8 i/o input/output port, external interrupt md0 o melody 0 output 72 67 p51/exi8 i/o input/output port, external interrupt ? ? ? 71 66 p52/exi8 i/o input/output port, external interrupt ? ? ? 70 65 p53/exi8 i/o input/output port, external interrupt ? ? ?
fedl610q476-02 ml610q474/ML610Q475/ml610q476 10/28 primary function secondary function pin no. pad no. pin name i/o function pin name i/o function 7 6 p54/exi8/ cmpp0 i/o input/output port, external interrupt analog comparator noninverting input0 pin ? ? ? 6 5 p56/exi8/ cmpm0 i/o input/output port, external interrupt analog comparator inverting input0 pin ? ? ?
fedl610q476-02 ml610q474/ML610Q475/ml610q476 11/28 primary function secondary function pin no. pad no. pin name i/o function pin name i/o function 27 25 com0 o lcd common pin ? ? ? 28 26 com1 o lcd common pin ? ? ? 29 27 com2/seg0 o lcd common/segment pin ? ? ? 30 28 com3/seg1 o lcd common/segment pin ? ? ? 31 29 com4/seg2 o lcd common/segment pin ? ? ? 32 30 seg3 o lcd segment pin ? ? ? 33 31 seg4 o lcd segment pin ? ? ? 34 32 seg5 o lcd segment pin ? ? ? 35 33 seg6 o lcd segment pin ? ? ? 36 34 seg7 o lcd segment pin ? ? ? 37 35 seg8 o lcd segment pin ? ? ? 38 36 seg9 o lcd segment pin ? ? ? 39 37 seg10 o lcd segment pin ? ? ? 41 38 seg11 o lcd segment pin ? ? ? 42 39 seg12 o lcd segment pin ? ? ? 43 40 seg13 o lcd segment pin ? ? ? 44 41 seg14 o lcd segment pin ? ? ? 45 42 seg15 o lcd segment pin ? ? ? 46 43 seg16 o lcd segment pin ? ? ? 47 44 seg17 o lcd segment pin ? ? ? 48 45 seg18 o lcd segment pin ? ? ? 49 46 seg19 o lcd segment pin ? ? ? 50 47 seg20 o lcd segment pin ? ? ? 51 48 seg21 o lcd segment pin ? ? ? 52 49 seg22 o lcd segment pin ? ? ? 53 50 seg23 o lcd segment pin ? ? ? 54 51 seg24 o lcd segment pin ? ? ? 55 52 seg25 o lcd segment pin ? ? ? 56 53 seg26 o lcd segment pin ? ? ? 57 54 seg27 o lcd segment pin ? ? ? 58 55 seg28 o lcd segment pin ? ? ? 59 56 seg29 o lcd segment pin ? ? ? p67(*2) o output port ? ? ? 62 57 seg30(*3) (*4) o lcd segment pin ? ? ? p66(*2) o output port ? ? ? 63 58 seg31(*3) (*4) o lcd segment pin ? ? ? p65(*2) o output port ? ? ? 64 59 seg32(*3) (*4) o lcd segment pin ? ? ? p64(*2) o output port ? ? ? 65 60 seg33(*3) (*4) o lcd segment pin ? ? ? p63(*2) (*3) o output port ? ? ? 66 61 seg34(*4) o lcd segment pin ? ? ? p62(*2) (*3) o output port ? ? ? 67 62 seg35(*4) o lcd segment pin ? ? ? p61(*2) (*3) o output port ? ? ? 68 63 seg36(*4) o lcd segment pin ? ? ? p60(*2) (*3) o output port ? ? ? 69 64 seg37(*4) o lcd segment pin ? ? ? (*1) internally generated, or connect to either positive power supply pin (v dd ) or power supply pin for internal logic (v ddl ). for details, see user?s manual. (*2) pad for ml610q474. (*3) pad for ML610Q475. (*4) pad for ml610q476.
fedl610q476-02 ml610q474/ML610Q475/ml610q476 12/28 pin description pin name i/o description primary/ secondary logic system reset_n i reset input pin. when this pin is set to a ?l? level, system reset mode is set and the internal section is initialized. when this pin is set to a ?h? level subsequently, program execution starts. a pull-up resistor is internally connected. ? negative xt0 i ? ? xt1 o crystal connection pin for low-speed clock. a 32.768 khz crystal resonator is connected to this pin. capacitors c dl and c gl are connected across this pin and v ss . (see appendix c measuring circuit 1) ? ? lsclk o low-speed clock output. assigned to the secondary function of the p20 pin. secondary ? outclk o high-speed clock output pin. this pin is used as the secondary function of the p21 pin. secondary ? general-purpose input port p00 to p03 i general-purpose input port. primary positive general-purpose output port p20, p21 o general-purpose output port. this cannot be used as the general output port when used as the secondary function. primary positive general-purpose input/output port p42 to p45 i/o general-purpose input/output port. this cannot be used as the general input/output port when used as the secondary or tertiary function. primary positive p50 to p54, p56 i/o general-purpose input/output port. this cannot be used as the general input/output port when used as the secondary function. primary positive p60 to p63 o general-purpose output port. incorporated only into ml610q474/ML610Q475, and not into ml610q476. primary positive p64 to p67 o general-purpose output port. incorporated only into ml610q474, and not into ML610Q475/ ml610q476. primary positive
fedl610q476-02 ml610q474/ML610Q475/ml610q476 13/28 pin name i/o description primary/ secondary logic uart txd0 o uart data output pin. this pin is used as the secondary function of the p43 pin. secondary positive rxd0 i uart data input pin. this pin is used as the secondary function of the p42 or the primary function of the p02 pin. primary/ secondary positive external interrupt exi0-3 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the p00 to p03 pins. primary positive/ negative exi8 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. assigned to the primary function of the p50 to p54, p56 pins. primary positive/ negative capture cap0 i primary positive/ negative cap1 i capture trigger input pins. the value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. these pins are used as the primary functions of the p00 pin(cap0) and p01 pin(cap1). primary positive/ negative timer t02ck i external clock input pin used for both timer 0 and timer 2. this pin is used as the primary function of the p44 pin. primary ? t13ck i external clock input pin used for both timer 1 and timer 3. this pin is used as the primary function of the p45 pin. primary ? tcdrun i external trigger input pin used for timer c or timer d. this pin is used as the primary function of the p44 pin or the p45 pin. primary ? tprun0 i external trigger input pin used for timer c or timer d. this pin is used as the primary function of the p00 pin. primary ? tprun1 i external trigger input pin used for timer c or timer d. this pin is used as the primary function of the p01 pin. primary ? tprun2 i external trigger input pin used for timer c or timer d. this pin is used as the primary function of the p02 pin. primary ? tprun3 i external trigger input pin used for timer c or timer d. this pin is used as the primary function of the p03 pin. primary ? led drive led0, led1 o n-channel open drain output pins to drive led. this pin is used as the primary function of the p20 and the p21 pins. primary positive /negative melody md0 o melody/buzzer signal output pin. this pin is used as the secondary function of the p50 pin. secondary positive/ negative
fedl610q476-02 ml610q474/ML610Q475/ml610q476 14/28 pin name i/o description primary/ secondary logic analog comparator cmpp0 i analog comparator noninverting input0 pin. this pin is used as the secondary function of the p54. primary ? cmpm0 i analog comparator inverting input0 pin. this pin is used as the secondary function of the p56. primary ? lcd drive signal com0 to com4 o common output pins. com2, com3, and com4 can be switched to seg0, seg1, and seg2, respectively, through the register setting. to change the setting, switch between com4 and seg2 for one pin and switch between com3, com4 and seg1, seg2 for two pins. ? ? seg0 to seg29 o segment output pin. the seg0, seg1, and seg2 pins are for switching the register setting with the com2, com3, and com4. ? ? seg30 to seg33 o segment output pin. incorporated into ML610Q475/ml610q476, not into ml610q474. ? ? seg34 to seg37 o segment output pin. incorporated into ml610q476, not into ml610q474/ML610Q475. lcd driver power supply v l1 ? ? ? v l2 ? ? ? v l3 ? power supply pin for lcd bias (internally generated) or power supply connection pin. depending on lcd bias setting and v dd voltage level, v dd or v ddl or capacitor is connected. for details of the connection method, see chapter 20, "lcd drivers". ? ? c1 ? ? ? c2 ? power supply pins for lcd bias (internally generated). capacitor c 12 (see appendix c measuring circuit 1) is connected between c1 and c2. ? ?
fedl610q476-02 ml610q474/ML610Q475/ml610q476 15/28 pin name i/o description primary/ secondary logic test test0 i/o pin for testing. a pull-down resistor is internally connected. ? positive power supply v ss ? negative power supply pin. ? ? v dd ? positive power supply pin. ? ? v hf ? positive power supply pin (internally generated) for halver. capacitor c hf (see measuring circuit 1) should be connected between this pin and v ss . ? ? v ddl ? positive power supply pin (internally generated) for internal logic. capacitors c l (see measuring circuit 1) are connected between this pin and v ss . ? ? v ddx ? positive power supply pin (internally generated) for low-speed oscillation. capacitor c x (see measuring circuit 1) should be connected between this pin and v ss . ? ? ch1 ? ? ? ch2 ? capacitor connection pin for halver circuit. capacitor c h12 (see appendix c measuring circuit 1) are connected between ch1 and ch2. ? ? v pp ? power supply pin for programming flash rom. a pull-down resistor is internally connected. ? ?
fedl610q476-02 ml610q474/ML610Q475/ml610q476 16/28 termination of unused pins table 2 shows methods of terminating the unused pins. table 2 termination of unused pins pin recommended pin handling vpp open vl1 open vl2 open vl3 open c1, c2 open reset_n open test0 open p00 to p03 vdd or vss p20, p21 open p42 to p45 open p50 to p54, p56 open p60 to p67 open com0 to com4 open seg0 to seg37 open note: it is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting.
fedl610q476-02 ml610q474/ML610Q475/ml610q476 17/28 electrical characteristics absolute maximum ratings (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta=25c -0.3 to +4.6 v power supply voltage 2 v pp ta=25c -0.3 to +9.5 v power supply voltage 3 v ddl ta=25c -0.3 to +3.6 v power supply voltage 4 v l1 ta=25c -0.3 to +2.0 v power supply voltage 5 v l2 ta=25c -0.3 to +4.0 v power supply voltage 6 v l3 ta=25c -0.3 to +6.0 v input voltage v in ta=25c -0.3 to v dd +0.3 v output voltage v out ta=25c -0.3 to v dd +0.3 v output current 1 i out1 port 3 to 6, ta=25c -12 to +11 ma output current 2 i out2 port 2, ta=25c -12 to +20 ma power dissipation pd ta=25c 0.9 w storage temperature t stg D -55 to +150 c recommended operating conditions (v ss = 0v) parameter symbol condition range unit operating temperature t op D -20 to +70 c f op =30k to 625khz 1.25 to 3.6 f op =30k to 2.5mhz 1.8 to 3.6 operating voltage v dd f op =30k to 36khz, used halver 2.4 to 3.6 v v dd =1.25 to 3.6v 30k to 625k v dd =1.8 to 3.6v 30k to 2.5m operating frequency (cpu) f op v dd =2.4 to 3.6v, used halver 30k to 36k hz low-speed crystal oscillation frequency f xtl D 32.768k hz c dl D 3 to 18 low-speed crystal oscillation external capacitance c gl D 3 to 18 pf v ddl pin external capacitance c l D 0.4730% f v ddx pin external capacitance c x D 0.130% f v hf pin external capacitance c hf D 0.130% f v l1, 2, or 3 pin external capacitance c a,b,c D 0.130% f pin-to-pin (c1 to c2) external capacitance c 12 D 0.4730% f pin-to-pin (ch1 to ch2) external capacitance c h12 D 0.130% f
fedl610q476-02 ml610q474/ML610Q475/ml610q476 18/28 operating conditions of flashrom (vss= 0v) parameter symbol condition range unit operating temperature t op at write/erase 0 to +40 c v dd at write/erase 2.75 to 3.6 v ddl at write/erase *1 2.5 to 2.75 operating voltage v pp at write/erase 7.7 to 8.3 v rewrite count c ep D 80 cycles data retention y dr D 10 years *1 : when writing to and erasing on the flash memory, the voltage in the specified range needs to be supplied to the v ddl pin. the v pp pin has an internal pull-down resistor. operation conditions of comparator (vdd = 1.8 to 3.6v, vss =0v, ta= -20 to +70c, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measurement circuit common-mode input voltage cmv in D 0.2 D v dd ? 0.2 v analog comparator input offset voltage v cmpof ta=25 c -30 D 30 mv analog comparator response time t cmp ta=25 c, overdrive=100mv D D 1 s analog comparator supply current i cmp ta=25 c D 25 45 a analog comparator wakeup time t cmpw D D D 5 ms temperature sensor output voltage through x2 v tmp ta = +25c D 1355 D mv ta = -20 to +25c D -3.585 D temperature sensor output voltage through x2 (temperature property) ? v tmp ta = 25 to 70c D -3.718 D mv/c 0.7v voltage source output voltage through x2 v ref ta=25 c 1.386 1.400 1.414 v 0.7v voltage source temperature deviation ? v ref D D 0 D %/c 0.7v voltage source supply current i ref ta=25 c D 20 40 a 0.7v voltage source wakeup time t refw D D D 1 ms 1/2 vdd voltage source vdd2 D vdd/2x 0.96 vdd/2 vdd/2x 1.04 v 1/4 vdd voltage source vdd4 D vdd/4x 0.945 vdd/4 vdd/4x 1.055 v 1
fedl610q476-02 ml610q474/ML610Q475/ml610q476 19/28 dc characteristics (1/5) (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ta=25c typ. -10% 500 typ. +10% khz v dd =1.25 to 3.6v * 2 typ. -25% 500 typ. +25% khz ta=25 c typ. -10% 2.0 typ. +10% mhz 500khz/2mhz rc oscillation frequency f rc v dd =1.8 to 3.6v * 3 typ. -25% 2.0 typ. +25 % mhz low-speed crystal oscillation start time* 1 t xtl D D 0.6 2 s 500khz/2mhz rc oscillation start time t rc D D D 3 s reset pulse width p rst D 200 D D reset noise elimination pulse width p nrst D D D 0.3 s power-on reset generated power rise time t por D D D 10 ms lcd bias voltage generation time* 3 t bias D D D 100 ms 1 * 1 : 32.768khz crystal resonator dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =12pf). * 2 : recommended operating temperature (ta=-20 to 70c) * 3 : 1/3bias, vl2=vdd. reset t bias bson bit vl3 0 1 0.9x1.5xv dd t bias reset_n reset_n pin reset vdd 0.9xv dd 0.1xv dd t por power on reset p rst vil1 vil1
fedl610q476-02 ml610q474/ML610Q475/ml610q476 20/28 dc characteristics (2/5) (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit fop=30k to 36khz, used halver D 1.15 D fop=30k to 625khz D 1.2 D v ddl voltage v ddl fop=1.5m to 2.5mhz D 1.5 D v v ddl temperature deviation * 1 ? v ddl v dd =3.0v D -1 D mv/c v ddl voltage dependency * 1 ? v ddl D D 5 20 mv/v 1 * 1 : the maximum v ddl voltage becomes the v dd voltage level when the v ddl voltage determined by the temperature and voltage deviations mathematically exceeds the v dd voltage. dc characteristics (3/5) (vdd=3.0v, vss=0v, ta=-20 to +70c unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ta=25 c D 0.32 0.8 supply current 1 idd1 cpu: in stop state. low-speed/high-speed oscillation: stopped. * 5 D D 8 a ta=25 c D 0.25 0.5 supply current 2 idd2 cpu: in halt state. (ltbc, wdt: operating)* 3 * 4 . high-speed 500khz/2mhz oscillation: stopped. lcd/bias circuits: stopped used halver * 5 D D 4 a ta=25 c D 4.5 8 supply current 3-1 idd3-1 cpu: in 32.768khz operating state.* 1 * 3 high-speed 500khz/2mhz oscillation: stopped, lcd/bias circuits: operating * 2 not used halver * 5 D D 15 a ta=25 c D 2.5 4 supply current 3-2 idd3-2 cpu: in 32.768khz operating state.* 1 * 3 high-speed 500khz/2mhz oscillation: stopped, lcd/bias circuits: operating * 2 used halver * 5 D D 7.5 a ta=25 c D 75 100 supply current 4-1 idd4-1 cpu: in 500khz rc operating state. lcd/bias circuits: operating.* 2 not used halver * 5 D D 120 a ta=25 c D 300 350 supply current 4-2 idd4-2 cpu: in 2mhz rc operating state. lcd/bias circuits: operating.* 2 not used halver * 5 D D 400 a 1 * 1 : when the cpu operating rate is 100% (no halt state). * 2 : all segs: off waveform, no lcd panel load, 1/3 bias, 1/3 duty, frame frequency: approx. 64 hz, bias voltage multiplying clock : 1/128 lsclk (256hz) * 3 : 32.768khz crystal resonator dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =6pf) * 4 : significant bits of blkcon0 to blkcon4 registers are all ? 1 ? except dlcd bit on blkcon4 . * 5 : recommended operating temperature (ta=-20 to 70 c) * 6 : lcd stop mode, 1/3 bias, bias voltage multiplying clock: 1/128 lsclk (256hz)
fedl610q476-02 ml610q474/ML610Q475/ml610q476 21/28 dc characteristics (4/5) (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ioh1=-0.5ma, v dd =1.8 to 3.6v v dd -0.5 D D voh1 ioh1=-0.03ma, v dd =1.25 to 3.6v v dd -0.3 D D iol1=+0.5ma, v dd =1.8 to 3.6v D D 0.5 output voltage 1 (p20, p21 (n-channel open drain output mode is not selected)) (p42 to p45) (p50 to p54, p56) (p60 to p63) *2 (p60 to p67) *1 vol1 iol1=+0.1ma, v dd =1.25 to 3.6v D D 0.3 output voltage 2 (p20, p21 (n-channel open drain output mode is selected)) vol2 iol2=+5ma, v dd =1.8 to 3.6v D D 0.5 voh3 ioh3=-0.05ma, vl1=1.2v v l3 -0.2 D D voml3 ioml3=+0.05ma, vl1=1.2v D D v l2 +0.2 voml3s ioml3s=-0.05ma, vl1=1.2v v l2 -0.2 D D volm3 iolm3=+0.05ma, vl1=1.2v D D v l1 +0.2 volm3s iolm3s=-0.05ma, vl1=1.2v v l1 -0.2 D D output voltage 3 (com0 to 4) (seg0 to 29) *1 (seg0 to 33) *2 (seg0 to 37) *3 vol3 iol3=+0.05ma, vl1=1.2v D D 0.2 v 2 iooh voh=v dd (in high-impedance state) D D 1 output leakage (p20, p21) (p42 to p45) (p50 to p54, p56) (p60 to p63) *2 (p60 to p67) *1 iool vol=v ss (in high-impedance state) -1 D D a 3 iih1 vih1=v dd D D 1 input current 1 (reset_n, test1_n) iil1 vil1=v ss -600 -300 -2 iih2 vih2=v dd 2 300 600 input current 2 (test0) iil2 vil2=v ss -1 D D vih3=v dd, v dd =1.8 to 3.6v (when pulled-down) 2 30 200 iih3 vih3=v dd, v dd =1.25 to 3.6v (when pulled-down) 0.01 30 200 vil3=v ss, v dd =1.8 to 3.6v (when pulled-up) -200 -30 -2 iil3 vil3=v ss, v dd =1.25 to 3.6v (when pulled-up) -200 -30 -0.01 iih3z vih3=v dd (in high-impedance state) D D 1 input current 3 (p00 to p03) (p42 to p45) (p50 to p54, p56) iil3z vil3=v ss (in high-impedance state) -1 D D a 4 * 1 : characteristics for ml610q474. * 2 : characteristics for ML610Q475. * 3 : characteristics for ml610q476.
fedl610q476-02 ml610q474/ML610Q475/ml610q476 22/28 dc characteristics (5/5) (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit vih1 D 0.7 v dd D v dd input voltage 1 (reset_n) (test0) (p00 to p03) (p42 to p45) (p50 to p54, p56) vil1 v dd =1.25 to 3.6v 0 D 0.2 v dd v 5 input pin capacitance (p00 to p03) (p42 to p45) (p50 to p54, p56) cin f=10khz v rms =50mv ta=25c D D 5 pf D
fedl610q476-02 ml610q474/ML610Q475/ml610q476 23/28 measuring circuits measuring circuit 1 measuring circuit 2 input pin v v dd v ddl v l1 v l2 v l3 v ss vih vil output pin (note 1) input logic circuit to determine the specified measuring conditions. (note 2) repeats for the specified output pin (note 2) (note 1) v ddx xt0 xt1 a v dd v ddl c l v l1 c a v l2 v l3 c c v ss c2 c1 c 12 c v : 1f c l : 0.47uf cx : 0.15f c a ,c b ,c c : 0.1f c 12 : 0.47f c hf : 0.1f c h12 : 0.1f 32.768khz crystal resonator : dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) c gl , c dl : 6pf c v v ddx c x c h12 ch2 ch1 32.768khz crystal resonator c gl c dl v hf c hf
fedl610q476-02 ml610q474/ML610Q475/ml610q476 24/28 measuring circuit 3 measuring circuit 4 input pin a v dd v ddl v l1 v l2 v l3 v ss output pin (note 3) repeats for the specified input pin (note 3) v ddx input pin a v dd v ddl v l1 v l2 v l3 v ss vih vil output pin (note 1) input logic circuit to determine the specified measuring conditions. (note 2) repeats for the specified output pin (note 2) (note 1) v ddx
fedl610q476-02 ml610q474/ML610Q475/ml610q476 25/28 measuring circuit 5 input pin v dd v ddl v l1 v l2 v l3 v ss vih vil output pin (note 1) input logic circuit to determine the specified measuring conditions. (note 1) waveform observation v ddx
fedl610q476-02 ml610q474/ML610Q475/ml610q476 26/28 ac characteristics (external interrupt) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c unless otherwise specified) rating parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation system clock: 32.768khz 76.8 D 106.8 s ac characteristics (uart) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c unless otherwise specified) rating parameter symbol condition min. typ. max. unit transmit baud rate t tbrt D D brt* 1 D s receive baud rate t rbrt D brt* 1 -3% brt* 1 brt* 1 +3% s * 1 : baud rate period (including the error of the clock frequency selected) set with the uart baud rate register (ua0brtl,h) and the uart mode register 0 (ua0mod0). t rbrt txd0* rxd0* *: indicates the secondary function of the port. t tbrt t nul p00?p07 (rising-edge interrupt) p00?p07 (falling-edge interrupt) p00?p07 (both-edge interrupt) t nul t nul
fedl610q476-02 ml610q474/ML610Q475/ml610q476 27/28 revesion history page document no. date previous edition current edition description fedl610q476-01 jan.11,2013 ? ? final edition 1 fedl610q476-02 jul.31,2014 3,5,6,7, 30 3 delete package products
fedl610q476-02 ml610q474/ML610Q475/ml610q476 28/28 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of application circuits, circuit constants and any othe r information contained herein illustrate the standard usage an d operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circui ts for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accord ance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of h uman injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controlle r or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2013-2014 lapis semiconductor co., ltd. 2-4-8 shinyokohama, kouhoku-ku, yokohama 222-8575, japan http://www.lapis-semi.com/en/

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