cystech electronics corp. spec. no. : c386q8 issued date : 2007.06.08 revised date : 2011.12.07 page no. : 1/8 MTP4411Q8 cystek product specification p-channel enhancement mode power mosfet MTP4411Q8 bv dss -30v i d -5.3a r dson @v gs =-10v, i d =-5.3a 35m (typ) r dson @v gs =-4.5v,i d =-4.2a 56m (typ) description the MTP4411Q8 is a p-channel enhancement-mode mo sfet, providing the designer with the best combination of fast switching, ruggedized device de sign, low on-resistance and cost effectiveness. the sop-8 package is universally preferred for all commercial-industrial surface mount applications and suited for low voltage applicati ons such as dc/dc converters. features ? simple drive requirement ? low on-resistance ? fast switching speed ? pb-free lead plating package equivalent circuit outline ordering information device package shipping marking MTP4411Q8 sop-8 (pb-free lead plating package) 2500 pcs/ tape & reel 4411 MTP4411Q8 sop-8 g gate s source d drain
cystech electronics corp. spec. no. : c386q8 issued date : 2007.06.08 revised date : 2011.12.07 page no. : 2/8 MTP4411Q8 cystek product specification absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source breakdown voltage bv dss -30 v gate-source voltage v gs 20 v continuous drain current (note 1) i d -5.3 a pulsed drain current (note 2) i dm -24 a total power dissipation (note 1) pd 2.5 w linear derating factor 0.02 w / c operating junction temperature tj -55~+150 c storage temperature tstg -55~+150 c thermal resistance, junction-to-ambient (note 1) rth,j-a 50 c/w note : 1.surface mounted on fr-4 board, t 10sec. 2. pulse width 300 s, duty cycle 2% electrical characteristics (tj=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss -30 - - v v gs =0, i d =-250 a v gs(th) -1 -1.5 -2.5 v v ds =v gs , i d =-250 a i gss - - 100 na v gs =20v, v ds =0 i dss - - -1 a v ds =-30v, v gs =0 - 35 40 i d =-5.3a, v gs =-10v *r ds(on) - 56 60 m i d =-4.2a, v gs =-4.5v *g fs - 8 - s v ds =-5v, i d =-5.3a dynamic ciss - 730 - coss - 80 - crss - 68 - pf v ds =-15v, v gs =0, f=1mhz *t d(on) - 9 - *t r - 10 - *t d(off) - 37 - *t f - 23 - ns v dd =-15v, i d =-1a, v gs =-10v, r g =6 , r d =15 *qg - 11.7 - *qgs - 2.1 - *qgd - 2.9 - nc v ds =-15v, v gs =-10v, i d =-5.3a source drain diode *v sd - -0.84 -1.2 v v gs =0v, i s =-1.7a *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c386q8 issued date : 2007.06.08 revised date : 2011.12.07 page no. : 3/8 MTP4411Q8 cystek product specification typical characteristics typical output characteristics 0 2 4 6 8 10 12 14 16 18 20 02468 -vds, drain-source voltage(v) -i d , drain current (a) -10v -9 -8 -7 -4.5v v gs =-3v v gs =-2.5v v gs =-3.5v v gs =-4v brekdown voltage vs ambient temperature 25 30 35 40 -100 -50 0 50 100 150 200 tj, junction temperature(c) -bv dss , drain-source breakdown voltage(v) i d =-250 a, v gs =0v static drain-source on-state resistance vs drain current 10 100 1000 10000 0.001 0.01 0.1 1 10 -i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =-4.5v v gs =-2.5v v gs =-10v source drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 024681 -i s , source drain current(a) -v sd , source-drain voltage(v) 0 v gs =0v tj=25c tj=150c static drain-source on-state resistance vs gate-source voltage 20 60 100 140 180 220 260 300 340 380 420 024681 0 drain-source on-state resistance vs junction tempearture 20 40 60 80 100 -60 -20 20 60 100 140 180 tj, junction temperature(c) r ds( on) , static drain-source on-state resistance(m) v gs =-4.5v, i d =-4.2a v gs =-10v, i d =-5.3a -vgs, gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =-5.3a
cystech electronics corp. spec. no. : c386q8 issued date : 2007.06.08 revised date : 2011.12.07 page no. : 4/8 MTP4411Q8 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 10000 0.1 1 10 100 -v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.8 1 1.2 1.4 1.6 1.8 2 -60 -20 20 60 100 140 tj, junction temperature(c) -v gs( th) , threshold voltage(v) i d =-250 a forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.01 0.1 1 10 100 -i d , drain current(a) g fs , forward transfer admittance(s) v ds =-5v pulsed t a =25c gate charge characteristics 0 2 4 6 8 10 0246810121416 qg, total gate charge(nc) -v gs , gate-source voltage(v) v ds =-15v i d =-5.3a maximum safe operating area 0.01 0.1 1 10 100 0.1 1 10 100 -i d , drain-source voltage(v) -i d , drain current(a) operation in this area is limited by rds(on) dc 10ms 100ms 1ms 100 s 10 s maximum drain current vs junction temperature 0 1 2 3 4 5 6 7 25 50 75 100 125 150 175 tj, junction temperature(c) -i d , maximum drain current(a) t a =25c, v gs =-10v
cystech electronics corp. spec. no. : c386q8 issued date : 2007.06.08 revised date : 2011.12.07 page no. : 5/8 MTP4411Q8 cystek product specification typical characteristics(cont.) transient thermal response curves 0.01 0.1 1 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) z ja (t), normalized effective transient thermal impedance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.z ja (t)=50c/w max. 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *z ja (t)
cystech electronics corp. spec. no. : c386q8 issued date : 2007.06.08 revised date : 2011.12.07 page no. : 6/8 MTP4411Q8 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c386q8 issued date : 2007.06.08 revised date : 2011.12.07 page no. : 7/8 MTP4411Q8 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c386q8 issued date : 2007.06.08 revised date : 2011.12.07 page no. : 8/8 MTP4411Q8 cystek product specification sop-8 dimension *: typical inches millimeters inches millimeters dim min. max. min. max. 8-lead sop-8 plastic package cystek packa g e code: q8 marking: top view a b front view f c d e g part a i h j k o m l n right side view part a date code device name 4411 dim min. max. min. max. a 0.1890 0.2007 4.80 5.10 i 0.0098 ref 0.25 ref b 0.1496 0.1654 3.80 4.20 j 0.0118 0.0354 0.30 0.90 c 0.2283 0.2441 5.80 6.20 k 0.0074 0.0098 0.19 0.25 d 0.0480 0.0519 1.22 1.32 l 0.0145 0.0204 0.37 0.52 e 0.0138 0.0193 0.35 0.49 m 0.0118 0.0197 0.30 0.50 f 0.1472 0.1527 3.74 3.88 n 0.0031 0.0051 0.08 0.13 g 0.0531 0.0689 1.35 1.75 o 0.0000 0.0059 0.00 0.15 h 0.1889 0.2007 4.80 5.10 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance . 3
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