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RT8296B 1 ds8296b-03 march 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pin configurations (top view) applications z external storage device z wireless ap/router z set-top-box z industrial and commercial low power systems z lcd monitors and tvs z green electronics/appliances z point of load regulation of high-performance dsps sop-8 (exposed pad) 3a, 23v, 1.2mhz synchronous step-down converter general description the RT8296B is a high-efficiency, monolithic synchronous step-down dc/dc converter that can deliver up to 3a output current from a 4.5v to 23v input supply. the RT8296B's current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors. cycle-by-cycle current limit provides protection against shorted outputs and soft-start eliminates input current surge during start-up. fault conditions also include output under voltage protection and thermal shutdown protection. the low current (<3 a) shutdown mode provides output disconnection, enabling easy power management in battery-powered systems. the RT8296B is available in an sop-8 (exposed pad) package. features z z z z z 1.5% high accuracy feedback voltage z z z z z 4.5v to 23v input voltage range z z z z z 3a output current z z z z z integrated n-mosfet switches z z z z z current mode control z z z z z fixed frequency operation : 1.2mhz z z z z z adjustable output from 0.8v to 15v z z z z z up to 95% efficiency z z z z z programmable soft-start z z z z z stable with low-esr ceramic output capacitors z z z z z cycle-by-cycle over current protection z z z z z input under voltage lockout z z z z z output under voltage protection z z z z z thermal shutdown protection z z z z z rohs compliant and halogen free boot vin sw gnd ss en fb comp gnd 2 3 4 5 6 7 8 9 marking information RT8296Bxgsp : product number x : h or l ymdnn : date code RT8296Bxzsp : product number x : h or l ymdnn : date code RT8296Bx gspymdnn RT8296Bx zspymdnn RT8296Bxgsp RT8296Bxzsp package type sp : sop-8 (exposed pad-option 1) RT8296B lead plating system g : green (halogen free and pb free) z : eco (ecological element with halogen free and pb free) h : uvp hiccup l : uvp latch-off
RT8296B 2 ds8296b-03 march 2011 www.richtek.com functional pin description pin no. pin name pin function 1 boot bootstrap for high side gate driver. connect a 0.1 m f or greater ceramic capacitor from boot to sw pins. 2 vin input supply voltage, 4.5v to 23v. must bypass with a suitably large ceramic capacitor. 3 sw switch node. connect this pin to an external l-c filter. 4, 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 5 fb feedback input. this pin is connected to the converter output. it is used to set the output of the converter to regulate to the desired value via an internal resistive voltage divider. for an adjustable output, an external resistive voltage divider is connected to this pin. 6 comp compensation node. comp is used to compensate the regulation control loop. connect a series rc network from comp to gnd. in some cases, an additional capacitor from comp to gnd is required. 7 en chip enable (active high). a logic-low forces the RT8296B into shutdown mode reducing the supply current to less than 3 m a. attach this pin to vin with a 100k w pull up resistor for automatic startup. 8 ss soft-start control input. ss controls the soft-start period. connect a capacitor from ss to gnd to set the soft-start period. a 0.1 m f capacitor sets the soft-start period to 13.5ms. typical application circuit v out (v) r1 (k w ) r2 (k w ) r c (k w ) c c (nf) l ( m h) c out ( m f) 8 27 3 51 2.2 10 22 x 2 5 62 11.8 33 2.2 6.8 22 x 2 3.3 75 24 22 2.2 3.6 22 x 2 2.5 25.5 12 16 2.2 3.6 22 x 2 1.5 10.5 12 10 2.2 2 22 x 2 1.2 12 24 8.2 2.2 2 22 x 2 1 3 12 6.8 2.2 2 22 x 2 table 1. recommended component selection vin en gnd boot fb sw 7 5 2 3 1 l 3.6 h 100nf 22 f x 2 r1 75k r2 24k v out 3.3v/3a 10 f x 2 v in 4.5v to 23v RT8296B ss 8 c ss comp c c 2.2nf r c 22k c p open 6 4, 9 (exposed pad) c boot c in 0.1 f c out r en 100k
RT8296B 3 ds8296b-03 march 2011 www.richtek.com function block diagram v a + - + - + - uv comparator oscillator foldback control 0.4v internal regulator + - 2.7v shutdown comparator current sense amplifier boot vin gnd sw fb en comp 3v 5k v a v cc 6 a slope comp current comparator + - ea 0.8v s r q q ss + - 1.2v lockout comparator v cc + 85m w 85m w
RT8296B 4 ds8296b-03 march 2011 www.richtek.com electrical characteristics (v in = 12v, t a = 25 c, unless otherwise specified) absolute maximum ratings (note 1) l supply voltage, v in ----------------------------------------------------------------------------------------------- - 0.3v to 25v l input voltage, sw------------------------------------------------------------------------------------------------- - 0.3v to (v in + 0.3v) l v boot - v sw --------------------------------------------------------------------------------------------------------- - 0.3v to 6v l other pin voltages------------------------------------------------------------------------------------------------ - 0.3v to 6v l power dissipation, p d @ t a = 25 c sop-8 (exposed pad)--------------------------------------------------------------------------------------------1.333w l package thermal resistance (note 2) sop-8 (exposed pad), q ja ---------------------------------------------------------------------------------------75 c/w sop-8 (e xposed pad), q jc --------------------------------------------------------------------------------------15 c/w l lead temperature (soldering, 10 sec.)------------------------------------------------------------------------260 c l junction temperature---------------------------------------------------------------------------------------------150 c l storage temperature range------------------------------------------------------------------------------------- - 65 c to 150 c l esd susceptibility (note 3) hbm (human body mode)---------------------------------------------------------------------------------------2kv mm (machine mode)----------------------------------------------------------------------------------------------200v recommended operating conditions (note 4) l supply voltage, v in -----------------------------------------------------------------------------------------------4.5v to 23v l junction temperature range------------------------------------------------------------------------------------ - 40 c to 125 c l ambient temperature range------------------------------------------------------------------------------------ - 40 c to 85 c parameter symbol test conditions min typ max unit shutdown supply current v en = 0v -- 0.5 3 m a supply current v en = 3v, v fb = 0.9v -- 0.8 1.2 ma feedback voltage v fb 4.5v v in 23v 0.788 0.8 0.812 v error amplifier transconductance g ea d i c = 10 m a -- 940 -- m a/v high side switch on-resistance r ds(on)1 -- 85 -- m w low side switch on-resistance r ds(on)2 -- 85 -- m w high side switch leakage current v en = 0v, v sw = 0v -- 0 10 m a upper switch current limit min. duty cycle, v boot - v sw = 4.8v -- 5.1 -- a comp to current sense transconductance g cs -- 5.4 -- a/v oscillation frequency f osc1 1 1.2 1.4 mhz short circuit oscillation frequency f osc2 v fb = 0v -- 270 -- khz maximum duty cycle d max v fb = 0.7v -- 75 -- % minimum on-time t on -- 100 -- ns to be continued
RT8296B 5 ds8296b-03 march 2011 www.richtek.com parameter symbol test conditions min typ max unit logic-high v ih 2.7 -- 5.5 en input threshold voltage logic-low v il -- -- 0.4 v input under voltage lockout threshold v uvlo v in rising 3.8 4.2 4.5 v input under voltage lockout hysteresis d v uvlo -- 320 -- mv soft-start current i ss v ss = 0v -- 6 -- m a soft-start period t ss c ss = 0.1 m f -- 13.5 -- ms thermal shutdown t sd -- 150 -- c note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. q ja is measured in natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of q jc is on the exposed pad package of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT8296B 6 ds8296b-03 march 2011 www.richtek.com output voltage vs. output current 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.36 0 0.5 1 1.5 2 2.5 3 output current (a) output voltage (v) efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 output current (a) efficiency (%) reference voltage vs. input voltage 0.780 0.785 0.790 0.795 0.800 0.805 0.810 0.815 0.820 4 6 8 10 12 14 16 18 20 22 24 input voltage (v) reference voltage (v) frequency vs. temperature 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -50 -25 0 25 50 75 100 125 temperature ( c) frequency (mhz) 1 typical operating characteristics v in = 12v v out = 3.3v v in = 23v frequency vs. input voltage 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 4 6 8 10 12 14 16 18 20 22 24 input voltage (v) frequency (mhz) 1 v out = 3.3v, i out = 0.5a v out = 3.3v, v in = 12v, i out = 0.5a v in = 12v v in = 23v v out = 3.3v reference voltage vs. temperature 0.780 0.785 0.790 0.795 0.800 0.805 0.810 0.815 0.820 -50 -25 0 25 50 75 100 125 temperature ( c) reference voltage (v)
RT8296B 7 ds8296b-03 march 2011 www.richtek.com output current limit vs. input voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 4 6 8 10 12 14 16 18 20 22 24 input voltage (v) output current limit (a) current limit vs. temperature 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 -50 -25 0 25 50 75 100 125 temprature (c) current limit (a) v in = 12v, v out = 3.3v v out = 1.2v v out = 3.3v (add bootstrap diode) v out = 3.3v v in = 12v load transient response time (100 s/div) v out (50mv/div) i out (1a/div) v in = 12v, v out = 3.3v, i out = 1.5a to 3a load transient response time (100 s/div) v in = 12v, v out = 3.3v, i out = 0.3a to 3a i out (1a/div) v out (50mv/div) switching time (0.5 s/div) v in = 12v, v out = 3.3v, i out = 1.5a i l (2a/div) v out (5mv/div) v sw (10v/div) switching time (0.5 s/div) v in = 12v, v out = 3.3v, i out = 3a v out (5mv/div) v sw (10v/div) i l (2a/div)
RT8296B 8 ds8296b-03 march 2011 www.richtek.com power on from v in time (10ms/div) v in = 12v, v out = 3.3v, i out = 3a i l (2a/div) v out (2v/div) v in (5v/div) power off from vin time (10ms/div) i l (2a/div) v out (2v/div) v in (5v/div) v in = 12v, v out = 3.3v, i out = 3a power on from en time (5ms/div) v out (2v/div) v en (5v/div) i l (2a/div) v in = 12v, v out = 3.3v, i out = 3a power off from en time (10ms/div) v in = 12v, v out = 3.3v, i out = 3a v out (2v/div) v en (5v/div) i l (2a/div)
RT8296B 9 ds8296b-03 march 2011 www.richtek.com application information the RT8296B is a synchronous high voltage buck converter that can support an input voltage range from 4.5v to 23v and the output current can be up to 3a. output voltage setting the resistive voltage divider allows the fb pin to sense the output voltage as shown in figure 1. figure 1. output voltage setting RT8296B gnd fb r1 r2 v out the output voltage is set by an external resistive voltage divider according to the following equation : sw boot 5v RT8296B 100nf ?? + ? ? outfb r1 v = v1 r2 where v fb is the feedback reference voltage (0.8v typ.). external bootstrap diode connect a 100nf low esr ceramic capacitor between the boot pin and sw pin. this capacitor provides the gate driver voltage for the high side mosfet. it is recommended to add an external bootstrap diode between an external 5v and boot pin for efficiency improvement when input voltage is lower than 5.5v or duty cycle is higher than 65% .the bootstrap diode can be a low cost one such as in4148 or bat54. the external 5v can be a 5v fixed input from system or a 5v output of the RT8296B. note that the external boot voltage must be lower than 5.5v. figure 2. external bootstrap diode soft-start the RT8296B contains an external soft-start clamp that gradually raises the output voltage. the soft-start timing can be programmed by the external capacitor between ss pin and gnd. the chip provides a 6 m a charge current for the external capacitor. if 0.1 m f capacitor is used to set the soft-start, the period will be 13.5ms(typ.). chip enable operation the en pin is the chip enable input. pulling the en pin low (<0.4v) will shutdown the device. during shutdown mode, the RT8296B quiescent current will drop below 3 m a. driving the en pin high (>2.7v, < 5.5v) will turn on the device again. for external timing control (e.g.rc), the en pin can also be externally pulled high by adding a r en * resistor and c en * capacitor from the vin pin (see figure 5). an external mosfet can be added to implement digital control on the en pin when no system voltage above 2.5v is available, as shown in figure 3. in this case, a 100 k w pull-up resistor, r en , is connected between v in and the en pin. mosfet q1 will be under logic control to pull down the en pin. vin en gnd boot fb sw 7 5 2 3 1 l r1 r2 v out chip enable v in RT8296B ss 8 c ss comp c c r c c p 6 4, 9 (exposed pad) c boot c out c in r en 100k q1 figure 3. enable control circuit for logic control with low voltage
RT8296B 10 ds8296b-03 march 2011 www.richtek.com to prevent enabling circuit when v in is smaller than the v out target value, a resistive voltage divider can be placed between the input voltage and ground and connected to the en pin to adjust ic lockout threshold, as shown in figure 4. for example, if an 8v output voltage is regulated from a 12v input voltage, the resistor, r en2 , can be selected to set input lockout threshold larger than 8v. vin en gnd boot fb sw 7 5 2 3 1 l r1 r2 v out v in RT8296B ss 8 c ss comp c c r c c p 6 4, 9 (exposed pad) c boot c out c in r en1 100k 8v 10 f r en2 12v figure 4. the resistors can be selected to set ic lockout threshold having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. high frequency with small ripple current can achieve highest efficiency operation. however, it requires a large inductor to achieve this goal. outout l(max)in(max) vv l =1 fiv - d ???? the inductor's current rating (caused a 40 c temperature rising from 25 c ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. please see table 2 for the inductor selection reference. table 2. suggested inductors for typical application circuit component supplier series dimensions (mm) tdk vlf10045 10 x 9.7 x 4.5 tdk slf12565 12.5 x 12.5 x 6.5 taiyo yuden nr8040 8 x 8 x 4 c in and c out selection the input capacitance, c in, is needed to filter the trapezoidal current at the source of the high side mosfet. to prevent large ripple current, a low esr input capacitor sized for the maximum rms current should be used. the rms current is given by : hiccup mode for the RT8296Bh, it provides hiccup mode under voltage protection (uvp) is provided. when the fb voltage drops below half of the feedback reference voltage, v fb , the uvp function will be triggered and the RT8296Bh will shut down for a period of time and then recover automatically. the hiccup mode uvp can reduce input current in short-circuit conditions. latch-off mode for the RT8296Bl, it provides latch-off mode under voltage protection (uvp) is provided. when the fb voltage drops below half of the feedback reference voltage, v fb , the uvp will be triggered and the RT8296Bl will shut down in latch-off mode. in shutdown condition, the RT8296Bl can be reset via the en pin or power input vin. inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and output voltage. the ripple current d i l increases with higher v in and decreases with higher inductance. outout l in vv i =1 flv d- ???? for the ripple current selection, the value of d i l = 0.24(i max ) will be a reasonable starting point. the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation :
RT8296B 11 ds8296b-03 march 2011 www.richtek.com out in rmsout(max) inout v v i = i1 vv - this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for the input capacitor, two 10 m f low esr ceramic capacitors are recommended. for the recommended capacitor, please refer to table 3 for more detail. the selection of c out is determined by the required esr to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for c out selection to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, d v out , is determined by : outl out 1 viesr 8fc dd+ ?? the output ripple will be highest at the maximum input voltage since d i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirement. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr value. however, it provides lower capacitance density than other types. although tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr. however, it can be used in cost-sensitive applications for ripple current rating and long term reliability considerations. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to d i load (esr) and c out also begins to be charged or discharged to generate a feedback error signal for the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. emi consideration since parasitic inductance and capacitance effects in pcb circuitry would cause a spike voltage on the sw pin when high side mosfet is turned-on/off, this spike voltage on sw may impact on emi performance in the system. in order to enhance emi performance, there are two methods to suppress the spike voltage. one way is by placing an r-c snubber between sw and gnd and locating them as close as possible to the sw pin (see figure 5). another method is by adding a resistor in series with the bootstrap capacitor, c boot , but this method will decrease the driving capability to the high side mosfet. it is strongly recommended to reserve the r-c snubber during pcb layout for emi improvement. moreover, reducing the sw trace area and keeping the main power in a small loop will be helpful on emi performance. for detailed pcb layout guide, please refer to the section layout considerations.
RT8296B 12 ds8296b-03 march 2011 www.richtek.com figure 5. reference circuit with snubber and enable timing control thermal considerations for continuous operation, do not exceed the maximum operation junction temperature 125 c. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) - t a ) / q ja where t j(max) is the maximum operation junction temperature , t a is the ambient temperature and the q ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT8296B, the maximum junction temperature is 125 c. the junction to ambient thermal resistance q ja is layout dependent. for sop-8 (exposed pad) package, the thermal resistance q ja is 75 c/w on the standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c - 25 c) / (75 c/w) = 1.333w (min.copper area pcb layout) p d(max) = (125 c - 25 c) / (49 c/w) = 2.04w (70mm 2 copper area pcb layout) the thermal resistance q ja of sop-8 (exposed pad) is determined by the package architecture design and the pcb layout design. however, the package architecture design had been designed. if possible, it's useful to increase thermal performance by the pcb layout copper design. the thermal resistance q ja can be decreased by adding copper area under the exposed pad of sop-8 (exposed pad) package. as shown in figure 6, the amount of copper area to which the sop-8 (exposed pad) is mounted affects thermal performance. when mounted to the standard sop-8 (exposed pad) pad (figure 6.a), q ja is 75 c/w. adding copper area of pad under the sop-8 (exposed pad) (figure 6.b) reduces the q ja to 64 c/w. even further, increasing the copper area of pad to 70mm 2 (figure 6.e) reduces the q ja to 49 c/w. the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance q ja . for RT8296B packages, the derating curves in figure 7 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 7. derating curves for RT8296B package 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0 25 50 75 100 125 ambient temperature ( c) power dissipation (w) copper area 70mm 2 50mm 2 30mm 2 10mm 2 min.layout four-layer pcb vin en gnd boot fb sw 7 5 2 3 1 l 3.6 h 100nf 22 fx2 r1 75k r2 24k v out 3.3v/3a 10 f x 2 chip enable v in 4.5v to 23v RT8296B ss 8 c ss 0.1 f comp c c 2.2nf r c 22k c p nc 6 4, 9 (exposed pad) c boot c out c in r boot * r s * c s * r en * c en * * : optional
RT8296B 13 ds8296b-03 march 2011 www.richtek.com (a) copper area = (2.3 x 2.3) mm 2 , q ja = 75 c/w (b) copper area = 10mm 2 , q ja = 64 c/w (c) copper area = 30mm 2 , q ja = 54 c/w (d) copper area = 50mm 2 , q ja = 51 c/w (e) copper area = 70mm 2 , q ja = 49 c/w figure 6. themal resistance vs. copper area layout design layout consideration for best performance of the RT8296B, the following layout guidelines must be strictly followed. } input capacitor must be placed as close to the ic as possible. } sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace. } the feedback components must be connected as close to the device as possible
RT8296B 14 ds8296b-03 march 2011 www.richtek.com figure 8. pcb layout guide table 3. suggested capacitors for c in and c out location component supplier part no. capacitance ( m f) case size c in murata grm31cr61e106k 10 1206 c in tdk c3225x5r1e106k 10 1206 c in taiyo yuden tmk316bj106ml 10 1206 c out murata grm31cr60j476m 47 1206 c out tdk c3225x5r0j476m 47 1210 c out murata grm32er71c226m 22 1210 c out tdk c3225x5r1c22m 22 1210 v in v out gnd gnd c p c c r c sw v out c out l r1 r2 input capacitor must be placed as close to the ic as possible. sw should be connected to inductor by wide and short trace. keep sensitive components away from this trace. the feedback components must be connected as close to the device as possible. boot vin sw gnd ss en fb comp gnd 2 3 4 5 6 7 8 9 c ss r s * c s * gnd v in r en c in
RT8296B 15 ds8296b-03 march 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications is assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138

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