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commercial temperature range idtcv145 1-to-19 differential clock buffer 1 june 2006 idtcv145 commercial temperature range 1-to-19 differential clock buffer the idt logo is a registered trademark of integrated device technology, inc. ? 2005 integrated device technology, inc. dsc-6753/14 description: the cv145 differential buffer complies with intel db1900g , and is designed to work in conjunction with the main clock of ck409, ck410/ck410m and ck410b etc., pll is off in bypass mode and no clock detect. features: ? compliant with intel db1900g ? dif clock support ? 19 differential clock output pairs @ 0.7 v ? 150 ps skew performance across all outputs ? oe pin control of all outputs ? 3.3 v operation ? gear ratio supporting generation of clocks at a different frequency ratioed from the input. ? split outputs supporting options of 2 outputs @1:1 and remaining 17 pairs at an alternate gear ? pin level oe control of individual outputs ? multiple output frequency options up to 400mhz as a gear ratio of input clocks of 100-400mhz ? output is hcsl compatible ? smbus programmable configurations ? pll bypass configurable ? smbus address configurable to allow multiple buffer control in a single control network ? programmable bandwidth ? glitchfree transition between frequency states ? available in 72-pin vfqpfn package dif_0 dif_0# dif_1 dif_1# dif_2 dif_2# dif_3 dif_3# dif_4 dif_4# dif_5 dif_5# dif_6 dif_6# pll clk_in# clk_in high_bw# sa_2/pll_bypass# output buffer scl sda output control oe[16:5]# pd# sm bus controller oe_17_18# oe_01234# dif_18 dif_18# functional block diagram
commercial temperature range 2 idtcv145 1-to-19 differential clock buffer pin configuration vfqfpn top view 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 7 2 7 1 7 0 6 9 d i f _ 1 8 v d d v s s d i f _ 1 7 o e _ 1 7 _ 1 8 # s a _ 2 / p l l / b y p a s s # d i f _ 1 8 # c l k _ i n # c l k _ i n d i f _ 1 7 # d i f _ 1 6 d i f _ 1 6 # o e _ 1 6 # d i f _ 1 5 d i f _ 1 5 # o e _ 1 5 # d i f _ 1 4 d i f _ 1 4 # 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 1 9 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 o e _ 5 # d i f _ 5 d i f _ 5 # s c l s d a v s s v d d o e _ 6 # d i f _ 6 d i f _ 6 # o e _ 7 # d i f _ 7 d i f _ 7 # o e _ 8 # d i f _ 8 d i f _ 8 # s a _ 0 s a _ 1 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 53 52 54 v dd v ss dif_13 dif_13# oe_14# dif_12 dif_12# oe_13# dif_10 dif_10# oe_11# dif_9 dif_9# oe_10# dif_11 dif_11# oe_9# oe_12# iref v ss pd# high_bw# fsa 2 3 4 5 6 7 1 8 9 10 12 13 14 15 16 17 11 dif_0 dif_0# 18 dif_1 dif_1# v ss v dd dif_2 dif_2# dif_3 dif_3# dif_4 dif_4# oe_01234#
commercial temperature range idtcv145 1-to-19 differential clock buffer 3 pin description pin name type pin # description clk_in, clk_in# in 70, 71 0.7v differential input dif_[16:0] & dif_[16:0]# out 6 - 9, 12 - 17, 22, 23, 25, 0.7 v differential clock outputs, geared to a ratio of the input clock 26, 30, 31, 33, 34, 38, 39, 41, 42, 44, 45, 49, 50, 52, 53, 55, 56, 58, 59, 61, 62 dif & dif# [18:17] out 65 - 68 0.7 v differential clock outputs, which can be configured to be 1:1 instead of geared. default is geared same as 0-9 outputs. oe_[16:5]# i n 21, 24, 29, 32, 37, 40, 43, 3.3 v lvttl active low input for enabling corresponding differential output clock. clocks 48, 51, 54, 57, 60 also can be disabled via smbus registers oe _17_18# i n 69 3.3 v lvttl active low input for enabling both dif10 and 11differential output clocks. clocks also can be disabled via smbus registers individually. oe_01234# i n 18 3.3v lvttl input high_bw# in 4 3.3 v lvttl input for selecting the pll bandwidth. 0 = high bw, 1 = low bw. scl i n 19 smbus slave clock input sda i/o, oc 20 open collector smbus data iref in 1 a precision resistor is attached to this pin to set the differential output current sa_[1:0] i n 35, 36 3.3v lvttl input selecting the address. sa_[2:0] set device smbus address. sa_2/pll_bypass# in 72 3.3 v lvttl input for pllbypass and smbus address fs_a in 5 3.3v lvttl input to establish a high (>200mhz) or low frequency(<200mhz) range pd# i n 3 3.3 v lvttl input to power up or power down the device (see pd functionality table). oe functionality oe# - pin oe# - smbus bit dif diff]# 0 1 normal normal 0 0 tristate tristate 1 1 tristate tristate 1 0 tristate tristate symbol description min. max. unit v dda 3.3v core supply voltage 4.6 v v ddin 3.3v logic input supply voltage gnd - 0.5 4.6 v t stg storage temperature ?65 +150 c t ambient ambient operating temperature 0 +70 c t case case temperature +115 c esd prot input esd protection 2000 v human body model absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. pd functionality inputs outputs pd# / v dda clk_in / clk_in# dif dif# pll state 3.3v (nom) running running o n gnd x hi-z off
commercial temperature range 4 idtcv145 1-to-19 differential clock buffer index block write protocol bit # of bits from description 1 1 master start 2-9 8 master see smbus address mode table 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20-27 8 master byte count, n (0 is not valid) 28 1 slave ack (acknowledge) 29-36 8 master first data byte (offset data byte) 37 1 slave ack (acknowledge) 38-45 8 master 2nd data byte 46 1 slave ack (acknowledge) : master nth data byte slave acknowledge master stop index block read protocol master can stop reading any time by issuing the stop bit without waiting until nth byte (byte count bit30-37). bit # of bits from description 1 1 master start 2-9 8 master see smbus address mode table 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20 1 master repeated start 21-28 8 master see smbus address mode table 29 1 slave ack (acknowledge) 30-37 8 slave byte count, n (block read back of n bytes) 38 1 master ack (acknowledge) 39-46 8 slave first data byte (offset data byte) 47 1 master ack (acknowledge) 48-55 8 slave 2nd data byte ack (acknowledge) : master ack (acknowledge) slave nth data byte not acknowledge master stop index byte write setting bit[11:18] = starting address, bit[20:27] = 01h. index byte read setting bit[11:18] = starting address. after reading back the first data byte, master issues stop bit.
commercial temperature range idtcv145 1-to-19 differential clock buffer 5 gear ratios select fsa smbus3 smbus2 smbus1 smbus0 m n gear n/m 0 0 0 0 0 3 1 0.333 0 0 0 0 1 5 2 0.400 0 0 0 1 0 12 5 0.417 0 0 0 1 1 2 1 0.500 0 0 1 0 0 5 3 0.600 0 0 1 0 1 8 5 0.625 0 0 1 1 0 3 2 0.667 0 0 1 1 1 4 3 0.750 0 1 0 0 0 6 5 0.833 0 1 0 0 1 1 1 1.000 0 1 0 1 0 5 6 1.200 0 1 0 1 1 4 5 1.250 0 1 1 0 0 3 4 1.333 0 1 1 0 1 2 3 1.500 0 1 1 1 0 3 5 1.667 0 1 1 1 1 1 2 2.000 1 0 0 0 0 3 1 0.333 1 0 0 0 1 5 2 0.400 1 0 0 1 0 12 5 0.417 1 0 0 1 1 2 1 0.500 1 0 1 0 0 5 3 0.600 1 0 1 0 1 8 5 0.625 1 0 1 1 0 3 2 0.667 1 0 1 1 1 5 4 0.800 1 1 0 0 0 6 5 0.833 1 1 0 0 1 1 1 1.000 1 1 0 1 0 5 6 1.200 1 1 0 1 1 4 5 1.250 1 1 1 0 0 3 4 1.333 1 1 1 0 1 2 3 1.500 1 1 1 1 0 3 5 1.667 1 1 1 1 1 1 2 2.000
commercial temperature range 6 idtcv145 1-to-19 differential clock buffer targeted input and output frequencies input (mhz) output (mhz) m:n 200 200 1:1 267 133 2:1 160 320 1:2 333 167 2:1 200 400 1:2 400 200 2:1 200 133 3:2 133 200 2:3 400 133 3:1 133 167 4:5 167 133 5:4 333 133 5:2 200 267 3:4 267 200 4:3 400 160 5:2 167 200 5:6 200 167 6:5 200 333 3:5 333 200 5:3 267 167 8:5 targeted smbus address mode selection sa_[2:0] buffer address 000 d0h (write) d1h (read) 001 d2h, d3h 010 d4h, d5h 011 d6h, d7h 100 d8h, d9h 101 dah, dbh 110 dch, ddh 111 deh, dfh functionality at power-up (1) fsa clk_in (cpu fsb) dif[9:0] output dif[11:10] output 1 100mhz 100mhz 100mhz 1 133mhz 133mhz 133mhz 1 166mhz 166mhz 166mhz 1 reserved reserved reserved 0 200mhz 200mhz 200mhz 0 266.66mhz 266.66mhz 266.66mhz 0 333.33mhz 333.33mhz 333.33mhz 0 400mhz 400mhz 400mhz note: 1. fsa is a low-threshold input. please see the v il _ fs and v ih _ fs specifications in the dc operating characteristics table.
commercial temperature range idtcv145 1-to-19 differential clock buffer 7 byte 2 bit output(s) affected description/function 0 1 type power on 7 pll_bw# adjust high bw low bw rw 1 6 bypass# test mode / pll bypass pll rw 1 5 dif_13 output enable tristate enable rw 1 4 dif_12 output enable tristate enable rw 1 3 dif_11 output enable tristate enable rw 1 2 dif_10 output enable tristate enable rw 1 1 dif_9 output enable tristate enable rw 1 0 dif_8 output enable tristate enable rw 1 byte 3 bit output(s) affected description / function 0 1 type power on 7 readback - oe#_9 input r 6 readback - oe#_8 input r 5 readback - oe#_7 input depends on the state of the pin r 4 readback - oe#_6 input r 3 readback - oe#_5 input r 2 readback - oe#_01234 input r 1 readback - highbw# input latch value of pin at power-up r 0 readback - sa2/pll/bypass# input latch value of pin at power-up r byte 0 bit output(s) affected description/function 0 1 type power on 7 group of 17 gear # gr selection 1:1 = in rw 1 dif [16:0] speed selection 6 group of 2 gear # gr selection 1:1 = in rw 1 dif [18:17] speed selection 5 reserved rw 1 4 fsa latched input rw 3 smbus3 rw 2 smbus2 rw 1 smbus1 rw 0 smbus0 rw byte 1 bit output(s) affected description/function 0 1 type power on 7 dif_7 output enable tristate enable rw 1 6 dif_6 output enable tristate enable rw 1 5 dif_5 output enable tristate enable rw 1 4 dif_4 output enable tristate enable rw 1 3 dif_3 output enable tristate enable rw 1 2 dif_2 output enable tristate enable rw 1 1 dif_1 output enable tristate enable rw 1 0 dif_0 output enable tristate enable rw 1 control registers
commercial temperature range 8 idtcv145 1-to-19 differential clock buffer byte 5 bit output(s) affected description / function 0 1 type power on 7 revision id r 0 6 revision id r 0 5 revision id r 0 4 revision id r 0 3 vendor id r 0 2 vendor id r 1 1 vendor id r 0 0 vendor id r 1 byte 4 bit output(s) affected description / function 0 1 type power on 7 readback - oe#_17_18 input r 6 readback - oe#_16 input r 5 readback - oe#_15 input r 4 readback - oe#_14 input depends on the state of the pin r 3 readback - oe#_13 input r 2 readback - oe#_12 input r 1 readback - oe#_11 input r 0 readback - oe#_10 input r byte 6 - device id byte 7 - byte count byte 8 bit output(s) affected description / function 0 1 type power on 7 readback - fsa input latch value of pin at power-up r 6 reserved r 5 reserved r 4 dif_18 output enable tristate enable rw 1 3 dif_17 output enable tristate enable rw 1 2 dif_16 output enable tristate enable rw 1 1 dif_15 output enable tristate enable rw 1 0 dif_14 output enable tristate enable rw 1
commercial temperature range idtcv145 1-to-19 differential clock buffer 9 output relational timing parameters pll bandwidth and peaking dc operating characteristics following conditions apply unless otherwise specified: operating condition: v dd /v dda = 3.3v 5% symbol parameter test conditions min. typ. max. unit v dda 3.3 v core supply voltage 3.3 v 5% 3.135 - 3.465 v v dd 3.3 v i/o supply voltage 3.3 v 5% 3.135 - 3.465 v i dd 3.3 v supply current 3.3 v 5%, 0 to 70c - 450 600 ma i ddpd 3.3 v power down supply current 3.3 v 5%, 0 to 70c - 20 36 ma v ih 3.3 v input high voltage vdd 2.0 - vdd+0.3 v v il 3.3 v input low voltage vss-0.3 - 0.8 v i il input leakage current 0 < vin < vdd -5 - 5 a cin input pin capacitance 1.5 - 5 pf cout output pin capacitance - - 6 pf lpin pin inductance - - 7 nh ta ambient temperature no airflow 0 - 70 c group parameter min. typ. max. clk_in, dif [x:0] input to output skew in pll mode (1:1 only) -500ps 0 +500ps clk_in, dif [x:0] input to output skew in non pll mode (1:1 only) 2.5ns 4 4.5ns dif diff[x:0] pin-to-pin skew (output within same group) 0ps 115 125ps dif diff[x:0] pin-to-pin skew (across all outputs) 0ps 115 150ps dif accumulated differential phase jitter -100ps 0 +100ps group parameter min. typ. max. unit dif pll peaking (high_bw# = 0) 0 1 2.5 db dif pll peaking (high_bw# = 1) 0 1 2 db dif pll bandwidth (high_bw# = 0) 2 3.8 4 mhz dif pll bandwidth (high_bw# = 1) 0.7 0.9 1.4 mhz output phase jitter impact (pcie: including bw 1.5-22mhz) - 99 108 ps output phase jitter impact (fbd/csi: including bw 11-33mhz) -33 ps rms dif
commercial temperature range 10 idtcv145 1-to-19 differential clock buffer dif timing characteristics (non ssc clock input) dif 0.7 v ac timing characteristics (non-spread spectrum mode) dif timing characteristics (ssc clock input) dif 0.7 v ac timing characteristics (-0.5% spread spectrum mode) min. typ. max. laccuracy long accuracy - - 0 ppm tperiod average period -0.30% - 0.30% ns tabsmin absolute minimum host clk period -2.50% - - ns trise rise time 125 - 700 ps tfall fall time 125 - 700 ps ? trise rise time variation - - 75 ps ? tfall fall time variation - - 75 ps rise/fall matching - - 20% vhigh voltage high (typ 0.7 volts) 660 - 850 mv vlow voltage low (typ 0 volts) -300 - 150 mv vcross absolute absolute crossing point voltages 250 - 550 mv total ? vcross total variation of vcross over all edges - - 140 mv tccjitter pll mode cycle-to-cycle jitter fin = 100, 166,67, 200, 266.67, 333.33 mhz - - 50 ps tccjitter pll mode cycle-to-cycle jitter fin = 133.33, 400.00 mhz - - 75 ps tccjitter bypass mode cycle-to-cycle jitter (additive) - - 50 ps duty cycle 45 - 55 % vovs maximum voltage (overshoot) - - vh + 0.3v vuds minimum voltage (undershoot) - - -0.3 vrb ringback voltage 0.2 - n/a volt unit clk - 100mhz, 133.3mhz, 166.6mhz, 200mhz, 233.3mhz, 266.6mhz, 333mhz, 400mhz symbol parameter min. typ. max. laccuracy long accuracy --- - 0 ppm tperiod average period -0.30% - 0.53% ns tabsmin absolute minimum host clk period (period - 0.125ns) - - ns trise rise time 125 - 700 ps tfall fall time 125 - 700 ps ? trise rise time variation - - 75 ps ? tfall fall time variation - - 75 ps rise/fall matching - - 20% vhigh voltage high (typ 0.7 volts) 660 - 850 mv vlow voltage low (typ 0 volts) -300 - 150 mv vcross absolute absolute crossing point voltages 250 - 550 mv vcross relative relative crossing point voltages calc - calc tot al ? vcross total variation of vcross over all edges - - 140 mv tccjitter pll mode cycle-to-cycle jitter fin = 100, 166,67, 200, 266.67, 333.33 mhz - - 50 ps tccjitter pll mode cycle-to-cycle jitter fin = 133.33, 400.00 mhz - - 75 ps tccjitter bypass mode cycle-to-cycle jitter (additive) - - 50 ps duty cycle 45 - 55 % vovs maximum voltage (overshoot) - - vh + 0.3v vuds minimum voltage (undershoot) - - -0.3 vrb ringback voltage vx 0.2 - n/a volt unit clk - 100mhz, 133.3mhz, 166.6mhz, 200mhz, 233.3mhz, 266.6mhz, 333mhz, 400mhz symbol parameter
commercial temperature range idtcv145 1-to-19 differential clock buffer 11 buffer power-up state diagram s1 delay >0.25 ms s0 power off s2 wait for input clock and de-assertion p wrdwn # s3 normal operation no input clock p wrdwn # asserted buffer power-up state machine (1) note: 1. the total power up latency from power on to all outputs active must be less than 1ms (assuming a valid clock is present on clk_in input). if power is valid and p wrdwn is de-asserted but no input clocks are present on the clk_in input, dif clocks must remain disabled. only after valid input clocks are detected, valid power, p wrdwn # de-asserted with the pll locked/stable and the dif outputs enabled (doesn't apply to bypass mode). state description state0 power off state1 after 3.3v supply is detected to rise above 1.8-2v, the buffer enters state1 and initiates a 0.2ms-0.3ms delay.the total power up latency from power on to all outputs active must be less than 1ms (assume src_in is available) state2 buffer waits for a valid clock on the src_in input and pd de-assertion. state3 only after src_in and power valid, pd de-asserted with the current mirror stable, or pll lock, the dif outputs are enabled
commercial temperature range 12 idtcv145 1-to-19 differential clock buffer ordering information xxx xx package nl nlg very fine pitch quad flat pack vfqfpn - green 1-to-19 differential clock buffer 145 device type x grade blank idtcv commercial temperature range (0c to +70c) corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 logichelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com
commercial temperature range idtcv145 1-to-19 differential clock buffer 13 june 08, 2006 updated electrical characteristics pages (9-10). revision history

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