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? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? 1 ? ? ? ? ? ? preliminary device highlights low power programmable logic ? as low as tbd a ? 0.18 m, six layer metal cmos process ? 1.5 v or 1.8 v core voltage, 1.8/2.5/3.3 v drive capable i/os ? up to 27 kilobits of sram ? up to 85 i/os available ? up to 150,000 system gates ? nonvolatile, instant-on ? ieee 1149.1 boundary scan testing compliant embedded dual-port sram ? up to four dual-port 4-kilobit and four 2-kilobit high performance sram blocks ? true dual-port capability for ram and fifos ? embedded synchronous/asynchronous fifo controller ? configurable and cascadable aspect ratio programmable i/o ? bank programmable slew rate control ? eight independent i/o banks capable of supporting multiple i/o standards in one device ? bank programmable i/o standards: lvttl, lvcmos, lvcmos18, and pci advanced clock network ? multiple low skew clock networks 1 dedicated global clock network 4 programmable global clock networks ? quadrant-based segmentable clock networks 20 quad clock networks per device 4 quad clock networks per quadrant 1 dedicated clock network per quadrant ? one user configurable clock manager (ccm) very low power (vlp) mode ? quicklogic polarpro ii has a special vlp pin which can enable a low power sleep mode that significantly reduces the overall power consumption of the device by placing the device in standby ? enter vlp mode from normal operation in less than 10 s (typical) ? exit from vlp mode to normal operation in less than 10 s (typical) security links there are several security links to disable jtag access to the device. programming these optional links completely disables ac cess to the device from the outside world and provides an extra level of design security not possib le in sram-based fpgas. figure 1: quicklogic polarpro ii block diagram embedded ram blocks fabric embedded ram blocks fifo controller ccm gpio gpio gpio gpio gpio gpio gpio gpio gpio gpio fifo controller gpio gpio gpio gpio gpio gpio combining low power, perform ance, density, and embedded ram quicklogic polarpro? ii device data sheet
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 2 preliminary ultra-low power fpga combining performance, density, and embedded ram process data the quicklogic polarpro ii is fabricated on a 0.18, si x layer metal cmos process. the core voltage is 1.5 v or 1.8 v. the i/o voltage input tolerance and output drive can be set as 1.8 v, 2.5 v, and 3.3 v. programmable logic architectural overview the quicklogic polarpro ii logi c cell structure presented in figure 2 is a single register, multiplexer-based logic cell. it is designed for wide fan-in and multiple, simultaneous output functi ons. the cell has a high fan-in, fits a wide range of functions with up to 24 simultaneous in puts (including register control lines), and four outputs (three combinatorial and one registered). the high logi c capacity and fan-in of the logic cell accommodates many user functions with a si ngle level of logic delay. the quicklogic polarpro ii logic cell can implement: ? two independent 3-input functions ? any 4-input function ? 8 to 1 mux function ? independent 2 to 1 mux function ? single dedicated register with clock en able, active high set and reset signals ? direct input selection to the register, which allows combinatorial and register logic to be used separately ? combinatorial logic that can also be configur ed as an edge-triggered master-slave d flip-flop table 1: polarpro ii ql2p150 features ql2p150 max gates 150,000 logic cells 864 max i/o 85 ram modules 8 fifo controllers 8 ram bits 27,648 ccms 1 packages tfbga (0.5 mm) 121 tfbga (0.4 mm) 121
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 3 preliminary figure 2: polarpro ii logic cell ram modules the polarpro ii ql2p150 device has four 4-kilobit (4608 bits) as shown in figure 3 , and four 2-kilobit (2304) ram blocks as shown in figure 4 . the ram features include: ? independently configurable read and write data bus widths ? independent read and write clocks ? maximum of two ram blocks can be c oncatenated horizontally or vertically 4 kilobits for two 2-kilobit ram blocks and 8 kilobits for two 4-kilobit ram blocks ? write byte enables ? selectable pipelined or non-pipelined read data ? true dual-port ram functionality ? clock disabling during idle operation 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 d e q r s tz cz qz fz qds qst tbs tab tsl ti ta1 ta2 tb1 tb2 bab bsl bi ba1 ba2 bb1 bb2 fs f1 f2 qdi qen qck qrt
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 4 preliminary figure 3: 4-kilobit dual-port ram block figure 4: 2-kilobit dual-port ram block rd[17:0] wd[17:0] wa[7:0] wen[1:0] wd_sel wclk wclk_en ra[7:0] rd_sel rclk rclk_en rd[8:0] wd[8:0] wa[7:0] wen[1:0] wd_sel wclk wclk_en ra[7:0] rd_sel rclk rclk_en
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 5 preliminary table 2 describes the ram interface signals. the read and write data buses of a ram block can be a rranged to variable bus widths. the bus widths can be configured using the ram wizard avai lable in quickworks, quicklogic?s development software. the selection of the ram depth and width determin es how the data is addressed. the ram blocks also support data concatenation. desi gners can cascade multiple ram modules to increase the depth or width by connecting co rresponding address lines together and dividing the words between modules. generally, this requires the use of additi onal programmable logic resources. however, when concatenating only two 4-kilobit ram blocks or two 2-kilobit ram blocks, they can be concatenated horizontally or vertically without using any additional programmable fabric resources. for example, two internal 4-kilobit dual-port ram bloc ks can be concatenated vertically to create a 512x18 ram block or horizontally to create a 256x36 ram block. figure 5 displays a block diagram of 4-kilobit ram blocks horizontal and vertical concatenation. table 2: ram interface signals signal name function inputs wd write data wa write address wen write enable wd_sel write chip select wclk write clock wclk_en write clock enable ra read address rd_sel read chip select rclk read clock rclk_en read clock enable output rd read data
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 6 preliminary figure 5: 4-kilobit horizontal and vertical concatenation examples for example, two internal 2-kilobit dual-port ram bloc ks can be concatenated vertically to create a 256x18 ram block or horizontally to create a 128x36 ram block. figure 6 displays a block diagram of 2-kilobit ram blocks horizontal and vertical concatenation. figure 6: 2-kilobit horizontal and vertical concatenation examples 256x36 dual-port ram rd35 horizontal concatenation 512x18 dual-port ram vertical concatenation d35 a 1 d c c ra rd rc rc d1 a8 1 d c c ra8 rd rc rc rd1 128x36 dual-port ram rd35 horizontal concatenation 256x18 dual-port ram vertical concatenation d35 a6 1 d c c ra6 rd rc rc d1 a 1 d c c ra rd rc rc rd1
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 7 preliminary table 3 shows the various ram configurations supporte d by the polarpro ii 4-kilobit ram modules. table 4 shows the various ram configurations supporte d by the polarpro ii 2-kilobit ram modules. true dual-port ram polarpro ii dual-port ram modules can also be concatenat ed to generate true dual-port rams. the true dual- port ram module?s port1 and port2 have completely independent read and write ports, and separate read and write clocks. this allows port1 and port2 to have di fferent data widths and clock domains. it is important to note that there is no circuitry preventing a write an d read operation to the same address space at the same time. therefore, it is up to the designer to ensure that the same address is not read from and written to simultaneously, otherwise the data is considered invali d. likewise, the same address must not be written to from both ports at the same time. however, it is possible to read from the same address. table 3: available 4-kilobit ram configurations device number of ram blocks depth width description ql2p150 1 256 1-18 no concantenation 1 512 1-9 no concantenation 2 256 1-36 horizontal concantenation 2 512 1-18 vertical concantenation 2 1024 1-9 vertical concantenation table 4: available 2-kilobit ram configurations device number of ram blocks depth width description ql2p150 1 128 1-18 no concantenation 1 256 1-9 no concantenation 2 128 1-36 horizontal concantenation 2 256 1-18 vertical concantenation 2 512 1-9 vertical concantenation
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 8 preliminary figure 7 shows an example of a 512x18 true dual-port ram. figure 7: 512x18 4-kilobit true dual-port ram block figure 8 shows an example of a 256x18 true dual-port ram. figure 8: 256x18 2-kilobit true dual-port ram block port1_rd[17:0] port1_wd[17:0] port1_a[8:0] port1_wen[1:0] port1_cs port1_clk port1_clk_en port2_rd[17:0] port2_wd[17:0] port2_a[8:0] port2_wen[1:0] port2_cs port2_clk port2_clk_en port1_rd[17:0] port1_wd[17:0] port1_a[7:0] port1_wen[1:0] port1_cs port1_clk port1_clk_en port2_rd[17:0] port2_wd[17:0] port2_a[7:0] port2_wen[1:0] port2_cs port2_clk port2_clk_en
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 9 preliminary table 5 describes the true dual-port ram interface signals. table 6 lists the 4-kilobit true dual-port ram configurations that are available. table 7 lists the 2-kilobit true dual-port ram configurations that are available. table 5: true dual-port ram interface signals port signal name function port1 inputs port1_wd write data port1_a write address port1_wen write enable port1_cs chip select port1_clk clock port1_clk_en clock enable output port1_rd read data port2 inputs port2_wd write data port2_a write address port2_wen write enable port2_cs chip select port2_clk clock port2_clk_en clock enable output port2_rd read data table 6: available 4-kilobit true dual-port ram configurations device depth width ql2p150 512 1-18 1024 1-9 table 7: available 2-kilobit true dual-port ram configurations device depth width ql2p150 256 1-18 512 1-9
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 10 preliminary embedded fifo controllers every ram block can be implemented as a synchronou s or asynchronous fifo. there are built-in fifo controllers that allow for varying depths and widths without requiring programmable fabric resources. the polarpro ii fifo controller features include: ? x9, x18 and x36 data bus widths . ? independent push and pop clocks ? independent programmable data width on push and pop sides . ? configurable synchronous or asynchronous fifo operation ? 4-bit push and pop level indicators to provide fifo status outputs for each port ? pipelined read data to improve timing ? switchable clock domain between push and pop side during asynchronous operation ? clock disabling during idle operation ? asynchronous reset (apart from the synchronous flush) going to the pointers figure 9 shows an example a fifo module. figure 9: fifo module din[x:0] push fifo_push_flush push_clk push_clk_en pop fifo_pop_flush pop_clk pop_clk_en fifo_dir async_flush dout[x:0] almost_full almost_empty push_flag[3:0] pop_flag[3:0] a a a. x = {1,2,3,....35}.
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 11 preliminary table 8 lists the fifo configurations that are available. table 9 lists the fifo controller interface signals. table 8: available fifo configurations device number of ram blocks depth supported widths ql2p150 1 (2-kilobit ram block) 128 1-18 bits 1 (2-kilobit ram block) 256 1-9 bits 2 (2-kilobit ram block) 128 1-36 bits 2 (2-kilobit ram block) 256 1-18 bits 2 (2-kilobit ram block) 512 1-9 bits 1 (4-kilobit ram block) 256 1-18 bits 1 (4-kilobit ram block) 512 1-9 bits 2 (4-kilobit ram block) 256 1-36 bits 2 (4-kilobit ram block) 512 1-18 bits 2 (4-kilobit ram block) 1024 1-9 bits table 9: fifo interface signals signal name width (bits) direction function push signals din 1 to 36 i data bus input push 1 i initiates a data push fifo_push_flush 1 i empties the fifo push_clk 1 i push data clock push_clk_en 1 i push clock enable pop signals dout 1 to 36 o data bus output pop 1 i initiates a data pop fifo_pop_flush 1 i empties the fifo pop_clk 1 i pop data clock pop_clk_en 1 i pop clock enable common port signals fifo_dir 1 i push-pop domain switching async_flush 1 i asynchronous input to flush fifo status flags almost_full 1 o asserted when fifo has one location available almost_empty 1 o asserted when fifo has one location used push_flag 4 o fifo push level indicator pop_flag 4 o fifo pop level indicator
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 12 preliminary table 10 and table 11 highlight the corresponding fifo level indicator for each 4-bit value of the push_flag and pop_flag outputs. table 10: fifo push level indicator values value status 0000 full 0001 empty 0010 room for more than one-half 0011 room for more than one-forth 0100 room for less than one-forth to 64 a a. for a fifo depth of 256, value 0100 will not be asserted. the push flag will shift directly from 0011 to 1010 as data is pushed. for a fifo depth of 128, values 0100 and 1010 will not be asserted. the push flag will shift directly from 0011 to 1011 as data is pushed. 1010 room for 32 to 63 a 1011 room for 16 to 31 1100 room for 8 to 15 1101 room for 4 to 7 1110 room for 2 to 3 1111 room for 1 others reserved table 11: fifo pop level interface signals value status 0000 empty 0001 1 entry in fifo 0010 at least 2 entries in fifo 0011 at least 4 entries in fifo 0100 at least 8 entries in fifo 0101 at least 16 entries in fifo 0110 at least 32 entries in fifo a a. for a fifo depth of 256, value 1000 will not be asserted. the pop flag will shift directly from 1101 to 0110 as data is popped. for a fifo depth of 128, values 1000 and 0110 will not be asserted. the pop flag will shift directly from 1101 to 0101 as data is popped. 1000 64 entries to less than one-forth full a 1101 one-forth or more full 1110 one-half or more full 1111 full others reserved
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 13 preliminary push-pop domain switching during asynchronous operation, the fifo works in a half-duplex manner, meaning push on one clock domain and pop on the other clock domain. to provide each domain the push and pop capability, a dir port is added to choose what function each clock domain will have. the dir port determines the functions of p1 and p2, and the clock assigned to port1 and port2 of the fifo. after the direction switches, the fifo pointers must be reset. figure 10 shows the push-pop domain switching operation. figure 10: push-pop domain switching table 12 shows the push-pop direction switching. fifo synchronous flush procedure both push and pop domains are provided with a flush in put signal synchronized to their respective clocks. when a flush is triggered from one side of the fifo, th e signal propagates and re-synchronizes internally to the other clock domain. during a flush operation, the valu es of the fifo flags are invalid for a specific number of cycles (see figure 11 and figure 12 ). as shown in figure 11 , when the fifo_push_flush asserts, the almost_full and push_flag signals become invalid until the fifo can flush the data with re gards to the push clock domain as well as the pop clock domain. after the fifo_push_flush is asserted, the next rising edge of the pop clock starts the pop flush routine. table 12: push-pop direction switching dir direction 0 clk1/p1 push, clk2/p2 pop 1 clk1/p1 pop, clk2/p2 push push ckt pop ckt wclk rclk 0 1 0 1 0 1 0 1 p1 clk1 p2 clk2 p1 clk1 p2 clk2 push pop dir
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 14 preliminary figure 11 illustrates a fifo flush operation. after the fifo_push_flush is asserted at 2 ( push_clk ), four pop clock cycles (12 through 15) are required to update the pop_flag , and push_flag signals. the almost_empty signal is asserted to indicate that the push flush operation has been completed. on the following rising edge of the push_clk (8), the push_flag is accordingly updated to reflect the successful flush operation. figure 11: fifo flush from push side figure 12 illustrates a pop flush operation. after the fifo_pop_flush is asserted at 2 ( pop_clk ), four push clock cycles (12 through 15) are required to update the pop_flag , and push_flag signals. the almost_empty signal is asserted to indicate that the po p flush operation has been completed. on the following rising edge of the pop_clk (8), the pop_flag is updated accordingly to reflect the successful flush operation. push_clk fifo_push_flush pop_clk almost_full push_flag valid almost_empty pop_flag 0000 (empty) earliest push valid valid 12 3456 8 79 1 0 11 12 13 14 15 16 invalid invalid invalid
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 15 preliminary figure 12: fifo flush from pop side figure 11 and figure 12 are only true for this particular push-p op clock frequency combination. the clock frequency and phase difference between pop_clk and push_clk can cause an additional flush delay of one clock cycle in either domain because of the as ynchronous relationship between the two clocks. asynchronous flush apart from the synchronous flush controls, an as ynchronous flush is provided through the port async_flush. assertion of this signal fl ushes the fifo push and pop pointers. ql2p150 clock network architecture clock network architecture the polarpro ii clock network architecture cons ists of a 2-level h-tree network as shown in table 13 . the first level of each clock tree spans from the clock input pad to the global clock network and to the center of each quadrant of the chip. the second leve l spans from the quadrant clock network to every logic cell inside that quadrant. there are five global clocks in the global cloc k network, and five quadrant clocks in each quadrant clock network. all global clocks driv e the quadrant clock network inputs. the quadrant clock network passes eith er the original input clock or an in verted version of the input clock to the column clock buffer. the column clock buffer allows dynamically enabli ng or disabling all clocks in the column level. the global clocks can drive ram block cl ock inputs and reset, set, enable, and clock inputs to i/o registers. furthermore, the quadrant clock ou tputs can be routed to all logic cell inputs. pop_clk fifo_pop_flush push_clk almost_empty pop_flag 0000 (empty) almost_full push_flag valid invalid valid valid earliest push invalid 1 10 23456789 11 12 13 14 15 16 invalid
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 16 preliminary figure 13: polarpro ii clock network architecture of the five global clock networks: ? two can be either driven directly by clock pads, co nfigurable clock manager (ccm) outputs, or internally generated signals. these two global clocks go through 3-input global clock muxes located in the middle of the die. see figure 14 for a diagram of a 3-input global clock mux. ? two can be either driven directly by cl ock pads or internally generated signals. ? one is a dedicated global clock network that goes dire ctly to the quadrant clock network and is used as a dedicated fast clock. quadrant clock network global clock network x4 x4 x4 x4 x4 qmux (inversion selection) quadrant clock network quadrant clock network quadrant clock network cand (clock enable)
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 17 preliminary figure 14: global clock structure figure 15 illustrates the quadrant hsck 4-input mux. figure 15: quadrant clock structure the quadrant hsck mux is located at the middle of the quadrant. these 4- input hsck muxes output inverted or non-inverted output from global hsck, or inverted or non-inverted quad level hsck depending on the 2-bit select line. inte r na l ly ge ne ra te d c loc k , or clock from general routing network global clock (clk ) input pad t o quadrant c loc k s tructure g loba l c loc k b uffer ccm output 2-bit select internally generated clock, or clock from general routing network to macro cell columns from global clock buffer 2-bit select internally generated clock, or clock from general routing network from global clock buffer
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 18 preliminary a quadrant hsck mux can be implemented in verilog, vhdl, and schematic designs by instantiating the quadrant hsck mux macro, qmux. figure 16 shows the schematic representation of the qmux macro. figure 16: qmux macro it is important to note that the select lines for the gl obal clock and quadrant clock muxes are static signals and cannot be changed dynamically during device operation. using the column clock buffers , all clocks can be dynamically disabled at the column level. column clock buffers can be implemented in verilog, vhdl, and schematic de signs by instantiating the column clock buffer macro, cand. figure 17 shows the schematic representation of the cand macro. figure 17: cand macro dynamic clock enable the quicklogic polarpro ii ql2p150 devices provide a powerful dynami c clock enable feature that allows designers to dynamically enable and disable clocks routed into the quicklogic device. associated with each of the five clock inputs is a clock enable , which is an interface signal that ca n be either dynamically controlled via a routable signal or tied high or low. once an incoming clock is disabled, the clock is driven low internally. all the logic that is driven by the clock is held at the stat e when the clock was disabled. if a reset signal is passed through the clock pad, the dynami c disable should not be used. as an additional feature, polarpro ii devices have buil t-in deglitching circuitry to pr event clock glitching during transitions so that clocks can be enabled or disabled asynchronously without the possibility of false edge detection within the internal logic. the dynamic clock disable feature can be implemented in verilog, vhdl, and schematic designs by instantiating the dynamic clock enable macro, ckpad2_dyn_en. figure 18 shows the schematic representation of the dynamic clock enable macro. qmux is1 is0 cand
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 19 preliminary figure 18: clock pad macro for dynamic clock enable configurable clock manager (ccm) the ccm features include: ? input frequency range from 10 mhz to 150 mhz ? output frequency range from 25 mhz to 200 mhz ? output jitter is less than 200 ps peak-to-peak ? two outputs: pullout0 (with 0 ph ase shift), and pullout1 (with an option of 0, 90, 180, or 270 phase shift plus a programmable delay). ? programmable delay allows delays up to 2.5 ns at 250 ps intervals (typical) ? fixed feedback path ? output frequency lock time in less than 10 s figure 19: configurable clock manager the reset signal can be routed from a clock pad or gene rated using internal logic. the lock_out signal can be routed to internal logic and/or an output pad. ccm cl ock outputs can drive the glob al clock networks, as well as any general purpose i/o pin. once the ccm has sync hronized the output clock to the incoming clock, the lock_out signal will be asserted to indicate that the outp ut clock is valid. lock detection requires at least 10 s after reset to assert lock_out. the polarpro ii ccms have three modes of operation, based on the input frequency and desired output frequency. table 13 indicates the features of each mode. table 13: ccm pll mode frequencies output frequency input frequency range output frequency range pll mode x1 25 mhz to 150 mhz 25 mhz to 150 mhz pll_mult1 x2 15 mhz to 100 mhz 30 mhz to 200 mhz pll_mult2 x4 10 mhz to 50 mhz 40 mhz to 200 mhz pll_mult4 pllout0 ded_in ded_fd rst_in fc[1:0] s[1:0] tdctl[3:0] pllout1 lock_out
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 20 preliminary ccm signals table 14 provides the name, direction, functi on and description of the ccm ports. table 15 , and table 16 and table 17 give the values used to configure the set mode, and phase shift control and time delay control bits. table 14: ccm signals signal name direction function description routable ports ded_in i dedicated input clock pad ccm input source. rst_in i reset active high reset: if rst_in is asserted, pllout0 and pllout1 are reset to 0. this signal must be asserted and then released for lock_out to assert. pllout0 o 0 phase clock 0 phase clock output. pllout1 o configurable phase clock 0, 90,180, or 270 phase clock output with programmable delay. lock_out o lock detect active high lock detection signal. active when the pllout signals correctly output t he configured functionality. static ports fc[1:0] i phase shift control determines whether pllout1 is 0, 90, 180, or 270 degrees out of phase with pllout0 a . a. the pllout1 output can vary up to -5% with respect to t he pllout0 output. therefore, quic klogic recommends thorough post-lay out simulation in order to verify sa tisfactory operation of the ccms. s[1:0] i set mode determines pllout1 and pllout0 frequency multiplier (x1, x2, or x4). tdctl[3:0] i time delay control pllout1 programmable delay, configurable in 250 ps increments up to a maximum of 2.5 ns. note: 250 ps can vary depending on process variation. table 15: set mode values s[1:0] multiplier 00 x1 01 x2 10 x4 11 reserved table 16: phase shift control values fc[1:0] phase shift (deg.) 00 0 01 90 10 180 11 270
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 21 preliminary ccm configurations the main purpose of the ccm is to align the clock arri val times of two separate clock destinations, whether it is within the fpga or external to the chip. the diffe rence between the two clock destinations is referred to as clock skew. to correct for clock skew the ccms can be configured to shift the phase and/or delay of the pllout1 clock output. in most cases the desired phase or added delay can be ac complished by configuring bo th the clock source input and feedback input as dedicated. in the case of a dedicated clock source and dedicated feedback, the quicklogic development software calcul ates and generates all of the requir ed routing delays to produce the requested configuration. for more information on ccms and how to use them in quickworks, refer to application note 87 configurable clock managers . table 17: time delay control values tdctl[3:0] time delay (ps) 0000 0 0001 250 0010 500 0011 750 0100 1000 0101 1250 0110 1500 0111 1750 1000 2000 1001 2250 1010 2500 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 18: available configurations clock feedback example usage comments dedicated clock pad dedicated feedback standard pll application. reduce set-up or clock-to-out time. if the clock pad and destination are in phase.
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 22 preliminary simultaneously switching outp uts (ssos) while using a ccm ssos are outputs that transition at the same time in the same direction (either from vcc to gnd or gnd to vcc). to ensure that the ccm never loses lock over al l possible frequencies of operation, designers must follow the guidelines specified in th is section when using the fpga output s as ssos. these guidelines include the number of ssos placed adjacent to the ccm and the quality of the power filtering circuit sourcing the ccm block. figure 20 shows a basic layout of the eight i/o banks available in polarpro ii devices and the relative placement of the ccm. figure 20: basic layout of i/o banks and ccms ssos placed in i/o bank and i/o bank in cl ose proximity to the ccm can affect the ccm?s functionality. note: to define the boundary of operation when using ssos in conjunction with the ccm add ssos starting from the far end of a bank relative to the ccm?s location. i/o bank i/o bank i/o bank i/o bank i/o bank i/o bank i/o bank i/o bank ccm
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 23 preliminary figure 21: adding ssos when using the ccm to ensure proper operation of the ccm: 1. limit the number of ssos in i/o bank and i/o bank that are synchronous to the ccm (i.e., clocked by ccm outputs). 2. limit the number of ssos in i/o bank and i/o bank that are asynchronous to ccm (i.e., not clocked by ccm outputs). 3. the power supply to the ccms must ha ve adequate noise filtering circui ts. quicklogic reference design boards use the noise filtering circuit shown in figure 22 . figure 22: noise filtering circuit i/o bank i/o bank i/o bank i/o bank i/o bank i/o bank i/o bank i/o bank ccm polarpro 1.8v gnd 0.01uf 0.001uf ccmvcc ccmgnd mi0805k400r-10 polarpro ii
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 24 preliminary general purpose input output (gpio) cell structure the gpio features include: ? direct or registered input with input path select ? direct or registered output with output path select ? direct or registered output enable with oe path select ? input buffer enable to reduce power ? programmable pull-down control ? configurable slew rate ? support for jtag boundary scan figure 23: polarpro ii gpio cell fixhold logic dq dq dq oqi oqe osel ie esel iqe fixhold iqr iqc wpd i/o pad iz e iqz e slew 1 0 1 1 0 0
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 25 preliminary with bi-directional i/o pins and global clock input pi ns, the polarpro ii device maximizes i/o performance, functionality, and flexibility. all input and i/o pins are 1.8 v, 2.5 v, and 3.3 v tolerant and comply with the specific i/o standard selected. for single-ended i/o standard s, the corresponding vcci o bank input specifies the input tolerance and the output drive voltage. a weak pull-down function can be conf igured for an individual i/o. table 19 lists the gpio interface signals. programmable pull-down polarpro ii i/o support weak pull-down . a programmable weak pull-down resistor is available on each i/o. the i/o weak pull-down eliminates the need fo r external pull-down resistors. when wpd= 1 weak pull-down is enabled. table 19: gpio interface signals signal name direction function routable signals oqi i output path input oqe i output register enable signal ie i enable path input iz o input path combinatorial output to routing iqz o input path register output to routing iqe i input register enable signal iqc i register clock iqr i register reset pa d i/o i/o pad static signals esel i enable register/combinatorial path select '1' : combinatorial '0' : register osel i output register/combinatorial path select '1' : combinatorial '0' : register slew i slew selection '0' : slow slew '1' : fast slew fix_hold i input delay path selection '0' : non-delay '1' : delayed wpd i weak pull-down '0' : disable - no weak pull-down '1' : enable - weak pull-down enabled
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 26 preliminary programmable slew rate each i/o has programmable slew rate capability. the pola rpro ii gpios allow up to two different slew rate speeds (slow and fast). slow slew rates can be used to reduce noise caused by i/o switching. i/o interface standards are programmable on a per bank basis. table 20 illustrates the i/o bank configurations available. each i/o bank is independent of other i/o banks and each i/o bank has its own vccio supply inputs. a mixture of different i/o standards can be used on a polarpro ii device. however, there is a limitation as to which i/o standards can be supp orted within a given bank. on ly standards that share a common vccio can be shared within the same bank (e.g., pci and lvttl). very low power (vlp) mode the quicklogic polarpro ii devices have a unique feat ure, referred to as vlp mode, which reduces power consumption by placing the device in standby. specific ally, vlp mode can bring the total standby current down to less than 10 a at room temp erature when no incoming signals are toggled. the active low vlp pin controls vlp mode. for normal operation, the vlp pin must be driven to a voltage anywhere between 1.8 v and 3.3 v. at 1.8 v, the vpump pin can be tied to 3. 3 v for data retention in vlp mode, or to 0 v which does not allow data retention in vlp mode and draws ad ditional current during normal operation. if vlp is tied to 1.5 v, the vpump pin must be tied to 3.3 v for vlp mode to be operational. when the polarpro ii device goes into vlp mode, the following occurs: ? all logic cell registers and gpio registers values are held ? all ram cell data is retained ? the outputs from all gpio to th e internal logic are tied to ?0? ? gpio outputs drive the previous values ? gpio output enables retain the previous values ? clock pad inputs are gated ? ccm is held in the reset state during the transition from vlp mode to normal operation, the vlp pin can draw up to 1.5 ma. consequently, if using a pull-up re sistor, use a pull-up resistor with a value that is less than 2 k . the entire operation from normal mode to vlp mode requires 10 s . as the device exits out of vlp mode, which also takes 10 s, the data from the registers, ram, and gpio are used to recover the functionality of the device. furthermore, since the ccm was in a reset state during vlp mode, it must re-acquire the correct output signal before asserting lock_out. figure 24 displays the delays associated with entering and exiting vlp mode. table 20: i/o standards and applications i/o standard vccio voltage application lvttl 3.3 v general purpose lv c m o s 2 5 2.5 v general purpose lvcmos18 1.8 v general purpose pci 3.3 v pci bus applications
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 27 preliminary figure 24: typical vlp mode timing joint test access group (jtag) information figure 25: jtag block diagram vlp pin vlp status vlp mode normal operation vlp inactive vlp inactive 10 s 10 s tck tms trstb rdi tdo instruction decode & control logic tap controller state machine (16 states) instruction register boundary-scan register (data register) mux bypass register mux internal register i/o registers user defined data register
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 28 preliminary quicklogic?s polarpro ii devices comply with ieee standard 1149.1, the standard test access port and boundary scan architecture. the jtag boundary scan test methodology allows complete observation and control of the boundary pins of a jtag-compatible devi ce through jtag software. a test access port (tap) controller works in concert with the instruction register (ir), which allow users to run three required tests along with several user-defined tests. jtag tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for comprehensiv e verification of higher level system elements. the 1149.1 standard requires the following three tests: ? extest instruction. the extest instruction performs a printed circuit board (pcb) interconnect test. this test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the tap test data in (tdi) and te st data out (tdo) pins. boundary scan cells are preloaded with test patterns (through the sample/pre load instruction), and input boundary cells capture the input data for analysis. ? sample/preload instruction. the sample/preload instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the tdi and tdo pins. for this test, the boundary scan register can be accessed thro ugh a data scan operation, allowing users to sample the functional data entering and leaving the device. ? bypass instruction. the bypass instruction allows data to skip a device boundary scan entirely, so the data passes through the bypass regist er. the bypass instruction allows users to test a device without passing through other devices. the bypass register is conn ected between the tdi and tdo pins, allowing serial data to be transferred through a device wi thout affecting the operation of the device. jtag bsdl support ? boundary scan description language (bsdl) ? machine-readable data for test equipmen t to generate testing vectors and software ? bsdl files available for all device /package combinations from quicklogic ? extensive industry support available and at vg (automatic test vector generation)
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 29 preliminary electrical specifications dc characteristics the dc specifications are provided in table 21 through table 24 . table 21: absolute maximum ratings parameter value parameter value vcc voltage -0.5 v to 2.2 v esd pad protection tbd vccio voltage -0.5 v to 4.0 v leaded package storage temperature -65 c to + 150 c input voltage -0.5 v to 4.0 v laminate package (bga) storage temperature -55 c to + 125 c latch-up immunity 100 ma table 22: recommended operating range symbol parameter industrial commercial unit min. max. min. max. vcc supply voltage 1.43 1.89 1.43 1.89 v vccio i/o input tolerance voltage 1.71 3.60 1.71 3.60 v tj junction temperature -40 100 0 85 c table 23: dc characteristics symbol parameter conditions min. typ. max. units i l i or i/o input leakage current vi = vccio or gnd tbd tbd tbd a i oz 3-state output leakage cu rrent vi = vccio or gnd a c i i/o input capacitance vccio = 3.6 v pf c clock clock input capacitance vccio = 3.6 v pf i ref quiescent current on inref - a i pd current on programmable pull-down vccio = 3.6 v a vccio = 2.75 v a vccio = 1.89 v a i pu current on programmable pull-up vccio = 3.6 v a vccio = 2.75 v a vccio = 1.89 v a i vlp quiescent current on vlp pin vlp=3.3 a i ccm quiescent current on each ccmvcc vcc=1.89 v a i vcc quiescent current vlp=gnd a vlp=3.3v a i vccio quiescent current on vccio vccio = 3.6 v a vccio = 2.75 v a vccio = 1.89 v tbd a
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 30 preliminary table 24: dc input and output levels a a. the data provided in table 24 represents the jedec and pci specification. quicklogic devices either meet or exceed these requirements. symbol inref v il v ih v ol v oh i ol i oh v min v max v min v max v min v max v max v min ma ma lv t t l n/a n/a -0.3 0.8 2.2 vccio + 0.3 0.4 2.4 2.0 -2.0 lv c m o s 2 n/a n/a -0.3 0.7 1.7 vccio + 0.3 0.7 1.7 2.0 -2.0 lv c m o s 1 8 n/a n/a -0.3 0.63 1.2 vccio + 0.3 0.7 1.7 2.0 -2.0 pci n/a n/a -0.3 0.3 x vccio 0.6 x v ccio vccio + 0.5 0.1 x vccio 0.9 x vccio 1.5 -0.5
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 31 preliminary ac characteristics all ac data is tbd
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 32 preliminary package thermal characteristics the polarpro ii device is availa ble for commercial (0c to 85c ju nction), industrial (-40c to 100c junction), and military (-55c to 125c junction) temperature ranges. thermal resistance equations: jc = (t j - t c )/p ja = (tj - ta)/p p max = (t jmax - t amax )/ ja parameter description: jc : junction-to-case thermal resistance ja : junction-to-ambient thermal resistance t j : junction temperature t a : ambient temperature p: power dissipated by the device while operating p max : the maximum power dissipation for the device t jmax : maximum junction temperature t amax : maximum ambient temperature note: maximum junction temperature (t jmax ) is 125c. to calculate the maximum power dissipation for a device package look up ja from table 25 , pick an appropriate t amax and use: p max = (125c - t amax ) / ja . moisture sensitivity level all polarpro ii devices are moisture sensitivity level 3. table 25: package thermal characteristics package description theta-ja ( c/w) device package code package type pin count 0 lfm 200 lfm 400 lfm ql2p150 pu tfbga (6 mm x 6 mm) 121 tbd tbd tbd ql2p150 pd tfbga (5 mm x 5 mm) 121 tbd tbd tbd table 26: solder composition lead type pb-free bga solder sn3agcu:sn4agcu a a. sn3agcu:sn4agcu means that ag can r ange from 3% to 4%. cu is always 0.5%.
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 33 preliminary power-up sequencing figure 26: power-up sequencing figure 26 shows an example where all vccio = 3.3 v, vp ump = 3.3 v and vlp = 1.8 v. when powering up a polarpro ii device, vcc, vccio rails must take 10 s or longer to reach the maximum value (refer to figure 26 ). ramping vcc and vccio faster than 10 s can cause the device to behave improperly . it is also important to ensure vccio and vlp ar e within 500 mv of vcc when ramping up the power supplies. in the case where vccio or vlp are greater than vcc by more than 500 mv an additional current draw can occur as vcc passes its threshold voltage. in a case where vcc is greater than vccio by more than 500 mv the protection diodes between the power su pplies become forward biased . if this occurs then there will be an additional current load on the powe r supply. having the diodes on can cause a reliability problem, since it can wear out the diodes and subsequently damage the internal transistors. programming stipulation for polarpro ii devices to correctly program, there must not be any race conditions or internally generated free-running oscillators in the design. this will ca use an icc programming failure during the programming process. quicklogic cannot guarantee the operation of any device that fails programming. therefore, race conditions and free-running oscillators must be removed from designs so that polarpro ii devices can correctly pass programming. voltage v ccio ,v pump v cc , vlp |v ccio - v cc | max time 10 us v cc
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 34 preliminary pin descriptions table 27: pin descriptions pin direction function description dedicated pin descriptions gpio(h:a) i/o general purpose input/output pin the i/o pin is a bi-directional pin, configurable to either an input-only, output-only, or bi -directional pin. the letter inside the parenthesis means that the i/o is located in the bank with that letter. if an i/ o is not used, the development software provides the option of tying that pin to gnd, vccio, or hi-z. clk(h:g) clk(d:c) i global clock network pin low skew global clock this pin provides access to a distributed network capable of driving the clock, set, r eset, all inputs to the logic cell, read and write clocks, read and write enables of the embedded ram blocks, and i/o inputs. dedclk(h) i dedicated clock network pin low skew clock this pin provides access to a distributed network capable of driving the clock, set, r eset, all inputs to the logic cell, read and write clocks, read and write enables of the embedded ram blocks, and i/o inputs. the voltage tolerance of this pin is specified by vccio. ccmin(h) i ccm clock input input clock for ccm. the voltage tolerance for this pin is specified by vccio(h). ccmvcc i power supply pin for ccm ccm input voltage level. configurable as 1.8 v only. ccmgnd i ground pin for ccm connect to ground. vlp i voltage low power active low. therefore, when vlp is 0 v, the device will go into low power mode. tie vlp to any voltage between 1.8 v and 3.3 v to disable low power mode. vpump i charge pump disable this pin disables the internal charge pump, which lowers static power consumption. to disable the charge pump, connect vpump to 3.3 v. vpump must be connected to 3.3 v for data retention to work in vlp mode. if vcc is 1.5 v, vpump must be tied to 3.3 v for vlp mode to be available. vcc i power supply pin connect to 1.8 v or 1.5 v supply. when vcc is 1.5 v, it will adversely affect the timing by 40%. vccio(h:a) i input voltage tolerance pin this pin provides the flexibility to interface the device with either a 3.3 v, 2.5 v, or 1.8 v device. the letter inside the parenthesis means t hat the vccio is located in the bank with that letter. every i/o pin in the same bank will be tolerant of the same vcci o input signals and will drive vccio level output signals. even if certain vccio banks are not used, all vccio pins must be driven when the device is powered up. gnd i ground pin connect to ground.
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 35 preliminary jtag pin descriptions tdi i test data in for jtag hold high during normal operation. connect to vccio(d) if unused. trstb i active low reset for jtag hold low during normal operation. connect to gnd if unused. during jtag, a high voltage is based on vccio(d). tms i test mode select for jtag hold high during normal operation. connect to vccio(d) if not used for jtag. tck i test clock for jtag hold high or low during normal operation. connect to vccio(d) or gnd if not used for jtag. tdo o test data out for jtag must be left unconnected if not used for jtag. the output voltage drive is specified by vccio(d). table 27: pin descriptions (continued) pin direction function description
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 36 preliminary recommended unused pin termin ations for polarpro ii devices all unused, general purpose i/o pins can be tied to vccio, gnd, or hi-z (high impedance) internally. by default, quicklogic quickworks so ftware ties unused i/os to gnd. terminate the rest of the pins at the board level as recommended in table 28 . table 28: recommended unused pin terminations signal name recommended termination clk connect to gnd or vccio(x) if unused. vlp tie vlp to any voltage between 1.8 v and 3.3 v to disable low power mode. ccmvcc if a ccm is not used, the corresponding ccmvcc must be tied to 1.8v. when a ccm is not used, the software tools will automatically configure the device to hold the ccm in a reset state. tdi connect to vccio(d) if not used for jtag. trstb connect to gnd if not used for jtag. tms connect to vccio(d) if not used for jtag tck connect to vccio(d) or gnd if not used for jtag. tdo must be left unconnected if not used for jtag.
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 37 preliminary polarpro ii ql2p150 - 121 (6 mm x 6 mm) tfbga pinout table table 29: ql2p150 - 121 (6 mm x 6 mm) tfbga pinout table pin function pin function pin function pin function a1 vcc c10 gpio(h) f8 vcc j6 gnd a2 gpio(g) c11 gpio(a) f9 gpio(a) j7 gpio(c) a3 gpio(g) d1 gpio(f) f10 gpio(a) j8 gpio(c) a4 gpio(g) d2 gpio(f) f11 gpio(a) j9 gpio(b) a5 clk(g)/gpio(g) d3 gpio(f) g1 tck j10 gpio(b) a6 dedclk(h)/gpio(h) d4 vccio(g) g2 vccio(d) j11 gpio(b) a7 gpio(h) d5 vcc g3 gpio(d) k1 gnd a8 ccmin(h)/clk(h)/gpio(h) d6 gpio(f) g4 vcc k2 gpio(e) a9 gpio(h) d7 gpio(a) g5 vccio(f) k3 gpio(d) a10 gpio(h) d8 gpio(c) g6 gnd k4 gpio(d) a11 vcc d9 gpio(h) g7 gnd k5 tdi b1 vlp d10 gpio(a) g8 vcc k6 gpio(d) b2 gpio(g) d11 gpio(a) g9 trstb k7 gpio(c) b3 gpio(g) e1 gpio(f) g10 gpio(b) k8 gpio(c) b4 gpio(g) e2 gpio(f) g11 gpio(b) k9 gpio(c) b5 gpio(g) e3 gpio(f) h1 gpio(e) k10 gpio(b) b6 tms e4 gpio(f) h2 gpio(e) k11 gpio(b) b7 gpio(h) e5 vccio(h) h3 gpio(e) l1 vcc b8 gpio(h) e6 gnd h4 gpio(e) l2 gpio(d) b9 gpio(h) e7 gnd h5 vccio(e) l3 gpio(d) b10 ccmgnd e8 vccio(a) h6 gnd l4 tdo b11 gnd e9 vccio(b) h7 vccio(d) l5 clk(c)/gpio(c) c1 gpio(f) e10 gpio(a) h8 vccio(c) l6 clk(d)/gpio(d) c2 gpio(g) e11 gpio(a) h9 vccio(d) l7 gpio(c) c3 gpio(g) f1 gpio(e) h10 gpio(b) l8 gpio(c) c4 gpio(g) f2 gpio(f) h11 gpio(b) l9 vpump c5 gpio(g) f3 gpio(f) j1 gpio(e) l10 gnd c6 gpio(h) f4 gnd j2 gpio(e) l11 vcc c7 gpio(h) f5 gnd j3 gpio(e) c8 gpio(a) f6 gnd j4 gpio(d) c9 ccmvcc f7 gnd j5 gpio(d)
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 38 preliminary polarpro ii ql2p150 - 121 (5 mm x 5 mm) tfbga pinout table table 30: ql2p150 - 121 (5 mm x 5 mm) tfbga pinout table pin function pin function pin function pin function a1 gpio(g) c10 gpio(a) f8 vccio(a) j6 gpio(c) a2 gpio(g) c11 gpio(a) f9 trstb j7 gpio(c) a3 gpio(g) d1 gpio(f) f10 gpio(a) j8 gpio(c) a4 gpio(g) d2 gpio(f) f11 gpio(a) j9 gpio(c) a5 clk(g)/gpio(g) d3 gpio(f) g1 gpio(e) j10 gpio(b) a6 dedclk(h)/gpio(h) d4 vccio(f) g2 gpio(e) j11 gpio(b) a7 gpio(h) d5 vcc g3 gpio(e) k1 gpio(e) a8 ccmin(h)/clk(h)/gpio(h) d6 vccio(g) g4 tdo k2 gpio(d) a9 gpio(h) d7 tms g5 gnd k3 gpio(d) a10 gpio(h) d8 vccio(h) g6 gnd k4 gpio(d) a11 vcc d9 gpio(a) g7 vccio(d) k5 gpio(d) b1 vlp/vccio(d) d10 gpio(a) g8 vcc k6 gpio(c) b2 gpio(g) d11 gnd g9 gpio(b) k7 gpio(c) b3 gpio(g) e1 gpio(f) g10 gpio(b) k8 gpio(c) b4 gpio(g) e2 gpio(f) g11 gpio(b) k9 gpio(c) b5 gpio(g) e3 gpio(f) h1 gpio(e) k10 gpio(b) b6 gpio(h) e4 tck h2 gpio(e) k11 gpio(b) b7 gpio(h) e5 vccio(d) h3 gpio(e) l1 gnd b8 gpio(h) e6 gnd h4 vccio(d) l2 gpio(d) b9 gpio(h) e7 gnd h5 vcc l3 gpio(d) b10 ccmgnd e8 vcc h6 vccio(c) l4 gpio(d) b11 ccmvcc e9 gpio(a) h7 tdi l5 clk(d)/gpio(d) c1 gpio(f) e10 gpio(a) h8 vccio(b) l6 clk(c)/gpio(c) c2 gpio(f) e11 gpio(a) h9 gpio(b) l7 gnd c3 gpio(g) f1 gnd h10 gpio(b) l8 gpio(c) c4 gpio(g) f2 gpio(f) h11 gpio(b) l9 gpio(c) c5 gpio(g) f3 gpio(f) j1 gpio(e) l10 vpump/vccio(d) c6 gpio(h) f4 vccio(e) j2 gpio(e) l11 vcc c7 gpio(h) f5 gnd j3 gpio(e) c8 gpio(h) f6 gnd j4 gpio(d) c9 gpio(a) f7 gnd j5 gpio(d)
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 39 preliminary polarpro ii ql2p150 - 121 tfbga pinout diagram top bottom ii ql2p150-pun121c
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 40 preliminary package mechanical drawing 121 tfbga (6 mm x 6 mm) packaging drawing
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 41 preliminary 121 tfbga (5 mm x 5 mm) packaging drawing tbd
www.quicklogic.com ? 2008 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 42 preliminary packaging information the polarpro ii ql2p150 device packaging info rmation is presented in table 31 . ordering information * lead-free packaging is denoted by the ch aracter 'n' preceding the number of pins. table 31: ql2p150 packaging options device information device ql2p150 pin pb pb-free package definitions a a. tfbga = thin profile fine pitch ball grid array 121 tfbga (6 mm x 6 mm) pitch - 0.50 mm x 121 tfbga (5 mm x 5 mm) pitch - 0.40 mm x ql 2p150 -6 pu121 c operating range: c = commercial i = industrial m = military package lead count: pun121* = 121-pin tfbga (0.5 mm) pdn121* = 121-pin tfbga (0.4 mm) speed grade: -6 - fast -7 - faster -8 - fastest part number: 2p150 quicklogic device
? 2008 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? ii device data sheet rev. a 43 preliminary contact information phone: (408) 990-4000 (us) (905) 940-4149 (canada) +(44) 1932-57-9011 (europe) +(852) 2297-2297 (asia) e-mail: info@quicklogic.com sales: www.quicklogic.com/sales support: www.quicklogic.com/support internet: www.quicklogic.com revision history notice of disclaimer quicklogic is providing this design, produc t or intellectual property "as is." by providing the de sign, product or intellectual property as one possible implementation of your desired system-level feature, application, or standard, quicklogic makes no representation that this implementation is free from any claims of infringement and any implied warranties of merchantabil ity or fitness for a particula r purpose. you are responsible for obtaining any rights you may require for your system implementa tion. quicklogic shall not be liable for any damages arising out of or in connection with the use of the de sign, product or intellectual prop erty including liability for lo st profit, business interruption, or any other damages whatsoever . quicklogic products are not designed fo r use in life-support equipment or applic ations that would cause a life-threatening situation if any such products failed . do not use quicklogic pro ducts in these types of equ ipment or applications. quicklogic does not assume any liability for errors which may ap pear in this document. however, quicklogic attempts to notify customers of such errors. quicklogic retain s the right to make changes to either the documentation, specification, or product w ithout notice. verify with quicklogic that you have the latest specifications before finalizing a product design. copyright and trademark information copyright ? 2008 quicklogic corpor ation. all rights reserved. the information contained in this document is protected by copyright. all righ ts are reserved by quicklogic corporation. quickl ogic corporation reserves the right to modify this document without an y obligation to notify any person or entity of such revision. copying, duplicating, selling, or otherwis e distributing any part of this product without the prior written consent of an authorized rep resentative of quicklogic is prohibited . quicklogic and the quicklogic logo, and quickworks are registered trademarks of quicklogic corporation; polarpro and spde are trademarks of quicklogic corporation. revision date originator and comments a march 2008 jason lew and kathleen murchek - first release.

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