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mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 1 abov semiconductor co., ltd. 4 - bit single - chip microcontrollers MC40P5004B mc40p5104b mc40p5204b mc40p5404b users manual free datasheet http:///
mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 2 revision history ver . 1. 6 ( m a r , 1 9 , 201 2 ) this book added mc40p5404br to ordering information table . added circuit guide note for ir led resistor at circuit diagrams . ver . 1. 5 ( aug 3 , 201 1 ) removed 0.1uf bypass capacitor at the application circuit diagram. ver . 1.4 .1 (dec 2 8 , 2010) added 0.1uf bypass capacitor at the application circuit diagram. ver . 1.3 (sep 3, 2010) modified supply voltage of abso lute maximum ratings. ver . 1.2 (aug 12, 2010) modified circuit diagram of MC40P5004B. added circuit diagram of mc40p5404b. added diagram of ir led current by power. ver . 1.1 (jul 16, 2010) added 16sopn package diagram. added explanation of pgnd pin as internally n.c. pin. ver . 1.0 (mar 10, 2010) first released version. version 1. 6 published by abu ? 20 1 0 abov semiconductor co., ltd. all rights reserved. additional information of this manual may be served by abov semiconductor offices in korea or distributors. abov semiconductor reserves the right to make changes to any information here in at any time without notice. the information, diagrams and other data in this manual are correct and reliable; however, abov semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 3 table of contents 1. overview ................................ ................................ ................................ ................................ ...................... 4 1.1 description ................................ ................................ ................................ ................................ ................... 4 1.2 features ................................ ................................ ................................ ................................ ........................ 4 1.3 ordering informa tion ................................ ................................ ................................ ................................ ... 5 2. block diagram ................................ ................................ ................................ ................................ ......... 6 2.1 MC40P5004B (20 pin package) ................................ ................................ ................................ ................... 6 2. 2 mc40p5104b (16 pin package) ................................ ................................ ................................ ................... 7 2.3 mc40p5204b (24 pin package) ................................ ................................ ................................ ................... 8 2.4 mc40p5404b (20 pin package) ................................ ................................ ................................ ................... 9 3. pin assignment ................................ ................................ ................................ ................................ ....... 10 4. package diagram ................................ ................................ ................................ ................................ .. 11 5. pin function ................................ ................................ ................................ ................................ ............. 14 6. port structures ................................ ................................ ................................ ................................ .. 15 7. electrical characteristics ................................ ................................ ................................ ......... 17 7.1 absolute maximum ratings (ta = 25 ) ................................ ................................ ................................ .. 17 7.2 recommended operating conditions ................................ ................................ ................................ ........ 17 7.3 electrical characteristics (ta=25 , v dd = 3v) ................................ ................................ ....................... 18 8. architecture ................................ ................................ ................................ ................................ .................. 21 8.1 program memo ry (eprom) ................................ ................................ ................................ ...................... 21 8.2 eprom address register ................................ ................................ ................................ ......................... 22 8.3 da ta memory (ram) ................................ ................................ ................................ ................................ . 23 8.4 x - register (x) ................................ ................................ ................................ ................................ ............. 24 8.5 y - register (y) ................................ ................................ ................................ ................................ ............. 24 8.6 accumulator (acc) ................................ ................................ ................................ ................................ .... 24 8.7 arithm etic and logic unit (alu) ................................ ................................ ................................ ............. 24 8.8 state counter (sc) ................................ ................................ ................................ ................................ ..... 24 8.9 clock generator ................................ ................................ ................................ ................................ ......... 25 8.10 pulse generator ................................ ................................ ................................ ................................ ........ 26 8.11 reset operation ................................ ................................ ................................ ................................ ........ 27 8.12 stop operation ................................ ................................ ................................ ................................ ....... 29 9. instruction ................................ ................................ ................................ ................................ ..................... 30 9.1 instruction table ................................ ................................ ................................ ................................ ........ 31 9.2 detail s of instruction system ................................ ................................ ................................ . 33 9.3 assembler macro ................................ ................................ ................................ ................................ ....... 46 10. spgm (serial program) ................................ ................................ ................................ ............................ 47 10.1 summary of protocol ................................ ................................ ................................ ............................... 47 option program / read data format ................................ ................................ ............................. 48 4k mtp (multi time programming) ................................ ................................ ................................ ............... 49 11. application ................................ ................................ ................................ ................................ ............ 51 mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 4 MC40P5004B mc40p5104b mc40p5204b mc40p5404b cmos single - chip 4 - bit microcontroller 1. overview 1.1 description the mc40p5x 0 4b series is 4 - bit remote control mcu which uses cmos te chnology and the 4 k bytes eprom version. this enables transmission code outputs of different con figurations, multiple custom code output, and double push key output for easy fabrication. the mc40p5x 0 4b series is suitable for remote control of tv, vcr, fans , air - conditioners, audio equipments, toys, games etc. 1.2 features ? program memory : 4,096 bytes ? mtp : 1k * 4, 2k * 2, 4k * 1 times programmable ? data memory : 32 4 bits ? 43 types of instruction set ? 3 levels of subroutine nesting ? operating frequency : 2.4mhz ~ 4mhz ? instruction cycle : f osc /48 or f osc / 12 ? cmos process (single 3.0v power supply) ? stop mode (through internal instruction) ? released stop mode by key input ? built in power - on reset circuit ? built in transis tor for i.r led drive - i ol = 2 5 0 ma at v dd = 3 v and v o =0.3v - i ol = 5 00 ma at v dd = 3 v and v o =0.52v ? built in low voltage reset circuit ? built in a watch dog timer (wdt) ? low operating voltage : 1.2 ~ 3 . 6 v (1 battery supported) ? 16 sop n, 20 sop / t s s op , 24 sop package mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 5 1.3 ordering information series mc40p5004 b d mc40p5 1 04 bm mc40p5 2 04 b d mc40p5 4 04 b d program memory 4,096 4,096 4,096 4,096 data memory 32 x 4 32 x 4 32 x 4 32 x 4 i/o ports 2 2 2 2 i nput ports 6 4 6 6 output ports 6 (d0~d5) 5 (d 2 ~d 6 ) 10 (d0~d9) 7 (d0~d6) built - in drive tr. o o o o package 20sop 16sop n 24sop 20sop series mc40p5004 br mc40p5 4 04 b d program memory 4,096 4,096 data memory 32 x 4 32 x 4 i/o ports 2 2 i nput ports 6 6 output ports 6 (d0~d5) 7 (d0~d6) built - in drive tr. o o package 20 t ssop 20 t s sop mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 6 2. block diagram 2.1 mc40p50 0 4b ( 20 pin package) program counter 3 - level stack eprom 4bank 64word 16 page 8 bit watchdog timer p ower - on reset instruction decoder m u x mux alu x - reg ram 16word 2page 4bit ram w ord selector y - reg st acc d - latch r - latch pulse generator i.r. led drive tr osc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 4 4 4 4 4 8 8 12 12 4 4 4 4 4 16 4 6 6 4 2 control signal osc1 osc2 k0 ~ k3 r0 ~ r3 d0 d1 d2 d3 d4 d5 pgnd (n.c.) remout vdd gnd mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 7 2.2 mc40p5104b ( 16 pin package) program counter 3 - level stack eprom 4bank 64word 16 page 8 bit watchdog timer p ower - on reset instruction decoder m u x mux alu x - reg ram 16word 2page 4bit ram w ord selector y - reg st acc d - latch r - latch pulse generator i.r. led drive tr osc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 4 4 4 4 4 8 8 12 12 4 4 4 4 4 16 4 6 6 4 2 control signal osc1 osc2 k0 ~ k3 r2 ~ r3 d2 d3 d4 d5 d6 remout vdd gnd mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 8 2.3 mc40p520 4b ( 24 pin package) program counter 3 - level stack eprom 4bank 64word 16 page 8 bit watchdog timer p ower - on reset instruction decoder m u x mux alu x - reg ram 16word 2page 4bit ram w ord selector y - reg st acc d - latch r - latch pulse generator i.r. led drive tr osc 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 22 23 24 1 4 4 4 4 4 8 8 12 12 4 4 4 4 4 16 4 10 10 4 2 control signal osc1 osc2 k0 ~ k3 r0 ~ r3 d0 d1 d2 d3 d4 d5 pgnd (n.c.) remout vdd gnd 19 20 21 4 d6 d7 d8 d9 mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 9 2.4 mc40p5 4 0 4b ( 20 pin package) program counter 3 - level stack eprom 4bank 64word 16 page 8 bit watchdog timer p ower - on reset instruction decoder m u x mux alu x - reg ram 16word 2page 4bit ram w ord selector y - reg st acc d - latch r - latch pulse generator osc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 4 4 4 4 4 8 8 12 12 4 4 4 4 4 16 4 7 7 4 2 control signal osc1 osc2 k0 ~ k3 r0 ~ r3 d0 d1 d2 d3 d4 d5 d6 remout vdd gnd i.r. led drive tr mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 10 3. pin assignmen t fig 3 - 1 mc40p50 04b (20 pin) remout : open drain output vpp : k3 ( pin no.7) fig 3 - 2 mc40p5 4 04b (20 pin) remout : open drain output vpp : k3 ( pin no.7) fig 3 - 3 mc40p5 2 04b (2 4 pin) remout : open drain output vpp : k 3 ( pin no. 8 ) fig 3 - 4 mc40p5 1 04b ( 16 pin) remout : open drain output vpp : k 3 ( pin no. 7 ) 1 2 3 4 5 6 7 8 9 10 20 gnd 11 12 13 14 15 16 17 18 19 osc1 osc2 scl/k0 k1 k2 vpp/k3 r0 r1 r2 r3 d5/sda d4 d3 d2 d1 d0 vdd pgnd remout 1 2 3 4 5 6 7 8 9 10 20 gnd 11 12 13 14 15 16 17 18 19 osc1 osc2 scl/k0 k1 k2 vpp/k3 r0 r1 r2 r3 d5/sda d4 d3 d2 d1 d0 vdd d6 remout 1 2 3 4 5 6 7 8 9 10 20 gnd 13 14 15 16 17 18 19 osc1 osc2 scl/k0 k1 k2 vpp/k3 r0 r1 r2 d7 d6 d5/sda d4 d3 vdd pgnd 11 12 d8 r3 d9 24 23 22 21 d2 d1 d0 mc40p50 04b mc40p5 404b mc40p5 204b remout remout 1 2 3 4 5 6 7 8 16 gnd 9 10 11 12 13 14 15 osc1 osc2 scl/k0 k1 k2 vpp/k3 r2 r3 d5/sda d4 d3 d2 vdd d6 mc40p5 104b mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 11 4. package diagram fig 4 - 1 20sop (300mil) fig 4 - 2 24sop (300mil) mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 12 fig 4 - 4 2 0 t s sop mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 13 fig 4 - 5 16 sop n mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 14 5. pin function note : d port pin mapping is mc40p5 0 0 4b ( d0~d 5 ), mc40p5 2 0 4b(d0~d9), mc40p5 4 0 4b(d0~d6), mc40p5 1 0 4b(d 2 ~d 6 ) pin i/o function vdd - connected to 1. 2~ 3.6v power supply gnd - connected to 0v power supply. k0 ~ k3 input 4 - bit input port with built in pull - up resistor. stop mode is released by "l" input of each pin. d0 ~ d 9 output each can be set and reset independently. the output is the structure of n - channel - open - drain. d0~d3 are l output mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 15 6. port structures pin i/o i/o circuit note r0 ~ r1 i - built in mos tr for pull - up, about 140 ? . r2 ~ r3 i/o - cmos output. - "h" output at reset. - built in mos tr for pull - up, about 140 ? . k0 ~ k3 i - built in mos tr for pull - up, about 140 ? . d0 ~ d 9 o - open drain output. - "l" output at reset. remout o - open drain output - output tr. disable at reset or stop . pgnd - internally n.c.(not connected) pgnd pin is just nominal for old compatibility , so this can be open or connected to any other point. mc 40p5004b/5104b/5204b/5404b m a r c h , 20 1 2 ver.1. 6 16 osc2 o - built in feedback - resistor about 1 ? osc1 i note : the gate voltage of rem out port (nmos transistor) is always higher than vdd voltage when it drives rem out port as logic low .. mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 17 7. electrical characteristics 7.1 absolute maximum ratings (ta = 25 parameter symbol max. rating unit supply voltage v dd - 0.3 ~ 5 v power dissipation p d 700 * mv storage temperature range t stq - 55 ~ 125 in - 0.3 ~ v dd +0.3 v output voltage v out - 0.3 ~ v dd +0.3 v * thermal derating above 25 : 6mw per degree rise in temperature 7.2 recommended operating conditions parameter symbol condition rating unit supply voltage v dd 2.4mhz ~ 4mhz 1.2 ~ 3.6 v operating temperature t opr - - 20 ~ +70 mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 18 7.3 electrical characteristics (ta=25 dd = 3 v) parameter symbol limits unit condition min. typ. max. input h current i ih - - 1 ua vi=v dd k pull - up resistance r pu1 70 140 300 ? pu2 70 140 300 ? fd 0.3 1.0 3.0 ? osc1 =gnd, v osc2 =vdd k, r input h voltage v ih1 2. 1 - - v - k, r input l voltage v il1 - - 0. 9 v - d, r output l voltage v ol2 *1 - 0.1 5 0. 4 v i ol =3ma osc2 output l voltage v ol3 - 0. 4 0. 9 v i ol =150ua osc2 output h voltage v oh3 2. 1 2 . 5 - v i oh = - 150ua remout output l current i ol4 * 2 - 2 5 0 5 00 - ma v ol4 =0.3v v ol4 =0.52v d, r output leakage current i olk2 - - 1 ua v 0ut =v dd , output off low voltage reset voltage v lvr - 1. 15 - v current on stop mode i stp - - 1 ua at stop mode operating supply current i dd2 * 3 - 3 ma f osc =4mhz system clock frequency f osc /48 f osc 2.4 - 4 mhz mhz version * 1 refer to fig. 7 - 1 < i ol1 vs. v ol1 graph> * 2 refer to fig. 7 - 2 < i o l4 vs. v o l4 graph> * 3 i dd1 , i dd2 , is measured at reset mode. mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 19 fig 7 - 1 . i ol2 vs. v ol2 graph. ( d, r port ) fig 7 - 2 . i ol4 vs. v ol4 graph ( rem out port with built - in transistor) mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 20 fig 7 - 3 . a pproximate ir led current (reference data of sample) (ir led : bir - bm13e4g - 2 - kr ) 0 50 100 150 200 250 300 350 400 450 500 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 ir led currnt(ma) power(v) mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 21 8. architecture 8.1 program memory (eprom) the mc40p5x 0 4b series can incorporate maximum 4 ,0 96 words ( 4 bank x 64 words x 1 6 page x 8bits) for program memory. program counter pc (a0~a5) , p age address register (a6~a9) and bank address register (a10, a11) are used to address the whole area of program memory having an instruction (8bits) to be next executed. the program memory consists of 64 words on each page, and thus each page can hold up to 64 steps of instructions. the program memory is composed as shown below fig 8 - 1 configuration of program memory 0 1 4 3 5 6 7 8 2 63 page 0 page 1 page 2 page 15 program counter (pc) page address register (pa) a0 ~ a5 0 1 2 15 stack register ( sr ) ( psr ) ( level 1 ) ( level 2 ) ( level 3 ) 6 6 a6 ~ a9 (page select) 6 a10 ~ a11 (bank select) 2 page buffer (pb) bank 0 bank 3 mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 22 8.2 eprom address register the following registers are used to address the eprom. ? page address register (pa) holds eproms page number (0~fh) and bank address (0 ~ 3h) to be addressed. ? page buffer register (pb) value of pb is loaded by an lpbi command when newly addressing a page. then it is shifted into the pa when rightly executing a branch instruction (br) and a subroutine call (cal). w hen addressing more than 1k, lpbi command must be used continuously. f ir st lpbi value will be written at lsb 4bits, second is written at msb 2 bits. fig 8 - 2 c ompare mc40p5x01 with mc40p5x 0 4b example of command flow ? program counter (pc) available for addressing word on each page. ? stack register (sr) stores returned - word address in the subroutine call mode. (1) page address reg ister and page buffer register address one of pag es #0 to #15 in the eprom by the 4 - bit binary counter. unlike the program counter, the page address register is usually unchanged so that the program will repeat on the same page unless a page changing command is issued. to change the page address, take two steps such as (1) writing in the page buffer what page to jump (execution of lpbi) and (2) execution of br or cal, because instruction code is of eight bits so that page and word can not be specified at the same time. command pa pb pc xx_xxxx xx_xxxx pc lpbi #7 ( high 2bits 00, low 4bits #7) xx_xxxx 00 _ 0111 n ext pc lpbi #3 ( high 2bits #3, low 4bits keep) xx_xxxx 11_0111 n ext pc br #2a 11_0111 11_0111 #2a mc40p5x01 mc40p5x04b pa/pb pc 4 bit 6 bit 6 bit 6 bit mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 23 in case a return instruction (r tn) is executed within the subroutine that has been called in the other page, the page address will be changed at the same time. (2) program counter this 6 - bit binary counter increments for each fetch to address a word in the currently addressed page ha ving an instruction to be next executed. for easier programming, at turning on the power, the program counter is reset to the zero location. the pa is also set to "0". then the program counter specifies the next eprom address in random sequence. when b r, cal or rtn instructions are decoded, the switches on each step are turned off not to update the address. then, for br or cal, address data are taken in from the instruction operands (a0 to a5), or for rtn, and address is fetched from stack register no . 1. (3) stack register this stack register provides three stages each for the program counter (6bits) and the page address register (4bits) so that subroutine nesting can be made on three levels. 8.3 data memory (ram) up to 32 nibbles (16 words x 2pages x 4bits) is incorporated for storing data. the whole data memory area is indirectly specified by a data pointer (x, y). page number is specified by zero bit of x register, and words in the page by 4 bits in y - register. data memory i s composed in 16 nibbl es/page. fig . 8 - 3 shows the configuration. fig 8 - 3 configuration of data memory y - register (y) x - register (x) output port page 0 page 1 0 1 2 3 15 12 13 14 0 1 4 2 4 a0 ~ a3 d0 d9 r0 r3 remout data memory page (0 ~ 1) mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 24 8.4 x - register (x) x - register is consist of 2bit, x0 is a data pointer of page in the ram, x1 is only used for selecting of d8~d9 with value of y - register x1 = 0 (x=0 or 1) x1 = 1 (x=2 or 3) y = 0 d0 d8 y = 1 d1 d9 table 8 - 1 mapping table between x and y register for port access 8.5 y - register (y) y - register has 4 bits. it operates as a data pointer or a general - purpose register. y - register specifies and address (a0~a3 ) in a page of data memory, as well as it is used to specify an output port. further it is used to specify a mode of carrier signal outputted from the remout port. it can also be treated as a general - purpose register on a program. 8.6 accumulator (acc) the 4 - bit register for holding data and calculation results. 8.7 arithmetic and logic unit (alu) in this unit, 4bits of adder/comparator are connected in parallel as it's main components and they are combined with status latch and status logic (flag.) (1) operati on circuit (alu) the adder/comparator serves fundamentally for full addition and data comparison. it executes subtraction by making a complement by p rocessing an inversed output of acc (acc +1) (2) status logic this is to bring an st, or flag to contro l the flow of a program. it occurs when a specified instruction is executed in three cases such as overflow or underflow in operation and two inputs unequal. 8.8 state counter (sc) a fundamental machine cycle timing chart is shown below. every instruction i s one byte length. its execution time is the same. execution of one instruction takes 48 clocks for fetch cycle and 48clocks for execute cycle (96 clocks in total). virtually these two cycles proceed simultaneously, and thus it is apparently completed in 48clocks (one machine cycle). exceptionally br, cal and rtn instructions is normal execution time since they change an addressing sequentially. therefore, the next instruction is prefetched so that its execution is completed within the fetch cycle. mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 25 fig 8 - 4 fundamental timing chart 8.9 clock generator the oscillator circuit is designed to operate with an external ceramic resonator. oscillator circuit is able to organize by connecting ceramic resonator to outside. * it is necessary to connect capacitor to outside in order to change ceramic resonator, you must refer to a manufacturer`s resonator matching guide. figure 8 - 5 oscillator circuit with external capacitor osc1 osc2 port no.2 port no.3 c1 c2 t2 t47 t48 t1 t2 t47 t1 t48 fetch cycle n execute cycle n execute cycle n - 1 fetch cycle n - 1 phase i phase ii phase iii machine cycle machine cycle mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 26 8.10 pulse g enerator the following frequency and duty ratio are selected for carrier signal outputted from the remout port depending on a pmr (pulse mode register) value set in a program. pmr remout signal carrier frequency (f osc = 3.64mhz) 0 t=1/f pul = 96/ f osc , t1/t = 1/2 37.9 2 khz 1 t=1/f pul = 96/ f osc , t1/t = 1/3 37.9 2 khz 2 t=1/ f pul = 64/ f osc , t1/t = 1/2 56.8 8 khz 3 t=1/ f pul = 65/ f osc , t1/t = 22/65 56.00khz 4 t=1/ f pul = 87/ f osc , t1/t = 1/3 41.8 4 khz 5 no carrier (same to inversion of d0~d9) - 6 t=1/ f pul = 91/ f osc , t1/t =31/91 40.00khz 7 t= 1/ f pul = 101 / f osc , t1/t = 34/101 36.0 4 khz *default value is 0 * f pul = carrier pulse frequency, f osc = oscillation frequency table 8 - 3 pmr selection table t t1 remout port mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 27 8.11 reset operation mc40p5x 0 4b series have three reset sources. one is a built - in power - on reset circuit, another is a built - in low vdd detection circuit, the other is the o verflow of watch dog timer wdt). all reset operations are internal in the mc40p 5 x 0 4b . 8.11.1 built - in power on reset circuit mc40p5x 0 4b series has a built - in power - on reset circuit consisting of an about 1 ? resistor and a 3pf capacitor. when the power - on reset pulse occurs, system reset signal is latched and wdt is cleared. after the overflow time of wdt(2 13 x system clock time), system reset signal is released. fig 8 - 6 power C on reset circuit and timing chart 1m 3pf counter ( wdt ) vcc gnd system resetb vcc system resetb t reset about 108m sec at f osc = 3.64mhz mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 28 8.11.2 built - in low vdd reset circuit mc40p5x 0 4b series have a low vdd detection circuit. if vdd become reset voltage of low vdd detection circuit at a active status, system reset occur and wdt is cleared. after vdd is increased upper reset voltage again, wdt is re - counted and if wdt is overflowed, system reset is released. fig 8 - 7 low voltage detection timing chart 8.11.3 watch dog timer (wdt) watch dog timer is organized binary of 14 steps. the signal of fosc /48 or fosc/12 cycle comes in the first step of wdt after wdt reset. if this counter was overflowed, reset signal automatically come out so that internal circuit is initialized. the overflow time is 8 x 6 x 2 13 /fosc (108.026ms at fosc = 3.64mhz) normally, the binary counter must be reset before the overflow by using reset instruction (wdtr), power - on reset pulse or low vdd detection pulse. * it is constantly reset in stop mode. when stop is released, counting is restarted. (refer to stop operation ) f osc /48 or 12 reset by instruction binary counter ( 14 steps ) reset (edge - trigger ) power - on reset low vdd detection about 108m sec at f osc = 3.64mhz vdd reset voltage internal resetb mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 29 8.12 stop operation stop mode can be achieved by stop instructions. in stop mode 1. oscillator is stopped, the operating current is low. 2. watch dog timer is reset, d0~d3 output are l , and remout output are high - z . 3. part of output pin other than wdt, d0~d3 and remout output have a value before come into stop mode. stop mode is released when one of k or r input is going to "l". 1. state of d0~d 7 output and remout output is return to state of before stop mode is achiev ed. 2. after 1,024 x 8 enable clocks for stable oscillating, first instruction start to operate. 3. in return to normal operation, wdt is counted from zero again. but, at executing stop instruction, if one of k or r input is chosen to "l", stop instruction is same to nop (no operation) instruction. value of x - reg value of y - reg operation 0 or 1 0 ~ 7 s0 : d(y) mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 30 9. instruction instruction format all of the 43 instruction in mc40p5x04 serie s is format in two fields of op code and operand which consist of eight bits. the following formats are available with different types of operands. *format all eight bits are for op code without operand. *format two bits are for op erand and six bits for op code. two bits of operand are used for specifying bits of ram and x - register (bit 1 and bit 7 are fixed at 0 ) *format four bits are for oper and and the others are op code. four bits of operand are used for specifying a constant loaded in ram or y - register, a comparison value of compare command, or page addressing in rom. *format six bits are for oper and and the others are op code. six bits of operand are used for word addressing in the rom. mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 31 9.1 instruction table the mc40p5x 0 4b series provides the following 43 basic instructions. category mnemonic function st *1 1 register to register lay a a s 3 laz a 0 s 4 ram to register lma m(x, y) a s 5 lmaiy m(x, y) a, y y + 1 s 6 lym y m(x, y) s 7 lam a m(x, y) s 8 xma a ? m(x, y) s 9 immediate lyi i y i s 10 lmiiy i m(x, y) i, y y + 1, s 11 lxi n x n s 12 ram bit manipulation sem n m(n) 1 s 13 rem n m(n) 0 s 14 tm n test m(n) 1 e 15 rom address br a if st = 1 then branch s 16 cal a if st = 1 then subroutine call s 17 rtn return from subroutine s 18 lpbi i pb i ( ( pb3~0 or pb 5 ~ 4 loading) * 3 s 19 arithmetic am a a + m(x, y) c 20 sm a m(x, y) C a b 21 im a m(x, y) + 1 c 22 dm a m(x, y) - 1 b 23 ia a a + 1 s 24 iy y y + 1 c mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 32 25 arithmetic da a a - 1 b 26 dy y y - 1 b 27 eorm a a m(x, y) s 28 nega a + 1 z 29 comparison alem test a m(x, y) e 30 ale i i test a i e 31 mnez test m(x, y) 0 n 32 ynea test y a n 33 ynei i test y i n 34 knez test k 0 n 35 rnez test r 0 n 36 input/ output lak a k s 37 lar a r s 38 so output(y) 1 *2 s 39 ro output(y) 0 *2 s 40 control wdtr watch dog timer reset s 41 stop stop operation s 42 lpy pmr y s 43 nop no operation s note) i = 0~f, n = 0~3, a = 6bit pc address *1 column st indicates conditions for changing status. symbols have the following meanings s: on executing an instruction, status is unconditionally set. c : status is only set when carry or borrow has occurred in operation. b: status is only set when borrow has not occurred in operation. e: status is only set when equality is found in comparison. n: status is only set when equality is not found in comparison. z : status is only set when the result is zero. *2 operation is settled by a value of y - register.. *3 lpbi instruction loads data to pb3~0 or pb 5 ~ 4 according to position. refer to abl and acall macro. mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 33 9.2 details of instruction system a ll 43 basic instructions of the mc40p5x 04b series are one by one described in detail below. description form . each instruction is headlined with its mne monic symbol according to the in structions table given earlier. then, for quick reference, it is described with basic items as shown below. after that, detailed comment follows. * items : - naming : full spelling of mnemonic symbol - status : check of status function - format : categorized into to - operand : omitted for format - function (1) lay naming : load accumulator from y - regis ter status : set format : i function : a y mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 34 (5) lmaiy naming : load memory from accumulator and increment y - register status : set format : i function : m(x,y) a, y y+1 mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 35 (10) lmiiy i naming : load memory from immediate and inc rement y - register status : set format : operand : constant 0 i 15 function : m(x,y) i, y y + 1 mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 36 (14) tm n naming : test memory bit status : comparison results to status format : operand : bit address 0 n 3 function : m(x,y,n) = 1 ? st 1 when m(x,y,n)=1, st 0 when m( x,y,n)=0 mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 37 (16) cal a naming : subroutine call on status 1 status : conditional depending on the status format : operand : subroutine code address a(addr) function : when st =1 , pc a(addr) pa pb sr1 pc + 1, psr1 pa sr2 sr1 psr2 psr1 sr3 sr2 psr3 psr2 when st = 0 , pc pc + 1 pb ps st 1 note : pc actually has pseudo - r andom count against the next instruction. mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 38 (18) lpbi i naming : load page buffer register from immediate status : set format : operand : rom page address 0 i 15 function : pb i mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 39 (22) dm naming : decrement memory and status 1 on not borrow status : carry to status format : function : a m(x,y) - 1 st 1(when m(x,y) 1) st 0 (when m(x,y) = 0) mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 40 (26) dy naming : decrement y - register and status 1 on not borrow status : carry to status format : function : y y - 1 st 1 (when y 1) st 0 (when y = 0) mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 41 (30) alei naming : accumulator less equal immediate status : carry to status format : operand : constant 0 i 15 function : a i st 1 (when a i) st 0 (when a > i) mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 42 (34) knez naming : k not equal zero status : the status is set only when not equal format : function : when k 0, st 1 mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 43 (38) so naming : set output register latch status : set format : function : d(y) 1 0 y 7 remout 0 y = 8 d0~d9 1 (high - z) y = 9 r(y) 1 ah y dh r 1 y = eh d0~d9, r 1 y = fh mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 44 (39) ro naming : reset output register latch status : set format : function : d(y) 0 0 y 7 remout 1(high - z) y = 8 d0~d9 0 y = 9 r(y) 0 ah y dh r 0 y = eh d0~d9, r 0 y = fh mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 45 (42) lpy naming : pulse mode set status : set format : function : pmr y mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 46 9.3 assembler macro (44) call a (2 or 3 byte) : l ong_call macro page call within same bank (2byte s instruction ) : lpbi i ; i = low_ page address (4bits), pb3~0(low_ page address) < -- i cal a ; see you "cal" instruction. page call out of bank (3 byte s instruction ) : lpbi i ; i = low_page address(4bits), pb3~0(low_page address) < -- i lpbi i ; i = high_page addre ss(2bits), pb5~4(high_page address) < -- i cal a ; see you "cal" instruction. (45) bl a (2 or 3 byte) : long_branch macro page branch within same bank (2byte s instruction ) : lpbi i ; i = low_ page address(4bits), pb0~3(low_page address) < -- i br a ; see you "br" instruction. page branch out of bank ( 3 byte s instruction ) : lpbi i ; i = low_page address(4bits), pb3~0(low_page address) < -- i lpbi i ; i = high_page address(2bits), pb5~4(high_page address) < -- i br a ; see y ou "br" instruction. (46) acall a (3byte) : absolute call macro full - range rom address call (3 byte s instruction ) : lpbi i ; i = low_page address(4bits), pb3~0(low_page address) < -- i lpbi i ; i = high_page address(2bits), pb5~4(high_page address) < -- i cal a ; see you "cal" instruction. (47) abl a (3byte) : absolute branch macro full - range rom address branch ( 3 byte s instruction ) : lpbi i ; i = low_page address(4bits), pb3~0(low_page address) < -- i lpbi i ; i = high_page address(2bits), pb5~4(high_page address) < -- i br a ; see you "br" instruction. * a(address) : 6bits, i (low_page address) : 4bits, i (high_page address) : 2bits bank(16pages unit) mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 47 10. spgm (serial program) 10.1 summary of protocol the i 2 c bus protocol the i 2 c bus protocol is a method of communication. it physically consists of 2 active wires. the active wires, called scl and sda, are both bi - directional. scl is the serial clock line. it is used to synchronize all data transfers over the i 2 c bus. and sda is the serial data line. the scl & sda lines are connected to all devices on the i 2 c bus. ? necessary pins (5pins) - serial data (sda) : d5 - serial clock (scl) : k 0 - programming power( vpp ) : k3 - vdd - vss mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 48 option program / read data format clksel : change the main clock fosc/48, fosc/12 (default fosc/48) . if you select fosc/12, instruction cycle is 4 times faster than fosc/48, but carrier frequency isn t affected. 0 : fosc/12 1 : fosc/48 offset : at normal mode, change the rom address ? lock : when pro gram is read by pgm - plus, data protection ? id 7 C id0 : it can be treated as user id. mc40p50 04b id: 1000 1111 b mc40p52 04b id: 1010 1111 b mc40p5 4 04b id: 1100 1111b mc40p5 1 04b id: 1 0 01 1111b for protection the written program code, in other words it can not be read, you have to clear the option bit to 0, and for this, you have to write the option register to 1111_1110b. in this time, id 7 C id0 keep the existing value without any effect id 7 id 6 id 5 id 4 id 3 id 2 id 1 id0 - - - - lock 3 lock 2 lock 1 lock 0 - - - clksel offset3 offset2 offset1 offset0 mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 49 4k mtp (multi time programming) option bit offset 4bits lock 4bits id byte id 8bit lock 4bits : block address (block 0 ~ block 3) when lock is set, 00h is read ( 0 = lock , 1 = unlock ) offset bit b l o c k 3 b l o c k 2 b l o c k 1 b l o c k 0 111 0 : cpu start address is 0x000 1st write 1k 1st write 2k 1st write 4k 11 0 0 : cpu start address is 0x400 2nd write 1k 1 0 x0 : cpu start address is 0x800 1000: 3rd write 1k 1010: 2nd write 2k 0 xx0 : cpu start address is 0xc00 0000: 4th write 1k 000 000 000 400 800 800 c00 blank programmed expired mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 50 ? case of available mtp case 1k 1k 1k 1k available 1k*4 o 2k*2 o 4k*1 o 1k, 1k, 2k x 1k, 2k o 1k, 2k, 1k x 2k, 1k, 1k o 1 st pgm 2 nd pgm 3 rd pgm 4 th pgm e xpired mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 51 11. application circuit diagram of MC40P5004B *note 1. power stabilization capacitor : is recommended to be placed as close to vdd/gnd pins as possible for better mcu operation . 2. ir led serial resistance : coin cell batteries generally causes large vdd level drop during ir led emission due to low current c apacity and high internal resistance . therefore , users ha ve to optimize the circuit conditions by adjusting ir led serial resistance to reduce ir led current and to avoid early occurrence of lvd reset and to meet a im ing ir reaching range and longer battery lifetime. mc 40p5004b/5104b/5204b/5404b ma rc h , 20 1 2 ver.1. 6 52 circuit diagram of mc40p5404b *note 1. power stabilization capacitor : is recommended to be placed as close to vdd/gnd pins as possible for better mcu operation . 2. ir led serial resistance : coin cell batteries generally causes large vdd level drop during ir led emission due to low current c apacity and high internal resistance . therefore , users ha ve to optimize the circuit conditions by adjusting ir led serial resistance to reduce ir led current and to a void early occurrence of lvd reset and to meet aim ing ir reaching range and longer battery lifetime. |
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