1/10 december 2004 stb40nf10 n-channel 100v - 0.025 ? - 50a - d2pak low gate charge stripfet?ii mosfet table 1: general features typical r ds (on) = 0.025 ? exceptional dv/dt capability low gate charge at 100c application oriented characterization 100% avalanche tested description this mosfet is the latest development of stmi- croelectronics unique ?single feature size ?? strip-based process. the resulting transistor shows extremely high packing density for low on- resistance, rugged avalance characteristics and less critical alignment steps therefore a remark- able manufacturing reproducibility. applications dc-dc & dc-ac converters motor control, audio amplifiers high current, high speed switching solenoid and relay drivers automotive environment table 2: order codes figure 1: package figure 2: internal schematic diagram type v dss r ds(on) i d STB40NF10T4 100 v < 0.028 ? 50 a 1 3 d 2 pak sales type marking package packaging STB40NF10T4 b40nf10 d 2 pak tape & reel rev.2
stb40nf10 2/10 table 3: absolute maximum ratings ( ) pulse width limited by safe operating area (*) limited by package (1) i sd 50a, di/dt 600 a/s, v dd v (br)dss , t j t jmax. (2) starting t j = 25 c, i d = 50a, v dd = 25v table 4: thermal data electrical characteristics (t case =25 c unless otherwise specified) table 5: on/off symbol parameter value unit v ds drain-source voltage (v gs = 0) 100 v v dgr drain-gate voltage (r gs = 20 k ? ) 100 v v gs gate- source voltage 20 v i d (*) drain current (continuous) at t c = 25 c 50 a i d drain current (continuous) at t c = 100 c 35 a i dm ( ) drain current (pulsed) 200 a p tot total dissipation at t c = 25 c 150 w derating factor 1 w/ c dv/dt (1) peak diode recovery voltage slope 20 v/ns e as (2) single pulse avalanche energy 150 mj t stg storage temperature ? 55 to 175 c t j operating junction temperature rthj-case thermal resistance junction-case max 1 c/w rthj-amb thermal resistance junction-ambient max 62.5 c/w t l maximum lead temperature for soldering purpose 300 c symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 100 v i dss zero gate voltage v ds = max rating 1a drain current (v gs = 0) v ds = max rating, t c = 125 c 10 a i gss gate-body leakage current (v ds = 0) v gs = 20v 100 na v gs(th gate threshold voltage v ds = v gs , i d = 250 a 22.8 4v r ds(on) static drain-source on resistance v gs = 10v, i d = 25 a 0.024 0.028 ?
3/10 stb40nf10 electrical characteristics (continued) table 6: dynamic table 7: switching on table 8: switching off table 9: source drain diode (1) pulsed: pulse duration = 300 s, duty cycle 1.5 %. (2) pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit g fs (1) forward transconductance v ds = 25v , i d = 25 a 20 s c iss input capacitance v ds = 25v, f = 1 mhz, v gs = 0 1780 pf c oss output capacitance 265 pf c rss reverse transfer capacitance 11 2 pf symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time v dd = 50 v, i d = 25 a r g =4.7 ? v gs = 10v (see test circuit, figure 3) 28 ns t r rise time 63 ns q g total gate charge v dd = 80v, i d = 50a, v gs = 10v 60.6 80 nc q gs gate-source charge 9.6 nc q gd gate-drain charge 22.8 nc symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off-delay time fall time v dd = 50 v, i d = 25 a, r g =4.7 ?, v gs = 10v (see test circuit, figure 3) 84 28 ns ns symbol parameter test conditions min. typ. max. unit i sd source-drain current 50 a i sdm (2) source-drain current (pulsed) 200 a v sd (1) forward on voltage i sd = 50 a, v gs = 0 1.3 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 50 a, di/dt = 100a/s, v dd = 25v, t j = 150 c (see test circuit, figure 5) 11 4 456 8 ns nc a
stb40nf10 4/10 figure 3: safe operating area figure 4: output characteristics figure 5: transconductance figure 6: thermal impedance figure 7: transfer characteristics figure 8: static drain-source on resistance
5/10 stb40nf10 figure 9: gate charge vs gate-source voltage figure 10: normalized gate thereshold volt- age vs temperature figure 11: source-drain diode forward char- acteristics figure 12: capacitance variations figure 13: normalized on resistance vs tem- perature figure 14: normalized breakdown voltage vs temperature
stb40nf10 6/10 figure 15: unclamped inductive load test cir- cuit figure 16: switching times test circuit for resistive load figure 17: test circuit for inductive load switching and diode recovery times figure 18: unclamped inductive wafeform figure 19: gate charge test circuit
7/10 stb40nf10 to-247 mechanical data 1 dim. mm. inch min. typ max. min. typ. max. a 4.4 4.6 0.173 0.181 a1 2.49 2.69 0.098 0.106 a2 0.03 0.23 0.001 0.009 b 0.7 0.93 0.027 0.036 b2 1.14 1.7 0.044 0.067 c 0.45 0.6 0.017 0.023 c2 1.23 1.36 0.048 0.053 d 8.95 9.35 0.352 0.368 d1 8 0.315 e 10 10.4 0.393 e1 8.5 0.334 g 4.88 5.28 0.192 0.208 l 15 15.85 0.590 0.625 l2 1.27 1.4 0.050 0.055 l3 1.4 1.75 0.055 0.068 m 2.4 3.2 0.094 0.126 r0.4 0.015 v2 0 o 4 o d 2 pak mechanical data 3
stb40nf10 8/10 tape and reel shipment (suffix ?t4?)* tube shipment (no suffix)* d 2 pak footprint * on sales type dim. mm inch min. max. min. max. a 330 12.992 b 1.5 0.059 c 12.8 13.2 0.504 0.520 d 20.2 0795 g 24.4 26.4 0.960 1.039 n 100 3.937 t 30.4 1.197 base qty bulk qty 1000 1000 reel mechanical data dim. mm inch min. max. min. max. a0 10.5 10.7 0.413 0.421 b0 15.7 15.9 0.618 0.626 d 1.5 1.6 0.059 0.063 d1 1.59 1.61 0.062 0.063 e 1.65 1.85 0.065 0.073 f 11.4 11.6 0.449 0.456 k0 4.8 5.0 0.189 0.197 p0 3.9 4.1 0.153 0.161 p1 11.9 12.1 0.468 0.476 p2 1.9 2.1 0.075 0.082 r 50 1.574 t 0.25 0.35 0.0098 0.0137 w 23.7 24.3 0.933 0.956 tape mechanical data
9/10 stb40nf10 table 10: revision history date revision description of changes 14-dec-2004 2 new stylesheet
stb40nf10 10/10 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america
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