STD40NF3LL n-channel 30v - 0.0095 w - 40a dpak low gate charge stripfet ? power mosfet preliminary data n typical r ds(on) = 0.0115 w @ 4.5v n optimal r ds(on) xq g trade-off @ 4.5v n conduction losses reduced n switching losses reduced description this application specific power mosfet is the third generation of stmicroelectronics unique osingle feature size ? o strip-based process. the resul- ting transistor shows the best trade-off between on-resistance and gate charge. when used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. this is extremely important for motherboards where fast switching and high effi- ciency are of paramount importance. applications n specifically designed and optimised for high efficiency cpu core dc/dc converters ? internal schematic diagram september 2001 absolute maximum ratings symbol parameter value un it v ds drain-source voltage (v gs =0) 30 v v dgr drain- gate voltage (r gs =20k w )30v v gs gate-source voltage 16 v i d drain current (continuous) at t c =25 o c40a i d drain current (continuous) at t c =100 o c28a i dm ( ? ) drain current (pulsed) 160 a p tot total dissipation at t c =25 o c55w derating factor 0.37 w/ o c t stg storage temperature -65 to 175 o c t j max. operating junction temperature 175 o c ( ? ) pulse width limited by safe operating area type v dss r ds(on) i d STD40NF3LL 30 v < 0.0115 w 40 a add suffix ot4o for ordering in tape & reel 1 3 dpak to-252 (suffix ot4o) 1/6
thermal data r thj-case r thj-amb t l thermal resistance junction-case max thermal resistance junction-ambient max maximum lead temperature for soldering purpose 2.73 62.5 300 o c/w o c/w o c electrical characteristics (t case =25 o c unless otherwise specified) off symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d =250 m av gs =0 30 v i dss zero gate voltage drain current (v gs =0) v ds =maxrating v ds =maxrating t c =125 o c 1 10 m a m a i gss gate-body leakage current (v ds =0) v gs = 16 v 100 na on ( * ) symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds =v gs i d = 250 m a12.5v r ds(on) static drain-source on resistance v gs =10v i d =20a v gs =4.5v i d =10a 0.0095 0.0115 0.0115 0.0135 w w i d(o n) on state drain current v ds >i d(o n) xr ds(on )ma x v gs =10v 40 a dynamic symbol parameter test conditions min. typ. max. unit g fs ( * )forward transconductance v ds >i d(o n) xr ds(on )ma x i d =20 a 40 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds =25v f=1mhz v gs = 0 1700 500 115 pf pf pf STD40NF3LL 2/6
electrical characteristics (continued) switching on symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd =15v i d =20a r g =4.7 w v gs =4.5v (resistive load, see fig. 3) 20 170 ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =24v i d =40a v gs =10v 43 10 10 56 nc nc nc switching off symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off delay time fall time v dd =15v i d =20a r g =4.7 w v gs =4.5v (resistive load, see fig. 3) 40 60 ns ns source drain diode symbol parameter test conditions min. typ. max. unit i sd i sdm ( ? ) source-drain current source-drain current (pulsed) 40 160 a a v sd ( * )forwardonvoltage i sd =40 a v gs =0 1.5 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 40 a di/dt = 100 a/ m s v dd =15v t j =150 o c (see test circuit, fig. 5) 40 52 2.4 ns nc a ( * ) pulsed: pulse duration = 300 m s, duty cycle 1.5 % ( ? ) pulse width limited by safe operating area STD40NF3LL 3/6
fig. 1: unclamped inductive load test circuit fig. 3: switching times test circuits for resistive load fig. 2: unclamped inductive waveform fig. 4: gate charge test circuit fig. 5: test circuit for inductive load switching and diode recovery times STD40NF3LL 4/6
dim. mm inch min. typ. max. min. typ. max. a 2.2 2.4 0.086 0.094 a1 0.9 1.1 0.035 0.043 a2 0.03 0.23 0.001 0.009 b 0.64 0.9 0.025 0.035 b2 5.2 5.4 0.204 0.212 c 0.45 0.6 0.017 0.023 c2 0.48 0.6 0.019 0.023 d 6 6.2 0.236 0.244 e 6.4 6.6 0.252 0.260 g 4.4 4.6 0.173 0.181 h 9.35 10.1 0.368 0.397 l2 0.8 0.031 l4 0.6 1 0.023 0.039 == d l2 l4 13 == b e == b2 g 2 a c2 c h a1 detail oao a2 detail oao to-252 (dpak) mechanical data 0068772-b STD40NF3LL 5/6
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics ? 2001 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com STD40NF3LL 6/6
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