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| geometry process details principal device types cjd32c tip32c gross die per 4 inch wafer 2,630 process CP608 power transistor pnp - amp/switch transistor chip process epitaxial planar die size 66 x 66 mils die thickness 12.5 1.0 mils base bonding pad area 12 x 24 mils emitter bonding pad area 11 x 14 mils top side metalization al - 50,000? back side metalization cr/ni/ag - 16,000? backside collector www.centralsemi.com r4 (22-march 2010)
process CP608 typical electrical characteristics www.centralsemi.com r4 (22-march 2010) |
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