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description the CXP80732A/80740a is a cmos 8-bit micro- computer which consists of a/d converter, serial interface, timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit, pwm generator, pwm for tuner, viss/vass circuit, 32khz timer/event counter, remote control receiving circuit, vcr vertical sync separation circuit and the measuring circuit which measure signals of capstan fg and drum fg/pg and other servo systems, as well as basic configurations like 8-bit cpu, rom, ram and i/o port. they are integrated into a single chip. also CXP80732A/80740a provides sleep/stop function which enables to lower power consumption and ultra- low speed instruction mode in 32khz operation. features a wide instruction set (213 instructions) which cover various types of data ?16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction minimum instruction cycle during operation 250ns/16mhz (supply voltage 4.5 to 5.5v) during operation 122 s/32khz incorporated rom capacity 32k bytes (CXP80732A) 40k bytes (cxp80740a) incorporated ram capacity 800 bytes peripheral functions ?a/d converter 8-bit, 12-channel, successive approximation system (conversion time 20.0 s/16mhz) ?serial interface incorporated 8-bit and 8-stage fifo, 1-channe (1 to 8 bytes auto transfer) 8-bit serial i/o, 1-channel ?timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32khz timer/counter ?high precision timing pattern generator ppg 19 pins 32-stage programmable rtg 5-pins 2-channel ?pwm/da gate output 12-bit, 2-channel (repetitive frequency 62khz/16mhz) ?servo input control capstan fg, drum fg/pg, ctl input ?vsync separator ?frc capture unit incorporated 26-bit and 8-stage fifo ?pwm output 14-bit, 1-channel ?viss/vass circuit pulse duty auto detection circuit ?remote control receiving circuit 8-bit pulse measuring counter, 6-stage fifo interruption 21 factors, 15 vectors, multi-interruption possible ? standby mode sleep/stop package 100-pin plastic qfp/lqfp piggyback/evaluation chip cxp87700 100-pin ceramic qfp/lqfp ?1 CXP80732A/80740a e94z09-st cmos 8-bit single chip microcomputer sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 100 pin qfp (piastic) 100 pin lqfp (piastic) structure silicon gate cmos ic
? 2 CXP80732A/80740a a p a 0 t o p a 7 p b 0 t o p b 7 p c 0 t o p c 7 p d 0 t o p d 7 p e 0 t o p e 1 p e 2 t o p e 7 p f 0 t o p f 3 p f 4 t o p f 7 p g 0 t o p g 7 p i 1 t o p i 7 p j 0 t o p j 7 v s s v d d m p r s t x t a l e x t a l c l o c k g e n e r a t o r / s y s t e m c o n t r o l r a m 8 0 0 b y t e s s p c 7 0 0 c p u c o r e r o m 3 2 k / 4 0 k b y t e s i n t e r r u p t c o n t r o l l e r 2 2 3 2 k h z t i m e r / c o u n t e r f i f o f r c c a p t u r e u n i t p r o g r a m m a b l e p a t t e r n g e n e r a t o r r a m 2 5 1 9 a v s s a v r e f a v d d 2 a / d c o n v e r t e r s e r i a l i n t e r f a c e u n i t ( c h 0 ) f i f o 8 b i t t i m e r / c o u n t e r 0 8 b i t t i m e r 1 v s y n c s e p a r a t o r 1 4 b i t p w m g e n e r a t o r 1 2 b i t p w m g e n e r a t o r c h 0 s e r v o i n p u t c o n t r o l c a p s t a n d r u m c t l 2 3 2 1 2 b i t p w m g e n e r a t o r c h 1 4 p e 7 / d a b 1 p e 5 / d a a 1 p e 3 / p w m 1 p e 6 / d a b 0 p e 4 / d a a 0 p e 2 / p w m 0 p i 2 / p w m p i 1 / r m c p g 3 / p b c t l p g 2 / d p g p g 1 / d f g p g 0 / c f g p g 7 / e x i 1 p g 6 / e x i 0 p g 5 / s y n c 1 p g 4 / s y n c 0 p i 3 / t o / d d o p e 1 / e c p i 5 / s c k 1 p i 6 / s o 1 p i 7 / s i 1 s c k 0 s o 0 s i 0 c s 0 a n 0 t o a n 3 r e a l t i m e p u l s e g e n e r a t o r p e 1 / i n t 2 p e 0 / i n t 0 p i 4 / i n t 1 / n m i 1 2 8 p o r t a 8 p o r t b 8 p o r t c 8 p o r t d 6 2 p o r t e 4 4 p o r t f 8 p o r t g 8 p o r t h 7 p o r t i p h 0 t o p h 7 t x t e x a n m i p r e s c a l e r / t i m e b a s e t i m e r v i s s / v a s s r e m o c o n i n p u t f i f o s e r i a l i n t e r f a c e u n i t ( c h 1 ) c h 0 c h 1 8 p o r t j p i 3 / a d j p a 0 / p p o 0 p c 2 / p p o 1 8 t o p c 3 / r t o 3 p c 7 / r t o 7 t o p f 0 / a n 4 p f 7 / a n 1 1 t o block diagram ? 3 CXP80732A/80740a pin configuration 1 (top view) 100 pin qfp package p b 5 / p p o 1 3 p b 4 / p p o 1 2 p b 3 / p p o 1 1 p b 2 / p p o 1 0 p b 1 / p p o 9 p b 0 / p p o 8 p c 7 / r t o 7 p c 6 / r t o 6 p c 5 / r t o 5 p c 4 / r t o 4 p c 3 / r t o 3 p c 2 / p p o 1 8 p c 1 / p p o 1 7 p c 0 / p p o 1 6 p j 7 p j 6 p j 5 p j 4 p j 3 p j 2 p j 1 p j 0 p d 7 p d 6 p d 5 p d 4 p d 3 p d 2 p d 1 p d 0 p i 6 / s o 1 p i 7 / s i 1 p e 0 / i n t 0 p e 1 / e c / i n t 2 p e 2 / p w m 0 p e 3 / p w m 1 p e 4 / d a a 0 p e 5 / d a a 1 p e 6 / d a b 0 p e 7 / d a b 1 p g 0 / c f g p g 1 / d f g p g 2 / d p g p g 3 / p b c t l p g 4 / s y n c 0 p g 5 / s y n c 1 p g 6 / e x i 0 p g 7 / e x i 1 a n 0 a n 1 a n 2 a n 3 p f 0 / a n 4 p f 1 / a n 5 p f 2 / a n 6 p f 3 / a n 7 a v d d a v r e f a v s s p f 4 / a n 8 p b 6 / p p o 1 4 p b 7 / p p o 1 5 p a 0 / p p o 0 p a 1 / p p o 1 p a 2 / p p o 2 p a 3 / p p o 3 p a 4 / p p o 4 p a 5 / p p o 5 p a 6 / p p o 6 p a 7 / p p o 7 n c v d d v s s t x t e x p i 1 / r m c p i 2 / p w m p i 3 / t o / d d o / a d j p i 4 / i n t 1 / n m i p i 5 / s c k 1 p h 7 p h 6 p h 5 p h 4 p h 3 p h 2 p h 1 p h 0 m p r s t v s s x t a l e x t a l c s 0 s i 0 s o 0 s c k 0 p f 7 / a n 1 1 p f 6 / a n 1 0 p f 5 / a n 9 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 1 8 1 8 2 8 3 8 4 8 8 8 7 8 6 8 5 8 9 9 0 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 1 9 2 9 3 note) 1. nc (pin 90) is always connected to v dd . 2. vss (pins 41 and 88) are both connected to gnd. ? 4 CXP80732A/80740a pin configuration 2 (top view) 100 pin lqfp package p b 3 / p p o 1 1 p b 2 / p p o 1 0 p b 1 / p p o 9 p b 0 / p p o 8 p c 7 / r t o 7 p c 6 / r t o 6 p c 5 / r t o 5 p c 4 / r t o 4 p c 3 / r t o 3 p c 2 / p p o 1 8 p c 1 / p p o 1 7 p c 0 / p p o 1 6 p j 7 p j 6 p j 5 p j 4 p j 3 p j 2 p j 1 p j 0 p d 7 p d 6 p d 5 p d 4 p d 3 p e 1 / e c / i n t 2 p e 2 / p w m 0 p e 3 / p w m 1 p e 4 / d a a 0 p e 5 / d a a 1 p e 6 / d a b 0 p e 7 / d a b 1 p g 0 / c f g p g 1 / d f g p g 2 / d p g p g 3 / p b c t l p g 4 / s y n c 0 p g 5 / s y n c 1 p g 6 / e x i 0 p g 7 / e x i 1 a n 0 a n 1 a n 2 a n 3 p f 0 / a n 4 p f 1 / a n 5 p f 2 / a n 6 p f 3 / a n 7 a v d d a v r e f p b 4 / p p o 1 2 p b 5 / p p o 1 3 p b 6 / p p o 1 4 p b 7 / p p o 1 5 p a 0 / p p o 0 p a 1 / p p o 1 p a 2 / p p o 2 p a 3 / p p o 3 p a 4 / p p o 4 p a 5 / p p o 5 p a 6 / p p o 6 p a 7 / p p o 7 n c v d d v s s t x t e x p i 1 / r m c p i 2 / p w m p i 3 / t o / d d o / a d j p i 4 / i n t 1 / n m i p i 5 / s c k 1 p i 6 / s o 1 p i 7 / s i 1 p e 0 / i n t 0 p d 2 p d 1 p d 0 p h 7 p h 6 p h 5 p h 4 p h 3 p h 2 p h 1 p h 0 m p r s t v s s x t a l e x t a l c s 0 s i 0 s o 0 s c k 0 p f 7 / a n 1 1 p f 6 / a n 1 0 p f 5 / a n 9 p f 4 / a n 8 a v s s 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 1 7 6 7 7 7 8 7 9 8 0 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 8 1 8 2 8 3 8 4 8 8 8 7 8 6 8 5 8 9 9 0 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 1 9 2 9 3 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 7 3 7 4 7 5 note) 1. nc (pin 88) is always connected to v dd . 2. vss (pins 39 and 86) are both connected to gnd. ? 5 CXP80732A/80740a output/ real time output output/ real time output i/o/ real time output i/o/ real time output i/o input/input input/input/input output/output output/output output/output output/output output/output output/output input input/input output/input i/o ouput input input (port a) 8-bit output port. data is gated with ppo contents by or-gate and they are output. (8 pins) (port b) 8-bit output port. data is gated with ppo contents by or-gate and they are output. (8 pins) (port c) 8-bit i/o port, enables to specify i/o by bit unit. data is gated with ppo or rto contents by or-gate and they are output. (8 pins) (port d) 8-bit i/o port. enable to specify i/o by 4-bit unit. enables to drive 12ma sink current. (8 pins) (port e) 8-bit port. lower 2 bits are input pins and upper 6 bits are output pins. (8 pins) analog input pins to a/d converter. (12 pins) (port f) lower 4 bits are input port and upper 4 bits are output port. lower 4 bits also serve as standby release input pin. (8 pins) serial clock (ch0) i/o pin. serial data (ch0) output pin. serial data (ch0) input pin. serial chip select (ch0) input pin. external event input pin for timer/counter. input pin to request external interruption. active when falling edge. input pin to request external interruption. active when falling edge. pwm output pins. (2 pins) da gate pulse output pins. (4 pins) programmable pattern generator (ppg) output. functions as high precision real time pulse output port. (19 pins) real time pulse generator (rtg) output. functions as high precision real time pulse output port. (5 pins) symbol i/o description pa0/ppo0 to pa7/ppo7 pb0/ppo8 to pb7/ppo15 pc0/ppo16 to pc2/ppo18 pc3/rto3 to pc7/rto7 pd0 to pd7 pe0/int0 pe1/ec/int2 pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 an0 to an3 pf0/an4 to pf3/an7 pf4/an8 to pf7/an11 sck0 so0 si0 cs0 pin description ? 6 CXP80732A/80740a pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0 pg5/sync1 pg6/exi0 pg7/exi1 ph0 to ph7 pi1/rmc pi2/pwm pi3/to/ ddo/adj pi4/int1/ nmi pi5/sck1 pi6/so1 pi7/si1 pj0 to pj7 extal xtal tex tx rst mp av dd av ref avss v dd vss input/input input/input input/input input/input input/input input/input input/input input/input output i/o/input i/o/output i/o/output/ output/output i/o/input/input i/o/i/o i/o/output i/o/input i/o input output input output input input input capstan fg input pin. drum fg input pin. drum pg input pin. playback ctl pulse input pin. composite sync signal input pin. external input pin to frc capture unit. (port g) 8-bit input port. (8 pins) (port h) 8-bit output port ; medium withstand voltage (12v) and high current (12ma), n-ch open drain output. (8 pins) remote control receiving circuit input pin. 14-bit pwm output pin. timer/counter, ctl duty detection, 32khz oscillation adjustment output pin. input pin to request external interruption and non maskable interruption. active when falling edge. serial clock (ch1) i/o pin. serial data (ch1) output pin. serial data (ch1) input pin. (port i) 7-bit i/o port. i/o port can be specified by bit unit. (7 pins) (port j) 8-bit i/o port. function as standby release input can be specified by bit unit. i/o can be specified by bit unit. connecting pin of crystal oscillator for system clock. when supplying the external clock, input the external clock to extal pin and input opposite phase clock to xtal pin. connecting pin of crystal oscillator for 32khz timer clock. when used as event counter, input to tex pin and leave tx pin open. (feedback resistor is not removed.) system reset pin of active "l" level. microprocessor mode input pin. always connect to gnd. positive power supply pin of a/d converter. reference voltage input pin of a/d converter. gnd pin of a/d converter. positive power supply pin. gnd pin. connect both vss pins to gnd. symbol i/o description ? 7 CXP80732A/80740a d a t a b u s r d ( p o r t d ) a a a a a a a a a a p o r t d d i r e c t i o n a a a a a a a a p o r t d d a t a h i g h c u r r e n t 1 2 m a i p ( e v e r y 4 b i t s ) a a a a p d 0 t o 3 p d 4 t o 7 p p o , r t o d a t a d a t a b u s r d ( p o r t c ) a a a a a a p o r t c d i r e c t i o n a a a a a a a a p o r t c d a t a i n p u t p r o t e c t i o n c i r c u i t i p ( e v e r y b i t ) a a a a port c 16 pins hi-z hi-z when reset pa0/ppo0 to pa7/ppo7 pb0/ppo8 to pb7/ppo15 pc0/ppo16 to pc2/ppo18 pc3/rto3 to pc7/rto7 port d 8 pins 8 pins hi-z pd0 to pd7 a a a a a a a a a a a a p p o d a t a d a t a b u s o u t p u t b e c o m e s a c t i v e f r o m h i g h i m p e d a n c e b y d a t a w r i t i n g t o p o r t r e g i s t e r . p o r t a o r p o r t b r d input/output circuit formats for pins port a port b pin circuit format ? 8 CXP80732A/80740a r d ( p o r t f ) d a t a b u s a a a a a a a a i p i n p u t m u l t i p l e x e r a / d c o n v e r t e r 2 pins hi-z hi-z pin when reset circuit format pe0/int0 pe1/ec/int2 pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 4 pins 2 pins 4 pins hi-z hi-z h level pe6/dab0 pe7/dab1 d a t a b u s r d ( p o r t e ) a a a a a a a a a a a a a a a a a a a a a a a a d a g a t e o u t p u t h i - z c o n t r o l m p x a a a a a a a a p o r t e d a t a p o r t / d a o u t p u t s e l e c t d a t a b u s r d ( p o r t e ) a a a a a a a a a a a a a a a a a a d a g a t e o u t p u t o r p w m o u t p u t h i - z c o n t r o l m p x a a a a p o r t e d a t a p o r t / d a o u t p u t s e l e c t a a a a a a i p r d ( p o r t e ) d a t a b u s s c h m i t t i n p u t port e an0 to an3 a a a a a a i p a / d c o n v e r t e r i n p u t m u l t i p l e x e r 4 pins pf0/an4 to pf3/an7 port f port e port e ? 9 CXP80732A/80740a 4 pins hi-z pin when reset circuit format pf4/an8 to pf7/an11 a / d c o n v e r t e r d a t a b u s r d ( p o r t f ) a a a a a a a a a a a a p o r t / a d s e l e c t i p a a a a a a a a a a a a p o r t f d a t a i n p u t m u l t i p l e x e r port f 8 pins hi-z pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0 pg5/sync1 pg6/exi0 pg7/exi1 a a a a i p r d ( p o r t g ) d a t a b u s s c h m i t t i n p u t s e r v o i n p u t n o t e ) f o r p g 4 / s y n c 0 , p g 5 / s y n c 1 , c m o s s c h m i t t i n p u t a n d t t l s c h m i t t i n p u t c a n b e s e l e c t e d w i t h t h e m a s k o p t i o n . port g 8 pins hi-z ph0 to ph7 d a t a b u s r d ( p o r t h ) a a a a a a a a a a a a p o r t h d a t a h i g h c u r r e n t 1 2 m a m e d i u m w i t h s t a n d v o l t a g e 1 2 v port h 2 pins hi-z pi2/pwm pi3/to/ ddo/adj a a a a a a a a a a p i 2 f r o m 1 4 - b i t p w m p i 3 f r o m t i m e r / c o u n t e r , c t l d u t y d e t e c t i o n c i r c u i t , 3 2 k h z t i m e r m p x a a a a a a a a p o r t i d a t a a a i p d a t a b u s r d ( p o r t i ) a a a a a a a a p o r t i d i r e c t i o n a a a a a a a a p o r t i f u n c t i o n s e l e c t port i ? 10 CXP80732A/80740a s o 0 o u t p u t e n a b l e a a a a s o 0 f r o m s i o 3 pins hi-z hi-z pin when reset circuit format pi1/rmc pi4/int1/nmi pi7/si1 pi5/sck1 pi6/so1 2 pins 8 pins 1 pin hi-z hi-z hi-z pj0 to pj7 a a a a s t a n d b y r e l e a s e a a a a p o r t j d a t a a a i p d a t a b u s r d ( p o r t j ) a a a a a a a a p o r t j d i r e c t i o n a e d g e d e t e c t i o n a a a a a a a a a a m p x a a a a a a a a p o r t i d a t a a a i p d a t a b u s r d ( p o r t i ) a a a a p o r t i d i r e c t i o n a a a a a a a a p o r t i f u n c t i o n s e l e c t a a a a a a m p x t o s e r i a l c h 1 n o t e ) p i 5 i s s c h m i t t i n p u t p i 6 i s i n v e r t e r i n p u t f r o m s e r i a l c h 1 a a a a a a a a a a a a p o r t i d a t a a a i p d a t a b u s r d ( p o r t i ) a a a a a a a a p o r t i d i r e c t i o n s c h m i t t i n p u t p i 1 t o r e m o t e c o n t r o l c i r c u i t p i 4 t o i n t e r r u p t i o n c i r c u i t p i 7 t o s e r i a l c h 1 port j cs0 si0 a a a a a a i p s c h m i t t i n p u t t o s i o 2 pins so0 port i port i ? 11 CXP80732A/80740a 2 pins oscillation pin when reset circuit format extal xtal a a a a a i p a a a a e x t a l x t a l s h o w s t h e c i r c u i t c o m p o s i t i o n d u r i n g o s c i l l a t i o n . f e e d b a c k r e s i s t o r i s r e m o v e d d u r i n g s t o p . x t a l b e c o m e s " h " l e v e l . 2 pins oscillation tex tx a a a a a i p a a a a t e x t x s h o w s t h e c i r c u i t c o m p o s i t i o n d u r i n g o s c i l l a t i o n . f e e d b a c k r e s i s t o r i s r e m o v e d d u r i n g 3 2 k h z o s c i l l a t i o n c i r c u i t s t o p b y s o f t w a r e . a t t h i s t i m e t e x p i n o u t p u t s " l " l e v e l a n d t x p i n o u t p u t s " h " l e v e l . 3 2 k h z t i m e r c o u n t e r 1 pin hi-z sck0 s c k 0 o u t p u t e n a b l e a a a a i n t e r n a l s e r i a l c l o c k f r o m s i o a a a a i p s c h m i t t i n p u t e x t e r n a l s e r i a l c l o c k t o s i o 1 pin hi-z mp a a a a a a i p c p u m o d e 1 pin l level rst a a a a a a a a i p s c h m i t t i n p u t p u l l - u p r e s i s t o r m a s k o p t i o n o p ? 12 CXP80732A/80740a * 1) av dd and v dd should be set to a same voltage. * 2) v in and v out should not exceed v dd + 0.3v. * 3) the high current operation transistors are the n-ch transistors of the pd and ph ports. note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should better take place under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. supply voltage input voltage output voltage medium withstand output voltage high level output current high level total output current low level total output current operating temperature storage temperature allowable power dissipation v dd av dd av ss v in v out v outp i oh i oh i ol i olc i ol topr tstg p d low level output current ?.3 to +7.0 avss to +7.0 * 1 ?.3 to +0.3 ?.3 to +7.0 * 2 ?.3 to +7.0 * 2 ?.3 to +15.0 ? ?0 15 20 130 ?0 to +75 ?5 to +150 600 380 v v v v v v ma ma ma ma ma c c mw ph pin total of output pins other than high current output pins: per pin high current port pin * 3 : per pin total of output pins qfp package type lqfp package type item symbol rating unit remarks absolute maximum ratings (vss = 0v) ? 13 CXP80732A/80740a analog power supply high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 5.5 5.5 v dd v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.8 0.4 +75 v v v v v v v v v v v v v c item symbol min. max. unit remarks 4.5 3.5 2.7 2.5 4.5 0.7v dd 0.8v dd 2.2 v dd ?0.4 0 0 0 ?.3 ?0 av dd v ih v ihs v ihts v ihex v il v ils v ilts v ilex topr guaranteed range during high speed mode (1/2 dividing clock) operation guaranteed range during low speed mode (1/16 dividing clock) operation guaranteed operation range by tex clock guaranteed data hold operation range during stop * 1 * 2 cmos schmitt input * 3 ttl schmitt input * 4 extal pin * 5 tex pin * 6 * 2 cmos schmitt input * 3 ttl schmitt input * 4 extal pin * 5 tex pin * 6 v dd * 1) av dd and v dd should be set to a same voltage. * 2) normal input port (each pin of pc, pd, pe0 to pe1, pf0 to pf3, pg, pi and pj), mp pin. * 3) each pin of cs0, si0, sck0, rst, pe0/int0, pe1/ec/int2, pg (for pg4 and pg5, when cmos schmitt input is selected with mask option), pi1/rmc, pi4/int1/nmi, pi5/sck1 and pi7/si1. * 4) each pin of pg4 and pg5 (when ttl schmitt input is selected with mask option) * 5) it specifies only when the external clock is input. * 6) it specifies only when the event count clock is input. recommended operating conditions (vss=0v) ? 14 CXP80732A/80740a v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v high level output voltage 4.0 3.5 0.5 ?.5 0.1 ?.1 ?.5 v v v v v a a a a a a a pd, ph pa to pd, pe2 to pe7, pf4 to pf7, ph (v ol only) pi1 to pi7 pj, so0, sck0 extal tex rst * 1 item symbol pins conditions min. other than v dd , vss, av dd , and avss clock 1mhz 0v other than the measured pins v dd i dd1 i iz i loh i dds1 i dd2 i dds2 i dds3 c in v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current typ. 0.4 0.6 1.5 40 ?0 10 ?0 ?00 10 50 max. unit electrical characteristics dc characteristics (ta = ?0 to +75 c, vss = 0v) * 1) rst pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. * 2) when entire output pins are open. * 3) when setting upper 2 bits (cpu clock selection) of clock control register clc (address: 00fe h ) to "00" and operating in high speed mode (1/2 dividing clock). v dd = 5v 0.5v * 3 sleep mode v dd = 5v 0.5v v dd = 5v 0.5v supply current * 2 input capacity v dd = 5.5v, v il = 0.4v v dd = 5.5v, v i = 0, 5.5v v dd = 5.5v v oh = 12v 16mhz crystal oscillation (c 1 =c 2 =15pf) stop mode (extal and tex pins oscillation stop) i/o leakage current open drain output leakage current (n-ch tr off in state) pa to pg, pi, pj, mp an0 to an3, cs0, si0, so0 sck0, rst * 1 ph 22 1.1 33 7 10 45 8 100 30 10 20 ma ma a a a pf v dd =3v 0.3v sleep mode v dd = 3v 0.3v 32khz crystal oscillation (c 1 =c 2 =47pf) ? 15 CXP80732A/80740a * t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2-bit = ?0?, 4000/fc (upper 2-bit = ?1?, 16000/fc (upper 2-bit = ?1? e x t a l t x h t x l t c f t c r 0 . 4 v v d d 0 . 4 v 1 / f c a a a a a a a a a a a a a a a e x t e r n a l c l o c k e x t a l x t a l 7 4 h c 0 4 a a a a a a a a a a a a c r y s t a l o s c i l l a t i o n c e r a m i c o s c i l l a t i o n e x t a l x t a l c 1 c 2 a a a a a a a a a a a a a a a 3 2 k h z c l o c k a p p l y i n g c o n d i t i o n c r y s t a l o s c i l l a t i o n t e x t x c 1 c 2 ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise and fall times event count clock input pulse width event count clock input rise and fall times system clock frequency event count clock input pulse width event count clock input rise and fall times f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal xtal extal xtal extal ec ec tex tx tex tex mhz ns ns ns ns khz s ms item symbol pins conditions unit fig. 1, fig. 2 fig. 1, fig. 2 (external clock drive) fig. 1, fig. 2 (external clock drive) fig. 3 fig. 3 fig. 2 v dd = 2.7 to 5.5v (32khz clock applied condition) fig. 3 fig. 3 min. 1 28 t sys 4 * 32.768 10 max. 16 200 20 20 (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) fig. 1. clock timing fig. 2. clock applied condition t e x e c t e h t e l t e f t e r 0 . 2 v d d 0 . 8 v d d t t h t t l t t f t t r fig. 3. event count clock timing ? 16 CXP80732A/80740a input mode output mode input mode output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode chip select transfer mode (sck0 = output mode) chip select transfer mode (sck0 = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2-bit = ?0?, 4000/fc (upper 2-bit = ?1?, 16000/fc (upper 2-bit = ?1? note 2) the load of sck0 output mode and so0 output delay time is 50pf + 1ttl. (2) serial transfer (ch0) (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item cs0 ? sck0 delay time cs0 - ? sck0 floating delay time cs0 ? so0 delay time cs0 - ? so0 floating delay time cs0 high level width sck0 cycle time sck0 high and low level widths si0 input setup time (against sck0 - ) si0 input hold time (against sck0 - ) sck0 ? so0 delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 ns ns ns ns ns symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc ?50 100 200 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns t sys + 200 100 max. unit condition ? 17 CXP80732A/80740a fig. 4. serial transfer ch0 timing c s 0 s c k 0 0 . 2 v d d 0 . 8 v d d t w h c s t d c s k t d c s k f 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d t k c y t k l t k h 0 . 8 v d d 0 . 2 v d d s i 0 t s i k t k s i i n p u t d a t a t d c s o t k s o t d c s o f o u t p u t d a t a 0 . 8 v d d 0 . 2 v d d s o 0 ? 18 CXP80732A/80740a fig. 5. serial transfer ch1 timing s c k 1 s i 1 s o 1 t k c y t k l t k h 0 . 2 v d d 0 . 8 v d d t s i k t k s i t k s o i n p u t d a t a o u t p u t d a t a 0 . 2 v d d 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d serial transfer (ch1) (ta=?0 to +75 c, v dd =4.5 to 5.5v, vss=0v) item symbol pins min. max. unit conditions sck1 cycle time sck1 high and low level widths si1 input setup time (against sck1 - ) si1 input hold time (against sck1 - ) sck1 ? so1 delay time t kcy t kh t kl t sik t ksi t kso sck1 sck1 si1 si1 so1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 1000 16000/fc 400 8000/fc ?50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns note) the load of sck1 output mode and so1 output delay time is 50pf + 1ttl. ? 19 CXP80732A/80740a t conv t samp v ref v ian i ref i refs ta=25 c v dd = av dd = av ref = 5.0v v ss = av ss = 0v operating mode sleep mode stop mode 32khz operating mode resolution linearity error absolute error conversion time sampling time reference input voltage analog input voltage av ref current av ref 160/f adc * 12/f adc * av dd ?0.5 0 0.6 item symbol pins conditions min. typ. max. unit (3) a/d converter characteristics (ta = ?0 to +75 c, v dd = av dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = av ss = 0v) 8 1 2 av dd 1.0 10 bits lsb lsb s s v v ma a a n a l o g i n p u t l i n e a r i t y e r r o r v f t v z t 0 0 h 0 1 h f e h f f h d i g i t a l c o n v e r s i o n v a l u e * t h e v a l u e o f f a d c i s a s f o l l o w s b y s e l e c t i n g a d c o p e r a t i o n c l o c k ( m s c : a d d r e s s 0 1 f f h b i t 0 ) . w h e n p s 2 i s s e l e c t e d , f a d c = f c / 2 w h e n p s 1 i s s e l e c t e d , f a d c = f c fig. 6. definitions of a/d converter terms av ref an0 to an11 ? 20 CXP80732A/80740a external interruption high and low level widths reset input low level width int0 int1 int2 nmi pj0 to pj7 rst 1 32/fc s s item symbol pins conditions min. max. unit t ih t il t rsl (4) interruption, reset input (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) 0 . 2 v d d 0 . 8 v d d t i h t i l i n t 0 i n t 1 i n t 2 n m i p j 0 t o p j 7 ( d u r i n g s t a n d b y r e l e a s e i n p u t ) ( f a l l i n g e d g e ) fig. 7. interruption input timing t r s l 0 . 2 v d d r s t fig. 8. reset input timing (5) others (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item cfg input high and low level widths dfg input high and low level widths dpg minimum pulse width dpg minimum removal time pbctl input high and low level widths exi input high and low level widths t cfh t cfl t dfh t dfl t dpw t rem t cth t ctl t eih t eil cfg dfg dpg dpg pbctl exi0 exi1 ns ns ns ns ns ns symbol pins min. t frc 24 + 200 t frc 8 + 200 50 50 t frc 8 + 200 + t sys t frc 8 + 200 + t sys max. unit t sys = 2000/fc t sys = 2000/fc conditions note) t sys indicates three values according to the contents of the clock control register (address; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2-bit = ?0?, 4000/fc (upper 2-bit = ?1?, 16000/fc (upper 2-bit = ?1? t frc [ns] = 1000/fc ? 21 CXP80732A/80740a 0 . 8 v d d c f g t c f h t c f l 0 . 2 v d d 0 . 8 v d d d f g t d f h t d f l 0 . 2 v d d 0 . 8 v d d p b c t l t c t h t c t l 0 . 2 v d d 0 . 8 v d d e x i 0 e x i 1 t e i h t e i l 0 . 2 v d d 0 . 8 v d d t r e m t d p w t r e m d p g fig. 9. other timings ? 22 CXP80732A/80740a supplement fig. 10. recommended oscillation circuit a a a a a a a a a a a a e x t a l x t a l c 1 c 2 r d ( i ) ( i i ) a a a a a a a a a a a a a a a t e x t x c 1 c 2 r d manufacturer river eletec co., ltd. kinseki ltd. model hc-49/u03 hc-49/u (-s) p3 fc (mhz) 8.00 10.00 12.00 16.00 8.00 10.00 12.00 16.00 32.768khz 470k (ii) 10 10 10 10 16 16 12 12 30 12 12 12 12 18 0 0 c 1 (pf) c 2 (pf) rd ( ) circuit example (i) (i) those marked with an asterisk ( * ) signify types with built-in ground capacitance (c 1 , c 2 ). * in pg4/sync0 pin and pg5/sync1 pin, the input circuit format can be selected to every pin. item content reset pin pull-up resistor input circuit format * non-existent c-mos schmitt existent ttl schmitt mask option table ? 23 CXP80732A/80740a characteristics curve ( 1 0 0 a ) 3 4 5 6 0 . 1 5 . 0 1 . 0 v d d s u p p l y v o l t a g e [ v ] i d d s u p p l y c u r r e n t [ m a ] i d d v s . v d d ( f c = 1 6 m h z , t a = 2 5 c , t y p i c a l ) 7 2 0 . 0 5 ( 5 0 a ) 0 . 0 1 ( 1 0 a ) 0 . 5 1 0 . 0 2 0 . 0 1 / 2 d i v i d i n g m o d e 1 / 4 d i v i d i n g m o d e 1 / 1 6 d i v i d i n g m o d e s l e e p m o d e 0 1 5 1 0 5 f c s y s t e m c l o c k [ m h z ] i d d s u p p l y c u r r e n t [ m a ] i d d v s . f c ( v d d = 5 v , t a = 2 5 c , t y p i c a l ) 5 1 0 1 6 2 0 1 / 1 6 d i v i d i n g m o d e 1 / 4 d i v i d i n g m o d e s l e e p m o d e 3 2 k h z m o d e ( i n s t r u c t i o n ) 3 2 k h z m o d e s l e e p 1 / 2 d i v i d i n g m o d e ? 24 CXP80732A/80740a package outline unit : mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e 2 3 . 9 0 . 4 q f p - 1 0 0 p - l 0 1 1 0 0 p i n q f p ( p l a s t i c ) 2 0 . 0 0 . 1 + 0 . 4 0 . 1 5 0 . 0 5 + 0 . 1 1 5 . 8 0 . 4 1 7 . 9 0 . 4 1 4 . 0 0 . 1 + 0 . 4 2 . 7 5 0 . 1 5 + 0 . 3 5 a 0 . 6 5 m 0 . 1 3 q f p 1 0 0 - p - 1 4 2 0 1 . 7 g 1 1 0 0 8 1 8 0 5 1 5 0 3 1 3 0 0 . 3 0 . 1 + 0 . 1 5 d e t a i l a 0 t o 1 0 0 . 8 0 . 2 ( 1 6 . 3 ) 0 . 1 5 0 . 1 0 . 0 5 + 0 . 2 s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 a l l o y p a c k a g e s t r u c t u r e d e t a i l a l q f p - 1 0 0 p - l 0 1 l q f p 1 0 0 - p - 1 4 1 4 1 0 0 p i n l q f p ( p l a s t i c ) 1 6 . 0 0 . 2 * 1 4 . 0 0 . 1 7 5 5 1 5 0 2 6 2 5 1 7 6 0 . 5 0 . 1 8 0 . 0 3 + 0 . 0 8 ( 0 . 2 2 ) a 1 . 5 0 . 1 + 0 . 2 0 . 1 2 7 0 . 0 2 + 0 . 0 5 0 . 5 0 . 2 ( 1 5 . 0 ) 0 t o 1 0 0 . 1 0 . 1 0 . 5 0 . 2 1 0 0 0 . 1 n o t e : d i m e n s i o n * d o e s n o t i n c l u d e m o l d p r o t r u s i o n . 0 . 8 g 0 . 1 3 m |
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