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document number: mc34709 rev. 1.0, 8/2012 freescale semiconductor ? product preview ? freescale semiconductor, in c., 2012. all rights reserved. *this document contains certain information on a new product. ? specifications and information herei n are subject to change without notice. power management integrated circuit (pmic) for i.mx50/53 families the 34709 is the power management integrated circuit (pmic) designed primarily for use with the freescale i.mx50 and i.mx53 families. it offers a lower cost al ternative to the mc34708, targeting embedded applications that do not r equire a battery charger. however, it can be easily combined with an external charger, allowing flexibility for either single or multi-cell li-ion battery configurations. it supports both consumer and industrial applications with a single 130-pin 8x8 mapbga 0.5 mm pitch package that is easily routable in low cost board designs. features ? five buck converters configurable to provide up to six independent outputs for direct supply of the processor core, memory, and peripherals. ? boost regulator for usb phy domain on i.mx processors. ? seven ldo regulators with internal and external pass devices for thermal budget optimization ? one low current, high accuracy, voltage reference for ddr memory ? 10-bit adc for monitoring battery and other inputs ? real time clock and crystal oscillator circuitry with a coin cell backup/charger ? spi/i 2 c bus for control and register interface ? four general purpose low-voltage i/os with interrupt capability ? two pwm outputs figure 1. simplified application diagram power management 34709 applications tablets smart mobile devices patient monitors digital signage human machine interfaces (hmi) vk suffix (pb-free) 98asa00333d 130 mapbga 8.0 x 8.0 (0.5 mm pitch)

analog integrated circuit device data ? freescale semiconductor 2 34709 table of contents 1 orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 part identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 format and examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 simplified internal diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.1 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3.1 general pmic specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3.2 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.1 start-up requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2 bias and references block description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 clocking and oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3.1 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3.2 srtc support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3.3 coin cell battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.4 interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4.1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4.2 interrupt bit summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.5 power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5.1 power tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5.3 power control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.5.4 buck switching regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.5.5 boost switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.5.6 linear regulators (ldos) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.6 analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.1 input selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.3 dedicated readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.6.4 touch screen interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.6.5 adc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.7 auxiliary circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.7.1 general purpose i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.7.2 pwm outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.8 serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.8.1 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.8.2 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.8.3 spi/i2c specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
analog integrated circuit device data ? 3 freescale semiconductor 34709 7.9 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.9.1 register set structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.9.2 specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.9.3 spi/i2c register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.9.4 spi register?s bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.1 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.2 bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.3 34709 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.3.1 general board recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.3.2 general routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.3.3 parallel routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 8.3.4 switching regulator layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 8.4 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.4.1 rating data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.4.2 estimation of junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.1 package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10 reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
analog integrated circuit device data ? freescale semiconductor 4 34709 orderable parts 1 orderable parts this section describes the part numbers av ailable to be purchased, along with their differences. valid orderable part numbers are provided on the web. to determine the or derable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers. table 1. orderable part variations part number (1) temperature (t a ) package pc34709vk -40 to 85 c 130 mapbga - 8.0 x 8.0 mm - 0.5 mm pitch notes 1. to order parts in tape & reel, add the r2 suffix to the part number.
analog integrated circuit device data ? 5 freescale semiconductor 34709 part identification 2 part identification this section provides an explanation of the part numbers and their alpha numeric breakdown. 2.1 description part numbers for the chips have fields that identify the specific part configuration. you can use the values of these fields to determine the specific part you have received. 2.2 format and examples part numbers for a given device have the following format, followed by a device example: table 2 - part numbering - analog : pc tt xxx r v ppp rr - pc34709vkr2 2.3 fields these tables list the possible values for each field in the part number (not a ll combinations are valid). table 2: part numbering - analog field description values pc product category ? mc- qualified standard ? pc- prototype device tt temperature range ? 33 = -40 c to > 105 c ? 34 = -40 c to ? 105 c ? 35 = -55 c to ? 125 c xxx product number ? assigned by marketing r revision ? (default blank) v variation ? (default blank) ppp package identifier ? varies by package rr tape and reel indicator ? r2 = 13 inch reel hub size
analog integrated circuit device data ? freescale semiconductor 6 34709 internal block diagram 3 internal block diagram 3.1 simplified internal diagram figure 2. simplified internal block diagram bp resetb resetbmcu wdi switchers gndadc adin11 mux 10 bit gp adc int clk32k xtal1 xtal2 gndrtc licell gpio control gpiolv1 gpiolv2 rtc + calibration gndsw2 sw2fb sw2lx sw1in sw2in o/p drive ` gndsw1a sw1fb sw3in o/p drive gndsw3 sw3fb sw3lx gndswbst swbstfb swbstin swbstlx o/p drive pwron1 pums1 py monitor timer o/p drive pll 32 khz crystal osc standby gpiolv3 to interrupt section die temp & thermal warning detection lcell switch enables & control spi result registers interrupt inputs gndctrl core control logic, timers, & interrupts 32 khz internal osc gpiolv4 adin10 clk32kmcu gndreg1 gndreg2 adin9 a/d result a/d control ictest 32 khz buffers output pin input pin bi-directional pin package pin legend spi interface + muxed i2c optional interface cs clk gndspi miso spi registers mosi shift register shift register spivcc to enables & control to trimmed circuits spi control logic trim-in-package startup sequencer decode trim pumsx control logic li cell charger sw2 lp 1000 ma buck sw3 int mem 500 ma buck swbst 380 ma boost sw4 dual phase ddr 1000 ma buck vsrtc vsrtc vpll vpll 50 ma pass fet vinusb vusb best of supply licell bp vcoredig gndcore vcore vcoreref vusb regulator vinpll pums2 pwron2 glbrst sw5in o/p drive gndsw5 sw5fb sw5lx sw5 i/o 1000 ma buck vusb2 250ma vdacdrv vdac vusb2 vusb2drv vdac 250ma sw1alx dvs control sw1pwgd sw2pwgd pwm outputs pwm1 pwm2 gndsw1b o/p drive sw1blx sw4ain gndsw4a sw4fba o/p drive sw4alx sw4bin gndsw4b sw4bfb o/p drive sw4blx sw4cfg vddlp vgen1 250ma vgen2drv vgen2 vgen2 250ma pass fet vgen1 pass fet vingen1 pums3 pums4 sdwnb digital core bp sw1 dual phase gp 2000 ma buck sw1cfg sw1vsssns pums5 gpiovdd gndgpio gndref1 gndref2 gndref ldovdd pass fet adin14/tsy1 adin15/tsy2 adin13/tsx2 tsref touch screen interface adin12/tsx1 vinrefddr vrefddr 10ma vrefddr vhalf subsana1 subspwr1 subsref subsana2 subsldo subspwr2 subsana3 subsgnd gndusb reference generation
analog integrated circuit device data ? 7 freescale semiconductor 34709 pin connections 4 pin connections 4.1 pinout diagram figure 3. top view ballmap 123456789101112131415 a miso gndspi spivcc glbrst pwron1 pwm2 pwm1 ictest sw2lx sw2fb sw2pwgd nc_2 b clk cs mosi int resetb gndctrl gpiolv1 gpiolv2 gndsw2 sw2in gndref2 sw3fb nc_3 c gndusb gpiolv0 gpiovdd gndgpio d vinusb vusb resetbmcu sdwnb gndsw3 sw3lx e xtal1 clk32k pwron2 pums5 subspwr1 gpiolv3 subspwr2 sw3in f gndrtc clk32kvcc pums4 pums3 subspwr1 subspwr1 subsana2 gndswbst swbstin g xtal2 clk32kmcu pums2 pums1 subspwr1 subspwr1 subspwr3 swbstlx h gndcore vsrtc gndadc adin9 subspwr1 subspwr1 subsldo vgen1 vingen1 swbstfb j vcoredig vcore adin10 adin11 subsgnd subspwr1 gndreg2 vinrefddr vhalf k vcoreref wdi tsx1 tsref subsref subspwr sw1pwgd subsana1 vpll vrefddr l vddlp tsy2 tsx2 tsy1 sw1cfg vgen2drv vinpll m gndref licell sw4cfg sw5fb gndreg1 vgen2 n bp sw4afb gndref1 vdacdrv ldovdd p standby sw4bfb gndsw4a sw4ain sw4bin gndsw4b sw5in gndsw5 gndsw1a sw1in sw1in gndsw1b sw1fb vusb2drv vdac r nc_1 sw4alx sw4blx sw5lx sw1alx sw1blx sw1vsssns vusb2
analog integrated circuit device data ? freescale semiconductor 8 34709 pin connections 4.2 pin definitions table 3. pin definitions pin number pin name pin function rating [v] # balls definition supply n1 bp i 5.5 1 1. application supply point 2. input supply to the ic core circuitry d6 sdwnb o 3.6 1 indication of imminent system shutdown ic core j2 vcore o - 1 regulated supply for the ic analog core circuitry j1 vcoredig o - 1 regulated supply for the ic digital core circuitry k1 vcoreref o - 1 main bandgap reference l1 vddlp o - 1 vddlp reference h1 gndcore gnd - 1 ground for the ic core circuitry m1 gndref gnd - 1 ground reference for ic core circuitry switching regulators p10 p11 sw1in i 5.5 2 regulator 1 input r9 sw1alx o 5.5 1 regulator 1a switch node connection p13 sw1fb i 3.6 1 regulator 1 feedback p9 gndsw1a gnd - 1 ground for regulator 1a r13 sw1vsssns gnd - 1 regulator 1 sense k10 sw1pwgd o 3.6 1 power good signal for sw1 r11 sw1blx o 5.5 1 regulator 1b switch node connection p12 gndsw1b gnd - 1 ground for regulator 1b l12 sw1cfg i 3.6 1 regulator 1a/b mode configuration b11 sw2in i 5.5 1 regulator 2 input a10 sw2lx o 5.5 1 regulator 2 switch node connection a12 sw2fb i 3.6 1 regulator 2 feedback b10 gndsw2 gnd - 1 ground for regulator 2 a13 sw2pwgd o 3.6 1 power good signal for sw2 e14 sw3in i 5.5 1 regulator 3 input d15 sw3lx o 5.5 1 regulator 3 switch node connection b13 sw3fb i 3.6 1 regulator 3 feedback d14 gndsw3 gnd - 1 ground for regulator 3 b12 gndref2 gnd - 1 ground reference for regulators p4 sw4ain i 5.5 1 regulator 4a input r3 sw4alx o 5.5 1 regulator 4a switch node connection n2 sw4afb i 3.6 1 regulator 4a feedback
analog integrated circuit device data ? 9 freescale semiconductor 34709 pin connections p3 gndsw4a gnd - 1 ground for regulator 4a p5 sw4bin i 5.5 1 regulator 4b input r6 sw4blx o 5.5 1 regulator 4b switch node connection p2 sw4bfb i 3.6 1 regulator 4b feedback p6 gndsw4b gnd - 1 ground for regulator 4b m6 sw4cfg i 3.6 1 regulator 4a/b mode configuration p7 sw5in i 5.5 1 regulator 5 input r8 sw5lx o 5.5 1 regulator 5 output m8 sw5fb i 3.6 1 regulator 5 feedback p8 gndsw5 gnd - 1 ground for regulator 5 n9 gndref1 gnd - 1 ground reference for regulators f15 swbstin i 5.5 1 boost regulator bp supply g14 swbstlx o 7.5 1 swbst switch node connection h15 swbstfb i 5.5 1 boost regulator feedback f14 gndswbst gnd - 1 ground for regulator boost ldo regulators j14 vinrefddr i 3.6 1 vrefddr input supply k15 vrefddr o 1.5 1 vrefddr regulator output j15 vhalf o 1.5 1 half supply reference for vrefddr l15 vinpll i 5.5 1 vpll input supply k14 vpll o 2.5 1 vpll regulator output n14 vdacdrv o 5.5 1 drive output for vdac regulator using an external pnp device p15 vdac o 3.6 1 vdac regulator output n15 ldovdd i 5.5 1 supply pin for vusb2, vdac, and vgen2 d2 vusb o 3.6 1 usb transceiver regulator output d1 vinusb i 5.5 1 vusb input supply c1 gndusb gnd - 1 ground for vusb ldo p14 vusb2drv i 5.5 1 1. vusb2 input using internal pmos fet o 2. drive output for vusb2 regulator using an external pnp device r14 vusb2 o 3.6 1 vusb2 regulator output h14 vingen1 i 2.5 1 vgen1 input supply h12 vgen1 o 2.5 1 vgen1 regulator output l14 vgen2drv i 5.5 1 1. vgen2 input using internal pmos fet o 2. drive output for vgen2 regulat or using an external pnp device m15 vgen2 o 3.6 1 vgen2 regulator output h2 vsrtc o 2.5 1 output regulator for srtc module on processor m14 gndreg1 gnd - 1 ground for regulator 1 table 3. pin definitions (continued) pin number pin name pin function rating [v] # balls definition
analog integrated circuit device data ? freescale semiconductor 10 34709 pin connections j12 gndreg2 gnd - 1 ground for regulator 2 c8 gpiovdd i 2.5 1 supply for gpiolv pins c7 gpiolv0 i/o 2.5 1 general purpose input/output 1 b7 gpiolv1 i/o 2.5 1 general purpose input/output 2 b9 gpiolv2 i/o 2.5 1 general purpose input/output 3 e10 gpiolv3 i/o 2.5 1 general purpose input/output 4 a8 pwm1 o 2.5 1 pwm output 1 a7 pwm2 o 2.5 1 pwm output 2 c9 gndgpio gnd - 1 gpio ground clock/rtc/coin cell m2 licell i 3.6 1 1. coin cell supply input o 2. coin cell charger output e1 xtal1 i 2.5 1 32.768 khz oscillator crystal connection 1 g1 xtal2 i 2.5 1 32.768 khz oscillator crystal connection 2 f1 gndrtc gnd - 1 ground for the rtc block f3 clk32kvcc i 3.6 1 supply voltage for 32 k buffer e3 clk32k o 3.6 1 32 khz clock output for peripherals g3 clk32kmcu o 3.6 1 32 khz clock output for processor control logic b5 resetb o 3.6 1 reset output for peripherals d5 resetbmcu o 3.6 1 reset output for processor k3 wdi i 3.6 1 watchdog input p1 standby i 3.6 1 standby input signal from processor b4 int o 3.6 1 interrupt to processor a6 pwron1 i 3.6 1 power on/off button connection 1 e5 pwron2 i 3.6 1 power on/off button connection 2 a5 glbrst i 3.6 1 global reset g6 pums1 i 3.6 1 power up mode supply setting 1 g5 pums2 i 3.6 1 power up mode supply setting 2 f6 pums3 i 3.6 1 power up mode supply setting 3 f5 pums4 i 3.6 1 power up mode supply setting 4 e6 pums5 i 3.6 1 power up mode supply setting 5 a9 ictest i 3.6 1 normal mode, test mode selection, & anti-fuse bias b6 gndctrl gnd - 1 ground for control logic a4 spivcc i 3.6 1 supply for spi bus b2 cs i 3.6 1 primary spi select input b1 clk i 3.6 1 primary spi clock input table 3. pin definitions (continued) pin number pin name pin function rating [v] # balls definition
analog integrated circuit device data ? 11 freescale semiconductor 34709 pin connections b3 mosi i 3.6 1 primary spi write input a2 miso o 3.6 1 primary spi read output a3 gndspi gnd - 1 ground for spi interface a to d converter h6 adin9 i 4.8 1 adc generic input channel 9 j5 adin10 i 4.8 1 adc generic input channel 10 j6 adin11 i 4.8 1 adc generic input channel 11 k5 tsx1 i 4.8 1 touch screen interface x1 or adc generic input channel 12 l4 tsx2 i 4.8 1 touch screen interface x2 or adc generic input channel 13 l6 tsy1 i 4.8 1 touch screen interface y1 or adc generic input channel 14 l3 tsy2 i 4.8 1 touch screen interface y2 or adc generic input channel 15 k6 tsref o 4.8 1 touch screen reference h5 gndadc gnd - 1 ground for a to d circuitry substrate grounds k8 subsref gnd - 1 substrate ground connection k9 subspwr gnd - 1 substrate ground connection e8 f8 f9 g8 g9 h8 h9 j9 subspwr1 gnd - 8 substrate ground connection e11 subspwr2 gnd - 1 substrate ground connection g10 subspwr3 gnd - 1 substrate ground connection h10 subsldo gnd - 1 substrate ground connection k12 subsana1 gnd - 1 substrate ground connection f10 subsana2 gnd - 1 substrate ground connection j8 subsgnd gnd - 1 substrate ground connection no connects a14 b15 r1 nc - - 3 do not connect table 3. pin definitions (continued) pin number pin name pin function rating [v] # balls definition
analog integrated circuit device data ? freescale semiconductor 12 34709 general product characteristics 5 general product characteristics 5.1 maximum ratings 5.2 thermal characteristics table 4. maximum ratings all voltages are with respect to ground, unless otherwise noted. exceeding these rati ngs may cause a malfunction or permanent damage to the device. symbol description (rating) min. max. unit notes electrical ratings v ictest ictest pin voltage - 1.8 v v bp bp voltage - 4.5 v v licell coin cell voltage - 3.6 v v esd esd ratings ? human body model all pins ? charge device model all pins - - ? 2000 ? 500 v (2) (2) notes 2. esd testing is performed in accordanc e with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ? ), and the charge device model (cdm), robotic (c zap = 4.0 pf). table 5. thermal ratings all voltages are with respect to ground, unless otherwise noted. exceeding these rati ngs may cause a malfunction or permanent damage to the device. symbol description (rating) min. max. unit notes thermal ratings t a ambient operating temperature range - -40 to 85 c t j operating junction temperature range - -40 to 125 c t st storage temperature range - -65 to 150 c t pprt peak package reflow temperature during reflow - note 3 c (3) , (4) thermal resistance and package dissipation ratings r ja junction to ambient natural convection ? single layer board (1s) - 93 c/w (5) , (6) r jma junction to ambient natural convection ? four layer board (2s2p) - 53 c/w (5) , (7) r jma junction to ambient (@200 ft/min.) ? single layer board (1s) - 80 c/w (5) , (7) r jma junction to ambient (@200 ft/min.) ? four layer board (2s2p) - 49 c/w (5) , (7) r jb junction to board - 34 c/w (8) r jc junction to case - 25 c/w (9)
analog integrated circuit device data ? 13 freescale semiconductor 34709 general product characteristics 5.2.1 power dissipation during operation, the temperature of the die should not exceed the maximum junction temperature. to optimize the thermal management scheme and avoid overheating, the 34709 pmic provid es a thermal management syste m. the thermal protection is based on a circuit with a voltage output that is proportional to the absolute temper ature. this voltage can be read out via the adc for specific temperature readouts, see serial interfaces . this voltage is monitored by an integr ated comparator. interrupts therm110, therm120, therm125, and therm130 will be generated when respectively crossing in either direction of the thresholds specified in table 6 . the temperature range can be determined by reading the thermxxxs bits. thermal protection is integrated to power off the 34709 pmic, in case of over dissipation. this thermal protection will act abo ve the maximum junction temperature to avoid any unwan ted power downs. the protection is debounced for 8.0 ms in order to suppress any (thermal) noise. this protection should be cons idered as a fail-safe mechanis m and therefore the application design should be dimensioned such that this protection is not tripped under normal co nditions. the temperat ure thresholds and the sense bit assignment are listed in table 6 . thermal resistance and package dissipation ratings (continued) ? jt junction to package top ? natural convection - 6.0 c/w (10) notes 3. pin soldering temperature limit is for 10 seconds maximum duration. not designed for immersion soldering. exceeding these lim its may cause a malfunction or permanent damage to the device. 4. freescale's package reflow capability m eets the pb-free requirements for jedec standard j-std-020c, for peak package reflow temperature and moisture sensitivity levels (msl). 5. junction temperature is a function of on- chip power dissipation, package thermal re sistance, mounting site (board) temperatur e, ambient temperature, air flow, power dissipation of othe r components on the board, and board thermal resistance. 6. per jedec jesd51-2 with the single layer board horizontal. board meets jesd51-9 specification. 7. per jedec jesd51-6 with the board horizontal. 8. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 9. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) . 10. thermal characterization parameter indicating the temperat ure difference between package top and the junction temperature pe r jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. table 6. thermal protection thresholds parameter min typ max units notes thermal 110 c threshold (therm110) 105 110 115 c thermal 120 c threshold (therm120) 115 120 125 c thermal 125 c threshold (therm125) 120 125 130 c thermal 130 c threshold (therm130) 125 130 135 c thermal warning hysteresis 2.0 - 4.0 c (11) thermal protection threshold 130 140 150 c notes 11. equivalent to approx. 30 mw min, 60 mw max table 5. thermal ratings (continued) all voltages are with respect to ground, unless otherwise noted. exceeding these rati ngs may cause a malfunction or permanent damage to the device. symbol description (rating) min. max. unit notes
analog integrated circuit device data ? freescale semiconductor 14 34709 general product characteristics 5.3 electrical characteristics 5.3.1 general pmic specifications table 7. general electrical characteristic pin name internal termination (16) parameter load condition min max (19) unit notes pwron1, pwron2, glbrst pull-up input low 47 kohm 0.0 0.3 v (13) input high 1.0 mohm 1.0 vcoredig v (13) standby, wdi weak pull-down input low - 0.0 0.3 v (18) input high - 0.9 3.6 v (18) clk32k cmos output low -100 ? a 0.0 0.2 v output high 100 ? a clk32kvcc - 0.2 clk32kvcc v clk32kmcu cmos output low -100 ? a 0.0 0.2 v output high 100 ? a vsrtc - 0.2 vsrtc v resetb, resetbmcu, sdwnb, sw1pwgd, sw2pwgd open-drain output low -2.0 ma 0.0 0.4 v (17) output high open-drain - 3.6 v (17) vsrtc voltage output off /coin cell mode - 1.15 1.28 v pums[4 :0] = (0110, 0111, 1000, 1001) 1.2 v setting 1.15 1.25 v pums[4 :0] = (0110, 0111, 1000, 1001) 1.3 v setting 1.25 1.35 v gpiolv1,2,3,4 cmos input low - 0.0 0.3 * gpiovdd v input high - 0.7 * gpiovdd gpiovdd + 0.3 v output low - 0.0 0.2 v output high - gpiovdd - 0.2 gpiovdd v open-drain output low -2.0 ma 0.0 0.4 v output high open-drain - gpiovdd + 0.3 v pwm1, pwm2 cmos output low - 0.0 0.2 v output high - gpiovdd - 0.2 gpiovdd v clk, mosi input low - 0.0 0.3 * spivcc v (12) input high - 0.7 * spivcc spivcc + 0.3 v (12) cs weak pull-down input low - 0.0 0.4 v (12) input high - 1.1 spivcc + 0.3 v (12) cs, mosi (at booting for spi / i 2 c decoding) weak pull-down on cs input low - 0.0 0.3 * vcoredig v (12) , (20) input high - 0.7 * vcoredig vcoredig v (12) , (20) miso, int cmos output low -100 ? a 0.0 0.2 v miso (12) (21) output high 100 ? a spivcc - 0.2 spivcc v miso (12) (21)
analog integrated circuit device data ? 15 freescale semiconductor 34709 general product characteristics pums1,2,3,4,5 input low pumsxs = 0 - 0.0 0.3 v (14) input high pumsxs = 1 - 1.0 vcoredig v (14) ictest input low - 0.0 0.3 v (15) input high - 1.1 1.7 v (15) sw1cfg, sw4cfg input low - 0.0 0.3 v input mid - 1.3 2.0 v input high - 2.5 3.1 v adin8,9,10 input must not exceed - - bp v tsx1,tsx2, tsy1, tsy2 input must not exceed - - bp or vcore v notes 12. spivcc is typically connected to the output of buck regulator sw5 and set to 1.800 v 13. input has internal pull-up to vcoredig equivalent to 200 kohm 14. input state is latched in first phase of cold start, refer to serial interfaces for a description of the pums configuration 15. input state is not latched 16. a weak pull-down represents a nominal internal pull-down of 100 na, unless otherwise noted 17. resetb, resetbmcu, sdwnb, sw1pwgd, sw2pwgd have open-drain outputs, external pull-ups are required 18. spivcc needs to remain enabled for proper detec tion of wdi high to avoid involuntary shutdown 19. the maximum should never exceed the ma ximum rating of the pin as given in pin connections 20. the weak pull-down on cs is disabled if a vih is detected at start-up to avoid extra consumption in i 2 c mode 21. the output drive strength is programmable table 7. general electrical characteristic pin name internal termination (16) parameter load condition min max (19) unit notes
analog integrated circuit device data ? freescale semiconductor 16 34709 general product characteristics 5.3.2 current consumption the current consumption of the individual blocks is described in detail through out this specification. for convenience, a summa ry table follows for standard use cases. table 8. current consumption summary (24) characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. mode description typ max unit notes rtc / power cut all blocks disabled, bp=0, coin cell is attached to licell ? (at 25 c only) ? rtc logic ? vcore module ? vsrtc ?32 k oscillator ? clk32kmcu buffer active(10 pf load) 4.0 7.0 ? a off (good battery) all blocks disabled, bp>3.0 v(at 25 c only) ?digital core ? rtc logic ? vcore module ? vsrtc ?32 k oscillator ? clk32kmcu buffer active (10 pf load) ? coinchen = 0 20 55 ? a on standby low-power mode (standby pin asserted and on_stby_lp=1) ?digital core ? rtc logic ? vcore module ? vsrtc ? clk32kmcu/clk32k active (10 pf load) ?32 k oscillator ?i ref ? sw1, sw2, sw3, sw4a, sw4b, sw5 in pfm (23) , (27) ? vddref, vpll, vgen1, vgen2, vusb2, vdac ? in low-power mode (22) , (25) 260 650 ? a on standby ?digital core ? rtc logic ? vcore module ? vsrtc ? clk32kmcu/clk32k active (10 pf load) ?32 k oscillator ?digital ?i ref ? sw1, sw2, sw3, sw4a, sw4b, sw5 in pfm (23) , (27) ? vddref, vpll, vgen1, vgen2, vusb2, vdac on ? in low-power mode (23) , (25) ?pll 370 750 ? a
analog integrated circuit device data ? 17 freescale semiconductor 34709 general product characteristics on typical use case ?digital core ? rtc logic ? vcore module ? vsrtc clk32kmcu/clk32k active (10 pf) ?32 k oscillator ?i ref ? sw1, sw2, sw3, sw4a, sw4b, sw5 in aps swbst (23) , (26) , (27) ? vddref, vpll, vgen1, vgen2, vusb2, vdac on ? in low-power mode (22) , (25) ?digital ?pll 1600 3000 ? a notes 22. equivalent to approx. 30 mw min, 60 mw max 23. current in rtc mode is from licell=2.5 v; in all other modes from bp = 3.6 v. 24. external loads are not included 25. vusb2, vgen2 external pass pnps 26. swbst in auto mode 27. sw4a output 2.5 v table 8. current consumption summary (24) characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. mode description typ max unit notes
analog integrated circuit device data ? freescale semiconductor 18 34709 general description 6 general description the 34709 is the pmic designed specifically for use with the freescale i.mx50 and i. mx53 families. as the companion pmic on several i.mx reference designs, it is a proven solution, wh ich enables a faster time to market with fewer resources. 6.1 features power generation ? five buck switching regulators ? two single/dual phase buck regulators ? three single phase buck regulators ? up to six independent outputs ? pfm/auto pulse skip/pwm operation mode ? dynamic voltage scaling ?5 v boost regulator ? support for usb physical layer on i.mx processor (usb phy) ? seven ldo regulators ? two with selectable internal or external pass devices ? four with embedded pass devices ? one with an external pnp device ? one voltage reference for ddr memory with internal pmos device analog to digital converter ? seven general purpose channels ? eight dedicated channels for monitoring the charger ? resistive touchscreen interface auxiliary circuits ? general purpose i/os ? pwm outputs clocking and oscillators ? real time clock ? time and day counters ? time of day alarm ? 32.768 khz crystal oscillator ? coin cell battery backup ? coin cell charger serial interface ? spi ?i 2 c
analog integrated circuit device data ? 19 freescale semiconductor 34709 general description 6.2 block diagram figure 4. functional block diagram 6.3 functional description the 34709 power management integrated circuit (pmic) represents a complete system power solution in a single package. designed primarily for use with the freescale i.mx50/53 fami lies. the 34709 integrates five multi-mode buck regulators and seven ldo regulators and one voltage reference for direct supply of the processor core, memory, and peripherals. the 34709 also integrates a real time clock, co in cell charger, a 16-channel 10-bit adc, 5.0 v usb boost regulator, two pwm outputs, touch-screen interface, st atus led drivers, and four gpios. control interface spi/i 2 c bias & references trimmed bandgap ddr memory voltage reference five buck regulators processor core split power domains ddr memory i/o seven ldo regulators peripherals 5.0 v boost regulator 10 bit adc core general purpose resistive touch screen interface power control logic state machine general purpose i/o & pwm outputs 32.768 khz crystal oscillator real time clock srtc support coin cell charger pc34709
analog integrated circuit device data ? freescale semiconductor 20 34709 functional block description 7 functional block description 7.1 start-up requirements at power-up, switching and linear regulators are sequentially enabled in time slots of 2.0 ms steps, to limit the inrush current after an initial delay of 8.0 ms, in which the core circuitry gets enabled. to ens ure a proper power-up sequence, the outputs of the switching regulators that are no t enabled, are discharged at the b eginning of the cold start with weak pull-downs on the output . for that same reason, an 8.0 ms delay allows the outputs of t he linear regulators to be fully discha rged as well, through the built in discharge path. the peak inrush current per event is limited. any under-voltage de tection at bp is masked while the power-up sequencer is running. when the switching regulato r is enabled, it will start in pwm mode for 3.0 ms. then it will switch over to the mode that it is prog rammed to in the spi. the power-up mode select pins pumsx (x = 1,2,3,4,5) are used to confi gure the start-up characteristi cs of the regulators. supply enabling and output level options are sele cted by hardwiring the pumsx pins for the desired configuration. the recommended power-up strategy for end products is to bring up as little of the system as possible at booting, essentially sequestering just the bare essentials to allow processor start-up and software to run. with such a strategy, the start-up transients are controlled a t lower levels, and the rest of the system power tree can be brought up by software. th is allows optimization of supply ordering, where specific sequences may be required, as well as supply def ault values. software code can load up all of the required programmable options, to avoid sneak pat hs, under/over-voltage issues, start-up su rges, etc, without any change in hardware. the state of the pumsx pins are latched in before any of the switching or linear regu lators are enabled, with the exception of vcore. pumsx options and start-up configurat ions will be robust to a pcut event, whether occurring during normal operation or during the 8.0 ms of pre-sequencer initialization, i.e., the system will not end up in an unexpected / undesirable consumption state. table 9 shows the initial setup for the voltage level of the s witching and linear regulators, and whether they get enabled. table 9. power-up defaults i.mx reserved 53 lpm 53 ddr2 53 ddr3 53 lvddr3 53 lvddr2 50 50 50 50 50 50 pums[4:1] 0000-0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 pums5=0 vusb2 vgen2 reserved ext pnp ext pnp ext pnp ext pnp ext pnp ext pnp ext pnp ext pnp ext pnp ext pnp ext pnp pums5=1 vusb2 vgen2 reserved internal pmos internal pmos internal pmos internal pmos internal pmos internal pmos internal pmos internal pmos internal pmos internal pmos internal pmos sw1a (vddgp) reserved 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 sw1b (vddgp) reserved 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 sw2 (28) (vcc) reserved 1.225 1.3 1.3 1.3 1.3 1.2 1.2 1.2 1.2 1.2 1.2 sw3 (28) (vdda) reserved 1.2 1.3 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 sw4a (28) (ddr/sys) reserved 1.5 1.8 1.5 1.35 1.2 1.8 1.2 3.15 3.15 3.15 3.15 sw4b (28) (ddr/sys) reserved 1.5 1.8 1.5 1.35 1.2 1.8 1.2 1.2 1.8 1.2 1.8 sw5 (28) (i/o) reserved 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 swbst reserved off off off off off off off off off off off
analog integrated circuit device data ? 21 freescale semiconductor 34709 functional bloc k description the power-up sequence is shown in tables 10 and 11 . vcoredig, vsrtc, and vcore, are brought up in the pre-sequencer start-up. vusb (29) reserved 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 vusb2 reserved 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 vsrtc reserved 1.2 1.3 1.3 1.3 1.3 1.2 1.2 1.2 1.2 1.2 1.2 vpll reserved 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 vrefddr reserved on on on on on on on on on on on vdac reserved 2.775 2.775 2.775 2.775 2.775 2.5 2.5 2.5 2.5 2.5 2.5 vgen1 reserved 1.2 1.3 1.3 1.3 1.3 1.2 1.2 1.2 1.2 1.2 1.2 vgen2 reserved 2.5 2.5 2.5 2.5 2.5 3.1 3.1 3.1 3.1 2.5 2.5 notes 28. the swx node are activated in aps m ode when enabled by the start-up sequencer. 29. vusb is supplied by swbst. table 10. power-up sequence i.mx53 tap x 2.0 ms pums [4:1] = [0101,0110,0111,1000,1001] (i.mx53) 0 sw2 (vcc) 1 vpll (nvcc_ckih = 1.8 v) 2 vgen2 (vdd_reg= 2.5 v, external pnp 3 sw3 (vdda) 4 sw1a/b (vddgp) 5 sw4a/b, vrefddr (ddr/sys) 6 7 sw5 (i/o), vgen1 8 vusb, vusb2 9 vdac table 11. power-up sequence i.mx50 tap x 2.0 ms pums [4:1] = [0100, 1011, 1100, 1101, 1110, 1111] (i.mx50/i.mx53) 0 sw2 1 sw3 2 sw1a/b 3 vdac 4 sw4a/b, vrefddr 5 sw5 6 vgen2, vusb2 7 vpll 8 vgen1 9 vusb table 9. power-up defaults i.mx reserved 53 lpm 53 ddr2 53 ddr3 53 lvddr3 53 lvddr2 50 50 50 50 50 50
analog integrated circuit device data ? freescale semiconductor 22 34709 functional block description 7.2 bias and references block description and application information all regulators use the main bandgap as the reference. the main bandgap is bypassed with a capacitor at refcore. the bandgap and the rest of the core circuitry is supplied from vcor e. the performance of the regula tors is directly dependent on the performance of vcoredig and the bandgap. no external dc loading is allowed on vcoredig or refcore. vcoredig is kept powered as long as there is a valid supply and/or coin cell. table 12 shows the main characteristics of the core circuitry. 7.3 clocking and oscillators 7.3.1 clock generation a system clock is generated for internal digital circuitry as well as for external applicati ons utilizing the clock output pins . a crystal oscillator is used for the 32.768 khz time base and generation of related derivative clocks. if the crystal o scillator is not running (for example, if the crystal is not present), an internal 32 khz oscillator will be used instead. table 12. core voltages electrical specifications characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes vcoredig (digital core supply) v coredig output voltage ? on mode ? off with good battery and rtc mode - - 1.5 0.0 - - v (30) c coredig v coredig bypass capacitor - 1.0 - ? f vddlp (digital core supply - lower power) v ddlp output voltage ? on mode with good battery ? off mode with good battery ? rtc mode - - - 1.5 1.2 1.2 - - - v (31) c ddlp v ddlp bypass capacitor - 100 - pf (32) vcore (analog core supply) v core output voltage ? on mode and charging ? off and rtc mode - - 2.775 0.0 - - v (30) c core v core bypass capacitor - 1.0 - ? f vrefcore (bandgap / regulator reference) v refcore output voltage - 1.2 - v (30) absolute accuracy - 0.5 - % temperature drift - 0.25 - % c refcore v refcore bypass capacitor - 100 - nf notes 30. 3.0 v < bp < 4.5 v, no external loading on vcoredig, vddlp, vcore, or refcore. extended operation down to uvdet, but no system malfunction. 31. powered by vcoredig 32. maximum capacitance on v ddlp should not exceed 1000 pf, including the board capacitance.
analog integrated circuit device data ? 23 freescale semiconductor 34709 functional bloc k description support is also provided fo r an external secure real ti me clock (srtc), which may be in tegrated on a companion system processor ic. for media prot ection in compliance with digital rights management (drm) system requirements, the clk32kmcu can be provided as a reference to the sr tc module where tamper pr otection is implemented. 7.3.1.1 clocking scheme the internal 32 khz oscillator is an integrated backup for th e crystal oscillator, and provides a 32.768 khz nominal frequency at ? 60% accuracy, if running. the internal oscill ator only runs if a valid supply is availa ble at bp, and would not be used as long as the crystal oscillator is active. in absence of a valid supply at the bp supply node (for instance due to a dead battery), the crystal oscillator continues running supplied from the coin cell battery . all control functions will run off the crystal derived freque ncy, occasionally refe rred to as ?32 khz? for brevity?s sake. during the switchover between the two clock sources (such as w hen the crystal oscillator is starting up), the output clock is maintained at a stable active low or high phase of the internal 32 khz clock to avoid any clocking glitches. if the xltal clock source suddenly disappears during operation, the ic will revert ba ck to the internal clock source. given the unpredictable natu re of the event and the start-up times involved, the clock may be absent long enough for the application to shut down during this transition, such as a sag in the r egulator output voltage or absence of a signal on the clock output pins. a status bit, clks, is available to indicate to the processo r which clock is currently selected: clks=0 when the internal rc is used and clks=1 if the crystal source is used. the clki interrupt bit will be set whenever a change in the clock source occurs, and an interrupt will be generated if the corresponding clkm mask bit is cleared. 7.3.1.2 oscillator specifications the crystal oscillator has been optimized for use in conjunction with the micro crystal cc7v-t1a32.768 khz-9.0 pf-30 ppm or equivalent (such as micro crystal cc5v-t1a or epson fc135 ) and is capable of handling its parametric variations. the electrical characteristics of the 32 khz crystal oscillator are given in the following table, taking into account the crystal characteristics noted above. the oscillator accuracy depends largely on the temper ature characteristics of the used crystal. application circuits can be optimized for required accuracy by ad apting the external crystal osci llator network (via component accuracy and/or tuning). additionally, a clock calibration system is provided to adjust the 32,768 cycle counter that generates the 1.0 hz timer and rtc registers; see srtc support for more detail. table 13. oscillator and clock ma in electrical specifications characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes oscillator and clock output v inrtc operating voltage ? oscillator and rtc block from bp ? oscillator and rtc block from licell 1.8 1.8 - - 4.5 3.6 v i inrtc operating current crystal oscillator and rtc module ? all blocks disabled, no main battery attached, coin cell is attached to licell - 2.0 5.0 ? a t start-rtc rtc oscillator start-up time ? upon application of power - - 1.0 sec v rtclo output low ? clk32k output sink 100 ? a ? clk32kmcu output source 50 ? a 0.0 - 0.2 v v rtchi output high ? clk32k output source 100 ? a ? clk32kmcu output sink 50 ? a clk32k vcc -0.2 vsrtc-0.2 - - clk32k vcc vsrtc v
analog integrated circuit device data ? freescale semiconductor 24 34709 functional block description 7.3.2 srtc support when configured for drm mode (spi bit drm = 1), the clk32kmcu driver will be kept enabled through all operational states to ensure that the srtc module a lways has its reference clock. if drm = 0, the clk32kmcu driver wi ll not be maintained in the off state. it is also necessary to provide a means for the processor to do an rtc initiated wake-up of the system if it has been programme d for such capability. this can be accomplished by connecting an open-drain nmos driver to t he pwron pin of the 34709 pmic, so that it is in effect, a parallel path for the power key. th e 34709 pmic will not be able to discern the turn on event from a normal power key initiated turn on, but the processor should have the k nowledge, since the rtc initiated turn on is generated locally. figure 5. srtc block diagram oscillator and clock output (continued) t clk32ket clk32k rise and fall time, cl = 50 pf ? clk32kdrv [1:0] = 00 ? clk32kdrv [1:0] = 01 (default) ? clk32kdrv [1:0] = 10 ? clk32kdrv [1:0] = 11 - - - - 6.0 2.5 3.0 2.0 - - - - ns t ckl32k mcuet clk32kmcu rise and fall time ?cl = 12 pf - 22 - ns clk32k dc/ clk32k mcu dc clk32k and clk32kmcu output duty cycle ? crystal on xtal1, xtal2 pins 45 - 55 % rms output jitter ? 1 sigma for gaus sian distribution - - 30 ns rms table 13. oscillator and cloc k main electrical specifications characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes processor lp-rtc hp-rtc 34709 srtc ckil: vsrtc i/o core supply sog supply 32 khz for dsm timing vcoredig pwronx on/off button open drain output for rtc wake-up on detect coin cell battery vcoredig main battery best of suppy clk32kmcu 32 khz vsrtc = 1.2 v vsrtc & detect spivcc=1.8 v gp domain=1.1 v lp domain=1.2 v 0.1 u
analog integrated circuit device data ? 25 freescale semiconductor 34709 functional bloc k description 7.3.2.1 vsrtc the vsrtc regulator provides the clk32kmcu output level. additionally, it is used to bias the low-power srtc domain of the srtc module integrated on certain fsl processors. the vsrtc regulator is enabled as soon as the rtcporb is detected. the vsrtc cannot be disabled. depending on the configuration of the pums[4:0] pi ns, the vsrtc voltage will be set to 1.3 or 1.2 v. with pums[4:0] = (0110, 0111, 1000, or 1001) vsrtc will be set to 1.3 v in on mode (on, on standby and on standby low-power modes). in off and coin cell modes the vsrtc voltage will drop to 1.2 v with the pums[4:0] = (0110, 0111, 1000 , or 1001). with pums[4:0] = (0110, 0111, 1000, or 1001), vsrtc will be set to 1.2 v for all modes (on, on standby, on stan dby low-power mode, off, and coin cell). 7.3.2.2 real time clock a real time clock (rtc) is provided with time and day counter s as well as an alarm function. the rtc utilizes the 32.768 khz crystal oscillator for the time base and is powered by the coin cell backup supply when bp has dropped below operational range. in configurations where the srtc is used , the rtc can be disabled to conserve current drain by setting the rtcdis bit to a 1 (defaults on at power up). time and day counters table 14. vsrtc electrical specifications characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes general v srtcin operating input voltage range ? valid coin cell range ?valid bp 1.8 1.8 - - 3.6 4.5 v i srtc operating current load range 0.0 - 50 ? a co srtc bypass capacitor value - 0.1 - ? f vsrtc - active mode - dc v srtc output voltage ?v srtcinmin < v strcin < v srtcinmax ?i srtcmin < i srtc < i srtcmax ? off and coin cell mode 1.15 1.20 1.28 v vsrtc - active mode - dc (continued) v srtc output voltage ?v srtcinmin < v strcin < v srtcinmax ?i srtcmin < i srtc < i srtcmax ? pums[4:0] (0110, 0111, 1000, 1001) ? on, standby, and standby lpm modes 1.15 1.2 1.25 v v srtc output voltage ?v srtcinmin < v strcin < v srtcinmax ?i srtcmin < i srtc < i srtcmax ? pums[4:0] = (0110, 0111, 1000, 1001) ? on, standby, and standby lpm modes 1.25 1.3 1.35 v i srtcq active mode quiescent current ?v srtcinmin < v strcin < v srtcinmax ?i srtc = 0 - 0.8 - ? a
analog integrated circuit device data ? freescale semiconductor 26 34709 functional block description the 32.768 khz clock is divi ded into a 1.0 hz time tick which drives a 17-bit time of day (tod) counter. the tod counter counts the seconds during a 24 hour period from 0 to 86,399 and will then roll over to 0. when the roll over occurs, it increments the ? 15-bit day counter. the day counter can count up to 32767 days. the 1.0 hz time tick can be used to generate a 1hzi interrupt if unmasked. time of day alarm a time of day alarm (toda) function can be used to turn on the application and alert the proce ssor. if the application is alrea dy on, the processor will be interrupted. the toda and daya regist ers are used to set the alarm time. when the tod counter is equal to the value in toda and the day counter is equal to the value in daya, the todai interrupt will be generated. timer reset as long as the supply at bp is valid, the real time clock will be supplied from vcoredig. if bp is not valid, the real time clo ck can be backed up from a coin cell via the licell pin. w hen the vsrtc voltage drops to the range of 0.9 to 0.8 v, the rtcporb reset signal is generated and the contents of the rtc will be re set. additional registers backed up by coin cell will also rese t with rtcporb. to inform the processor that the contents of the rtc are no longer valid due to the reset, a timer reset interrupt function is implemented with the rtcrsti bit. rtc timer calibration a clock calibration system is provided to adjust the 32,768 cycle counter that generates the 1.0 hz timer for rtc ti ming registers. the general implementation relies on the system processor to measure the 32.768 khz crystal oscillator against a higher frequency and more accurate system clock, such as a tcxo. if the rtc timer needs a correction, a 5-bit 2?s complement calibration word can be sent via the spi, to compensa te the rtc for inaccuracy in its reference oscillator. the available correction range should be sufficient to ensure drift accuracy in compliance with standards for drm time keeping. note that the 32.768 khz oscillator is not affected by rtccal settings; calibr ation is only applied to the rtc time base counter. therefore, the frequency at the cloc k output clk32k is not affected. the rtc system calibration is enabled by programming the rtccalmode[1:0] fo r desired behavior by operational mode. the rtc calibration circuitry can be automatically disabled when ma in battery contact is lost or if it is so deeply discharged that rtc power draw is switched to the coin cell (configured with rtccalmode=01). because of the low rtc consumption, rtc ac curacy can be maintained through long periods of the application being shut down, even after the main battery has discharged. however, it is not ed that the calibration can only be as good as the rtccal data table 15. rtc calibration settings code in rtccal[4:0] correction in counts per 32768 relative correction in ppm 01111 +15 +458 00011 +3 +92 00001 +1 +31 00000 0 0 11111 -1 -31 11101 -3 -92 10001 -15 -458 10000 -16 -488 table 16. rtc calibration enabling rtccalmode function 00 rtc calibration disabled (default) 01 rtc calibration enabled in all modes except coin cell only 10 reserved for future use. do not use. 11 rtc calibration enabled in all modes
analog integrated circuit device data ? 27 freescale semiconductor 34709 functional bloc k description that has been provided, so occasional refreshing is recommended to ensure that any drift infl uencing environmental factors have not skewed the clock beyond desired tolerances. 7.3.3 coin cell battery backup the licell pin provides a connection for a coin cell backup bat tery or supercap. if the main battery is deeply discharged, removed, or contact-bounced (i .e., during a power cut), the rt c system and coin cell maintained logic will switch over to the licell for backup power. this switch over occurs for a bp below 1.8 v threshold with licell greater than bp. a small capacitor should be placed from licell to ground under all circumstances. upon initial insertion of the coin cell, it is not immediatel y connected to the on chip circui try. the cell gets connected when the ic powers on, or after enabling the coin ce ll charger when the ic was already on. the coin cell charger circuit will function as a current-limited voltage source, result ing in the cc/cv taper characteristic ty pically used for rechargeable lithium-ion batteries. the coin cell char ger is enabled via the coinchen bit. the coin cell voltage is programmable through the vcoin[2:0] bits . the coin cell charger voltage is program mable in the on state where the charge current is fixed at icoinhi. if coinchen=1 when the system goes into an off or user off state, the coin cell charger will continue to charge to the predefin ed voltage setting, but at a lower maximum cu rrent icoinlo. this compensates for self discharge of the coin cell and ensures that if/when the main cell gets depleted, that the coin cell will be topped off for maximum rtc retention. the coin cell charging wi ll be stopped for the bp below uvdet. the bit coinchen itself is only cleared when an rtcporb occurs. table 17. coin cell voltage specifications vcoin[2:0] output voltage 000 2.50 001 2.70 010 2.80 011 2.90 100 3.00 101 3.10 110 3.20 111 3.30 table 18. coin cell electrical specifications characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes coin cell charger v licellacc voltage accuracy - 100 - mv i licellon coin cell charge current in on and watchdog modes icoinhi - 60 - ? a i licelloff coin cell charge current in off, cold start/warm start, and low-power off modes (user off / memory hold) icoinlo - 10 - ? a i licelacc current accuracy - 30 - % co licell licell bypass capacitor - 100 - nf licell bypass capacitor as coin cell replacement - 4.7 - ? f
analog integrated circuit device data ? freescale semiconductor 28 34709 functional block description 7.4 interrupt management 7.4.1 control the system is informed about important events, based on interr upts. unmasked interrupt events are signaled to the processor by driving the int pin high; this is true whether th e communication interface is configured for spi or i 2 c. each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. e ach interrupt can be cleared by writing a 1 to the appropriate bit in the interrupt status register, which will also cause the inte rrupt line to go low. if a new interrupt occurs while the processor clear s an existing interrupt bit, the interrupt line will remain high. each interrupt can be masked by setting the corresponding mask bit to a 1. as a result, when a masked interrupt bit goes high, the interrupt line will not go high. a masked interrupt can still be read from the interrupt status register. this gives the pr ocessor the option of polling for status from the ic. the ic powers up wi th all interrupts masked, so t he processor must initially poll the device to determine if any interrupts are ac tive. alternatively, the processor can unma sk the interrupt bits of interest. if a masked interrupt bit was already high, the interrupt line will go high after unmasking. the sense registers contain status and input sense bits, so the system processor can poll the cu rrent state of interrupt source s. they are read only, and not latched or clearable. interrupts generated by external events are debounced. therefore, the event needs to be stable throughout the debounce period before an interrupt is generated. nominal debounce periods for each event are documented in the int summary table following later in this section. due to the asynchronous nature of th e debounce timer, the effective d ebounce time can vary slightly. 7.4.2 interrupt bit summary table 19 summarizes all interrupt, mask, and sens e bits associated with int control. for more detailed behavioral descriptions, refer to the related chapters. table 19. interrupt, mask and sense bits interrupt mask sense purpose trigger debounce time adcdonei adcdonem - adc has finished r equested conversions l2h 0.0 tsdonei tsdonem - touch screen has fi nished conversion l2h 0.0 tspendet tspendetm - touch screen pen detect dual 1.0 ms lowbatt lowbattm - low battery detect sense is 1 if below lowbat threshold h2l programmable vbattdb scpi scpm - regulator short-circuit protection tripped l2h min. 4.0 ms max 8.0 ms 1hzi 1hzm - 1.0 hz time tick l2h 0.0 todai todam - time of day alarm l2h 0.0 pwron1i pwron1m pwron1s power on button 1 event sense is 1 if pwron1 is high. h2l 30 ms (33) l2h 30 ms pwron2i pwron2m pwron2s power on button 2 event sense is 1 if pwron2 is high. h2l 30 ms (33) l2h 30 ms sysrsti sysrstm - system reset through pwronx pins l2h 0.0 wdireseti wdiresetm - wdi silent system restart l2h 0.0 pci pcm - power cut event l2h 0.0 warmi warmm - warm start event l2h 0.0 memhldi memhldm - memory hold event l2h 0.0
analog integrated circuit device data ? 29 freescale semiconductor 34709 functional bloc k description clki clkm clks 32 khz clock source change sense is 1 if source is xtal dual 0.0 rtcrsti rtcrstm - rtc reset has occurred l2h 0.0 therm110 therm110m therm110s thermal 110 c threshold sense is 1 if above threshold dual 30 ms therm120 therm120m therm120s thermal 120 c threshold sense is 1 if above threshold dual 30 ms therm125 therm125m therm125s thermal 125 c threshold sense is 1 if above threshold dual 30 ms therm130 therm130m therm130s thermal 130 c threshold sense is 1 if above threshold dual 30 ms gpiolvxi gpiolvxm gpiolvxs general purpose input interrupt programmable programmable notes 33. debounce timing for the falling edge can be extended with pwronxdbnc[1:0]; refer to serial interfaces for details. table 19. interrupt, mask and sense bits interrupt mask sense purpose trigger debounce time
analog integrated circuit device data ? freescale semiconductor 30 34709 functional block description 7.5 power generation the 34709 pmic provides reference and supply voltages fo r the application processor as well as peripheral device. six buck (step down) converters and one boost (step up) converters are included. one of the buck regulators can be configured in multiphase, single phase mode, or operat e as separate independent outpu ts (in this case, there are six buck converters). the buck converters provide the supply to processor cores and to ot her low-voltage circuits such as io and memory. dynamic voltage scaling is provided to allow controlled supply rail adjustments fo r the processor cores and/or ot her circuitry. the boost conve rter supplies the vusb regulator for the usb phy on the processor. the vusb regulator is powered from the boost to ensure sufficient headroom for the ldo through the no rmal discharge range of the main battery. linear regulators are directly supplied fr om the battery or from th e switching regulator, and include supplies for io and peripherals, such as audio, camera, bluetooth, wireless lan, etc. naming conventions are suggestive of typical or possible use case applications, but the switching and linear regulators may be utilized for othe r system power requirements within the guidelines of specified capabilities. four general purpose i/os ar e available, which can be conf igured as inputs/outputs. as in puts they can be configured as interrupts. 7.5.1 power tree refer to the representative tables and text specifying each su pply for information on performance metrics and operating ranges. table 20 summarizes the available power supplies. 7.5.2 modes of operation the 34709 pmic is fully programmable via the spi interface and associ ated register map. additiona l communication is provided by direct logic interfacing, including inte rrupt, watchdog, and reset. default start-up of the device is selectable by hardwiri ng the power-up mode sele ct (pums) pins. table 20. power tree summary supply purpose (typical application) output voltage (in v) load capability (in ma) sw1 buck regulator for processor vddgp domain 0.650 ? 1.4375 2000 sw2 buck regulator for processor vcc domain 0.650 ? 1.4375 1000 sw3 buck regulator for processor vdd domain and peripherals 0.650 ? 1.425 500 sw4a buck regulator for ddr memory and peripherals 1.200 ? 1.85: 2.5/3.15 500 sw4b buck regulator for ddr memory and peripherals 1.200 ? 1.85: 2.5/3.15 500 sw5 buck regulator for i/o domain 1.200 ? 1.85 1000 swbst boost regulator for usb phy support 5.00/5.05/5.10/5.15 380 vsrtc secure real time clock supply 1.2 0.05 vpll quiet analog supply 1.2/1.25/1.5/1.8 50 vrefddr ddr ref supply 0.6 ? 0.9 10 vdac tv dac supply, external pnp 2.5/2.6/2.7/2.775 250 vusb2 vusb/peripherals supply, internal pmos 2.5/2.6/2.75/3.0 65 vusb/peripherals external pnp 2.5/2.6/2.75/3.0 350 vgen1 general peripherals supply #1 1.2/1.25/1.3/1.35/1.4/1.45/1.5/1.55 250 vgen2 general peripherals supply #2, internal pmos 2.5/2.7/2.8/2.9/3.0/3.1/3.15/3.3 50 general peripherals suppl y #2, external pnp 2.5/2.7/2.8/2.9/3.0/3.1/3.15/3.3 250 vusb usb transceiver supply 3.3 100
analog integrated circuit device data ? 31 freescale semiconductor 34709 functional bloc k description power cycling of the application is driven by the 34709 pmic. it has the interfaces for the power buttons and dedicated signali ng interfacing with the processor. it also ensures the supply of t he real time clock (rtc), critical internal logic, and other cir cuits from the coin cell, in case of brief interruptions from the main battery. a charger for the coin cell is included to ensure tha t it is kept topped off until needed. the 34709 pmic provides the timekeeping, based on an integr ated low-power oscillator runni ng with a standard watch crystal. this oscillator is used for internal clocking, the control logi c, and as a reference for the regulator pll. the timekeeping inc ludes time of day, calendar, and alarm, and is backed up by coin ce ll. the clock is driven to the processor for reference and deep sl eep mode clocking.
analog integrated circuit device data ? freescale semiconductor 32 34709 functional block description figure 6. power control state machine flow diagram the following are text descriptions of the power states of the system for additional details of the state machine to complement the drawing in figure 6 . note that the spi control is only possible in the watchdog, on and user off wait states, and that the interrupt line int is kept low in all states except for watchdog and on. cold start watchdog on start up modes application of power before pcut timer pct[7:0] expiration (pcen=1 and pcmaxcnt not exceeded) reset timer expired reset timer expired watchdog timer expired turn on event (warm start) turn on event (warm boot) processor request for user off: useroffspi=1 warm start enabled warmen=1 warm start not enabled wdi low, wdireset=0 pcut timer pct[7:0] expired pcutexpb cleared to 0 internal memhold power cut warmen=0 user off memory hold from any mode: loss of power with power cuts enabled (pcen=1) and pcmaxcnt not exceeded wdi low, wdireset=1 and pcmaxcnt not exceeded wdi low, wdireset=1 and pcmaxcnt is exceeded user off wait pct[7:0] expired low power off modes from any mode: loss of power with pcen=0, thermal protection trip, or system reset turn on event unqual?d turn on off unqual?d turn on warm start coin cell bp > uvdet bp < uvdet
analog integrated circuit device data ? 33 freescale semiconductor 34709 functional bloc k description 7.5.2.1 coin cell the rtc module is powered from either the battery or the coin cell, due to insufficient voltage at bp, and the ic is not in a p ower cut. no turn on event is accepted in the coin cell state. tr ansition out (to the off state) requires bp restoration with a thre shold above uvdet. resetb, and resetbmcu are held low in this mode. the rtc module remains active (32 khz oscillator + rtc timers), along with bp level detection to qualify ex it to the off state. vcoredig is off and the vddl p regulator is on, the rest of the system is put into it s lowest power configuration. if the coin cell is depleted (vstrc drops to 0.9 v to 0.8 v while in the coin cell state), a co mplete system rese t will occur. at next power application / turn on event, the system will start- up reinitialized with all spi bits including those that reset on rtcporb restored to their default states. 7.5.2.2 off (with good battery) if the supply valways is above the uvdet threshold, only the ic core circuitry at vcoredig and the rtc module are powered, all other supplies are inactive. to ex it the off mode, a valid turn on event is required. no specific timer is running in this mode. resetb and resetbmcu are held low in this mode. if bp is below the uvdet threshold, no turn on events are accepted. if a valid coin cell is present, the core gets powered from licell. the only active circuitry is the rtc module and the detection vcore module powering vcoredig at 1.5 v. to exit the off mode, a valid turn on event is required. 7.5.2.3 cold start cold start is entered upon a turn on event from off, warm boot , successful pcut, or a silent system restart. the first 8.0 ms is used for initialization which includes bias generation, pu msx configuration latching, and qualification of the input supply level bp. the switching and linear regulators are then powered up sequ entially to limit the inrush current; see the power-up section for sequencing and de fault level details. the reset sign als resetb and resetbmcu are kept low. the rese t timer starts running when entering cold start. the co ld start state is exited for the watchdog state and both resetb and resetbmcu become high (open-drain output wit h external pull-ups) when the reset timer is expired. the input control pins wdi, and standby are ignored. 7.5.2.4 watchdog the system is fully powered and under spi control. rese tb and resetbmcu are high. the watchdog timer starts running when entering the watchdog st ate. when expired, the system transitions to the on state, where wdi will be checked and monitored. the input control pins wdi and standby are ignored while in the watchdog state. 7.5.2.5 on mode the system is fully powered and under spi control. resetb and resetbmcu are high. the wdi pin must be high to stay in this mode. the wdi io supply voltage is refe renced to spivcc (normally connected to sw5 = 1.8 v); spivcc must therefore remain enabled to allow fo r proper wdi detection. if wdi goes low, the system will transi tion to the off state or cold start (depending on the configuration; refer to the section on silent system restart with wdi ev ent for details). 7.5.2.6 user off wait the system is fully powered and und er spi control. the wdi pin no longer has co ntrol over the part. t he wait mode is entered by a processor request for user off by setting the useroffspi bit high. this is normally initiate d by the end user via the powe r key; upon receiving the correspon ding interrupt, the system will det ermine if the prod uct has been configured for user off or memory hold states (both of which first require passing through user off wait) or just transition to off. the wait timer starts running when entering user off wait mode. this leaves the processor time to suspend or terminate its task s. when expired, the wait mode is exited fo r user off mode or memory hold mode depending on warm starts being enabled or not via the warmen bit. the useroffspi bit is bein g reset at this point by resetb going low.
analog integrated circuit device data ? freescale semiconductor 34 34709 functional block description 7.5.2.7 memory hold and user off (low-power off states) as noted in the user off wait description, the system is direct ed into low-power off states based on a spi command in response to an intentional turn off by the end user. the only exit then will be a turn on event. to an end user, the memory hold and use r off states look like the product has been shut down completely. however, a faster start-up is facilitated by maintaining extern al memory in self-refresh mode (m emory hold and user off mode) as well as power ing portions of the processor core for state retention (user off only). the switching regulator mode control bits allow selective powering of the buck regulators for optimi zing the supply behavior in the low-power off modes. linear regulator s and most functional blocks are disabled (the rtc module, spi bits resetting with rtcporb, and turn on event detection are maintained). by way of example, the following descriptions assume the typica l use case where sw1 supplies the processor core(s), sw2 is applied to the processor?s vcc domain, sw3 supplies the processo rs internal memory/peripherals, sw4 supplies the external memory, and sw5 supplies the i/o rail. the buck regulators are intended for direct connection to the aforementioned loads. 7.5.2.8 memory hold resetb and resetbmcu are low, and both clk32k and clk32kmcu are disabled (clk32km cu active if drm is set). to ensure that sw1, sw2, sw3, and sw5 shut off in memory hold, appropriate mode settings should be used such as sw1mhmode, = sw2mhmode, = sw3mhmode, = sw5mhmode set to = 0 (refer to the mode control description later in this section). since sw4 should be powered in pfm mode, sw4mhmode could be set to 1. upon a turn on event, the cold start state is entered, the de fault power-up values are loaded, and the memhldi interrupt bit is set. a cold start out of the memory hold state will result in shorter boot times co mpared to starting ou t of the off state, since software does not have to be loaded and expanded from flash. the st art-up out of memory hold is also referred to as warm boot. no specific timer is running in this mode. buck regulators that are configured to stay on in memhold mo de by their swxmhmode settings will not be turned off when coming out of memhold and entering a warm boot. the switching r egulators will be reconfigured for their default settings as selected by the pumsx pins in the norma l time slot that would affect them. 7.5.2.9 user off resetb is low and resetbmcu is kept high. the 32 khz peripheral clock driver clk32k is disabled; clk32kmcu (connected to the processor?s ckil input) is maintained in this mode if the clk32kmcuen and useroffclk bits are both set, or if drm is set. the memory domain is held up by setting sw4uomode = 1. similarly, the sw1 and/or sw2 and/or sw3 supply domains can be configured for swxuomode=1 to keep them powered through th e user off event. if one of the switching regulators can be shut down on in user off, its mode bits would typically be set to 0. since power is maintained for the core (w hich is put into its lowest power state), and since m cu resetbmcu does not trip, the processor?s state may be quickly recovered when exiting us eroff upon a turn on event. the clk32kmcu clock can be used for very low frequency / low-power idling of the core(s), minimizi ng battery drain, while allowing a rapid recovery from where the system left off before the useroff command. upon a turn on event, warm start state is entered, and the default power-up values are loaded. a warm start out of user off wil l result in an almost instan taneous start-up of the system, sinc e the internal states of the pr ocessor were preserved along with external memory. no specific ti mer is running in this mode. 7.5.2.10 warm start entered upon a turn on event from user off. the first 8.0 ms is used for initialization, whic h includes bias generation, pumsx latching, and qualification of the input supply level bp. the sw itching and linear regulators are then powered up sequentially to limit the inrush current; see start-up requirements for sequencing and default level details . if sw1, sw2, sw 3, sw4, and/or sw5, were configured to stay on in user off mode by their swxuomode settings, t hey will not be turned off when coming out of user off and entering a warm start. the buck regulators will be reconfigured for their default settings as selected by the pumsx pins in the respective time sl ot defined in the sequencer selection. resetb is kept low and resetbmcu is kept high. clk32kmcu is kept active if cl k32kmcu was set. the reset timer starts running when entering warm start. when expir ed, the warm start state is exited for the watchdog state, a warmi interrupt is generated, and resetb will go high.
analog integrated circuit device data ? 35 freescale semiconductor 34709 functional bloc k description 7.5.2.11 internal memhold power cut as described in the power cut description , a momentary power interruption will put t he system into the inte rnal memhold power cut state if pcuts are enabled. the backup coin cell will now supply the 34709 core along with the 32 k crystal oscillator, the rtc system, and coin cell backed up register s. all regulators will be shut down to preserve the coin cell and rtc as long as possible. both resetb and resetbmcu are tr ipped, bringing th e entire system dow n along with the su pplies and external clock drivers, so the only recovery out of a power cut state is to reestablish power and initiate a cold start. if the pct timer expires before po wer is re-established, the system transitions to the off state and awaits a sufficient supply recovery. 7.5.3 power control logic 7.5.3.1 power cut description when the bp drops below the uvdet threshold, due to battery bounce or battery removal, th e internal memhold power cut mode is entered and a power cut (pcut) timer starts running. the ba ckup coin cell will now supply the rtc as well as the on chip memory registers and some other power contro l related bits. all other supplies will be disabled. the maximum duration of a power cut is determined by the pcut timer pct [7:0] preset via the spi. when a pcut occurs, the pcut timer will be started. the contents of pct [7:0] does not reflect the actual count do wn value, but will keep the programmed value, and therefore does not have to be reprogrammed after each power cut. if power is not re-e stablished above the 3.0 v threshold before the pcut timer expires, the state machine transitions to the off mode at expiration of the counter, and clears the pcutexb bit by sett ing it to 0. this transition is referred to as an ?unsucce ssful? pcut. in addition the pmic will bring the sdwnb pin low for one 32 khz clock cycle befo re powering down. upon re-application of power bef ore expiration (a ?successful pcut?, defined as bp first rising above the uvdet threshold and then battery above the 3.0 v threshold before the pcut timer expires), a cold start is engaged after the uvtimer has expired. in order to distinguish a non-pcut initiate d cold start from a cold start after a p cut, the pci interrupt should be checked by software. the pci interrupt is cleared by so ftware or when cycling through the off state. because the pcut system quickly disables the entire power tree, the battery voltage may recover to a level with the appearance of a valid supply once the battery is unloaded. however, upon a restart of the ic and power sequencer, the surge of current through the battery and trace impedances ca n once again cause the bp node to droop below uvdet. this chain of cyclic power down / power-up sequences is referred to as ?ambulance mode?, and the power control system includes strategies to minimize the chance of a product falling into and getting stuck in ambulance mode. first, the successful recovery out of a pcut requires the bp node to rise above lobatt threshold, providing hysteretic margin from the lobatt (h to l) threshold. se condly, the number of times the pcut m ode is entered is coun ted with the counter pccount [3:0], and the allowed count is limited to pcmaxcnt [3:0] set through the spi. when the contents of both become equal, then the next pcut will not be support ed and the system will go to off mo de, after the pcut time expires. after a successful power-up after a pcut (i.e ., valid power is reestablis hed, the system comes out of reset, and the processor reassumes control), softwa re should clear the pccount [3:0] counter. counting of pc ut events is enabled via the pccounten bit. this mode is only supported if the power cu t mode feature is enabled by setting the pcen bit. when not enabled, then in case of a power failure, the state machine will transition to the of f state. spi control is not possible durin g a pcut event and the interrupt line is kept low. spi configur ation for pcut support should also include setting the pcutexpb = 1 (see silent restart from pcut event ). 7.5.3.2 silent restart from pcut event if a short duration power cut event occurs (such as from a batte ry bounce, for example), it may be desirable to perform a silen t restart, so the system is reinitialized without alerti ng the user. this can be facilitated by setting the pcut expb bit to ?1? a t booting or after a cold start. this bit resets on rtcporb, therefore any subs equent cold start can first check the status of pcutexpb and the pci bit. the pcutexpb is cleared to ?0? when transitioning from pcut to off. if there was a pcut interrupt and pcutexpb is still ?1?, then the state machine has not transitione d through off, which confirms t hat the pct timer has not expir ed during the pcut event (i.e., a successful power cut). in this case, a silent restart may be appropriate.
analog integrated circuit device data ? freescale semiconductor 36 34709 functional block description if pcutexpb is found to be ?0? after the cold start where pci is found to be ?1?, th en it is inferred that the pct timer has ex pired before power was reestablished, flagging an unsuccessful power cu t or first power-up, so the start-up user greeting may be desirable for playback. 7.5.3.3 silent system restart with wdi event a mechanism is provided for recovery if the system software somehow gets into an abnormal state which requires a system reset, but it is desired to make the reset a silent event so as to ha ppen without end user awareness. the default response to wdi goin g low is for the state machine to transi tion to the off state (when wdireset = 0). however, if wdireset = 1, the state machine will go to cold start without passing through off mode (i.e., does not generate an offb signal). a wdireset event will generate a maskable wd ireseti interrupt and also increment th e pccount counter. this function is unrelated to pcuts, but it shares the p cut counter so that the number of silent system restarts can be limited by the programmable pcmaxcnt counter. when pcut support is used, the software should set the pcutexpb bit to ?1?. since th is bit resets with rtcporb, it will not be reset to ?0? if a wdi falls and the state machine goes straig ht to the cold start state. t herefore, upon a restart, software can discern a silent system re start if there is a wdir eseti interrupt and pcutexpb = 1. the application may then determine that an inconspicuous restart without fanfare may be more app ropriate than launching into the welcoming routine. a pcut event does not trip the wdireseti bit. note that the system response to wdi is gated by the watchdog ti mer?once the timer has expired, then the system will respond as programmed by wdireset and described above. 7.5.3.4 turn on events when in off mode, the circuit can be powered on via a turn on event. the turn on events are listed by the following. to indicat e to the processor what event caused the system to power on, an interrupt bit is asso ciated with each of the turn on events. masking the interrupts related to the turn on events will not prevent the part to turn on except for the time of day alarm. if the part was already on at the time of the turn on event, the interrupt is still generated. ? power button press: pwron1, or pwron2 pulled low with correspo nding interrupts and sense bits pwron1i or pwron2i, and pwron1s or pwron2s. a power on/off button is connected from pwronx to ground. the pwronx can be hardware debounced through a pr ogrammable debouncer pwronxdbnc [1:0] to avoid a response upon a very short (i.e., unintentional) key press. bp should be a bove uvdet to allow a power-up. the pwro nxi interrupt is generated for both the falling and the rising edge of the pwronx pin. by default, a 30 ms interrupt debounce is applied to both falling and rising edges. the falling edge debounce timing can be extended with pwronxdbnc[1:0] as defined in the following table. the pwronxi interrupt is cleared by softwa re or when cycling through the off mode. ? battery attach: this occurs when bp crosses the 3.0v threshold and the uvdet rising threshold which is equivalent to attaching a charged battery or supply to the product. ? rtc alarm: tod and day become equal to the alarm setting programm ed. this allows powering up a product at a preset time. bp should be above 3.0v, and bp should have crossed the uvdet rising threshold and not transitioned below the uvdet falling threshold. ? system restart: system restart which may occu r after a system reset as descr ibed earlier in this sect ion. this is an optional function, see turn off events . bp should be above 3.0 v and bp should have crossed the uvdet rising threshold and not transitioned below the uvdet falling threshold. table 21. pwronx hardware debounce bit settings (34) bits state turn on debounce (ms) falling edge int debounce (ms) rising edge int debounce (ms) pwronxdbnc[1:0] 00 0.0 31.25 31.25 01 31.25 31.25 31.25 10 125 125 31.25 11 750 750 31.25 notes 34. the sense bit pwronxs is not debounced and follows the state of the pwronx pin.
analog integrated circuit device data ? 37 freescale semiconductor 34709 functional bloc k description ? global system reset: the global reset feature powers down the part, disabl es the charger, resets the spi registers to their default value including all the rtcporb registers (except the drm bit, and the rtc registers), and then powers back on. to enable a global reset, the glbrst pin needs to be pulled low for greater than glbrsttmr [1:0] seconds and then pulled back high (defaults to 12 s). bp should be above 3.0 v. 7.5.3.5 turn off events ? power button press (via wdi): user shut down of a product is typically do ne by pressing the power button connected to the pwronx pin. this will generate an interrupt (pwronxi), but will not directly power off the part. the product is powered off by the processor?s response to this interrupt, which will be to pull wdi low. pressing the power button is therefore under norm al circumstances not considered as a turn off event for the stat e machine. however, since the button press power down is the most common turn off method for end products, it is described in this section as the product im plementation for a wdi initiated turn off event. note that the software can configure a user in itiated power down, via a power button press for transition to a low-power off mode (memory hold or user off) for a quicke r restart than the default transition into the off state. ? power button system reset: a secondary application of the pwronx pins is the option to g enerate a system reset. this is recognized as a turn off event. by default, the system re set function is disabled but can be enabled by setting the pwronxrsten bits. when enabled, a four second long press on the power button will cause the device to go to the off mode, and as a result, the entire application will power down. an interrupt sysrsti is gener ated upon the next power-up. alternatively, the system can be configured to rest art automatically by sett ing the restarten bit. ? thermal protection: if the die gets overheated, the thermal protection will power off the part to avoid damage. a turn on event will not be accepted while the thermal protection is still being tr ipped. the part will remain in off mode until cooling sufficiently to accept a turn on event. there are no specific interrupts related to this ot her than the warning interrupts. ? under-voltage detection: when the voltage at bp drops below the under-v oltage detection threshold uvdet, the state machine will transition to off mode if pcut is not enabled, or if the pct timer expires when pcut is enabled. the sdwnb pin is used to notify that the processor that the pmic is going to immediately shut down. the pmic will bring the sdwnb pin low for one 32 khz clock cycle before powering down. this signal will then be brought back high in the power off state. 7.5.3.6 timers the different timers as used by the state machine are listed by the following. this listing does not include rtc timers for timekeeping. a synchronization error of up to one clock peri od may occur with respect to the occurrence of an asynchronous event, the duration listed below is ther efore the effective minimum time period. table 22. global reset time settings bits state time (s) glbrsttmr[1:0] 00 invalid 01 4.0 10 8.0 11 (default) 12 table 23. timer main characteristics timer duration clock under-voltage timer 4.0 ms 32 k/32 reset timer 40 ms 32 k/32 watchdog timer 128 ms 32 k/32 power cut timer programmable 0 to 8 seconds in 31.25 ms steps 32 k/1024
analog integrated circuit device data ? freescale semiconductor 38 34709 functional block description 7.5.3.6.1 timing diagrams a turn on event timing diagrams shown in figure 7 . figure 7. power-up timing diagram 7.5.3.7 power monitoring the voltage at bp are monitored by detectors as summarized in table 24 . the uvdet and power on thresholds are related to the power on/off events as described earlier in this chapter. in order for the ic to power on, bp must rise above the uvdet rising threshold, and the power on threshold (3.0 v) threshold. when the bp node decreases below the 2.9 v threshold, a low input supply warning will be s ent to the processor via the lowbatti interrupt. the lowbatti detection threshold is debounc ed by the vbattdb[2:0] spi bits shown in table 25 . table 24. lowbatt detection thresholds threshold voltage (v) power on 3.0 low input supply warning ? bp (h to l) (35) 2.9 uvdet rising (36) 3.0 uvdt falling (36) 2.65 notes 35. 50 mv hysteresis is applied. 36. 4.0 % tolerance resetb wdi int uv masking 8 ms 20 ms 12 ms power up sequencer turn on verification 128 ms 2 - cold start 1 - off system core active 3 - watchdog 4 - on 1 - off 3- watchdog power up of the system upon a turn on event followed by a transition to the on state if wdi is pulled high ... or transition to off state if wdi remains low turn on event sequencer time slots wdi pulled low = indeterminate state ow turn on event is based on pwron being pulled low 8 ms
analog integrated circuit device data ? 39 freescale semiconductor 34709 functional bloc k description 7.5.3.8 power saving 7.5.3.8.1 system standby a product may be designed to enter dsm after periods of inactivity , the standby pin is provided for board level control of timi ng in and out of such deep sleep modes. when a product is in dsm, it may be able to reduce the overal l platform current by lowering the regulator output voltage, chang ing the operating mode of the switching regulators, or disabling some regulators. this can be obtained by controlling the standby pin. the configuration of the regulators in standby is pre-programmed through the spi. a lower power standby mode can be obtained by setting the on_stby_lp spi bit to a one. with the on_stby_lp spi bit set and the standby pin asserted, a lower power standby will be entered. in the on standby low-power mode, the switching regulators should all be programmed into pfm mode, and the ldo's should be configured to low-power mode when the standby pin is asserted. the pll is disabled in this mode note that the standby pin is programmable for active high or active low polarity, and the decoding of a standby event will take into account the programmed input pola rity associated with each pin. for simpli city, standby will generally be referred to as active high throughout this document, but as defined in table 26 , active low operation can be accommodated. finally, since the standby pin activity is driven asynchrono usly to the system, a finite time is required for the inte rnal logic to qualify and re spond to the pin level changes. the state of the standby pin only has influence in on mode, and are therefore it is ignored duri ng start-up and in the watchdog phase. this allows the system to power-up without concern of the requ ired standby pola rities since soft ware can make adjustments accordingly as soon as it is running. a command to transition to one of the low-power off states (u ser off or memory hold, initiat ed with use-roff spi=1) redefines the power tree configuration based on swxmode programming, and ha s priority over standby (which also influences the power tree configuration). 7.5.3.8.2 standby delay a provision to delay the standby response is included. this al lows the processor and peripherals, some time after a standby instruction has been received, to terminate processes to fa cilitate seamless standby exiti ng and re-entrance into normal operating mode. a programmable delay is provided to hold off the system response to a standby event. when enabled (stbydly = 01, 10, or 11), stbydly will delay the standby initiated response for the entire ic until the stbydly counter expires. table 25. vbattdb debounce times vattdb[1:0] debounce time (ms) 00 0.1 01 1.0 10 2.5 11 (default) 3.9 table 26. standby pin and polarity control standby (pin) standbyinv (spi bit) standby control (37) 0 0 0 0 1 1 1 0 1 1 1 0 notes 37. standby = 0: system is not in standby standby = 1: system is in standby
analog integrated circuit device data ? freescale semiconductor 40 34709 functional block description note that this delay is applied only when going into standby , and no delay is applied when coming out of standby. also, an allowance should be accounted for synchronization of the asynchronous standby event and the internal clocking edges (up to a full 32 k cycle of additional delay). 7.5.4 buck switching regulators six buck switching regulators are provided with integrated power switches and synchronous rectific ation. in a typical applicati on, sw1 and sw2 are used for supplying the application processo r core power domains. split power domains allow independent dvs control for processor power optimization, or to support te chnologies with a mix of device types with different voltage rati ngs. sw3 is used for powering internal processor memory as well as low-voltage peripheral devices and interfaces which can run at the same voltage level. sw4a/b is used for powering extern al ddr memory as well as low-voltage peripheral devices and interfaces, which can run at the same voltage level. sw5 is used to supply the i/o domain for the system. the buck regulators are supplied fr om the system supply bp, which is drawn from the main battery the switching regulators can operate in different modes depending on the load conditio ns. these modes can be set through the spi and include a pfm mode, pwm pulse skip, an automatic pulse skipping mode, and a pwm mode. buck modes of operation are programmable for explicitly defined or load-dependent control. when initially activated, regulators output s will apply controlled stepping to the progr ammed value. the soft start feature lim its the inrush current at start-up. during soft start, the regulator will be forced to pwm mode for 3.0 ms and then def ault to the aps mode a built in current limiter ensures that during normal operation the maximum current through the coil is not exceeded. point of load feedback is intended for minimi zing errors due to board level ir drops. 7.5.4.1 general control operational modes of the buck regulators can be controlled by direct spi programmi ng, altered by the state of the standby pin, by direct state machine influence (i .e., entering off or low-power off states, for example), or by load current magnitude when so configured (auto pulse skip mode). available modes inclu de pwm with no pulse skipping (pwm), pwm with pulse skipping (pwmps), pulse frequency mode (pfm), automatic pulse skip ( aps), and off. the transition between the two modes pwmps and pwm can occur automatically, based on the load current (auto pulse skip mode). for light loading, the regulators should be put into pfm mode to optimize efficiency. sw1a/b, sw2, sw3, sw4a/b, and sw5, can be configured fo r mode switching with standby or autonomously, based on load current auto pulse skip mode. additionally, provisions are made for maintaining pfm operation in user off and memhold modes, table 27. delay of standby- initiated response stbydly[1:0] function 00 no delay 01 one 32 k period (default) 10 two 32 k periods 11 three 32 k periods table 28. buck operating modes mode description off the regulator is switched off and the output voltage is discharged pfm the regulator is switched on and set to pfm mode operation. in this mode, the regulator is always running in pfm mode. useful at light loads for optim ized efficiency. aps the regulator is switched on and set to automatic pulse skipping. in this mo de the regulator moves automatically between pulse skipping and full pw m mode depending on load conditions. pwm the regulator is switched on and set to pwm mode. in this mode the regulator is always in full pwm mode operation regardless of load conditions. pwmps the regulator is alternating between pulse ski pping and pwm modes, depending on the load conditions.
analog integrated circuit device data ? 41 freescale semiconductor 34709 functional bloc k description to support state retention for faster start- up from the low-power off modes for warm start or warm boot. swxmode[3:0] bits will be reset to their default values defined by pumsx settings by the start-up sequencer. table 29 summarizes the buck regulators progra mmability for normal and standby modes. in addition to controlling the operating m ode in standby, the voltage setting can be changed. the transition in voltage is hand led in a controlled slope manner, see serial interfaces for details. each regulator has an associated set of spi bits for standby mode set points. by default, the standby settings are identical to the non-standby settings which are initially defined by pumsx programming. the actual operating mode of the switching regulators as a functi on of the standby pin is not re flected through the spi. in oth er words, the spi will read back what is programmed in swxmode[3: 0], not the actual state that may be altered as described previously. two tables follow for mode control in the low-power off states. note that a low-powe r off activated swx should use the standby set point as programmed by swxstby[4:0]. the activated regulato r(s) will maintain settings for mode and voltage until the next start-up event. when the respective time slot of the start-up sequencer is reached for a giv en regulator, its mode and voltage settings will be updated the same as if starting out of the off state (except that switching regulators active through a low-po wer off mode will not be off when the start-up sequencer is started). table 29. switching regulator mode control for normal and standby operation swxmode[3:0] normal mode standby mode 0000 off off 0001 pwm off 0010 pwmps off 0011 pfm off 0100 aps off 0101 pwm pwm 0110 pwm aps 0111 off off 1000 aps aps 1001 pwm pwmps 1010 pwmps pwmps 1011 pwmps aps 1100 aps pfm 1101 pwm pfm 1110 pwmps pfm 1111 pfm pfm table 30. switching regulator control in memory hold swxmhmode memory hold operational mode (38) 0 off 1 pfm notes: 38. for memory hold mode, an activated swx should use the standby set point as programmed by swxstby[4:0].
analog integrated circuit device data ? freescale semiconductor 42 34709 functional block description in normal steady state operating m ode, the sw1xpwgd pin is high. when the buck charger set point is changed to a higher or lower set point, the sw1xpwgd pin will go low and will go high again when the higher/lower set point is reached. 7.5.4.2 switching frequency a pll generates the switching system clocking from the 32.768 khz crystal oscillator referenc e. the switching frequency can be programmed to 2.0 mhz or 4.0 mhz by setting the pllx spi bit as shown in table 32 . the clocking system provides a near instantaneous activation wh en the switching regulators are enabled or when exiting pfm operation for pwm mode. the pll can be conf igured for continuous operation with pllen = 1. 7.5.4.3 sw1 sw1 is fully integrated synchronous buck pwm voltage mode contro l dc/dc regulator. it can be o perated in single phase/dual phase mode. the operating mode of the s witching regulators is configured by the sw 1cfg pin. the sw1cfg pin is sampled at start-up. table 31. switching regulator control in user off swxuomode user off operational mode (39) 0 off 1 pfm notes: 39. for user off mode, an ac tivated swx should use the standby set point as programmed by swxstby[4:0]. table 32. buck regulator frequency pllx switching frequency (hz) 0 2 000 000 1 4 000 000 table 33. sw1 configuration sw1cfg sw1a/b configuration mode vcoredig single phase mode ground dual phase mode
analog integrated circuit device data ? 43 freescale semiconductor 34709 functional bloc k description figure 8. sw1 single phase output mode block diagram figure 9. sw1 dual phase output mode block diagram driver controller sw1in sw 1alx sw 1 fb i sen se c osw1a c in sw 1 a l sw 1a spi interface gndsw1a sw 1 sw 1amode sw1 fault bp driver controller sw1 bin sw 1blx i sen se c in sw 1 b gndsw1b sw 1bmode sw1 bfault bp sw 1cfg vcoredig ea z1 z2 internal com pensation v ref dac spi d sw 1 driver contr oller ea z1 z2 internal compensation sw 1 in sw1 alx sw1 fb i sen se c osw1a c in sw 1 a l sw 1 a spi interface gndsw1a sw 1 sw1amode sw 1fault v ref dac spi bp driver contr oller sw 1bin sw1 blx i sen se c osw 1b c in sw 1 b l sw 1 b gndsw1b sw1bmode sw1bfault bp sw 1cfg d sw 1 a d sw 1 b
analog integrated circuit device data ? freescale semiconductor 44 34709 functional block description the peak current is sensed internally fo r over-current protection purposes. if an ove r-current condition is detected the regula tor will limit the current through cycle by cycle operation and alert the syst em through the sw1fault spi bit and issue an scpi interrupt via the int pin. sw1a/b output voltage is spi conf igurable in step sizes of 12.5 mv as shown in the table below. the spi bits sw1a[5:0] set the output voltage for both the sw1a and sw1b. table 34. sw1a/b output voltage programmability set point sw1a[5:0] sw1a/b output (v) set point sw1a[5:0] sw1a/b output (v) 0 000000 0.6500 32 100000 1.0500 1 000001 0.6625 33 100001 1.0625 2 000010 0.6750 34 100010 1.0750 3 000011 0.6875 35 100011 1.0875 4 000100 0.7000 36 100100 1.1000 5 000101 0.7125 37 100101 1.1125 6 000110 0.7250 38 100110 1.1250 7 000111 0.7375 39 100111 1.1375 8 001000 0.7500 40 101000 1.1500 9 001001 0.7625 41 101001 1.1625 10 001010 0.7750 42 101010 1.1750 11 001011 0.7875 43 101011 1.1875 12 001100 0.8000 44 101100 1.2000 13 001101 0.8125 45 101101 1.2125 14 001110 0.8250 46 101110 1.2250 15 001111 0.8375 47 101111 1.2375 16 010000 0.8500 48 110000 1.2500 17 010001 0.8625 49 110001 1.2625 18 010010 0.8750 50 110010 1.2750 19 010011 0.8875 51 110011 1.2875 20 010100 0.9000 52 110100 1.3000 21 010101 0.9125 53 110101 1.3125 22 010110 0.9250 54 110110 1.3250 23 010111 0.9375 55 110111 1.3375 24 011000 0.9500 56 111000 1.3500 25 011001 0.9625 57 111001 1.3625 26 011010 0.9750 58 111010 1.3750 27 011011 0.9875 59 111011 1.3875 28 011100 1.0000 60 111100 1.4000 29 011101 1.0125 61 111101 1.4125 30 011110 1.0250 62 111110 1.4250 31 011111 1.0375 63 111111 1.4375
analog integrated circuit device data ? 45 freescale semiconductor 34709 functional bloc k description table 35. sw1a/b electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes sw1a/b buck regulator v sw1in operating input voltage ? pwm operation, 0 < il < i max ? pfm operation, 0 < il < il max 3.0 2.8 - - 4.5 4.5 v v sw1acc output voltage accuracy ? pwm mode including ripple, lo ad regulation, and transients ? pfm mode, including ripple, load regulation, and transients nom-25 nom-25 nom nom nom+25 nom+25 mv (40) i sw1 continuous output load current, v inmin < bp < 4.5 v ? pwm mode single/dual phase (parallel) ? sw1 in pfm mode - - - 50 2000 - ma i sw1peak current limiter peak current detection ?v in = 3.6 v, current through inductor - 4.0 - a i sw1 transient transient load change ? 100 ma/s - - 1.0 a v sw1os- start start-up overshoot, il = 0 - 25 mv t on-sw1 turn-on time ? enable to 90% of end value il = 0 - - 500 s f sw1 switching frequency ? pllx = 0 ? pllx = 1 - - 2.0 4.0 - - mhz i sw1q quiescent current consumption ? pwmps or aps mode, il=0 ma; device not switching ? pfm mode, il=0 ma - - 160 15 - - a efficiency, ?pfm, 0.9 v, 1.0 ma ? pwm pulse skipping, 1.1 v, 200 ma ? pwm pulse skipping, 1.1 v, 800 ma ?pwm, 1.1 v, 1600 ma - - - - 54 75 81 76 - - - - % (41) notes: 40. transient loading for load steps of ilmax/2. 41. efficiency numbers at v in = 3.6 v, excludes the quiescent current
analog integrated circuit device data ? freescale semiconductor 46 34709 functional block description 7.5.4.4 sw2 sw2 is fully integrated synchronous buck pwm voltage-mode control dc/dc regulator. figure 10. sw2 block diagram the peak current is sensed internally for ov er-current protection purposes. if an over-current condition is detected, the regul ator will limit the current through cycle by cycle operation, alert th e system through the sw2fault spi bit, and issue an scpi interrupt via the int pin. sw2 can be programmed in step sizes of 12.5 mv as shown in table 36 . table 36. sw2 output voltage programmability set point sw2[5:0] sw2x output (v) set point sw2[5:0] sw2 output (v) 0 000000 0.6500 32 100000 1.0500 1 000001 0.6625 33 100001 1.0625 2 000010 0.6750 34 100010 1.0750 3 000011 0.6875 35 100011 1.0875 4 000100 0.7000 36 100100 1.1000 5 000101 0.7125 37 100101 1.1125 6 000110 0.7250 38 100110 1.1250 7 000111 0.7375 39 100111 1.1375 8 001000 0.7500 40 101000 1.1500 9 001001 0.7625 41 101001 1.1625 10 001010 0.7750 42 101010 1.1750 11 001011 0.7875 43 101011 1.1875 12 001100 0.8000 44 101100 1.2000 13 001101 0.8125 45 101101 1.2125 14 001110 0.8250 46 101110 1.2250 15 001111 0.8375 47 101111 1.2375 16 010000 0.8500 48 110000 1.2500 driver controller ea z1 z2 internal compensation sw 2 in sw 2lx sw2 fb i sen se c osw2 c in sw 3 l sw 2 spi interface gndsw2 sw 2 sw 2mode sw2fault v ref dac spi bp d sw 2
analog integrated circuit device data ? 47 freescale semiconductor 34709 functional bloc k description 17 010001 0.8625 49 110001 1.2625 18 010010 0.8750 50 110010 1.2750 19 010011 0.8875 51 110011 1.2875 20 010100 0.9000 52 110100 1.3000 21 010101 0.9125 53 110101 1.3125 22 010110 0.9250 54 110110 1.3250 23 010111 0.9375 55 110111 1.3375 24 011000 0.9500 56 111000 1.3500 25 011001 0.9625 57 111001 1.3625 26 011010 0.9750 58 111010 1.3750 27 011011 0.9875 59 111011 1.3875 28 011100 1.0000 60 111100 1.4000 29 011101 1.0125 61 111101 1.4125 30 011110 1.0250 62 111110 1.4250 31 011111 1.0375 63 111111 1.4375 table 37. sw2 electrical specifications characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes sw2 buck regulator v sw2in operating input voltage ? pwm operation, 0 < il < i max ? pfm operation, 0 < il < il max 3.0 2.8 - - 4.5 4.5 v v sw2acc output voltage accuracy ? pwm mode including ripple, lo ad regulation, and transients ? pfm mode, including ripple, load regulation, and transients nom-25 nom-25 nom nom nom+25 nom+25 mv (42) i sw2 continuous output load current, v inmin < bp < 4.5 v ? pwm mode ? pfm mode - - - 50 1000 - ma i sw2peak current limiter peak current detection ?v in = 3.6 v current through inductor - 2.0 - a i sw2 transient transient load change ? 100 ma/s - - 0.500 a v sw2os- start start-up overshoot, il = 0 - - 25 mv t on-sw2 turn-on time ? enable to 90% of end value il = 0 - - 500 s table 36. sw2 output voltage programmability set point sw2[5:0] sw2x output (v) set point sw2[5:0] sw2 output (v)
analog integrated circuit device data ? freescale semiconductor 48 34709 functional block description 7.5.4.5 sw3 sw3 is fully integrated synchronous buck pwm voltage mode control dc/dc regulator. figure 11. sw3 block diagram the peak current is sensed internally fo r over-current protection purposes. if an ove r-current condition is detected the regula tor will limit the current through cycle by cycle operation and alert the syst em through the sw3fault spi bit and issue an scpi interrupt via the int pin. sw3 can be programmed in step sizes of 25 mv as shown in table 38 . sw2 buck regulator (continued) f sw2 switching frequency ? pllx = 0 ? pllx = 1 - - 2.0 4.0 - - - mhz i sw2q quiescent current consumption ? pwmps or aps mode, il=0 ma; device not switching ? pfm mode, il = 0 ma; device not switching - - 160 15 - - a efficiency ?pfm, 0.9 v, 1.0 ma ? pwm pulse skipping, 1.2 v, 120 ma ? pwm pulse skipping, 1.2 v, 500 ma ?pwm, 1.2 v, 1000 ma - - - - 54 75 83 78 - - - - % (43) notes: 42. transient loading for load steps of ilmax/2. 43. efficiency numbers at v in = 3.6 v, excludes the quiescent current. table 37. sw2 electrical specifications characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes driver contr oller ea z1 z2 internal compensation sw3 in sw3lx sw 3 fb i sen se c osw3 c in sw 3 l sw 3 spi interface gndsw3 sw 3 sw3mode sw 3fault v ref dac spi bp d sw 3
analog integrated circuit device data ? 49 freescale semiconductor 34709 functional bloc k description table 38. sw3 output voltage programmability set point sw3[4:0] sw3 output (v) set point sw3[4:0] sw3 output (v) 0 00000 0.6500 16 10000 1.0500 1 00001 0.6750 17 10001 1.0750 2 00010 0.7000 18 10010 1.1000 3 00011 0.7250 19 10011 1.1250 4 00100 0.7500 20 10100 1.1500 5 00101 0.7750 21 10101 1.1750 6 00110 0.8000 22 10110 1.2000 7 00111 0.8250 23 10111 1.2250 8 01000 0.8500 24 11000 1.2500 9 01001 0.8750 25 11001 1.2750 10 01010 0.9000 26 11010 1.3000 11 01011 0.9250 27 11011 1.3250 12 01100 0.9500 28 11100 1.3500 13 01101 0.9750 29 11101 1.3750 14 01110 1.0000 30 11110 1.4000 15 01111 1.0250 31 11111 1.4250 table 39. sw3 electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes sw3 buck regulator v sw3in operating input voltage ? pwm operation, 0 < il < i max ? pfm operation, 0 < il < il max 3.0 2.8 - - 4.5 4.5 v v sw3acc output voltage accuracy ? pwm mode including ripple, lo ad regulation, and transients ? pfm mode, including ripple, load regulation, and transients nom-3% nom-3% nom nom nom+3% nom+3% mv (44) i sw3 continuous output load current, v inmin < bp < 4.5 v ? pwm mode ? pfm mode - - - 50 500 - ma i sw3peak current limiter peak current detection ?v in = 3.6 v current through inductor - 1.0 - a i sw3 transient transient load change ? 100 ma/s - - 250 ma v sw3os- start start-up overshoot, il = 100 ma/s - - 25 mv t on-sw3 turn-on time ? enable to 90% of end value il = 0 - - 500 s
analog integrated circuit device data ? freescale semiconductor 50 34709 functional block description 7.5.4.6 sw4 sw4a/b is fully integrated syn chronous buck pwm voltage mode control dc/dc regu lator. it can be operated in (single phase/ dual phase mode) or as separate independent outputs. the operat ing mode of the switching regulator is configured by the sw4cfg pin. the sw4cfg pi n is sampled at start-up. sw3 buck regulator (continued) f sw3 switching frequency ? pllx = 0 ? pllx = 1 - - 2.0 4.0 - - mhz i sw3q quiescent current consumption ? pwmps or aps mode, il=0 ma; device not switching ? pfm mode, il = 0 ma; device not switching - - 160 15 - - a efficiency ?pfm, 1.2 v, 1.0 ma ? pwm pulse skipping, 1.2 v, 120 ma ? pwm pulse skipping, 1.2 v, 250 ma ?pwm, 1.2 v, 500 ma - - - - 71 79 82 81 - - - - % (45) notes: 44. transient loading for load steps of ilmax/2 45. efficiency numbers at vin=3.6 v, excludes the qui escent current, table 40. sw4a/b configuration sw4cfg sw4a/b config uration mode ground separate independent output vcoredig single phase vcore dual phase table 39. sw3 electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? 51 freescale semiconductor 34709 functional bloc k description figure 12. sw4a/b separate output mode block diagram driver controller ea z1 z2 internal compensation sw 4in sw 4alx sw 4 afb i sen se c osw4a c in sw 4 a l sw 4 a spi interface gndsw4a sw4a sw 4amode sw4 afault v ref dac spi bp driver controller ea z1 z2 internal compensation sw4bin sw 4blx sw 4 bfb i sen se c osw 4b c in sw 4 b l sw 4 b gndsw4b sw4b sw 4bmode sw4 bfault v ref dac spi bp sw4 cfg d sw 4 a d sw 4 b
analog integrated circuit device data ? freescale semiconductor 52 34709 functional block description figure 13. sw4 single phase output mode block diagram driver controller ea z1 z2 internal compensation sw4in sw4alx sw4afb i sense c osw4a c insw4a l sw4a spi interface gndsw4a sw4 sw4amode sw4afault v ref dac spi bp driver controller ea z1 z2 internal compensation sw4bin sw4blx sw4bfb i sense c insw4b gndsw4b sw4bmode sw4bfault v ref dac spi bp sw4cfg vcoredig d sw4
analog integrated circuit device data ? 53 freescale semiconductor 34709 functional bloc k description figure 14. sw4 dual phase output mode block diagram the peak current is sensed internally for ov er-current protection purposes. if an ove r-current condition is detected, the regul ator will limit the current through cycle by cycle operation, alert th e system through the sw4xfault spi bit, and issue an scpi interrupt via the int pin. sw4a/b has a high output range (2.5 v or 3.15 v) and a low output range (1.2 v to1.85 v). the sw4a/b output range is set by the pums configuration at startup and cannot be changed dynamically by software. this means that if the pu ms are set to allow sw4a to come up in the high output voltage ra nge, the output can only be changed between 2.5 v or 3.15 v. it cannot be programmed in the low output range. if softw are sets the sw4ahi[1:0]= 00, when the pums is set to come up into the high voltage range, the output voltage will only go as low as the lowest setting in the high range which is 2.5 v. if the pums are set to start up in the low output voltage r ange, the voltage is controlled through the sw4x[4:0] bits by so ftware. it cannot be programmed into the high voltage range. when changing the volt age in either the high or low voltage range, the switcher shoul d be forced into pwm mode to change the voltage. table 41. sw4a/b output voltage select sw4xhi[1:0] set point selected by output voltage 00 sw4x[4:0] see table 42 01 sw4xhi[1:0] 2.5 v 10 sw4xhi[1:0] 3.15 v driver controller ea z1 z2 internal compensation sw4in sw4alx sw4afb i sense c osw4a c insw4a l sw4a spi interface gndsw4a sw4 sw4amode sw4afault v ref dac spi bp driver controller ea z1 z2 internal compensation sw4bin sw4blx sw4bfb i sense c osw4b c insw4b l sw4b gndsw4b sw4bmode sw4bfault v ref dac spi bp sw4cfg vcore d sw4a d sw4b
analog integrated circuit device data ? freescale semiconductor 54 34709 functional block description table 42. sw4a/b output voltage programmability set point sw4x[4:0] sw4x output (v) set point sw4x[4:0] sw4x output (v) 0 00000 1.2000 16 10000 1.6000 1 00001 1.2250 17 10001 1.6250 2 00010 1.2500 18 10010 1.6500 3 00011 1.2750 19 10011 1.6750 4 00100 1.3000 20 10100 1.7000 5 00101 1.3250 21 10101 1.7250 6 00110 1.3500 22 10110 1.7500 7 00111 1.3750 23 10111 1.7750 8 01000 1.4000 24 11000 1.8000 9 01001 1.4250 25 11001 1.8250 10 01010 1.4500 26 11010 1.8500 11 01011 1.4750 - - - 12 01100 1.5000 - - - 13 01101 1.5250 - - - 14 01110 1.5500 - - - 15 01111 1.5750 - - - table 43. sw4a/b electrical specifications characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes sw4a/b buck regulator v sw4in operating input voltage ? pwm operation, 0 < il < i max ? pfm operation, 0 < il < il max 3.0 2.8 - - 4.5 4.5 v (47) v sw4acc output voltage accuracy ? pwm mode including ripple, lo ad regulation, and transients ? pfm mode, including ripple, load regulation, and transients nom-3% nom-3% nom nom nom+3% nom+3% mv (46) i sw4 continuous output load current, v inmin < bp < 4.5 v ? pwm mode (separate) ? pwm mode single/dual phase ? pfm mode - - - - - 50 500 1000 - ma i sw4peak current limiter peak current detection ?v in = 3.6 v current through inductor (separate) ? current through inductor - - 1.0 2.0 - - a
analog integrated circuit device data ? 55 freescale semiconductor 34709 functional bloc k description sw4a/b buck regulator (continued) i sw4 transient transient load change ? single/dual phase ? separate ? 100 ma/s - - - - 500 250 ma v sw4os- start start-up overshoot, il = 100 ma/s - - 25 mv t on-sw4 turn-on time ? enable to 90% of end value il = 0 - - 500 s f sw4 switching frequency ? pllx = 0 ? pllx = 1 - - 2.0 4.0 - - mhz i sw4q quiescent current consumption ? pwmps or aps mode, il=0 ma; device not switching ? pfm mode, il = 0 ma; device not switching - - 160 15 - - a efficiency ?pfm, 3.15 v, 10 ma (a) ? pwm pulse skipping, 3.15 v, 50 ma (a) ? pwm pulse skipping, 3.15 v, 250 ma (a) ? pwm, 3.15 v, 500 ma (a) ?pfm, 1.2 v, 10 ma (b) ? pwm pulse skipping, 1.2 v, 50 ma (b) ? pwm pulse skipping, 1.2 v, 250 ma (b) ?pwm 1.2 v, 500 ma (b) - - - - - - - - 79 93 92 82 72 71 81 78 - - - - - - - - % (48) notes: 46. transient loading for load steps of il max / 2. 47. when sw4a/b is set to 3.0 v and above the regulator may drop out of regulation when bp nears the output voltage. 48. efficiency numbers at v in = 3.6 v, excludes the quiescent current. table 43. sw4a/b electrical specifications characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 56 34709 functional block description 7.5.4.7 sw5 sw5 is fully integrated synchronous buck pwm voltage mode control dc/dc regulator. figure 15. sw5 block diagram the peak current is sensed internally fo r over-current protection purposes. if an ove r-current condition is detected the regula tor will limit the current through cycle by cycle operation and alert the syst em through the sw5fault spi bit and issue an scpi interrupt via the int pin. sw5 can be programmed in step sizes of 25 mv as shown in table 44 . if the software wants to change the output voltage, after power-up the regulator should be forced into pwm mode to change the voltage. table 44. sw5 output voltage programmability set point sw5[4:0] sw5 output (v) set point sw5[4:0] sw5 output (v) 0 00000 1.2000 16 10000 1.6000 1 00001 1.2250 17 10001 1.6250 2 00010 1.2500 18 10010 1.6500 3 00011 1.2750 19 10011 1.6750 4 00100 1.3000 20 10100 1.7000 5 00101 1.3250 21 10101 1.7250 6 00110 1.3500 22 10110 1.7500 7 00111 1.3750 23 10111 1.7750 8 01000 1.4000 24 11000 1.8000 9 01001 1.4250 25 11001 1.8250 10 01010 1.4500 26 11010 1.8500 11 01011 1.4750 - - - 12 01100 1.5000 - - - 13 01101 1.5250 - - - 14 01110 1.5500 - - - 15 01111 1.5750 - - - driver controller ea z1 z2 internal compensation sw5in sw5lx sw5fb i sense c osw5 c insw5 l sw5 spi interface gndsw5 sw5 sw5mode sw5fault v ref dac spi bp d sw5
analog integrated circuit device data ? 57 freescale semiconductor 34709 functional bloc k description table 45. sw5 electrical specifications characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes sw5 buck regulator v sw5in operating input voltage ? pwm operation, 0 < il < i max ? pfm operation, 0 < il < il max 3.0 2.8 - - 4.5 4.5 v v sw5acc output voltage accuracy ? pwm mode including ripple, lo ad regulation, and transients ? pfm mode, including ripple, load regulation, and transients nom-3% nom-3% nom nom nom+3% nom+3% mv (49) i sw5 continuous output load current, v inmin < bp < 4.5 v ? pwm mode ? pfm mode - - - 50 1000 - ma i sw5peak current limiter peak current detection ?v in = 3.6 v current through inductor - 2.0 - a i sw5 transient transient load change ? 100 ma/s - - 500 ma v sw5 os-start start-up overshoot, il = 0 - - 25 mv t on-sw5 turn-on time ? enable to 90% of end value il = 0 - - 500 s f sw5 switching frequency ? pllx = 0 ? pllx = 1 - - 2.0 4.0 - - mhz i sw5q quiescent current consumption ? pwmps or aps mode, il=0 ma; device not switching ? pfm mode, il = 0 ma; device not switching - - 160 15 - - a efficiency ?pfm, 1.8 v, 1.0 ma ? pwm pulse skipping, 1.8 v, 50 ma ? pwm pulse skipping, 1.8 v, 500 ma ?pwm, 1.8 v, 1000 ma - - - - 80 79 86 82 - - - - % (50) notes 49. transient loading for load steps of ilmax/2 50. efficiency numbers at vin=3.6 v, excludes the qui escent current.
analog integrated circuit device data ? freescale semiconductor 58 34709 functional block description 7.5.4.8 dynamic voltage scaling to reduce overall power consumption, proc essor core voltages can be varied dependi ng on the mode or activity level of the processor. sw1a/b and sw2 allow for two different set points wi th controlled transitions to av oid sudden output voltage changes , which could cause logic disruptions on their loads. preset operating points for sw1a/b and sw2 can be set up for: ? normal operation: output value selected by spi bits swx[5:0]. voltage transitions in itiated by spi writes to swx[5:0] are governed by the dvs stepping rate shown in the following tables. ? standby (deep sleep): can be higher or lower than normal operatio n, but is typically selected to be the lowest state retention voltage of a given process. set by spi bi ts swxstby[5:0] and controlled by a standby event. voltage transitions initiated by standby are governed by the swxdvsspeed[1:0] spi bits shown in table 46 . the following table summarizes the set point contro l and dvs time stepping applied to sw1a/b and sw2. the regulator has a strong sourcing and sinking capability in th e pwm mode. therefore, the rising/falling slope is determined b y the regulator in pwm mode. however, if the regulators are programmed in pfm, pwm ps, or aps mode during a dvs transition, the falling slope can be influenced by the load. additionally, as the current capability in pfm mode is reduced, controlled dvs transitions in pfm mode could be affected. critically ti med dvs transitions are best a ssured with pwm mode operation. voltage transitions programmed through spi(swx[4:0]) on sw3 and sw5 will step in increments of 25 mv per 4.0 ? s, sw4a/b will step in increments of 25 mv per 8.0 ? s when sw4xhi[1:0]=00, and sw4a/b will step in increments of 25 mv per 16 ? s when sw4xhi[1:0] 00. additionally, sw3, sw4/b, and sw5 incl ude standby mode set point programmability. the following diagram shows the general behavior for the switch ing regulators when initiated with spi programming or standby control. sw1 and sw2 also contain power good (outputs from the 34709 to the application processor). the power good signal is an active high signal. when swxpwrgdb is high, it means that th e regulators output has reach ed its programmed voltage. the swxpwrgdb voltage outputs will be low during the dvs period and if the current limit is reach ed on the switching regulator. the swxpwrgd will be low from a low to high or a high to low transition of the regulator output voltage. during the dvs period, the over-current condition on the s witching regulator should be masked. if the cu rrent limit is reached outside of a dvs period , the swxpwrgd pin will stay low until the current limit condition is removed. table 46. dvs control logic table for sw1a/b and sw2 standby set point selected by 0 swx[4:0] 1 swxstby[4:0] table 47. dvs speed selection swxdvsspeed[1:0] function 00 12.5 mv step each 2.0 ? s 01 (default) 12.5 mv step each 4.0 ? s 10 12.5 mv step each 8.0 ? s 11 12.5 mv step each 16.0 ? s
analog integrated circuit device data ? 59 freescale semiconductor 34709 functional bloc k description figure 16. voltage stepping with dvs 7.5.5 boost switching regulator swbst is a boost switching regulator with a programmable output, which defaults to 5.0 v on power-up, operating at 2.0 mhz. swbst supplies the vusb regulator for the u sb phy. note that the parasitic leakage path for a boost regulator will cause the output voltage swbstout and swbstfb to sit at a schottky vo ltage drop below the battery voltage whenever swbst is disabled. the switching nmos transistor is integrated on-chip. an external fly back schottky di ode, inductor, and capacitor are required. figure 17. boost regulator architecture swbst output voltage programmable via the swbst[1:0] spi bits as shown in table 48 . table 48. swbst voltage programming parameter voltage swbst output voltage swbst[1:0] 00 5.000 (default) 01 5.050 10 5.100 11 5.150 ? actual output voltage example actual output voltage possible output voltage window internally controlled st eps output voltage wit h light load init ial set point voltage change request internally cont rolled steps output voltage request ed set point i nit iated by spi programming , standby control request for higher voltage request for lower voltage swxpwgd 22uf 2.2uh output drive swbstlx gndswbst swbstin boosted output voltage swbst swbst swbstin bp swbstfb spi spi registers 32 khz switcher core control = package pin 4.7u bp
analog integrated circuit device data ? freescale semiconductor 60 34709 functional block description swbst can be controlled by spi programming in pfm, pwm, an d auto mode. auto mode transitions between pfm and pwm mode based on the load current. by default swbst is powered up in auto mode. table 49. swbst mode control parameter voltage swbst mode swbstmode[1:0] swbststbymode[1:0] 00 off 01 pfm 10 auto (default) 11 pwm table 50. swbst electrical specifications characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes switch mode supply swbst v swbst average output voltage ?3.0 v < v in < 4.5 v, 0 < il < il max nom-4% v nom nom+3% v (51) v swbstacc output ripple ?3.0 v < v in < 4.5 v 0 < il < il max , excluding reverse recovery of schottky diode - - 120 mv vp-p swbst acc average load regulation ?v in = 3.6 v, 0 < il < il max - 0.5 - mv/ma v swbst lineareg average line regulation ?3.0 v < v in < 4.5 v il = il max - 50 - mv i swbst continuous load current ?3.0 v < v in < 4.5 v, v out = 5.0 v - 380 - ma i swbstpeak peak current limit ? at swbstin, v in = 3.6 v - 1800 - ma v swbstos- start start-up overshoot, il = 0 ma - - 500 mv t on-swbst turn-on time ? enable to 90% of v out il = 0 - - 2.0 ms f swbst switching frequency - 2.0 - mhz v swbs transient transient load response, il from 1.0 to 100 ma in 1.0 s steps ? maximum transient amplitude - - 300 mv v swbs transient transient load response, il from 100 to 1.0 ma in 1.0 s steps ? maximum transient amplitude - - 300 mv v swbs transient transient load response, il from 1.0 to 100 ma in 1.0 s steps ? time to settle 80% of transient - - 500 s v swbs transient transient load response, il from 100 to 1.0 ma in 1.0 s steps ? time to settle 80% of transient - - 20 ms efficiency, il = il max 65 80 - %
analog integrated circuit device data ? 61 freescale semiconductor 34709 functional bloc k description 7.5.6 linear regulators (ldos) this section describes the linear regulators provided. for convenience, these regulato rs are named to indicate their typical or possible applications, but the supplies are not limited to these uses and may be applied to any loads within the specified regu lator capabilities. a low-power standby mode controlled by standby is provided for th e regulators with an external pass device in which the bias current is aggressively reduced. this mode is useful for d eep sleep operation, where certain supplies cannot be disabled, but active regulation can be tolerated with lesser parametric re quirements. the output drive c apability and performance are limited in this mode. all regulators use the main bandgap as reference. the main bandgap is bypassed with a capacitor at refcore. the bandgap and the rest of the core circuitry are supplied from vcore. t he performance of the regulators is directly dependent on the performance of vcoredig and the bandgap. no external dc load ing is allowed on vcoredig or refcore. vcoredig is kept powered as long as there is a valid supply and/or coin cell. 7.5.6.1 general features the following applies to all linear regulators, unless otherwise specified. ? advised bypass capacitor is the murata grm155r60g225me95, which comes in a 0402 case. ? in general, parametric performance specifications assume the use of low esr x5r/x7r ceramic capacitors with 20% accuracy and 15% temperature spread, for a worst case stack up of 35% from the nominal value. use of other types with wider temperature variation may require a larger room temperatur e nominal capacitance value to meet performance specs over temperature. in addition, capacitor derating as a function of dc bias voltage requires special attention. finally, minimum bypass capacitor guidelines are provided for stability and tran sient performance. larger values may be applied; performance metrics may be altered and general ly improved, but should be conf irmed in system applications. ? regulators which require a minimum output capacitor esr (those with external pnps) can avoid an external resistor if esr is assured with capacitor specifications or board level trace resistance. ? the output voltage tolerance specified for each of the linear r egulators include process variation, temperature range, static line regulation, and static load regulation. ? in the low-power mode, the output performance is degraded. only those parameters listed in the low-power mode section are guaranteed. in this mode, the output current is limited to much lower currents than in the active mode. ? when a regulator gets disabled, the output will be pulled towa rds ground by an internal pull-down. the pull-down is also activated when resetb goes low. 7.5.6.2 ldo regulator control the regulators with embedded pass devices (vpll, vgen1, and vusb) have an adaptive biasing scheme thus, there are no distinct operating modes such as a normal mode and a low-power mode. therefore, no specific co ntrol is required to put these regulators in a low-power mode. switch mode supply swbst (continued) i swbstbias bias current consumption ? pfm or auto mode - 35 - a i leak-swbst nmos off leakage ?swbstin = 4.5 v, swbstmode [1:0] = 0 - 1.0 6.0 a notes: 51. v in is the low side of the inductor that is connected to bp. table 50. swbst electrical specifications characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 62 34709 functional block description the external pass regulator (vdac) can also operate in a normal and low-power mode. however , since a load current detection cannot be performed for this regulator, the transition between both modes is not automatic and is controlled by setting the corresponding mode bits for the operational behavior desired. the regulators vusb2, and vgen2 can be configured for using the in ternal pass device or external pass device as explained in supplies. for both configurations, the transition between both mode s is controlled by setting the vxmode bit for the specific regulator. therefore, depending on the configuration sele cted, the automatic low-power mode determines availability. the regulators can be disabled and the general purpose outputs can be forced low when going into standby (note that the standby response timing can be altered with the stbydly function , as described in the previous section). each regulator has an associated spi bit for this. when the bit is not set, standby is of no influence. the actual operating mode of the regulator s as a function of standby is not reflected through spi. in other words, the spi will read back what is programmed, not the actua l state. for regulators with internal pass devices, the previous t able can be simplified by elimination of the vxmode column. table 51. ldo regulator control (external pass device ldos) vxen vxmode vxstby standby (52) regulator vx 0 x x x off 1 0 0 x on 1 1 0 x low-power 1 x 1 0 on 1 0 1 1 off 1 1 1 1 low-power notes 52. standby refers to a standby event as described earlier table 52. ldo regulator control (internal pass device ldos) vxen vxstby standby (53) regulator vx 0 x x off 1 0 x on 1 1 0 on 1 1 1 off notes 53. standby refers to a standby event as described earlier
analog integrated circuit device data ? 63 freescale semiconductor 34709 functional bloc k description 7.5.6.3 transient response waveforms the transient load and line response are specified with the waveforms as depicted in figure 18 . note that where the transient load response refers to the overshoot only, so excluding the dc shift itself, the transient line response refers to the sum of both overshoot and dc shift. this is also valid for the mode transition response. figure 18. transient waveforms 7.5.6.4 short-circuit protection the higher current ldos, and those most accessible in pro duct applications, include short- circuit detection and protection (vdac, vusb, vusb2, vgen1, and vgen2). the short-circuit protection (scp) system includes debounced fault condition detection, regulator shutdown, and processor interrupt generatio n, to contain failures and minimize the chance of product damage. if a short-circuit condition is detected, the ldo will be di sabled by resetting its vxen bit, while at the same time, a n interrupt scpi will be generated to flag the fault to the system processor. the scpi interrupt is maskable through the scpm mask bit. the scp feature is enabled by setting the regscpen bit. if this bit is not set, then not only is no interrupt generated, but al so the regulators will not automatically be disabled upon a short-ci rcuit detection. however, the built-in current limiter will co ntinue to limit the output current of the regulator. note that by defaul t, the regscpen bit is not set, so at start-up, none of the re gulators in an overload condition are disabled. ? 1us ? 1us 0 ? ma ? i max ? i l i l stimulus for transient load response 10us ? 10us ? v nom ? + ? 0.8v ? v in v in stimulus for transient line response ? overshoot ? i l ? = ? 0 ? ma ? v out v out for transient load response i l ? = ? il max ? overshoot ? v nom ? + ? 0.3v overshoot ? active ? mode v out v out for mode transition response low ? power ? mode ? overshoot ? i l ? < ? il max i l ? < ? il maxlp i l ? < ? il max active ? mode mode ? transition ? time
analog integrated circuit device data ? freescale semiconductor 64 34709 functional block description 7.5.6.5 vpll vpll is provided for isolated biasing of the application processo rs plls for clock generation in support of protocol and periph eral needs. depending on the application and power requirements, this supply may be considered for sharing with other loads, but noise injection must be avoided and filtering added, if necessary to ensure suitable pll performance. the vpll regulator has a dedicated input supply pin. vinpll can be connected to either bp or a 1.8 v switched mode power supply rail such as from sw5 for the two lower set points of each regulator vpll[1:0] = [00], [01]. in addition, when the two upper set points (vpll[1:0] = [10],[11]) are used, the vinp ll inputs can be connected to either bp or a 2.2 v nominal external switched mode power supply rail, to improve power dissipation. table 53. vpll voltage control parameter value function iload max input supply vpll[1:0] 00 output = 1.2 v 50 ma bp or 1.8 v 01 output = 1.25 v 50 ma bp or 1.8 v 10 output = 1.50 v 50 ma bp or external switch 11 output = 1.8 v 50 ma bp or external switch table 54. vpll electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes general v inpll operating input voltage range ? vpll all settings, bp biased ? vpll [1:0] = 00, 01 (sw5 = 1.8 v) ? vpll, [1:0] = 10, 11, external switch uvdet 1.75 2.15 - 1.8 2.2 4.5 4.5 4.5 v i pll operating current load range - - 50 ma vpll active mode ? dc v pll output voltage v out ?v inmin < v in < v inmax il min < il < il max v nom ? 0.05 v nom v nom + 0.05 v v pll-lopp load regulation ?1.0 ma < il < il max for any v inmin < v in < v inmax - 0.35 - mv/ma v pll-lipp line regulation ?v inmin < v in < v inmax for any il min < il < il max - 5.0 - mv i pll-q quiescent current ?v inmin < v in < v inmax il = 0 - 8.0 - a i plllim current limit ?v inmin < v in < v inmax - 75 - ma vpll active mode ? ac vpll psrr psrr, il = 75% of il max , 20 hz to 20 khz ?v in = uvdet ?v in = v nom + 1.0 v, > uvdet 35 50 40 60 - - db
analog integrated circuit device data ? 65 freescale semiconductor 34709 functional bloc k description 7.5.6.6 vrefddr vrefddr is an internal pmos half supply voltage follower. the output voltage is at one half the input voltage. it?s typical application is as the v ref for ddr memories. a filtered resistor divider is utilized to create a low frequency pole. this divider then utilizes a voltage follo wer to drive the load. vpll noise output noise density, v in = v inmin il = 75% of il max ? 100 hz ? 1.0 khz ?> 1.0 khz ? 1.0 mhz - - 20 - - 2.5 db/dec ? v/ ? hz vpll active mode ? ac (continued) t on-vpll turn-on time ? enable to 90% of end value v in = v inmin , v inmax il = 0 - - 140 s t off-vpll turn-off time ? disable to 10% of initial value v in = v inmin , v inmax , il = 0 0.05 - 10 ms vpll os- start start-up overshoot ?v in = v inmin , v inmax il = 0 - 1.0 2.0 % v pll-lo transient transient load response ?v in = v inmin , v inmax - 50 70 mv v pll-li transient transient line response ?il = 75% of il max - 5.0 8.0 mv table 55. vrefddr electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes general v reffddrin operating input voltage range v inmin to v inmax 1.2 - 1.8 v i refddr operating current load range il min to il max 0.0 - 10 ma vrefddr active mode ? dc v refddr output voltage v out ?v inmin < v in < v inmax il min < il < il max 0.6 v in /2 0.9 v v refddrtol output voltage tolerance ?v inmin < v in < v inmax ?0.6 ma < il < 10 ma -1.0 - 1.0 % (54) v refddr lopp load regulation ?1.0 ma < il < il max for any v inmin < v in < v inmax - 5.0 - mv/ma i refddrq quiescent current ?v inmin < v in < v inmax il = 0 - 8.0 - a i refddrlim current limit ?v inmin < v in < v inmax - 36 - ma table 54. vpll electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 66 34709 functional block description 7.5.6.7 vusb the vusb regulator is used to supply 3.3 v to the external usb phy, it is powered from the swbst boost supply to ensure current sourcing compliance through the normal discharge range of the battery/supply input. vusb has an internal pmos pass fet which will support loads up to 100 ma. vrefddr active mode ? ac t on-vrefddr turn-on time ? enable to 90% of end value v in = v inmin , v inmax il = 0 - - 100 s t off- vrefddr turn-off time ? disable to 10% of initial value v in = v inmin , v inmax , il = 0 0.05 - 10 ms vrefddr active mode ? ac (continued) v refddros start-up overshoot ?v in = v inmin , v inmax il = 0 - 1.0 2.0 % v refddrl transient transient load response ?v in = v inmin , v inmax - 5.0 - mv notes 54. ?????? guaranteed at 25 c only table 56. vusb electrical characteristics characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes vusb regulator v usbin operating input voltage range v inmin to v inmax ? supplied by swbst v swbst - 4% - v swbst +3 % v i usb operating current load range il min to il max 0.0 - 100 ma vusb active mode - dc v usb output voltage v out ?v inmin < v in < v inmax il min < il < il ma v nom - 4% 3.3 v nom + 4% v v usblopp load regulation ? 0 < il < il max from dm / dp, for any v inmin < v in < v inmax - 1.0 - mv/ma v usblipp line regulation ?v inmin < v in < v inmax , for any il min < il < il max - - 20 mv v usbsocp over-current protection threshold ?v inmin < v in < v inmax , short-circuit v out to ground i max +20% - - ma i usblim current limit ?v inmin < v in < v inmax - 180 - ma table 55. vrefddr electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? 67 freescale semiconductor 34709 functional bloc k description 7.5.6.8 vusb2 vusb2 has an internal pmos pass fet which will support loads up to 65 ma. to support load currents an external pnp is provided. the external pnp configuration is offered to avoid e xcess on-chip power dissipation at high loads and large different ials between bp and output settings. for lower current requirements, an integrated pmos pass fet is included. the input pin for the integrated pmos option is shared with the base current driv e pin for the pnp option. the external pnp configuration must be committed as a hardwired board level implementation. the recommended pnp device is the on semiconductor? nss12100xv6t1g, which is capable of handling up to 250 mw of continuous dissipation, at minimum footprint and 75 c of ambient. for use cases where up to 500 mw of dissipation is required, the recommended pnp device is the on semiconductor nss12100uw3tcg. for stability reasons, a small minimum esr may be required. a short-circuit condition will shut down the vu sb2 regulator and generate an interrupt for scpi. the nominal output voltage of this regulator is spi configurable, and can be 2.5 v, 2.6 v, 2.75 v, or 3.0 v. the output current when working with the internal pass fet is 65 ma, and could be up to 350 ma when working with an external pnp. vusb active mode - ac vusb psrr psrr - il = 75% of il max 20 hz to 20 khz ?v in = v inmin + 100 mv 35 40 - db vusb noise output noise - v in = v inmin il = 75% of il max ? 100 hz ? 50 khz ?> 50 khz ? 1.0 mhz - - - - 1.0 0.2 ? v/ ? hz table 57. vusb2 voltage control parameter value output voltage iload max vusb2config=0 internal pass fet vusb2config=1 external pnp vusb2[1:0] 00 2.5 v 65 ma 350 ma 01 2.6 v 65 ma 350 ma 10 2.75 v 65 ma 350 ma 11 3.00 v 65 ma 350 ma table 58. vusb2 electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes general v usb2in operating input voltage range v inmin to v inmax v nom + 0.25 - 4.5 v i usb2 operating current load range il min to il max ? internal pass fet ? external pnp not exceeding pnp max power 0.0 0.0 - - 65 350 ma v usb2in extended input voltage range ? performance may be out of specification uvdet - 4.5 v table 56. vusb electrical characteristics characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 68 34709 functional block description vusb2 active mode - dc v usb2 output voltage v out ?v inmin < v in < v inmax il min < il < il max v nom - 3% v nom v nom + 3% v v usb2lopp load regulation ?1.0 ma < il < il max for any v inmin < v in < v inmax - 0.25 - mv/ma v usb2lipp line regulation ?v inmin < v in < v inmax for any il min < il < il max - 8.0 - mv vusb2 ocp over-current protection threshold ?v inmin < v in < v inmax short-circuit v out to gnd il max +20% - - ma i usb2q active mode quiescent current, v inmin < v in < v inmax ?il = 0, internal pmos configuration ?v inmin < v in < v inmax il = 0, external pnp configuration - - 25 30 - - a i usb2lim current limit ? external pnp mode only ?v inmin < v in < v inmax ? current on vusb2drv multiplied by ? of external pnp transistor (i usb2drv when vsusb2drv is forced to ldovdd) - 4.62* ? - ma vusb2 low-power mode - dc v usb2 output voltage v out ?v inmin < v in < v inmax il minlp < il < il maxlp v nom - 3% v nom v nom + 3% v i usb2 current load range il minlp to il maxlp 0.0 - 3.0 ma i usb2q low-power mode quiescent current ?v inmin < v in < v inmax il = 0 - 8.0 - a vusb2 active mode - ac vusb2 psrr psrr, il = 75% of il max 20 hz to 20 khz ?v in = v inmin + 100 mv ?v in = v nom + 1.0 v 35 50 40 60 - - db vusb 2 noise output noise density, v in = v inmin il = 75% of il max ? 100 hz ? 1.0 khz ?> 1.0 khz ? 1.0 mhz - - 20 - - 1.0 db/dec ? v/ ? hz t on-vusb2 turn-on time ? enable to 90% of end value v in = v inmin , v inmax il = 0 - - 1.0 ms t off-vusb2 turn-off time ? disable to 10% of initial value v in = v inmin , v inmax il = 0 0.05 - 10 ms vusb2 os- start start-up overshoot ?v in = v inmin , v inmax il = 0 - 1.0 2.0 % vusb2 lo transient transient load response, v in = v inmin , v inmax x ? vusb2=01, 10, 11 ? vusb2=00 - - 1.0 50 2.0 70 % mv table 58. vusb2 electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? 69 freescale semiconductor 34709 functional bloc k description vusb2 li transient transient line response ?il = 75% of il max - 5.0 8.0 mv t mod-vusb2 mode transition time ? from low-power to active and from active to low-power v in = v inmin , v inmax il = il maxlp - - 100 s vusb mode res mode transition response ? from low-power to active and from active to low-power v in = v inmin , v inmax il = il maxlp - 1.0 2.0 % table 58. vusb2 electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 70 34709 functional block description 7.5.6.9 vdac the primary applications of this power supply is the tv-dac. however, these supplies could also be used for other peripherals if one of these functions is not required. low-power modes a nd programmable standby options can be used to optimize power efficiency during deep sleep modes. an external pnp is utilized for vdac to avoid excess on-chip power dissipation at high loads and large differentials between bp and output settings. for stability reasons, a small minimum esr may be required. in the low-power mode for vdac, an internal bypass path is used instead of the external pnp. external pnp devices must always be connected to the bp line in the application. the recommended pnp device is the on semiconductor nss12100xv6t1g, which is capable of handling up to 250 mw of continuous dissipation at minimum footprint and 75 c of ambient. for use cases where up to 500 mw of dissipation is required, the recommended pnp device is the on semiconduc tor nss12100uw3tcg. for stability reasons, a small minimum esr may be required. a short-circuit condition will shut down the vdac regulator and generate an interrupt for scpi. the nominal output voltage of this regulator is spi configurable, and can be 2.5 v, 2.6 v, 2.7 v, or 2.775 v. the maximum output current along with an external pnp, is 250 ma. table 59. vdac voltage control parameter value output voltage iload max vdac 00 2.500 v 250 ma 01 2.600 v 250 ma 10 2.700 v 250 ma 11 2.775 v 250 ma table 60. vdac electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes general v dacin operating input voltage range v inmin to v inmax v nom + 0.25 - 4.5 v i dac operating current load range il min to il max ? not exceeding pnp max power 0.0 - 250 ma v dacin extended input voltage range ? performance may be out of specification uvdet - 4.5 v vdac active mode ? dc v dac output voltage v out ?v inmin < v in < v inmax il min < il < il max v nom ? 3% v nom v nom + 3% v v daclopp load regulation ?1.0 ma < il < il max for any v inmin < v in < v inmax - 0.20 - mv/ma v daclipp line regulation ?v inmin < v in < v inmax for any il min < il < il max - 5.0 - mv vdac ocp over-current protection threshold ?v inmin < v in < v inmax short-circuit v out to gnd il max +20% - - ma i dacq active mode quiescent current ?v inmin < v in < v inmax il = 0 - 30 - a
analog integrated circuit device data ? 71 freescale semiconductor 34709 functional bloc k description 7.5.6.10 vgen1, vgen2 general purpose ldos, vgen1, a nd vgen2, are provided for expansion of the power tree to support peripheral devices, which could include emmc cards, wlan, bt, gps, or other functional modules. these regulators include programmable set points for i daclim current limit ? external pnp mode only ?v inmin < v in < v inmax ? current on vdacdrv multiplied by ? of external pnp transistor (i dacdrv when vdacdrv is forced to ldovdd) - 3.2* ? - ma vdac low-power mode ? dc - vdacmode=1 v dac output voltage v out ?v inmin < v in < v inmax il minlp < il < il maxlp v nom ? 3% v nom v nom + 3% v i dac current load range il minlp to il maxlp 0.0 - 3.0 ma i dacq low-power mode quiescent current ?v inmin < v in < v inmax il = 0 - 8.0 - a vdac active mode ? ac vdac psrr psrr - il = 75% of il max 20 hz to 20 khz ?v in = v inmin + 100 mv ?v in = v nom + 1.0 v 35 50 40 60 - - db vdac noise output noise density, v in = v inmin il = 75% of il max ? 100 hz ? 1.0 khz ?> 1.0 khz ? 10 khz ?> 10 khz ? 1.0 mhz - - - - - - -115 -126 -132 ? v/ ? hz vdac spurs spurs ? 32.768 khz and harmonics - - -120 db t on-vdac turn-on time ? enable to 90% of end value v in = v inmin , v inmax il = 0 - - 1.0 ms t off-vdac turn-off time ? disable to 10% of initial value v in = v inmin , v inmax , il = 0 0.05 - 10 ms vdac os- start start-up overshoot ?v in = v inmin , v inmax il = 0 - 1.0 2.0 % vdac lo transient transient load response ?v in = v inmin , v inmax - 1.0 2.0 % v dacli transient transient line response ?il = 75% of il max - 5.0 8.0 mv t mode-vdac mode transition time ? from low-power to active v in = v inmin , v inmax il = il maxlp - - 100 s vdac mode res mode transition response ? from low-power to active and from active to low-power v in = v inmin , v inmax il = il maxlp - 1.0 2.0 % table 60. vdac electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 72 34709 functional block description system flexibility. vgen1 has an internal pmos pass fet, and is powered from the sw5 buck for an efficiency advantage and reduced power dissipation in the pass devices. vg en2 is powered directly from the battery. vgen2 has an internal pmos pass fe t, which will support loads up to 50 ma. for higher current capabilit y, drive for an external pnp is provided. the external pnp is offered to avoid excess on- chip power dissipation at high loads and large differentials between bp and output settings. the input pin for the integrated pmos option is shared with the base current drive pin for the pnp option. the external pnp device is always connected to th e bp line in the application. the recommended pnp device is the on semiconductor nss12100xv6t1g which is capable of handling up to 250 mw of continuous dissipation at minimum footprint and 75 c of ambient. for use cases where up to 500 mw of dissipation is required, the recommended pnp device is the on semiconductor nss12100uw3tcg. for stability, a small minimum esr may be required. a short-circuit condition will shut down the vgen1 and vgen2 regulators, and generate an interrupt for scpi. the nominal output voltage of both vgen1 and vgen2 are spi configurable with the vgenx[2:0] bits as shown in table 61 and table 62 . table 61. vgen1 control register bit assignments parameter value output voltage iload max vgen1[2:0] 000 1.2000 250 ma 001 1.2500 250 ma 010 1.3000 250 ma 011 1.3500 250 ma 100 1.4000 250 ma 101 1.4500 250 ma 110 1.5000 250 ma 111 1.5500 250 ma table 62. vgen2 control register bit assignments parameter value output voltage iload max vgen2config=0 internal pass fet vgen2config=1 external pnp vgen2[2:0] 000 2.50 50 ma 250 ma 001 2.70 50 ma 250 ma 010 2.80 50 ma 250 ma 011 2.90 50 ma 250 ma 100 3.00 50 ma 250 ma 101 3.10 50 ma 250 ma 110 3.15 50 ma 250 ma 111 3.30 50 ma 250 ma
analog integrated circuit device data ? 73 freescale semiconductor 34709 functional bloc k description table 63. vgen1 electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes general v gen1in operating input voltage range v inmin to v inmax ? all settings 1.75 1.8 1.85 v i gen1 operating current load range il min to il max ? not exceeding pnp max power 0.0 - 250 ma vgen1 active mode ? dc v gen1 output voltage v out ?v inmin < v in < v inmax il min < il < il max v nom ? 3% v nom v nom + 3% v v gen1lopp load regulation ?1.0 ma < il < il max for any v inmin < v in < v inmax - 0.25 - mv/ma v gen1lipp line regulation ?v inmin < v in < v inmax for any il min < il < il max - 5.0 - mv vgen1 ocp over-current protection threshold ?v inmin < v in < v inmax short-circuit v out to gnd il max +20% - - ma i gen1q active mode quiescent current ?v inmin < v in < v inmax il = 0 - 12 - a i gen1lim current limit ?v inmin < v in < v inmax - 375 - ma vgen1 active mode - ac vgen1 psrr psrr ?il = 75% of il max 20 hz to 20 khz vgen1[2:0] = 000-101 ? il = 75% of ilmax 20 hz to 20 khz vgen1[2:0] = 110-111 50 37 60 - - - db vgen 1 noise output noise density, v in = v inmin il = 75% of il max ? 100 hz ? 1.0 khz ?> 1.0 khz ? 10 khz ?> 10 khz ? 1.0 mhz - - - - - - -115 -126 -132 ? v/ ? hz vgen 1 spurs spurs ? 32.768 khz and harmonics - - -100 db t on-vgen1 turn-on time ? enable to 90% of end value v in = v inmin , v inmax , il = 0 - - 1.0 ms t off-vgen1 turn-off time ? disable to 10% of initial value v in = v inmin , v inmax , il = 0 0.01 - 10 ms vgen1 os- start start-up overshoot ?v in = v inmin , v inmax , il = 0 - 1.0 2.0 % vgen1 lo transient transient load response ?v in = v inmin , v inmax - 1.0 2.0 % v gen1li transient transient line response ?il = 75% of il max - 5.0 8.0 mv
analog integrated circuit device data ? freescale semiconductor 74 34709 functional block description vgen1 active mode - ac (continued) t mode-vgen1 mode transition time ? from low-power to active and from active to low-power v in = v inmin , v inmax il = il maxlp - - 100 s vgen 1 moderes mode transition response ? from low-power to active and from active to low-power v in = v inmin , v inmax il = il maxlp - 1.0 2.0 % table 64. vgen2 electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes vgen2 v gen2in operating input voltage range v inmin to v inmax ? all settings, bp biased v nom +0.25 - 4.5 v i gen2 operating current load range il mi to il max ? internal pass fet 0.0 - 50 ma i gen2 operating current load range il min to il max ? external pnp, not exceeding pnp max power 0.0 - 250 ma v gen2in extended input voltage range ? bp biased, performance may out of specification for output levels vgen2 [2:0] = 010 to 111 uvdet - 4.5 mv/ma vgen2 active mode - dc v gen2 output voltage v out ?v inmin < v in < v inmax il min < il < il max v nom - 3% v nom v nom + 3% v v gen2lopp load regulation ?1.0 ma < il < il max , for any v inmin < v in < v inmax - 0.20 - mv/ma v gen2lipp line regulation ?v inmin < v in < v inmax for any il min < il < il max - 8.0 - mv vgen2 ocp over-current protection threshold ?v inmin < v in < v inmax short-circuit v out to gnd ilmax +20% - - ma i gen2q active mode quiescent current ?v inmin < v in < v inmax il = 0 - 30 - a i gen2lim current limit ? external pnp mode only ?v inmin < v in < v inmax ? current on vgen2drv multiplied by ? of external pnp transistor (i gen2drv when vgen2drv is forced to ldovdd) - 3.4* ? - ma table 63. vgen1 electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? 75 freescale semiconductor 34709 functional bloc k description vgen2 low-power mode - dc - vgen2mode=1 v gen2 output voltage v out ?v inmin < v in < v inmax il minlp < il < il maxlp v nom - 3% v nom v nom + 3% v i gen2 current load range il minlp to il maxlp 0.0 - 3.0 ma i gen2q low-power mode quiescent current ?v inmin < v in < v inmax il = 0 - 8.0 - a vgen2 active mode - ac vgen2 psrr psrr - il = 75% of ilmax, 20 hz to 20 khz ?v in = v inmin + 100 mv ?v in = v nom + 1.0 v 35 55 40 60 - - db vgen 2 noise output noise density - v in = v inmin il = 75% of il max ? 100 hz ? 1.0 khz ?> 1.0 khz ? 10 khz ?> 10 khz ? 1.0 mhz - - - - - - -115 -126 -132 ? v/ ? hz t on-vgen22 turn-on time ? enable to 90% of end value v in = v inmin , v inmax , il = 0 - - 1.0 ms vgen2 active mode - ac (continued) t off-vgen2 turn-off time ? disable to 10% of initial value v in = v inmin , v inmax , il = 0 0.05 - 10 ms vgen2 os- start start-up overshoot ?v in = v inmin , v inmax il = 0 - 1.0 2.0 % vgen2 lo transient transient load response ?v in = v inmin , v inmax - 1.0 2.0 % v gen2li transient transient line response ?il = 75% of il max - 5.0 8.0 mv t mode-vgen2 mode transition time ? from low-power to active v in = v inmin , v inmax , il = il maxlp - - 100 s vgen 2 moderes mode transition response ? from low-power to active and from active to low-power v in = v inmin , v inmax , il = il maxlp - 1.0 2.0 % table 64. vgen2 electrical specification characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes
analog integrated circuit device data ? freescale semiconductor 76 34709 functional block description 7.6 analog to digital converter the adc core is a 10 bit converter. the adc core and logic run at an internally generated frequency of approximately 1.33 mhz. the adc is supplied from vcore. the adc core has an integrated auto calibration circuit which reduces the offset and gain errors. 7.6.1 input selector the adc has 16 input channels. table 65 gives an overview of the characteristics of each of these channels. some of the internal signals are first scaled to adapt the signal range to the input range of the adc. for details on scaling, see dedicated readings . when considerately exceeding the maximum input of the adc at the scaled or unscaled inputs, the reading result will return a full scale. it has to be noted however, that this full scale does not necessarily yield a 1022 dec reading due to the offsets a nd calibration applied. the same applies for when going below the minimum input where the corresponding 0000 dec reading may not be returned. table 65. adc inputs channel adselx[3:0] signal read input level scaling scaled version 0 0000 reserved reserved reserved reserved 1 0001 reserved reserved reserved reserved 2 0010 reserved reserved reserved reserved 3 0011 die temperature -40 ? 150 c 1.2 ? 2.4 v 4 0100 reserved reserved reserved reserved 5 0101 reserved reserved reserved reserved 6 0110 reserved reserved reserved reserved 7 0111 reserved reserved reserved reserved 8 1000 coin cell voltage 0 ? 3.6 v x2/3 0 ? 2.4 v 9 1001 adin9 0 ? 2.4 v x1 0 ? 2.4 v 10 1010 adin10 0 ? 2.4 v x1 0 ? 2.4 v 11 1011 adin11 0 ? 2.4 v x1 0 ? 2.4 v 12 1100 adin12/tsx1 0 ? 2.4 v x1/x2 0 ? 2.4 v / 0 -1.2 v 13 1101 adin13/tsx2 0 ? 2.4 v x1/x2 0 ? 2.4 v / 0 -1.2 v 14 1110 adin14/tsy1 0 ? 2.4 v x1/x2 0 ? 2.4 v / 0 -1.2 v 15 1111 adin15/tsy2 0 ? 2.4 v x1/x2 0 ? 2.4 v / 0 -1.2 v table 66. adc input specification parameter condition min typ max units source impedance no bypass capacitor at input - - 5.0 kohm bypass capacitor at input 10 nf - - 30 kohm
analog integrated circuit device data ? 77 freescale semiconductor 34709 functional bloc k description 7.6.2 control the adc parameters are programmed by the processor via th e spi. when a reading sequence is finished, an interrupt adcdonei is generated. the interrupt can be masked with the adcdonem bit. the adc is enabled by setting aden bit high. the adc can start a series of conversions through spi programming by setting the adstart bit. if the aden bit is low, the adc will be disabled and in low-power mode. the adc is automatically calibrated every time pmic is powered. the conversions will begin after a small analog synchronization of up to 30 microseconds, plus a programmable delay from 0 (default) up to 600 ? s, by programming the bits addly1[3:0]. the addly2[3:0] controls the delay between each of the conversions from 0 to 600 ? s. addly3[3:0] controls the delay after the final c onversion, and is only valid when adcont is high. addly1, 2, and 3 are set to 0 by default. there is a max of 8 conversions that will take place when the a dc is started. the register adse lx[3:0] selects the channel whic h the adc will read and store in the adresultx register. the adc wi ll always start at the channel indicated in adsel0, and read up to and including the channel set by the adstop[2:0] bits. for example, when adstop[2:0] = 010, it will request the adc to read channels indicated in adsel0, adsel1, and adsel2. when adstop[2:0] = 111, all eight channels programmed by the value in adsel0-7 will be read. when the adcont bit is set hi gh, it allows the adc to continuously loop and read the channels from address 0 to the stop address programmed in adstop. by def ault, the adcont is set low (disabled). in the continuous mode, the adhold bit will allow the software to hold the adc sequencer from updat ing the results register while the adc results are read. once the sequence of a/d conversions is complete, t he adresultx results are stored in 4 spi registers (adc 4 - adc 7). table 67. addlyx[3:0] addlyx[3:0] delay in ? s 0000 0.0 0001 40 0010 80 0011 120 0100 160 0101 200 0110 240 0111 280 1000 320 1001 360 1010 400 1011 440 1100 480 1101 520 1110 560 1111 600
analog integrated circuit device data ? freescale semiconductor 78 34709 functional block description 7.6.3 dedicated readings 7.6.3.1 channel 0 to 2 reserve channel 0 to channel 2 are reserved. 7.6.3.2 channel 3 die temperature the relation between the read out code and temperature is given in table 68 . the actual die temperature is obtained as fo llows: die temp = 25 + 0.426 * (adc code - 680) 7.6.3.3 channel 4 to 7 reserved channel 4 to channel 7 are reserved. 7.6.3.4 channel 8 coin cell voltage the voltage of the coin cell connected to the licell pin can be read on channel 8. since the voltage range of the coin cell exceeds the input voltage range of the adc, the licell voltage is scaled as v(licell)*2/3. in case the voltage at licell drops below the coin cell disconnect threshold, the voltage at licell can still be read through the adc. 7.6.3.5 channel 9-11 adin9-adin11 there are 3 general purpose analog input channels th at can be measured through the adin9-adin11 pins. 7.6.3.6 channel 12-15 adin12-adin15 if the touch screen is not used, the inputs tsx1, tsx2, tsy1, and tsy2 can be used as general purpose inputs. they are respectively mapped on adc channels 12, 13, 14, and 15. 7.6.4 touch screen interface the touch screen interface provides all ci rcuitry required for the readout of a four-wire resistive touch screen. the touch scr een x plate is connected to tsx1 and tsx2, while the y plate is connected to tsy1 and tsy2. a local supply tsref will serve as a reference. several readou t possibilities are offered. if the touchscreen is not used, the inputs tsx1, tsx2, tsy1 , and tsy2 can be used as general purpose inputs. they are respectively mapped on adc channels 12, 13, 14, and 15. table 68. die temperature voltage reading parameter min typ max unit die temperature read out code at 25 c - 680 - decimal slope temperature change per lsb - +0.426 - c/lsb slope error - - 5.0 % table 69. coin cell voltage reading coding conversion code adresultx[9:0] voltage at adc input (v) voltage ? at ? licell (v) 1 111 111 110 2.400 3.6 1 000 000 000 1.200 1.8 0 000 000 000 0.000 0
analog integrated circuit device data ? 79 freescale semiconductor 34709 functional bloc k description touch screen pen detection bias can be enabled via the tspende ten bit in the ad0 register. when this bit is enabled and a pen touch is detected, the tspendet bit in the interrupt status 0 register is set and the int pin is asserted - unless the inte rrupt is masked. pen detection is only active when tsen is low. the reference for the touch screen (touch bias) is tsref and is powered from vcore. duri ng touch screen operation, tsref is a dedicated regulator. no loads other than the touch screen should be connected here. when the adc performs non touch screen conversions, the adc does not rely on tsref and the reference is disabled. the readouts are designed such that the on chip switch resistances are of no influence on the overall readout. the readout scheme does not account for cont act resistances, as present in the touch screen connectors. the touch screen readings will have to be calibrated by the user or the factory, where one has to point with a stylus to the opposite corners of the screen. w hen reading the x-coordinate, the 10-bit adc re ading represents a 10-bit coordinate, with ?0? for a coordinate equal to x-, and ful l scale ?1023? when equal to x+. when reading the y-coordinate, th e 10-bit adc reading represents a 10-bit coordinate, with ?0? for a coordinate equal to y-, and full scale ?1023? when equal to y+. when reading contact resistance, the 10-bit adc reading represents the voltage drop over the contact resistance created by the known current source, multiplied by 2. the x-coordinate is determined by applyi ng tsref over the tsx1 and tsx2 pins, while performing a high-impedance reading on the y-plate through tsy1. the y-coordinate is determined by applying tsref between tsy1 and tsy2, while reading the tsx1 pin. the contact resistance is measured by applying a known current into the tsy1 pin of the touch screen and through the tsx2 pin, which is grounded. the voltage difference betwee n the two remaining terminals tsy2 and tsx1 is measured by the adc, and equals the voltage across the contact resistance. me asuring the contact resistance helps determine if the touch screen is touched with a finger or a stylus. the tsselx[1:0] allows the application pr ocessor to select its own reading sequence. the tsselx[1:0] determines what is read during the touch screen reading sequence, as shown in table 70 . the touch screen will always st art at tssel0 and read up to and including the channel set by tssel at the tsstop[2:0] bi ts. for example when tsstop[2:0] = 010, it will request the adc to read channels indicated in tssel0, tssel1, and tssel2. when tsstop[2:0] = 111, all eight addresses will be read. the touch screen readings can be repeated, as in the following example readout sequence, to reduce the interrupt rate and to allow for easier noise rejection. the dummy conversion inserted between the different readings allows the references in the system to be pre-biased for the change in touch screen plate polarity. it will read out as ?0?. a touch screen reading will take precedence over an adc sequence. if an adc reading is triggered during a touch screen event, the adc sequence will be overwritten by the touch screen data. the first touch screen conversion can be delayed from 0 (default) to 600 ? s by programming the tsdly1[3:0] bits. the tsdly2[3:0] controls the delay between each of the touch screen conversions from 0 to 600 ? s. tsdly[2:0] sets the delay after the last address is converted. tsdl y1, 2, and 3 are set to 0 by default. table 70. touch screen action select tsselx[1:0] signals sampled 00 dummy to discharge tsref cap 01 x - plate 10 y - plate 11 contact table 71. tsdlyx[3:0] tsdlyx[3:0] delay in us 0000 0 0001 40 0010 80 0011 120 0100 160 0101 200 0110 240
analog integrated circuit device data ? freescale semiconductor 80 34709 functional block description to perform a touch screen reading, the processor must do the following: 1. enable the touch screen with tsen 2. select the touch screen sequence by programming the tssel0-tssel7 spi bits. 3. program the tsstop[2:0] 4. program the delay between the conversi on via the tsdly1 and tsdly2 settings. 5. trigger the adc via the tsstart spi bit 6. wait for an interrupt indicating the conversion is done tsdonei 7. and then read out the data in the adresultx registers 7.6.5 adc specifications 0111 280 1000 320 1001 360 1010 400 1011 440 1100 480 1101 520 1110 560 1111 600 table 72. adc electrical specifications characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes adc conversion current - 1.0 - ma v adcin converter core input range ? single-ended voltage readings ? differential readings 0.0 -1.2 - - 2.4 1.2 v t convert conversion time per channel - - 10 ? s integral non-linearity - - 3 lsb differential non-linearity - - 1 lsb zero scale error (offset) - - ? 5 lsb full scale error (gain) - - ? 10 lsb drift over-temperature - - 1 lsb t on-off-adc turn on/off time - - 31 ? s table 71. tsdlyx[3:0] tsdlyx[3:0] delay in us
analog integrated circuit device data ? 81 freescale semiconductor 34709 functional bloc k description 7.7 auxiliary circuits 7.7.1 general purpose i/os the 34709 contains four configurable gpio input/outputs for gene ral purpose use. when configured as outputs, they can be configured as open-drain (od) or cmos (push-pull output s). these gpios are low-voltage capable (1.2 or 1.8 v). in open-drain configuration these outputs can only be pulled up to 2.5 v maximum. each individual gpio has a dedicated 16-bit control register. table 73 provides detailed bit descriptions. table 73. gpiolvx control (55) spi bit description dir gpiolvx direction 0: input (default) 1: output din input state of the gpiolvx pin 0: input low 1: input high dout output state of gpiolvx pin 0: output low 1: output high hys hysteresis 0: cmos in 1: hysteresis (default) dbnc[1:0] gpiolvx input debounce time 00: no debounce (default) 01: 10 ms debounce 10: 20 ms debounce 11: 30 ms debounce int[1:0] gpiolvx interrupt control 00: none (default) 01: falling edge 10: rising edge 11: both edges pke pad keep enable 0: off (default) 1: on ode open-drain enable 0: cmos (default) 1: od dse drive strength enable 0: 4.0 ma (default) 1: 8.0 ma pue pull-up/down enable 0: pull-up/down off 1: pull-up/down on (default) pus[1:0] pull-up/pull-down enable 00: 10 k active pull-down 01: 10 k active pull-up 10: 100 k active pull-down 11: 100 k active pull-up (default)
analog integrated circuit device data ? freescale semiconductor 82 34709 functional block description 7.7.2 pwm outputs there are two pwm outputs on the 34709 pwm1 and pwm2 and which are controlled by the pwmxduty and pwmxclkdiv registers shown in table 74 .the base clock will be the 2.0 mhz divided by 32. 32.768 khz crystal oscillator rtc block description and application information 7.8 serial interfaces the ic contains a number of programmabl e registers for control and communication. the majority of registers are accessed through a spi interface in a typical application. the same register set may alternatively be accessed with an i 2 c interface that is muxed on spi pins. table 76 describes the muxed pin options for the spi and i 2 c interfaces; further details for each interface mode follow. sre[1:0] slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast notes 55. x= 0, 1, 2, or 3 depending of the gpio channel it is being used table 74. pwmx duty cycle programming pwmxdc[5:0]( (56) ) duty cycle 000000 0/32, off (default) 000001 1/32 ? ? 010000 16/32 ? ? 011111 31/32 1xxxxx 32/32, continuously on notes 56. ?x? represent 1 and 2 table 75. pwmx clock divider programming pwmxclkdiv[5:0]( (57) ) duty cycle 000000 base clock 000001 base clock / 2 ? ? 001111 base clock / 16 ? ? 111111 base clock / 64 notes 57. ?x? represent 1 and 2 table 73. gpiolvx control (55) spi bit description
analog integrated circuit device data ? 83 freescale semiconductor 34709 functional bloc k description 7.8.1 spi interface the ic contains a spi interface port which allows access by a processor to the register set. via these registers the resources of the ic can be controlled. the registers also provide status info rmation about how the ic is operating, as well as information o n external signals. because the spi interface pins can be reconfigured for reuse as an i 2 c interface, a configuration protocol mandates that the cs pin is held low during a turn on event for the ic (a weak pull-do wn is integrated on the cs pin). the state of cs is latched in during the initialization phase of a cold start sequence, ensuring that the i 2 c bus is configured before the interface is activated. with the cs pin held low during start-up (as would be the case if co nnected to the cs driver of an unpowered processor due to the integrated pull-down), then the bus configuration will be latched for spi mode. the spi port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. t he addressable register map spans 64 registers of 24 data bits eac h. the map is not fully populated, but it follows the legacy conventions for bit positions corresponding to common functionality with previous generation fsl products. 7.8.1.1 spi interface description for a spi read, the first bit sent to the ic must be a zero indicati ng a spi read cycle. next, the six bit add ress is sent msb first. this is followed by one dead bit to allow for more address decode time. the 34709 will clock the above bits in on the rising ed ge of the spi clock. then the 24 data bits are driven out on the miso pin on the falling edge of the spi clock so the master can c lock them in on the rising edge of the spi clock. for each mosi spi transfer, first a one is written to the write/r ead_b bit if this spi transfer is to be a write. a zero is wri tten to the write/read_b bit if this is to be a read command. if a zero is written, then any data sent after the address bits are ignored a nd the internal contents of the field addressed do not change when the 32nd clk is sent. for a spi write the first bit sent to the 34709 must be a one indicating a spi write cycle. next the six bit address is sent ms b first. this is followed by one dead bit to allow for more address decode time. then the data is sent msb first. the spi data is writte n to the spi register whose address was sent at the start of the spi cycl e on the falling edge of the 32nd spi clock. additionall y, whenever a spi write cycle is taki ng place the spi read data is shifted out for the same address as for the write cycle. next t he 6-bit address is written, msb first. finally, da ta bits are writ ten, msb first. once all the dat a bits are written then the dat a is transferred into the actual registers on the falling edge of the 32nd clk. the cs polarity is active high. the cs line must remain high during the entire spi transfer. for a write sequence it is possibl e for the written data to be corrupted, if after the falling edge of the 32nd clock the cs goes low before it's required time. cs can go low before this point and the spi transaction will be ignored, but after that point the write process is started and cannot be stopped because the write strobe pulse is already being generated and cs going low may cause a runt pulse that may or may not be wide enough to clock all 24 data bits properly. to start a new spi transfer, the cs line must be toggled low and then pulled high ag ain. the miso line will be tri-stated while cs is low. the register map includes bits that are r ead/write, read only, read/write ?1? to clea r (i.e., interrupts), and clear on read, r eserved, and unused. refer to the spi/i2c register map and the individual subcircuit descriptions to determine the read/write capability of each bit. all unused spi bits in each register must be wr itten to as zeroes. a spi read back of the address field and unused bits are returned as zeroes. to read a field of data, the miso pin will output the data field pointed to by the 6 address bits loaded at the beginning of the spi sequence. table 76. spi / i 2 c bus configuration pin name spi mode functionality i 2 c mode functionality cs configuration (58) , chip select configuration (59) clk spi clock scl: i 2 c bus clock miso master in, slave out (data output) sda: bi-directional serial data line mosi master out, slave in (data input) a0 address selection (60) notes 58. cs held low at cold start, configures the interface for spi mode; once activated, cs functi ons as the spi chip select. 59. cs tied to vcoredig at cold st art, configures the interface for i 2 c mode; the pin is not used in i 2 c mode, other than for configuration. 60. in i 2 c mode, the mosi pin is hardwired to ground, or vcor edig is used to select bet ween two possible addresses.
analog integrated circuit device data ? freescale semiconductor 84 34709 functional block description figure 19. spi transfer protocol single read/write access figure 20. spi transfer protocol multiple read/write access 7.8.1.2 spi timing requirements figure 21 and table 77 summarize the spi timing requirements. the spi input and output levels are set via the spivcc pin, by connecting it to the desired supply. this woul d typically be tied to sw5 and programmed for 1.80 v. the strength of the miso driver is programmable through the spidrv [1:0] bits. see thermal protection thresholds for detailed spi electrical characteristics. figure 21. spi interface timing diagram ? cs clk mosi miso write_en a ddress5 a dd r e ss 4 a ddress3 a ddress2 a ddress 1 a ddress 0 data 23 d ata 1 data 0 data 23 d ata 1 data 0 d ata 22 d ata 22 ?d ead bit? ? 24 bits data 24 bits data 24 bits data 24 bits data pr ea mble first address preamble another address mosi miso cs cs clk t selsu t selhld t clkper t clkhigh t clklow mosi miso t wrtsu t wrtlhd t rdsu t rddis t rden t rdhld t sellow
analog integrated circuit device data ? 85 freescale semiconductor 34709 functional bloc k description 7.8.2 i 2 c interface 7.8.2.1 i 2 c configuration when configured for i 2 c mode, the interface may be used to access the complete register map previously described for spi access. since spi configuration is more typical, references within this document will generally refer to the common register se t as a ?spi map? and bits as ?spi bits?; however, it should be understood that access reverts to i 2 c mode when configured as such. the spi pins clk and miso are reused for the scl and sda lines respectively. selection of i 2 c mode for the interface is configured by hard-wiring the cs pin to vcoredig on the application board. the state of cs is latched in during the initializat ion phase of a cold start sequence, so the i 2 cs bit is defined for bus configuration before the interface is activated. the pull-down on cs will be deactivated if the high state is detected (indicating i 2 c mode). in i 2 c mode, the miso pin is connected to the bus as an open-drain dr iver, and the logic level is set by an external pull-up. the part can function only as an i 2 c slave device, not as a host. 7.8.2.2 i 2 c device id i 2 c interface protocol requires a device id for addressing the targ et ic on a multi-device bus. to allow flexibility in addressin g for bus conflict avoidance, pin programmable selection is provided to allow configuration for the address lsb(s). this product supports 7-bit addressing only; support is not provided for 10-bit or general call addressing. because the mosi pin is not utilized for i 2 c communication, it is reassigned for pin programmable address selection by hardwiring to vcoredig or gnd at th e board level when configured for i 2 c mode. mosi will act as bit 0 of the address. the i 2 c address assigned to fsl pm ics (shared am ongst our portfolio) is given as follows: 00010-a1-a0, the a1 and a0 bits are allowed to be configured for ei ther 1 or 0. the a1 address bi t is internally hardwired as a ?0?, leaving the lsb a0 for board level configuration. the designated address then is defined as: 000100-a0. table 77. spi interface timing specifications (61) parameter description t min (ns) t selsu time cs has to be high before the first rising edge of clk 15 t selhld time cs has to remain high after the last falling edge of clk 15 t sellow time cs has to remain low between two transfers 15 t clkper clock period of clk 38 t clkhigh part of the clock period w here clk has to remain high 15 t clklow part of the clock period where clk has to remain low 15 t wrtsu time mosi has to be stable bef ore the next rising edge of clk 4.0 t wrthld time mosi has to remain stable after the rising edge of clk 4.0 t rdsu time miso will be stable before the next rising edge of clk 4.0 t rdhld time miso will remain stable after the falling edge of clk 4.0 t rden time miso needs to become active after the rising edge of cs 4.0 t rddis time miso needs to become inacti ve after the falling edge of cs 4.0 notes 61. this table reflects a maxi mum spi clock frequency of 26 mhz.
analog integrated circuit device data ? freescale semiconductor 86 34709 functional block description 7.8.2.3 i 2 c operation the i 2 c mode of the interface is implemented generally follo wing the fast mode definition which supports up to 400 kbits/s operation. (exceptions to the standard are noted to be 7-bit only addressing, and no support for general call addressing) timin g diagrams, electrical specifications, and further details on th is bus standard, is available on the internet, by typing ? ?i 2 c specification? in the web search string field. standard i 2 c protocol utilizes bytes of eight bits, with an acknowledge bit (ack) required between each byte. however, the number of bytes per transfer is unrestricted. the register map is organized in 24-bit registers which corresponds to the 24-bit words supported by the spi protocol of this product. to ensure that i 2 c operation mimics spi transactions in behavior of a complete 24-bit word being written in one transaction, software is expected to perform write transactions to the device in 3-by te sequences, beginning with the msb. internally, data latching will be gated by the acknowl edge at the completi on of writing the third consecutive byte. failure to complete a 3-byte write sequence will abort the i 2 c transaction and the register will retain its previous value. this could be due to a premature stop command from the master, for example. i 2 c read operations are also performed in byte increments se parated by an ack. read operati ons also begin with the msb and 3-bytes will be sent out unless a stop command or nack is received prior to completion. the following examples show how to write and read data to the ic. the host initiates and terminates all communication. the host sends a master command packet after driving the start condition. the device will respond to the host if the master command packet contains the corresponding slave address. in the following examples, the device is shown always responding with an ack to transmissions from the host. if at any time a nak is rece ived, the host should terminate the current transaction and retry t he transaction. figure 22. i 2 c 3-byte write example ? device address r egi s ter addr es s packet type start r/w host sda (to mi so) a c k slave sda (from miso) a c k master driven data (byte 2) master driven data (byte 1) master driven data (byte 0) 16 23 0 7 8 15 stop host can also drive another start instead of stop a c k a c k a c k packet type 0 0 7 0 0 7 0 host sda (to miso) slave sda (from miso) continuation
analog integrated circuit device data ? 87 freescale semiconductor 34709 functional bloc k description figure 23. i 2 c 3-byte read example 7.8.3 spi/i 2 c specification table 78. spi/i 2 c electrical characteristics characteristics noted under conditions bp = 3.6 v, - 40 ? c ? t a ? 85 ? c, unless otherwise noted. typical values at bp = 3.6 v and t a = 25 c under nominal conditions, unless otherwise noted. symbol characteristic min typ max unit notes spi interface logic io v incslo input low cs 0.0 - 0.4 v v incshi input high cs 1.1 - spivcc+0.3 v v inmosilo / v inclklo input low, mosi, clk 0.0 - 0.3*spivcc v v inmosihi / v inclkhi input high, mosi, clk 0.7*spivcc - spivcc+0.3 v v misolo / v intlo output low miso, int ? output sink 100 ? a 0.0 - 0.2 v v misohi / v inthi output high miso, int ? output source 100 ? a spivcc-0.2 - spivcc v v cc-spi spivcc operating range 1.75 - 3.6 v t misoet miso rise and fall time, cl = 50 pf, spivcc = 1.8 v ?spidrv [1:0] = 00 ?spidrv [1:0] = 01 (default) ?spidrv [1:0] = 10 ?spidrv [1:0] = 11 - - - - 6.0 2.5 3.0 2.0 - - - - ns ? device ad dr e ss r egi ster addr ess device address packet type star t 0 0 r/w 16 23 8 15 16 23 0 7 8 15 a c k stop a c k a c k start 0 7 r/w a c k a c k na ck ap li te d r i ven d ata (byte 2) packet type ap lite driven data (byte 1) ap lite driven data (byte 0) host can also drive another start instead of stop 0 1 host sda (to miso) slave sda ( from miso) host sda (to miso) slave sda (from miso) continuation device data device data device data
analog integrated circuit device data ? freescale semiconductor 88 34709 functional block description 7.9 configuration registers 7.9.1 register set structure the general structure of the register set is given in table 79 . expanded bit descriptions are included in the following functional sections for application guidance. for brevity?s sake, references are occasionally made herein to the register set as the ?spi map? or ?spi bits?, but note that bit access is also possible through the i 2 c interface option so such references are implied as generically applicable to the register set accessible by either interface. table 79. register set register register register register 0 interrupt status 0 16 memory a 32 regulator mode 0 48 adc5 1 interrupt mask 0 17 memory b 33 gpiolv0 control 49 adc6 2 interrupt sense 0 18 memory c 34 gpiolv1 control 50 adc7 3 interrupt status 1 19 memory d 35 gpiolv2 control 51 reserved 4 interrupt mask 1 20 rtc time 36 gpiolv3 control 52 supply debounce 5 interrupt sense 1 21 rtc alarm 37 reserved 53 reserved 6 power up mode sense 22 rtc day 38 reserved 54 reserved 7 identification 23 rtc day alarm 39 reserved 55 pwm control 8 regulator fault sense 24 regulator 1 a/b voltage 40 reserved 56 unused 9 reserved 25 regulator 2 & 3 voltage 41 unused 57 unused 10 reserved 26 regulator 4 a/b voltage 42 unused 58 unused 11 reserved 27 regulator 5 voltage 43 adc 0 59 unused 12 unused 28 regulator 1 & 2 mode 44 adc 1 60 unused 13 power control 0 29 regulator 3, 4 and 5 mode 45 adc 2 61 unused 14 power control 1 30 regulator setting 0 46 adc 3 62 unused 15 power control 2 31 swbst control 47 adc4 63 unused
analog integrated circuit device data ? 89 freescale semiconductor 34709 functional bloc k description 7.9.2 specific registers 7.9.2.1 ic and version identification the ic and other version details can be read via the identifica tion bits. these are hardwired on the chip and described in table 80 . 7.9.2.2 embedded memory there are four register banks of general purpose embedded memory to store critical data. the data written to mema[23:0], memb[23:0], memc[23:0], and memd [23:0] is maintained by the coin cell when the main battery is deeply discharged, removed, or contact-bounced (i.e., during a power cut). the contents of the embedded memory are reset by rtcporb. a known pattern can be maintained in these registers to validate confidence in the rtc contents when power is restored after a power cut event. alternatively, the banks can be used for any system need for bit retention with coin cell backup. table 80. ic revision bit assignment identifier value purpose full_layer_rev[2:0] xxx represents the full mask revision pass 1.0 = 001 metal_layer_rev[2:0] xxx represents the full metal revision pass 1.0 = 000 fin[2:0] 000 options within same reticle pass 1.0 = 000 fab[2:0] 000 wafer manufacturing facility pass 1.0 = 000
analog integrated circuit device data ? freescale semiconductor 90 34709 functional block description 7.9.3 spi/i 2 c register map the complete spi bitmap is given in table 81 . table 81. spi/i 2 c register map register types register values reset r/w read / write 0 = low bits loaded at cold start based on pums value r/wm read / write modify 1 = high bits reset by por or global reset w1c write one to clear x = variable resetb / green reset bits reset by por or global or green reset ro read only bits reset by rtcporb or global reset nu not used bits reset by por or offb bits reset by rtcporb only address register name type default 34709 spi register map rev 0.1 0x00 interrupt status 0 table 82 w1c h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - lowbatt - - - - - 7 6 5 4 3 2 1 0 - - - - - tspendet tsdonei adcdonei 0x01 interrupt mask 0 table 83 r/w h00_20_07 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - lowbattm - - - - - 7 6 5 4 3 2 1 0 - - - - - tspendetm tsdonem adcdonem 0x02 interrupt sense 0 table 84 nu h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 0x03 interrupt status 1 table 85 w1c h40_80_80 23 22 21 20 19 18 17 16 - battdetbi - gpiolv3i gpiolv2i gpiolv1i gpiolv0i scpi 15 14 13 12 11 10 9 8 clki therm130 therm125 therm120 therm110 memhldi warmi pci 7 6 5 4 3 2 1 0 rtcrsti sysrsti wdiresti pwron2i pwron1i - todai 1hzi 0x04 interrupt mask 1 table 86 r/w h5f_ff_fb 23 22 21 20 19 18 17 16 - battdetbim - gpiolv3m gpiolv2m gpiolv1m gpiolv0m scpm 15 14 13 12 11 10 9 8 clkm therm130m therm125m therm120m therm110m memhldm warmm pcm 7 6 5 4 3 2 1 0 rtcrstm sysrstm wdirestm pwron2m pwron1m - todam 1hzm
analog integrated circuit device data ? 91 freescale semiconductor 34709 functional bloc k description 0x05 interrupt sense 1 table 87 ro hxx_xx_xx 23 22 21 20 19 18 17 16 - - - gpiolv3s gpiolv2s gpiolv1s gpiolv0s - 15 14 13 12 11 10 9 8 clks therm130s therm125s therm120s therm110s - - - 7 6 5 4 3 2 1 0 - - - pwron2s pwron1s - - - 0x06 power up mode sense table 88 ro h00_00_xx 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - pums5s pums4s pums3s pums2s pums1s ictests 0x07 identification table 89 ro h00_0x_xx 23 22 21 20 19 18 17 16 page[4:0] - - - 15 14 13 12 11 10 9 8 - - - - fab[2:0] fin[2] 7 6 5 4 3 2 1 0 fin[1:0] full_layer_rev[2:0] metal_layer_rev[2:0] 0x08 regulator fault sense table 90 r0 h00_xx_xx 23 22 21 20 19 18 17 16 regscpen - - - - - - - 15 14 13 12 11 10 9 8 - - - vgen2fault vgen1fault vdacfault vusb2fault vusbfault 7 6 5 4 3 2 1 0 swbstfault sw5fault sw4bfault sw4afault sw3fault sw2fault rsvd sw1fault 0x09 to 0x0c unused nu h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 0x0d power control 0 table 93 r/w h00_00_40 23 22 21 20 19 18 17 16 coinchen vcoin[2:0] - - - - 15 14 13 12 11 10 9 8 - - - - - - pcutexpb - 7 6 5 4 3 2 1 0 - clk32kmcuen useroffclk drm useroffspi warmen pccounten pcen 0x0e power control 1 table 94 r/w h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 pcmaxcnt[3:0] pccount[3:0] 7 6 5 4 3 2 1 0 pct[7:0] 0x0f power control 2 table 95 r/w h42_23_00 23 22 21 20 19 18 17 16 stbydly[1:0] on_stby_lp - - clkdrv[1:0] - 15 14 13 12 11 10 9 8 - spidrv[1:0] wdireset - standbyinv glbrsttmr[1:0] 7 6 5 4 3 2 1 0 pwron2dbnc[1:0] pwron1bdbnc[1:0] - pwron2rsten pwron1rsten restarten
analog integrated circuit device data ? freescale semiconductor 92 34709 functional block description 0x10 memory a table 96 r/w h00_00_00 23 22 21 20 19 18 17 16 mema[23:16] 15 14 13 12 11 10 9 8 mema[15:8] 7 6 5 4 3 2 1 0 mema[7:0] 0x11 memory b table 97 r/w h00_00_00 23 22 21 20 19 18 17 16 memb[23:16] 15 14 13 12 11 10 9 8 memb[15:8] 7 6 5 4 3 2 1 0 memb[7:0] 0x12 memory c table 98 r/w h00_00_00 23 22 21 20 19 18 17 16 memc[23:16] 15 14 13 12 11 10 9 8 memc[15:8] 7 6 5 4 3 2 1 0 memc[7:0] 0x13 memory d table 99 r/w h00_00_00 23 22 21 20 19 18 17 16 memd[23:16] 15 14 13 12 11 10 9 8 memd[15:8] 7 6 5 4 3 2 1 0 memd[7:0] 0x14 rtc time table 100 r/w h0x_xx_xx 23 22 21 20 19 18 17 16 rtccalmode[1:0] rtccal[4:0] tod[16] 15 14 13 12 11 10 9 8 tod[15:8] 7 6 5 4 3 2 1 0 tod[7:0] 0x15 rtc alarm table 101 r/w h01_ff_ff 23 22 21 20 19 18 17 16 rtcdis spare spare spare spare spare spare toda[16] 15 14 13 12 11 10 9 8 toda[15:8] 7 6 5 4 3 2 1 0 toda[7:0] 0x16 rtc day table 102 r/w h00_xx_xx 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - day[14:8] 7 6 5 4 3 2 1 0 day[7:0] 0x17 rtc day alarm table 103 r/w h00_7f_ff 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - daya[14:8] 7 6 5 4 3 2 1 0 daya[7:0]
analog integrated circuit device data ? 93 freescale semiconductor 34709 functional bloc k description 0x18 regulator 1a/b voltage table 104 r/wm hxx_xx_xx 23 22 21 20 19 18 17 16 rsvd[5:0] rsvd[5:4] 15 14 13 12 11 10 9 8 rsvd[3:0] sw1astby[5:2] 7 6 5 4 3 2 1 0 sw1astby[1:0] sw1a[5:0] 0x19 regulator 2&3 voltage table 105 r/wm hxx_xx_xx 23 22 21 20 19 18 17 16 - sw3stby[4:0] - sw3[4] 15 14 13 12 11 10 9 8 sw3[3:0] sw2stby[5:2] 7 6 5 4 3 2 1 0 sw2stby[1:0] sw2[5:0] 0x1a regulator 4 voltage table 106 r/wm hxx_xx_xx 23 22 21 20 19 18 17 16 sw4bhi[1:0] sw4bstby[4:0] sw4b[4] 15 14 13 12 11 10 9 8 sw4b[3:0] sw4ahi[1:0] sw4astby[4:3] 7 6 5 4 3 2 1 0 sw4astby[2:0] sw4a[4:0] 0x1b regulator 5 voltage table 107 r/wm h00_xx_xx 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - sw5tby[4:0] - - 7 6 5 4 3 2 1 0 - - - sw5[4:0] 0x1c regulator 1, 2 mode table 108 r/wm h52_80_48 23 22 21 20 19 18 17 16 pllx pllen sw2dvsspeed[1:0] sw2uomode sw2mhmode sw2mode[3:2] 15 14 13 12 11 10 9 8 sw2mode[1:0] - - - - - - 7 6 5 4 3 2 1 0 sw1dvsspeed[1:0] sw1auomode sw1amhmode sw1amode[3:0] 0x1d regulator 3, 4, 5 mode table 109 r/wm h52_08_48 23 22 21 20 19 18 17 16 sw5uomode sw5mhmode sw5mode[3:0] sw4buomode sw4bmhmode 15 14 13 12 11 10 9 8 sw4bmode[3:0] sw4auomode sw4amhmode sw4amode[3:2] 7 6 5 4 3 2 1 0 sw4amode[1:0] sw3uomode sw3mhmode sw3mode[3:0] 0x1e regulator setting 0 table 110 r/wm h00_xx_xx 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - vusb2[1:0] vpll[1:0] vgen2[2] 7 6 5 4 3 2 1 0 vgen2[1:0] vdac[1:0] - vgen1[2:0] 0x1f swbst control table 111 r/wm h00_00_0x 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 spare swbststbymode[1:0] spare swbstmode[1:0] swbst[1:0]
analog integrated circuit device data ? freescale semiconductor 94 34709 functional block description 0x20 regulator mode 0 table 112 r/wm h0x_xx_xx 23 22 21 20 19 18 17 16 - - - vusb2mode vusb2stby vusb2en vusb2config vpllstby 15 14 13 12 11 10 9 8 vpllen vgen2mode vgen2stby vgen2en vgen2config vrefddren - - 7 6 5 4 3 2 1 0 - vdacmode vdacstby vdacen vusben - vgen1stby vgen1en 0x21 gpiolv0 control table 113 r/w h00_38_0x 23 22 21 20 19 18 17 16 - - - - - - - spare 15 14 13 12 11 10 9 8 sre1 sre0 pus1 pus0 pue dse ode pke 7 6 5 4 3 2 1 0 int1 int0 dbnc1 dbnc0 hys dout din dir 0x22 gpiolv1 control table 114 r/w h00_38_0x 23 22 21 20 19 18 17 16 - - - - - - - spare 15 14 13 12 11 10 9 8 sre1 sre0 pus1 pus0 pue dse ode pke 7 6 5 4 3 2 1 0 int1 int0 dbnc1 dbnc0 hys dout din dir 0x23 gpiolv2 control table 115 r/w h00_38_0x 23 22 21 20 19 18 17 16 - - - - - - - spare 15 14 13 12 11 10 9 8 sre1 sre0 pus1 pus0 pue dse ode pke 7 6 5 4 3 2 1 0 int1 int0 dbnc1 dbnc0 hys dout din dir 0x24 gpiolv3 control table 116 r/w h00_38_0x 23 22 21 20 19 18 17 16 - - - - - - - spare 15 14 13 12 11 10 9 8 sre1 sre0 pus1 pus0 pue dse ode pke 7 6 5 4 3 2 1 0 int1 int0 dbnc1 dbnc0 hys dout din dir 0x25 to 0x2a unused nu h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 0x2b adc 0 table 119 r/w h00_00_00 23 22 21 20 19 18 17 16 spare spare spare tspendeten spare tsstop[2:0] 15 14 13 12 11 10 9 8 tshold tscont tsstart tsen spare spare spare therm 7 6 5 4 3 2 1 0 spare adstop[2:0] adhold adcont adstart aden 0x2c adc 1 table 120 r/w h00_00_00 23 22 21 20 19 18 17 16 tsdly3[3:0] tsdly2[3:0] 15 14 13 12 11 10 9 8 tsdly1[3:0] addly3[3:0] 7 6 5 4 3 2 1 0 addly2[3:0] addly1[3:0]
analog integrated circuit device data ? 95 freescale semiconductor 34709 functional bloc k description 0x2d adc 2 table 121 r/w h00_00_00 23 22 21 20 19 18 17 16 adsel5[3:0] adsel4[3:0] 15 14 13 12 11 10 9 8 adsel3[3:0] adsel2[3:0] 7 6 5 4 3 2 1 0 adsel1[3:0] adsel0[3:0] 0x2e adc 3 table 122 r/w h00_00_00 23 22 21 20 19 18 17 16 tssel7[1:0] tssel6[1:0] tssel5[1:0] tssel4[1:0] 15 14 13 12 11 10 9 8 tssel3[1:0] tssel2[1:0] tssel1[1:0] tssel0[1:0] 7 6 5 4 3 2 1 0 adsel7[3:0] adsel6[3:0] 0x2f adc 4 table 123 r/w h00_00_00 23 22 21 20 19 18 17 16 adresult1[9:2] 15 14 13 12 11 10 9 8 adresult1[1:0] - - adresult0[9:6] 7 6 5 4 3 2 1 0 adresult0[5:0] - - 0x30 adc 5 table 124 r/w h00_00_00 23 22 21 20 19 18 17 16 adresult3[9:2] 15 14 13 12 11 10 9 8 adresult3[1:0] - - adresult2[9:6] 7 6 5 4 3 2 1 0 adresult2[5:0] - - 0x31 adc 6 table 125 r/w h00_00_00 23 22 21 20 19 18 17 16 adresult5[9:2] 15 14 13 12 11 10 9 8 adresult5[1:0] - - adresult4[9:6] 7 6 5 4 3 2 1 0 adresult4[5:2] - - 0x32 adc 7 table 126 r/w h00_00_00 23 22 21 20 19 18 17 16 adresult7[9:2] 15 14 13 12 11 10 9 8 adresult7[9:2] - - adresult6[9:6] 7 6 5 4 3 2 1 0 adresult6[5:0] - - 0x33 unused nu h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 0x34 supply debounce table 128 r/w h03_00_00 23 22 21 20 19 18 17 16 - - - - - - die_temp_db[1:0] 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - vbattdb[1:0] - -
analog integrated circuit device data ? freescale semiconductor 96 34709 functional block description 7.9.4 spi register?s bit description 0x35 to 0x36 unused nu h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 0x37 pwm control table 130 r/w h00_00_00 23 22 21 20 19 18 17 16 pwm2clkdiv[5:0] pwm2duty[5:4] 15 14 13 12 11 10 9 8 pwm2duty[3:0] pwm1clkdiv[5:2] 7 6 5 4 3 2 1 0 pwm1clkdiv[1:0] pwm1duty[5:0] 0x38 to 0x3f unused nu h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - table 82. register 0, interrupt status 0 name bit # r/w reset default description adcdonei 0 rw1c resetb 0 adc has finished requested conversions tsdonei 1 rw1c resetb 0 touchscreen has finis hed requested conversions tspendet 2 rw1c resetb 0 touch screen pen detection reserved 3 r - - for future use reserved 4 r - - for future use reserved 5 r - - for future use reserved 6 r - - for future use reserved 7 r - - for future use reserved 8 r - - for future use reserved 9 r - - for future use reserved 10 r - - for future use reserved 11 r - - for future use reserved 12 r - - for future use lowbatt 13 rw1c resetb 0 low battery threshold warning reserved 14 r - - for future use reserved 15 r - - for future use reserved 16 r - - for future use reserved 17 r - - for future use reserved 18 r - - for future use reserved 19 r - - for future use
analog integrated circuit device data ? 97 freescale semiconductor 34709 functional bloc k description reserved 20 r - - for future use reserved 21 r - - for future use reserved 22 r - - for future use reserved 23 r - - for future use back to spi/i2c register map table 83. register 1, interrupt mask 0 name bit # r/w reset default description adcdonem 0 r/w resetb 1 adcdonei mask bit tsdonem 1 r/w resetb 1 tsdonei mask bit tspendetm 2 r/w resetb 1 touch screen pen detect mask bit reserved 3 r - - for future use reserved 4 r - - for future use reserved 5 r - - for future use reserved 6 r - - for future use reserved 7 r - - for future use reserved 8 r - - for future use reserved 9 r - - for future use reserved 10 r - - for future use reserved 11 r - - for future use reserved 12 r - - for future use lowbattm 13 r/w resetb 1 lobatli mask bit reserved 14 r - - for future use reserved 15 r - - for future use reserved 16 r - - for future use reserved 17 r - - for future use reserved 18 r - - for future use reserved 19 r - - for future use reserved 20 r - - for future use reserved 21 r - - for future use reserved 22 r - - for future use reserved 23 r - - for future use back to spi/i2c register map table 82. register 0, interrupt status 0 name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 98 34709 functional block description table 84. register 2, interrupt sense 0 name bit # r/w reset default description unused 0 r - 0 not available unused 1 r - 0 not available unused 2 r - 0 not available reserved 3 r - - for future use reserved 4 r - - for future use reserved 5 r - - for future use reserved 6 r - - for future use unused 7 r - 0 not available reserved 8 r - - for future use reserved 9 r - - for future use unused 10 r - 0 not available unused 11 r - 0 not available unused 12 r - 0 not available unused 13 r - 0 not available unused 14 r - 0 not available unused 15 r - 0 not available unused 16 r - 0 not available reserved 17 r - - for future use reserved 18 r - - for future use reserved 19 r - - for future use reserved 20 r - - for future use reserved 21 r - - for future use unused 22 r - 0 not available unused 23 r - 0 not available back to spi/i2c register map table 85. register 3, interrupt status 1 name bit # r/w reset default description 1hzi 0 rw1c rtcporb 0 1.0 hz time tick todai 1 rw1c rtcporb 0 time of day alarm unused 2 r 0 pwron1i 3 rw1c offb 0 pwron1 event pwron2i 4 rw1c offb 0 pwron2 event wdireseti 5 rw1c rtcporb 0 wdi system reset event sysrsti 6 rw1c rtcporb 0 pwron system reset event rtcrsti 7 rw1c rtcporb 1 rtc reset event pci 8 rw1c offb 0 power cut event warmi 9 rw1c rtcporb 0 warm start event
analog integrated circuit device data ? 99 freescale semiconductor 34709 functional bloc k description memhldi 10 rw1c rtcporb 0 memory hold event therm110 11 rw1c resetb 0 110 c thermal threshold therm120 12 rw1c resetb 0 120 c thermal threshold therm125 13 rw1c resetb 0 125 c thermal threshold therm130 14 rw1c resetb 0 130 c thermal threshold clki 15 rw1c resetb 0 clock source change scpi 16 rw1c resetb 0 short-circuit protec tion trip detection gpiolv1i 17 rw1c resetb 0 gpiolv1 interrupt gpiolv2i 18 rw1c resetb 0 gpiolv2 interrupt gpiolv3i 19 rw1c resetb 0 gpiolv3 interrupt gpiolv4i 20 rw1c resetb 0 gpiolv4 interrupt unused 21 r - 0 not available reserved 22 r - - for future use unused 23 r resetb 0 not available back to spi/i2c register map table 86. register 4, interrupt mask 1 name bit # r/w reset default description 1hzm 0 r/w rtcporb 1 1hzi mask bit todam 1 r/w rtcporb 1 todai mask bit unused 2 r 1 pwron1m 3 r/w offb 1 pwron1 mask bit pwron2m 4 r/w offb 1 pwron2 mask bit wdiresetm 5 r/w rtcporb 1 wdireseti mask bit sysrstm 6 r/w rtcporb 1 sysrsti mask bit rtcrstm 7 r/w rtcporb 1 rtcrsti mask bit pcm 8 r/w offb 1 pci mask bit warmm 9 r/w rtcporb 1 warmi mask bit memhldm 10 r/w rtcporb 1 memhldi mask bit therm110m 11 r/w resetb 1 therm110 mask bit therm120m 12 r/w resetb 1 therm120 mask bit therm125m 13 r/w resetb 1 therm125 mask bit therm130m 14 r/w resetb 1 therm130 mask bit clkm 15 r/w resetb 1 clki mask bit scpm 16 r/w resetb 1 short-circuit protection trip mask bit gpiolv1m 17 r/w resetb 1 gpiolv1 interrupt mask bit gpiolv2m 18 r/w resetb 1 gpiolv2 interrupt mask bit gpiolv3m 19 r/w resetb 1 gpiolv3 interrupt mask bit table 85. register 3, interrupt status 1 name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 100 34709 functional block description gpiolv4m 20 r/w resetb 1 gpiolv4 interrupt mask bit unused 21 r 0 not available reserved 22 r - - for future use unused 23 r 1 not available back to spi/i2c register map table 87. register 5, interrupt sense 1 name bit # r/w reset default description unused 0 r 0 not available unused 1 r 0 not available unused 2 r 0 not available pwron1s 3 r none s pwron1i sense bit pwron2s 4 r none s pwron2i sense bit unused 5 r 0 not available unused 6 r 0 not available unused 7 r 0 not available unused 8 r 0 not available unused 9 r 0 not available unused 10 r 0 not available therm110s 11 r none s therm110 sense bit therm120s 12 r none s therm120 sense bit therm125s 13 r none s therm125 sense bit therm130s 14 r none s therm130 sense bit clks 15 r none 0 clki sense bit unused 16 r 0 not available unused 17 r 0 not available unused 18 r 0 not available unused 19 r 0 not available unused 20 r 0 not available unused 21 r 0 not available reserved 22 r - - for future use unused 23 r none 0 not available back to spi/i2c register map table 86. register 4, interrupt mask 1 name bit # r/w reset default description
analog integrated circuit device data ? 101 freescale semiconductor 34709 functional bloc k description table 88. register 6, power-up mode sense name bit # r/w reset default description ictests 0 r none s ictest sense state pums1s 1 r none l pums1 state pums2s 2 r none l pums2 state pums3s 3 r none l pums3 state pums4s 4 r none l pums4 state pums5s 5 r none l pums5 state unused 6 r 0 not available unused 7 r 0 not available unused 8 r 0 not available reserved 9 r - - for future use unused 10 r 0 not available unused 11 r 0 not available unused 12 r 0 not available unused 13 r 0 not available unused 14 r 0 not available unused 15 r 0 not available unused 16 r 0 not available unused 17 r 0 not available unused 18 r 0 not available unused 19 r 0 not available unused 20 r 0 not available unused 21 r 0 not available unused 22 0 not available unused 23 0 not available back to spi/i2c register map table 89. register 7, identification name bit # r/w reset default description metal_layer_rev0 0 r none x metal layer version pass 1.0 = 000 metal_layer_rev1 1 r none x metal_layer_rev2 2 r none x full_layer_rev0 3 r none x full layer version pass 1.0 = 001 full_layer rev1 4 r none x full_layer rev2 5 r none x fin0 6 r none x fin version pass 1.0 = 000 fin1 7 r none x fin2 8 r none x
analog integrated circuit device data ? freescale semiconductor 102 34709 functional block description fab0 9 r none x fab version pass 1.0 = 000 fab1 10 r none x fab2 11 r none x unused 12 r 0 not available unused 13 r 0 not available unused 14 r 0 not available unused 15 r 0 not available unused 16 r 0 not available unused 17 r 0 not available unused 18 r 0 not available page0 19 r/w digresetb 0 spi page page1 20 r/w digresetb 0 page2 21 r/w digresetb 0 page3 22 r/w digresetb 0 page4 23 r/w digresetb 0 back to spi/i2c register map table 90. register 8, regulator fault sense name bit # r/w reset default description sw1fault 0 r none s sw1 fault detection reserved 1 r - - for future use sw2fault 2 r none s sw2 fault detection sw3fault 3 r none s sw3 fault detection sw4afault 4 r none s sw4a fault detection sw4bfault 5 r none s sw4b fault detection sw5fault 6 r none s sw5 fault detection swbstfault 7 r none s swbst fault detection vusbfault 8 r none s vusb fault detection vusb2fault 9 r none s vusb2 fault detection vdacfault 10 r none s vdac fault detection vgen1fault 11 r none s vgen1 fault detection vgen2fault 12 r none s vgen2 fault detection unused 13-22 r 0 not available rescgpen 23 r/w resetb 0 regulator short-circuit protect enable back to spi/i2c register map table 89. register 7, identification name bit # r/w reset default description
analog integrated circuit device data ? 103 freescale semiconductor 34709 functional bloc k description table 91. register 9, reserved name bit # r/w reset default description reserved 23-0 r - - for future use table 92. register 10 to 12, unused name bit # r/w reset default description reserved 23-0 r - - for future use table 93. register 13, power control 0 name bit # r/w reset default description pcen 0 r/w rtcporb 0 power cut enable pccounten 1 r/w rtcporb 0 power cut counter enable warmen 2 r/w rtcporb 0 warm start enable useroffspi 3 r/w resetb 0 spi command for entering user off modes drm 4 r/w rtcporb (62) 0 keeps vsrtc and clk32kmcu on for all states useroffclk 5 r/w rtcporb 0 keeps the clk32kmcu active during user off clk32kmcuen 6 r/w rtcporb 1 enables the clk32kmcu unused 7 r 0 not available unused 8 r 0 not available pcutexpb 9 r/w rtcporb 0 pcutexpb=1 at a start-up event indi cates that pcut timer did not expire (assuming it was set to 1 after booting) unused 10 r 0 not available unused 11 r 0 not available unused 12 r 0 not available unused 13 r 0 not available unused 14 r 0 not available unused 15 r 0 not available unused 16 r 0 not available unused 17 r 0 not available unused 18 r 0 not available reserved 19 r - - for future use vcoin0 20 r/w rtcporb 0 coin cell charger voltage setting vcoin1 21 r/w rtcporb 0 vcoin2 22 r/w rtcporb 0 coinchen 23 r/w rtcporb 0 coin cell charger enable notes: 62. reset by rtcporb but not during a glbrst (global reset) back to spi/i2c register map
analog integrated circuit device data ? freescale semiconductor 104 34709 functional block description table 94. register 14, power control 1 name bit # r/w reset default description pct0 0 r/w rtcporb 0 power cut timer pct1 1 r/w rtcporb 0 pct2 2 r/w rtcporb 0 pct3 3 r/w rtcporb 0 pct4 4 r/w rtcporb 0 pct5 5 r/w rtcporb 0 pct6 6 r/w rtcporb 0 pct7 7 r/w rtcporb 0 pccount0 8 r/w rtcporb 0 power cut counter pccount1 9 r/w rtcporb 0 pccount2 10 r/w rtcporb 0 pccount3 11 r/w rtcporb 0 pcmaxcnt0 12 r/w rtcporb 0 maximum allowed number of power cuts pcmaxcnt1 13 r/w rtcporb 0 pcmaxcnt2 14 r/w rtcporb 0 pcmaxcnt3 15 r/w rtcporb 0 unused 16 r 0 not available unused 17 r 0 not available unused 18 r 0 not available unused 19 r 0 not available unused 20 r 0 not available unused 21 r 0 not available unused 22 r 0 not available unused 23 r 0 not available back to spi/i2c register map table 95. register 15, power control 2 name bit # r/w reset default description restarten 0 r/w rtcporb 0 enables automatic restart after a system reset pwron1rsten 1 r/w rtcporb 0 enables system reset on pwron1 pin pwron2rsten 2 r/w rtcporb 0 enables system reset on pwron2 pin unused 3 r 0 not available pwron1dbnc0 4 r/w rtcporb 0 sets debounce time on pwron1 pin pwron1dbnc1 5 r/w rtcporb 0 pwron2dbnc0 6 r/w rtcporb 0 sets debounce time on pwron2 pin pwron2dbnc1 7 r/w rtcporb 0 glbrsttmr0 8 r/w rtcporb 1 sets global reset time glbrsttmr1 9 r/w rtcporb 1
analog integrated circuit device data ? 105 freescale semiconductor 34709 functional bloc k description standbyinv 10 r/w rtcporb 0 if set then standby is interpreted as active low unused 11 r 0 not available wdireset 12 r/w resetb 0 enables system reset through wdi spidrv0 13 r/w rtcporb 1 spi drive strength spidrv1 14 r/w rtcporb 0 unused 15 r 0 not available unused 16 r 0 not available clk32kdrv0 17 r/w rtcporb 1 clk32k and clk32kmcu drive strength (master control bits) clk32kdrv1 18 r/w rtcporb 0 unused 19 r 0 not available unused 20 r 0 not available on_stby_lp 21 r/w resetb 0 on standby low-power mode 0 = low-power mode disabled 1 =low-power mode enabled stbydly0 22 r/w resetb 1 standby delay control stbydly1 23 r/w resetb 0 back to spi/i2c register map table 96. register 16, memory a name bit # r/w reset default description mema0 0 r/w rtcporb 0 backup memory a mema1 1 r/w rtcporb 0 mema2 2 r/w rtcporb 0 mema3 3 r/w rtcporb 0 mema4 4 r/w rtcporb 0 mema5 5 r/w rtcporb 0 mema6 6 r/w rtcporb 0 mema7 7 r/w rtcporb 0 mema8 8 r/w rtcporb 0 mema9 9 r/w rtcporb 0 mema10 10 r/w rtcporb 0 mema11 11 r/w rtcporb 0 mema12 12 r/w rtcporb 0 mema13 13 r/w rtcporb 0 mema14 14 r/w rtcporb 0 mema15 15 r/w rtcporb 0 mema16 16 r/w rtcporb 0 mema17 17 r/w rtcporb 0 mema18 18 r/w rtcporb 0 table 95. register 15, power control 2 name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 106 34709 functional block description mema19 19 r/w rtcporb 0 backup memory a mema20 20 r/w rtcporb 0 mema21 21 r/w rtcporb 0 mema22 22 r/w rtcporb 0 mema23 23 r/w rtcporb 0 back to spi/i2c register map table 97. register 17, memory b name bit # r/w reset default description memb0 0 r/w rtcporb 0 backup memory b memb1 1 r/w rtcporb 0 memb2 2 r/w rtcporb 0 memb3 3 r/w rtcporb 0 memb4 4 r/w rtcporb 0 memb5 5 r/w rtcporb 0 memb6 6 r/w rtcporb 0 memb7 7 r/w rtcporb 0 memb8 8 r/w rtcporb 0 memb9 9 r/w rtcporb 0 memb10 10 r/w rtcporb 0 memb11 11 r/w rtcporb 0 memb12 12 r/w rtcporb 0 memb13 13 r/w rtcporb 0 memb14 14 r/w rtcporb 0 memb15 15 r/w rtcporb 0 memb16 16 r/w rtcporb 0 memb17 17 r/w rtcporb 0 memb18 18 r/w rtcporb 0 memb19 19 r/w rtcporb 0 memb20 20 r/w rtcporb 0 memb21 21 r/w rtcporb 0 memb22 22 r/w rtcporb 0 memb23 23 r/w rtcporb 0 back to spi/i2c register map table 96. register 16, memory a name bit # r/w reset default description
analog integrated circuit device data ? 107 freescale semiconductor 34709 functional bloc k description table 98. register 18, memory c name bit # r/w reset default description memc0 0 r/w rtcporb 0 backup memory c memc1 1 r/w rtcporb 0 memc2 2 r/w rtcporb 0 memc3 3 r/w rtcporb 0 memc4 4 r/w rtcporb 0 memc5 5 r/w rtcporb 0 memc6 6 r/w rtcporb 0 memc7 7 r/w rtcporb 0 memc8 8 r/w rtcporb 0 memc9 9 r/w rtcporb 0 memc10 10 r/w rtcporb 0 memc11 11 r/w rtcporb 0 memc12 12 r/w rtcporb 0 memc13 13 r/w rtcporb 0 memc14 14 r/w rtcporb 0 memc15 15 r/w rtcporb 0 memc16 16 r/w rtcporb 0 memc17 17 r/w rtcporb 0 memc18 18 r/w rtcporb 0 memc19 19 r/w rtcporb 0 memc20 20 r/w rtcporb 0 memc21 21 r/w rtcporb 0 memc22 22 r/w rtcporb 0 memc23 23 r/w rtcporb 0 back to spi/i2c register map table 99. register 19, memory d name bit # r/w reset default description memd0 0 r/w rtcporb 0 backup memory d memd1 1 r/w rtcporb 0 memd2 2 r/w rtcporb 0 memd3 3 r/w rtcporb 0 memd4 4 r/w rtcporb 0 memd5 5 r/w rtcporb 0 memd6 6 r/w rtcporb 0 memd7 7 r/w rtcporb 0 memd8 8 r/w rtcporb 0 memd9 9 r/w rtcporb 0
analog integrated circuit device data ? freescale semiconductor 108 34709 functional block description memd10 10 r/w rtcporb 0 backup memory d memd11 11 r/w rtcporb 0 memd12 12 r/w rtcporb 0 memd13 13 r/w rtcporb 0 memd14 14 r/w rtcporb 0 memd15 15 r/w rtcporb 0 memd16 16 r/w rtcporb 0 memd17 17 r/w rtcporb 0 memd18 18 r/w rtcporb 0 memd19 19 r/w rtcporb 0 memd20 20 r/w rtcporb 0 memd21 21 r/w rtcporb 0 memd22 22 r/w rtcporb 0 memd23 23 r/w rtcporb 0 back to spi/i2c register map table 100. register 20, rtc time name bit # r/w reset default description tod0 0 r/w rtcporb (63) 0 time of day counter tod1 1 r/w rtcporb (63) 0 tod2 2 r/w rtcporb (63) 0 tod3 3 r/w rtcporb (63) 0 tod4 4 r/w rtcporb (63) 0 tod5 5 r/w rtcporb (63) 0 tod6 6 r/w rtcporb (63) 0 tod7 7 r/w rtcporb (63) 0 tod8 8 r/w rtcporb (63) 0 tod9 9 r/w rtcporb (63) 0 tod10 10 r/w rtcporb (63) 0 tod11 11 r/w rtcporb (63) 0 tod12 12 r/w rtcporb (63) 0 tod13 13 r/w rtcporb (63) 0 tod14 14 r/w rtcporb (63) 0 tod15 15 r/w rtcporb (63) 0 tod16 16 r/w rtcporb (63) 0 table 99. register 19, memory d name bit # r/w reset default description
analog integrated circuit device data ? 109 freescale semiconductor 34709 functional bloc k description rtccal0 17 r/w rtcporb (63) 0 rtc calibration count rtccal1 18 r/w rtcporb (63) 0 rtccal2 19 r/w rtcporb (63) 0 rtccal3 20 r/w rtcporb (63) 0 rtccal4 21 r/w rtcporb (63) 0 rtccalmode0 22 r/w rtcporb (63) 0 rtc calibration mode rtccalmode1 23 r/w rtcporb (63) 0 notes 63. reset by rtcporb but not during a glbrst (global reset) back to spi/i2c register map table 101. register 21, rtc alarm name bit # r/w reset default description toda0 0 r/w rtcporb (64) 1 time of day alarm toda1 1 r/w rtcporb (64) 1 toda2 2 r/w rtcporb (64) 1 toda3 3 r/w rtcporb (64) 1 toda4 4 r/w rtcporb (64) 1 toda5 5 r/w rtcporb (64) 1 toda6 6 r/w rtcporb (64) 1 toda7 7 r/w rtcporb (64) 1 toda8 8 r/w rtcporb (64) 1 toda9 9 r/w rtcporb (64) 1 toda10 10 r/w rtcporb (64) 1 toda11 11 r/w rtcporb (64) 1 toda12 12 r/w rtcporb (64) 1 toda13 13 r/w rtcporb (64) 1 toda14 14 r/w rtcporb (64) 1 toda15 15 r/w rtcporb (64) 1 toda16 16 r/w rtcporb (64) 1 unused 17- 22 r 0 not available rtcdis 23 r/w rtcporb (64) 0 disable rtc notes 64. reset by rtcporb but not dur ing a glbrst (global reset) back to spi/i2c register map table 100. register 20, rtc time name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 110 34709 functional block description table 102. register 22, rtc day name bit # r/w reset default description day0 0 r/w rtcporb (65) 0 day counter day1 1 r/w rtcporb (65) 0 day2 2 r/w rtcporb (65) 0 day3 3 r/w rtcporb (65) 0 day4 4 r/w rtcporb (65) 0 day5 5 r/w rtcporb (65) 0 day6 6 r/w rtcporb (65) 0 day7 7 r/w rtcporb (65) 0 day8 8 r/w rtcporb (65) 0 day9 9 r/w rtcporb (65) 0 day10 10 r/w rtcporb (65) 0 day11 11 r/w rtcporb (65) 0 day12 12 r/w rtcporb (65) 0 day13 13 r/w rtcporb (65) 0 day14 14 r/w rtcporb (65) 0 unused 15 - 23 r 0 not available notes 65. reset by rtcporb but not dur ing a glbrst (global reset) back to spi/i2c register map
analog integrated circuit device data ? 111 freescale semiconductor 34709 functional bloc k description table 103. register 23, rtc day alarm name bit # r/w reset default description daya0 0 r/w rtcporb (66) 1 day alarm daya1 1 r/w rtcporb (66) 1 daya2 2 r/w rtcporb (66) 1 daya3 3 r/w rtcporb (66) 1 daya4 4 r/w rtcporb (66) 1 daya5 5 r/w rtcporb (66) 1 daya6 6 r/w rtcporb (66) 1 daya7 7 r/w rtcporb (66) 1 daya8 8 r/w rtcporb (66) 1 daya9 9 r/w rtcporb (66) 1 daya10 10 r/w rtcporb (66) 1 daya11 11 r/w rtcporb (66) 1 daya12 12 r/w rtcporb (66) 1 daya13 13 r/w rtcporb (66) 1 daya14 14 r/w rtcporb (66) 1 unused 15 - 23 r 0 not available notes 66. reset by rtcporb but not during a glbrst (global reset) back to spi/i2c register map table 104. register 24, regulator 1a/b voltage name bit # r/w reset default description sw1a0 0 r/wm none * sw1 setting in normal mode sw1a1 1 r/wm none * sw1a2 2 r/wm none * sw1a3 3 r/wm none * sw1a4 4 r/wm none * sw1a5 5 r/wm none * sw1astby0 6 r/wm none * sw1 setting in standby mode sw1astby1 7 r/wm none * sw1astby2 8 r/wm none * sw1astby3 9 r/wm none * sw1astby4 10 r/wm none * sw1astby5 11 r/wm none * reserved 12 - 23 r - - for future use back to spi/i2c register map
analog integrated circuit device data ? freescale semiconductor 112 34709 functional block description table 105. register 25, regulator 2 & 3 voltage name bit # r/w reset default description sw20 0 r/wm none * sw2 setting in normal mode sw21 1 r/wm none * sw22 2 r/wm none * sw23 3 r/wm none * sw24 4 r/wm none * sw25 5 r/wm none * sw2stby0 6 r/wm none * sw2 setting in standby mode sw2stby1 7 r/wm none * sw2stby2 8 r/wm none * sw2stby3 9 r/wm none * sw2stby4 10 r/wm none * sw2stby5 11 r/wm none * sw30 12 r/wm none * sw3 setting in normal mode sw31 13 r/wm none * sw32 14 r/wm none * sw33 15 r/wm none * sw34 16 r/wm none * unused 17 r 0 not available sw3stby0 18 r/wm none * sw3 setting in standby mode sw3stby1 19 r/wm none * sw3stby2 20 r/wm none * sw3stby3 21 r/wm none * sw3stby4 22 r/wm none * unused 23 r 0 not available back to spi/i2c register map table 106. register 26, regulator 4a/b name bit # r/w reset default description sw4a0 0 r/wm none * sw4a setting in normal mode sw4a1 1 r/wm none * sw4a2 2 r/wm none * sw4a3 3 r/wm none * sw4a4 4 r/wm none * sw4astby0 5 r/wm none * sw4a setting in standby mode sw4astby1 6 r/wm none * sw4astby2 7 r/wm none * sw4astby3 8 r/wm none * sw4astby4 9 r/wm none *
analog integrated circuit device data ? 113 freescale semiconductor 34709 functional bloc k description sw4ahi0 10 r/wm none * sw4a high setting sw4ahi1 11 r/wm none * sw4b0 12 r/wm none * sw4b setting in normal mode sw4b1 13 r/wm none * sw4b2 14 r/wm none * sw4b3 15 r/wm none * sw4b4 16 r/wm resetb * sw4bstby0 17 r/wm resetb * sw4b setting in standby mode sw4bstby1 18 r/wm resetb * sw4bstby2 19 r/wm resetb * sw4bstby3 20 r/wm resetb * sw4bstby4 21 r/wm resetb * sw4bhi0 22 r/wm resetb * sw4b high setting sw4bhi1 23 r/wm resetb * back to spi/i2c register map table 107. register 27, regulator 5 voltage name bit # r/w reset default description sw50 0 r/wm none * sw4 setting in normal mode sw51 1 r/wm none * sw52 2 r/wm none * sw53 3 r/wm none * sw54 4 r/wm none * unused 5 - 9 r * not available sw5stby0 10 r/wm none * sw5 setting in standby mode sw5stby1 11 r/wm none * sw5stby2 12 r/wm none * sw5stby3 13 r/wm none * sw5stby4 14 r/wm none * unused 15 - 23 r 0 not available back to spi/i2c register map table 108. register 28, regulators 1 & 2 operating mode name bit # r/w reset default description sw1amode0 0 r/w resetb 0 sw1a operating mode sw1amode1 1 r/w resetb 0 sw1amode2 2 r/w resetb 0 sw1amode3 3 r/w resetb 1 table 106. register 26, regulator 4a/b name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 114 34709 functional block description sw1amhmode 4 r/w offb 0 sw1a memory hold mode sw1auomode 5 r/w offb 0 sw1a user off mode sw1dvsspeed0 6 r/w resetb 1 sw1 dvs1 speed sw1dvsspeed1 7 r/w resetb 0 unused 8 - 13 r 0 not available sw2mode0 (67) 14 r/w resetb 0 sw2 operating mode sw2mode1 (67) 15 r/w resetb 0 sw2mode2 (67) 16 r/w resetb 0 sw2mode3 (67) 17 r/w resetb 1 sw2mhmode 18 r/w offb 0 sw2 memory hold mode sw2uomode 19 r/w offb 0 sw2 user off mode sw2dvsspeed0 20 r/w resetb 1 sw2 dvs1 speed sw2dvsspeed1 21 r/w resetb 0 pllen 22 r/w resetb 1 pll enable pllx 23 r/w resetb 0 pll multiplication factor notes 67. swxmode[3:0] bits will be reset to their default values by the start-up sequencer, based on pums settings. an enabled switch will default to aps mode for both normal and standby operation. back to spi/i2c register map table 109. register 29, regulators 3, 4, and 5 operating mode name bit # r/w reset default description sw3mode0 0 r/w resetb 0 sw3 operating mode sw3mode1 1 r/w resetb 0 sw3mode2 2 r/w resetb 0 sw3mode3 3 r/w resetb 1 sw3mhmode 4 r/w offb 0 sw3 memory hold mode sw3uomode 5 r/w offb 0 sw3 user off mode sw4amode0 6 r/w resetb 0 sw4a operating mode sw4amode1 7 r/w resetb 0 sw4amode2 8 r/w resetb 0 sw4amode3 9 r/w resetb 1 sw4amhmode 10 r/w offb 0 sw4a memory hold mode sw4auomode 11 r/w offb 0 sw4a user off mode sw4bmode0 12 r/w resetb 0 sw4b operating mode sw4bmode1 13 r/w resetb 0 sw4bmode2 14 r/w resetb 0 sw4bmode3 15 r/w resetb 1 sw4bmhmode 16 r/w offb 0 sw4b memory hold mode table 108. register 28, regulators 1 & 2 operating mode name bit # r/w reset default description
analog integrated circuit device data ? 115 freescale semiconductor 34709 functional bloc k description sw4buomode 17 r/w offb 0 sw4b user off mode sw5mode0 (68) 18 r/w resetb 0 sw5 operating mode sw5mode1 (68) 19 r/w resetb 0 sw5mode2 (68) 20 r/w resetb 0 sw5mode3 (68) 21 r/w resetb 1 sw5mhmode 22 r/w offb 0 sw5 memory hold mode sw5uomode 23 r/w offb 0 sw5 user off mode notes 68. swxmode[3:0] bits will be reset to t heir default values by the start-up sequencer, based on pums settings. an enabled regula tor will default to aps mode for both normal and standby operation. back to spi/i2c register map table 110. register 30, regulator setting 0 name bit # r/w reset default description vgen10 0 r/wm resetb * vgen1 setting vgen11 1 r/wm resetb * vgen12 2 r/wm resetb * unused 3 r 0 not available vdac0 4 r/wm resetb * vdac setting vdac1 5 r/wm resetb * vgen20 6 r/wm resetb * vgen2 setting vgen21 7 r/wm resetb * vgen22 8 r/wm resetb * vpll0 9 r/wm resetb * vpll setting vpll1 10 r/wm resetb * vusb20 11 r/wm resetb * vusb2 setting vusb21 12 r/wm resetb * unused 13 -23 r 0 not available back to spi/i2c register map table 111. register 31, swbst control name bit # r/w reset default description swbst0 0 r/w none * swbst setting swbst1 1 r/w none * swbstmode0 2 r/w resetb 0 swbst mode swbstmode1 3 r/w resetb 1 spare 4 r/w resetb 0 not available swbststbymode0 5 r/w resetb 0 swbst standby mode swbststbymode1 6 r/w resetb 1 table 109. register 29, regulators 3, 4, and 5 operating mode
analog integrated circuit device data ? freescale semiconductor 116 34709 functional block description spare 7 r/w resetb 0 not available unused 8 - 23 r 0 not available back to spi/i2c register map table 112. register 32, regulator mode 0 name bit # r/w reset default description vgen1en 0 r/w none * vgen1 enable vgen1stby 1 r/w resetb 0 vgen1 controlled by standby unused 2 r 0 not available vusben 3 r/w resetb 1 vusb enable (pums4:1=[0100]). vdacen 4 r/w none * vdac enable vdacstby 5 r/w resetb 0 vdac controlled by standby vdacmode 6 r/w resetb 0 vdac operating mode unused 7 r 0 not available unused 8 r 0 not available unused 9 r 0 not available vrefddren 10 r/w none * vrefddr enable vgen2config 11 r/w none * pums5 tied to ground = 0: vgen2 with external pnp pums5 tied to vcroredig =1:vgen2 internal pmos vgen2en 12 r/w none * vgen2 enable vgen2stby 13 r/w resetb 0 vgen2 controlled by standby vgen2mode 14 r/w resetb 0 vgen2 operating mode vpllen 15 r/w none * vpll enable vpllstby 16 r/w resetb 0 vpll controlled by standby vusb2config 17 r/w none * pums5 tied to ground = 0: vusb2 with external pnp pums5 tied to vcroredig =1:vusb2 internal pmos vusb2en 18 r/w none * vusb2 enable vusb2stby 19 r/w resetb 0 vusb2 controlled by standby vusb2mode 20 r/w resetb 0 vusb2 operating mode unused 21 r 0 not available unused 22 r 0 not available unused 23 r 0 not available back to spi/i2c register map table 111. register 31, swbst control name bit # r/w reset default description
analog integrated circuit device data ? 117 freescale semiconductor 34709 functional bloc k description table 113. register 33, gpiolv0 control name bit # r/w reset default description dir 0 r/w resetb 0 gpiolv0 direction 0: input 1: output din 1 r/w resetb 0 input state of gpiolv0 pin 0: input low 1: input high dout 2 r/w resetb 0 output state of gpiolv0 pin 0: output low 1: output high hys 3 r/w resetb 1 hysteresis 0: cmos in 1: hysteresis dbnc0 4 r/w resetb 0 gpiolv0 input debounce time dbnc1 5 r/w resetb 0 00: no debounce 01: 10 ms debounce 10: 20 ms debounce 11: 30 ms debounce int0 6 r/w resetb 0 gpiolv0 interrupt control 00: none 01: falling edge 10: rising edge 11: both edges int1 7 r/w resetb 0 pke 8 r/w resetb 0 pad keep enable 0: off 1: on ode 9 r/w resetb 0 open-drain enable 0: cmos 1: od dse 10 r/w resetb 0 drive strength enable 0: 4.0 ma 1: 8.0 ma pue 11 r/w resetb 1 pull-up/down enable 0: pull-up/down off 1: pull-up/down on (default) pus0 12 r/w resetb 1 pull-up/pull-down select 00: 10 k pull-down 01: 100 k pull-down 10: 10 k pull-up 11: 100 k pull-up pus1 13 r/w resetb 1 (1.0 default 10)
analog integrated circuit device data ? freescale semiconductor 118 34709 functional block description sre0 14 r/w resetb 0 slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast sre1 15 r/w resetb 0 unused 16 - 23 r 0 not available back to spi/i2c register map table 114. register 34, gpiolv1 control name bit # r/w reset default description dir 0 r/w resetb 0 gpiolv1directon 0: input 1: output din 1 r/w resetb 0 input state of gpiolv1 pin 0: input low 1: input high dout 2 r/w resetb 0 output state of gpiolv1 pin 0: output low 1: output high hys 3 r/w resetb 1 hysteresis 0: cmos in 1: hysteresis dbnc0 4 r/w resetb 0 gpiolv1 input debounce time dbnc1 5 r/w resetb 0 00: no debounce 01: 10 ms debounce 10: 20 ms debounce 11: 30 ms debounce int0 6 r/w resetb 0 gpiolv1 interrupt control 00: none 01: falling edge 10: rising edge 11: both edges int1 7 r/w resetb 0 pke 8 r/w resetb 0 pad keep enable 0: off 1: on ode 9 r/w resetb 0 open-drain enable 0: cmos 1: od dse 10 r/w resetb 0 drive strength enable 0: 4.0 ma 1: 8.0 ma table 113. register 33, gpiolv0 control name bit # r/w reset default description
analog integrated circuit device data ? 119 freescale semiconductor 34709 functional bloc k description pue 11 r/w resetb 1 pull-up/down enable 0: pull-up/down off 1: pull-up/down on (default) pus0 12 r/w resetb 1 pull-up/pull-down select 00: 10 k pull-down 01: 100 k pull-down 10: 10 k pull-up 11: 100 k pull-up pus1 13 r/w resetb 1 (1.0 default 10) sre0 14 r/w resetb 0 slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast sre1 15 r/w resetb 0 unused 16 - 23 r 0 not available back to spi/i2c register map table 115. register 35, gpiolv2 control name bit # r/w reset default description dir 0 r/w resetb 0 gpiolv2 direction 0: input 1: output din 1 r/w resetb 0 input state of gpiolv2 pin 0: input low 1: input high dout 2 r/w resetb 0 output state of gpiolv2 pin 0: output low 1: output high hys 3 r/w resetb 1 hysteresis 0: cmos in 1: hysteresis dbnc0 4 r/w resetb 0 gpiolv2 input debounce time dbnc1 5 r/w resetb 0 00: no debounce 01: 10 ms debounce 10: 20 ms debounce 11: 30 ms debounce int0 6 r/w resetb 0 gpiolv2 interrupt control 00: none 01: falling edge 10: rising edge 11: both edges int1 7 r/w resetb 0 table 114. register 34, gpiolv1 control name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 120 34709 functional block description pke 8 r/w resetb 0 pad keep enable 0: off 1: on ode 9 r/w resetb 0 open-drain enable 0: cmos 1: od dse 10 r/w resetb 0 drive strength enable 0: 4.0 ma 1: 8.0 ma pue 11 r/w resetb 1 pull-up/down enable 0: pull-up/down off 1: pull-up/down on (default) pus0 12 r/w resetb 1 pull-up/pull-down select 00: 10 k pull-down 01: 100 k pull-down 10: 10 k pull-up 11: 100 k pull-up pus1 13 r/w resetb 1 (1.0 default = 10) sre0 14 r/w resetb 0 slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast sre1 15 r/w resetb 0 unused 16 - 23 r 0 not available back to spi/i2c register map table 116. register 36, gpiolv3 control name bit # r/w reset default description dir 0 r/w resetb 0 gpiolv3 direction 0: input 1: output din 1 r/w resetb 0 input state of gpiolv3 pin 0: input low 1: input high dout 2 r/w resetb 0 output state of gpiolv3 pin 0: output low 1: output high hys 3 r/w resetb 1 hysteresis 0: cmos in 1: hysteresis dbnc0 4 r/w resetb 0 gpiolv3 input debounce time table 115. register 35, gpiolv2 control name bit # r/w reset default description
analog integrated circuit device data ? 121 freescale semiconductor 34709 functional bloc k description dbnc1 5 r/w resetb 0 00: no debounce 01: 10 ms debounce 10: 20 ms debounce 11: 30 ms debounce int0 6 r/w resetb 0 gpiolv3 interrupt control 00: none 01: falling edge 10: rising edge 11: both edges int1 7 r/w resetb 0 pke 8 r/w resetb 0 pad keep enable 0: off 1: on ode 9 r/w resetb 0 open-drain enable 0: cmos 1: od dse 10 r/w resetb 0 drive strength enable 0: 4.0 ma 1: 8.0 ma pue 11 r/w resetb 1 pull-up/down enable 0: pull-up/down off 1: pull-up/down on (default) pus0 12 r/w resetb 1 pull-up/pull-down select 00: 10 k pull-down 01: 100 k pull-down 10: 10 k pull-up 11: 100 k pull-up (1.0 default = 10) pus1 13 r/w resetb 1 sre0 14 r/w resetb 0 slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast sre1 15 r/w resetb 0 unused 16 - 23 r 0 not available back to spi/i2c register map table 117. register 37 - 40, reserved name bit # r/w reset default description unused 0 - 23 r 0 not available table 118. register 41 - 42, unused name bit # r/w reset default description unused 0-23 r 0 not available table 116. register 36, gpiolv3 control name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 122 34709 functional block description table 119. register 43, adc 0 name bit # r/w reset default description aden 0 r/w digresetb 0 enables adc from the low-power mode adstart 1 r/w digresetb 0 request a start of the adc reading sequencer adcont 2 r/w digresetb 0 run adc reads continuously when high or one time when low. note that the tsstart request will have higher priority adhold 3 r/w digresetb 0 hold the adc reading sequencer while saved adc results are read from spi adstop0 4 r/w digresetb 0 channel selection to stop when complete. always start at 000 and read up to and including this channel value. adstop1 5 r/w digresetb 0 adstop2 6 r/w digresetb 0 spare 7 r/w digresetb 0 not available therm 8 r/w digresetb 0 0: ntcref not forced on 1: force ntcref on spare 9 r/w digresetb 0 not available spare 10 r/w digresetb 0 not available spare 11 r/w digresetb 0 not available tsen 12 r/w digresetb 0 enable the touch screen from low-power mode. tsstart 13 r/w digresetb 0 request a start of the adc reading sequencer for touch screen readings. tscont 14 r/w digresetb 0 run adc reads of touch screen conti nuously when high or one time when low. tshold 15 r/w digresetb 0 hold the adc reading sequencer while saved touch screen results are read from spi tsstop0 16 r/w digresetb 0 just like the adstop above, but for the touch screen read programming. this will allow independent code for adc sequence readings and touch screen adc sequence readings. tsstop1 17 r/w digresetb 0 tsstop2 18 r/w digresetb 0 spare 19 r/w digresetb 0 not available tspendet en 20 r/w digresetb 0 enable the touch screen pen detection. no te that tsen must be off for pen detection. spare 21 r/w digresetb 0 not available spare 22 r/w digresetb 0 not available spare 23 r/w digresetb 0 not available back to spi/i2c register map table 120. register 44, adc 1 name bit # r/w reset default description addly10 0 r/w digresetb 0 this will allow delay before the adc readings. addly11 1 r/w digresetb 0 addly12 2 r/w digresetb 0 addly13 3 r/w digresetb 0
analog integrated circuit device data ? 123 freescale semiconductor 34709 functional bloc k description addly20 4 r/w digresetb 0 this will allow delay between each of adc readings in a set. addly21 5 r/w digresetb 0 addly22 6 r/w digresetb 0 addly23 7 r/w digresetb 0 addly30 8 r/w digresetb 0 this will allow delay after the set of adc readings. this delay is only valid between subsequent wrap around reading sequences with adcont addly31 9 r/w digresetb 0 addly32 10 r/w digresetb 0 addly33 11 r/w digresetb 0 tsdly10 12 r/w digresetb 0 this will allow delay before the adc touch screen readings. this is like the addly1, but allows independent programming of touc h screen readings from general purpose adc readings to prevent code replacement in the system. tsdly11 13 r/w digresetb 0 tsdly12 14 r/w digresetb 0 tsdly13 15 r/w digresetb 0 tsdly20 16 r/w digresetb 0 this will allow delay between each of adc touc h screen readings in a set. this is like the addly2, but allows independent programming of touch screen readings from general purpose adc readings to prevent code replacement in the system. tsdly21 17 r/w digresetb 0 tsdly21 18 r/w digresetb 0 tsdly23 19 r/w digresetb 0 tsdly30 20 r/w digresetb 0 this will allow delay after the set of ad c touch screen readings. this delay is only valid between subsequent wrap around reading sequences with tscont mode. this is like the addly3, but allows independent programming of touch screen readings from general purpose adc readings to prevent code replacement in the system. tsdly31 21 r/w digresetb 0 tsdly31 22 r/w digresetb 0 tsdly33 23 r/w digresetb 0 back to spi/i2c register map table 121. register 45, adc 2 name bit # r/w reset default description adsel00 0 r/w digresetb 0 channel selection to place in adresult0 adsel01 1 r/w digresetb 0 adsel02 2 r/w digresetb 0 adsel03 3 r/w digresetb 0 adsel10 4 r/w digresetb 0 channel selection to place in adresult1 adsel11 5 r/w digresetb 0 adsel12 6 r/w digresetb 0 adsel13 7 r/w digresetb 0 adsel20 8 r/w digresetb 0 channel selection to place in adresult2 adsel21 9 r/w digresetb 0 adsel22 10 r/w digresetb 0 adsel23 11 r/w digresetb 0 table 120. register 44, adc 1 name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 124 34709 functional block description adsel30 12 r/w digresetb 0 channel selection to place in adresult3 adsel31 13 r/w digresetb 0 adsel32 14 r/w digresetb 0 adsel33 15 r/w digresetb 0 adsel40 16 r/w digresetb 0 channel selection to place in adresult4 adsel41 17 r/w digresetb 0 adsel42 18 r/w digresetb 0 adsel43 19 r/w digresetb 0 adsel50 20 r/w digresetb 0 channel selection to place in adresult5 adsel51 21 r/w digresetb 0 adsel52 22 r/w digresetb 0 adsel53 23 r/w digresetb 0 back to spi/i2c register map table 122. register 46, adc 3 name bit # r/w reset default description adsel60 0 r/w digresetb 0 channel selection to place in adresult6 adsel61 1 r/w digresetb 0 adsel62 2 r/w digresetb 0 adsel63 3 r/w digresetb 0 adsel70 4 r/w digresetb 0 channel selection to place in adresult7 adsel71 5 r/w digresetb 0 adsel72 6 r/w digresetb 0 adsel73 7 r/w digresetb 0 tssel00 8 r/w digresetb 0 touch screen selection to place in adresult0. select the action for the touch screen; 00 = dummy to discharge tsref capacitance, 01 = to read x-plate, 10 = to read y-plate, and 11 = to read contact. tssel01 9 r/w digresetb 0 tssel10 10 r/w digresetb 0 touch screen selection to place in adresult1. see tssel0 for modes. tssel11 11 r/w digresetb 0 tssel20 12 r/w digresetb 0 touch screen selection to place in adresult2. see tssel0 for modes. tssel21 13 r/w digresetb 0 tssel30 14 r/w digresetb 0 touch screen selection to place in adresult3. see tssel0 for modes. tssel31 15 r/w digresetb 0 tssel40 16 r/w digresetb 0 touch screen selection to place in adresult4. see tssel0 for modes. tssel41 17 r/w digresetb 0 tssel50 18 r/w digresetb 0 touch screen selection to place in adresult5. see tssel0 for modes. tssel51 19 r/w digresetb 0 tssel60 20 r/w digresetb 0 touch screen selection to place in adresult6. see tssel0 for modes. tssel61 21 r/w digresetb 0 table 121. register 45, adc 2 name bit # r/w reset default description
analog integrated circuit device data ? 125 freescale semiconductor 34709 functional bloc k description tssel70 22 r/w digresetb 0 touch screen selection to place in adresult7. see tssel0 for modes. tssel71 23 r/w digresetb 0 back to spi/i2c register map table 123. register 47, adc 4 name bit # r/w reset default description unused 0 r 0 not available unused 1 r 0 adresult00 2 r digresetb 0 adc result for adsel0 adresult01 3 r digresetb 0 adresult02 4 r digresetb 0 adresult03 5 r digresetb 0 adresult04 6 r digresetb 0 adresult05 7 r digresetb 0 adresult06 8 r digresetb 0 adresult07 9 r digresetb 0 adresult08 10 r digresetb 0 adresult09 11 r digresetb 0 unused 12 r 0 not available unused 13 r 0 adresult10 14 r digresetb 0 adc result for adsel1 adresult11 15 r digresetb 0 adresult12 16 r digresetb 0 adresult13 17 r digresetb 0 adresult14 18 r digresetb 0 adresult15 19 r digresetb 0 adresult16 20 r digresetb 0 adresult17 21 r digresetb 0 adresult18 22 r digresetb 0 adresult19 23 r digresetb 0 back to spi/i2c register map table 122. register 46, adc 3 name bit # r/w reset default description
analog integrated circuit device data ? freescale semiconductor 126 34709 functional block description table 124. register 48, adc5 name bit # r/w reset default description unused 0 r 0 not available unused 1 r 0 adresult20 2 r digresetb 0 adc result for adsel2 adresult21 3 r digresetb 0 adresult22 4 r digresetb 0 adresult23 5 r digresetb 0 adresult24 6 r digresetb 0 adresult25 7 r digresetb 0 adresult26 8 r digresetb 0 adresult27 9 r digresetb 0 adresult28 10 r digresetb 0 adresult29 11 r digresetb 0 unused 12 r 0 not available unused 13 r 0 adresult30 14 r digresetb 0 adc result for adsel3 adresult31 15 r digresetb 0 adresult32 16 r digresetb 0 adresult33 17 r digresetb 0 adresult34 18 r digresetb 0 adresult35 19 r digresetb 0 adresult36 20 r digresetb 0 adresult37 21 r digresetb 0 adresult38 22 r digresetb 0 adresult39 23 r digresetb 0 back to spi/i2c register map
analog integrated circuit device data ? 127 freescale semiconductor 34709 functional bloc k description table 125. register 49, adc6 name bit # r/w reset default description unused 0 r 0 not available unused 1 r 0 adresult40 2 r digresetb 0 adc result for adsel4 adresult41 3 r digresetb 0 adresult42 4 r digresetb 0 adresult43 5 r digresetb 0 adresult44 6 r digresetb 0 adresult45 7 r digresetb 0 adresult46 8 r digresetb 0 adresult47 9 r digresetb 0 adresult48 10 r digresetb 0 adresult49 11 r digresetb 0 unused 12 r 0 not available unused 13 r 0 adresult50 14 r digresetb 0 adc result for adsel5 adresult51 15 r digresetb 0 adresult52 16 r digresetb 0 adresult53 17 r digresetb 0 adresult54 18 r digresetb 0 adresult55 19 r digresetb 0 adresult56 20 r digresetb 0 adresult57 21 r digresetb 0 adresult58 22 r digresetb 0 adresult59 23 r digresetb 0 back to spi/i2c register map
analog integrated circuit device data ? freescale semiconductor 128 34709 functional block description table 126. register 50, adc7 name bit # r/w reset default description unused 0 r 0 not available unused 1 r 0 adresult60 2 r digresetb 0 adc result for adsel6 adresult61 3 r digresetb 0 adresult62 4 r digresetb 0 adresult63 5 r digresetb 0 adresult64 6 r digresetb 0 adresult65 7 r digresetb 0 adresult66 8 r digresetb 0 adresult67 9 r digresetb 0 adresult68 10 r digresetb 0 adresult69 11 r digresetb 0 unused 12 r 0 not available unused 13 r 0 adresult70 14 r digresetb 0 adc result for adsel7 adresult71 15 r digresetb 0 adresult72 16 r digresetb 0 adresult73 17 r digresetb 0 adresult74 18 r digresetb 0 adresult75 19 r digresetb 0 adresult76 20 r digresetb 0 adresult77 21 r digresetb 0 adresult78 22 r digresetb 0 adresult79 23 r digresetb 0 back to spi/i2c register map table 127. register 51, reserved name bit # r/w reset default description unused 0 - 23 r 0 not available table 128. register 52, supply debounce name bit # r/w reset default description reserved 0 r - - for future use reserved 1 r - - for future use vbattdb0 2 r/w resetb 1 low input warning (bp) debounce vbattdb1 3 r/w resetb 1 reserved 4 - 23 r - - for future use back to spi/i2c register map
analog integrated circuit device data ? 129 freescale semiconductor 34709 functional bloc k description table 129. register 53 - 54, reserved name bit # r/w reset default description unused 0 - 23 r 0 not available table 130. register 55, pwm control name bit # r/w reset default description pwm1duty0 0 r/w resetb 0 pwm1 duty cycle pwm1duty1 1 r/w resetb 0 pwm1duty2 2 r/w resetb 0 pwm1duty3 3 r/w resetb 0 pwm1duty4 4 r/w resetb 0 pwm1duty5 5 r/w resetb 0 pwmclkdiv0 6 r/w resetb 0 pwm1 clock divide setting pwm1clkdiv1 7 r/w resetb 0 pwm1clkdiv2 8 r/w resetb 0 pwm1clkdiv3 9 r/w resetb 0 pwm1clkdiv4 10 r/w resetb 0 pwm1clkdiv5 11 r/w resetb 0 pwm2duty0 12 r/w resetb 0 pwm2 duty cycle pwm2duty1 13 r/w resetb 0 pwm2duty2 14 r/w resetb 0 pwm2duty3 15 r/w resetb 0 pwm2duty4 16 r/w resetb 0 pwm2duty5 17 r/w resetb 0 pwm2clkdiv0 18 r/w resetb 0 pwm2 clock divide setting pwm2clkdiv1 19 r/w resetb 0 pwm2clkdiv2 20 r/w resetb 0 pwm2clkdiv3 21 r/w resetb 0 pwm2clkdiv4 22 r/w resetb 0 pwm2clkdiv5 23 r/w resetb 0 back to spi/i2c register map table 131. register 56 - 63, unused name bit # r/w reset default description unused 0-23 r 0 not available
analog integrated circuit device data ? freescale semiconductor 130 34709 typical applications 8 typical applications figure 24 gives a typical application diagram of the 34709 pmic together with its functional components. for details on component references and additional components such as filters, refer to the individual sections. 8.1 application diagram figure 24. typical application schematic bp resetb resetbmcu wdi switchers gndadc adin11 mux 10 bit gp adc int clk32k xtal1 xtal2 gndrtc licell gpio control gpiolv1 gpiolv2 rtc + calibration gndsw2 sw2fb sw2lx sw1in sw2in o/p drive ` gndsw1a sw1fb sw3in o/p drive gndsw3 sw3fb sw3lx gndswbst swbstfb swbstin swbstlx o/p drive pwron1 pums1 monitor timer o/p drive pll 32 khz crystal osc standby gpiolv3 lcell switch enables & control spi result registers interrupt inputs gndctrl core control logic, timers, & interrupts 32 khz internal osc gpiolv4 adin10 clk32kmcu gndreg1 gndreg2 adin9 a/d result a/d control ictest 32 khz buffers output pin input pin bi-directional pin package pin legend spi interface + muxed i2c optional interface cs clk gndspi miso spi registers mosi shift register shift register spivcc to enables & control to trimmed circuits spi control logic trim-in-package startup sequencer decode trim? pumsx control logic li cell charger sw2 lp 1000 ma buck sw3 int mem 500 ma buck swbst 380 ma boost mc34709 sw4 dual phase ddr 1000 ma buck vsrtc vsrtc vinrefddr vpll vpll 50 ma pass fet vrefddr 10ma vrefddr vinusb vusb best of supply licell bp reference generation vcoredig gndcore vcore vcoreref vusb regulator subsana1 subspwr1 subsref subsgnd subspwr2 subsana3 subsana2 subsldo vinpll pums2 pwron2 glbrst sw5in o/p drive gndsw5 sw5fb sw5lx sw5 i/o 1000 ma buck vusb2 350ma vdacdrv vdac vusb2 vusb2drv vdac 250ma sw1alx dvs control sw1pwgd sw2pwgd pwm outputs pwm1 pwm2 gndsw1b o/p drive sw1blx sw4ain gndsw4a sw4fba o/p drive sw4alx sw4bin gndsw4b sw4bfb o/p drive sw4blx gndusb sw4cfg vddlp vgen1 250ma vgen2drv vgen2 vgen2 250ma pass fet vgen1 pass fet vingen1 pums3 pums4 sdwnb digital core bp sw1 dual phase gp 2000 ma buck sw1cfg sw1vsssns vhalf pums5 gpiovdd gndgpio gndref1 gndref2 gndref ldovdd pass fet 100n coin cell battery 2.2u swbst 100pf 1u 1u spi sw5 general purpose adc inputs: i.e., pa thermistor, light sensor, etc. 100n 10u bp 10u swbst output (boost) 2.2u 4.7u bp sw4b 1u bp 2.2u 1.0u 2 x22u sw1 output bp 4.7u bp 4.7u 1.0u 22u sw2 output to ap bp 4.7u 1.0u 10u sw3 output 1.0u 10u sw4a output bp 4.7u 4.7u 1.0u 10u sw4b output 1.0u 22u sw5 output bp 4.7u to ap 2.2u bp 2.2u bp sw5 2.2u bp 2.2u vcoredig bp 100n bp to ap to peripherals to gnd, or vcoredig to/from ap on/off button wakeup from ap reset button 32.768 khz crystal 18p sw5 or sw3 0.1u 100k 100k 100k 100k 100k adin14/tsy1 adin15/tsy2 adin13/tsx2 tsref touch screen interface adin12/tsx1 touch screen interface 2.2u 100n c1 c34 c33 c32 c31 c30 c29 c28 c2 l1a c3/c4 r18 c5 l2 c6 r19 c7 l3 c8 c9 l4a c10 c13 c12 l4b c14 l5 l6 c15 d7 c16 c17 c18 c19 c20 c21 q1 q2 c22 c23 q3 c24 c25 c27 r20 r4 c26 18p y1 r3 c11 d1 d2 d3 d4 d5 d6 main input supply - bp
analog integrated circuit device data ? 131 freescale semiconductor 34709 typical applications 8.2 bill of material table 132 provides a complete list of the reco mmended components on a full featured system using the 34709 device. critical components such as inductors, transistors, and diodes ar e provided with a recommended part number, but equivalent components may be used. table 132. 34709 bill of material (69) item reference quantity description vendor comments 1 u1 1 34709 freescale pmic battery/supply input 2 c1 1 10 ? f tdk battery filter miscellaneous 3 c25 1 100 nf vsrtc 4 c33 1 1.0 ? f vcore 5 c32 1 1.0 ? f vcoredig 6 c31 1 100 pf vddlp 7 c30 1 100 nf vcoreref 8 c34 1 2.2 ? f tsref 9 c28 1 100 nf coin cell 10 y1 1 crystal 32.768 khz cc7 oscillator 11 c26, c27 2 18 pf oscillator load capacitors 12 r3, r4 2 100 k resetb, resetbmcu pull-ups 13 r20 1 100 k sdwnb pull-up boost 14 l6 1 2.2 ? h lps3015-222ml coilcraft boost inductor 15 d7 1 diode bas52 infineon boost diode 16 c16 1 10 ? f 16 v boost output capacitor 17 c15 1 4.7 ? f boost input capacitor sw1 18 l1a, l1b 2 1.0 ? h vls201612et-1r0n tdk buck 1 inductor (i max < 1.6 amps) alternate part numbers: ?1.0 ? h vls252010et-1r0n (tdk) ?1.0 ? h brl3225t1rom (taiyo yuden) ? 1.0 uh lps4012-102nl (coilcraft) 19 c3, c4 2 22 ? f buck 1 output capacitor 20 c2 1 4.7 ? f buck 1 input capacitor 21 d1 1 diode bas3010-03lrh infineon sw1lx diode
analog integrated circuit device data ? freescale semiconductor 132 34709 typical applications sw2 22 l2 1 1.0 ? h vls252010et-1r0n tdk buck 2 inductor 23 c6 1 22 ? f buck 2 output capacitor 24 c5 1 4.7 ? f buck 2 input capacitor 25 d2 1 diode bas3010-03lrh infineon sw2lx diode sw3 26 l3 1 1.0 ? h vls201612et-1r0n tdk buck 3 inductor 27 c8 1 10 ? f buck 3 output capacitor 28 c7 1 4.7 ? f buck 3 input capacitor 29 d3 1 diode bas3010-03lrh infineon sw3lx diode sw4a 30 l4a 1 1.0 ? h vls201612et-1r0n tdk buck 4a inductor alternate part number: 1.0 ? h vls252010et-1r0n (tdk) 31 c10 1 10 ? f buck 4a output capacitor 32 c9 1 4.7 ? f buck 4a input capacitor 33 d4 1 diode bas3010-03lrh infineon sw4alx diode sw4b 34 l4b 1 1.0 ? h vls201612et-1r0n tdk buck 4b inductor alternate part numbers: 1.0 ? h vls252010et-1r0n (tdk) 35 c12 1 10 ? f buck 4b output capacitor 36 c11 1 4.7 ? f buck 4b input capacitor 37 d5 1 diode bas3010-03lrh infineon sw4blx diode sw5 38 l5 1 1.0 ? h vls252010et-1r0n tdk buck 5 inductor 39 c14 1 22 ? f buck 5 output capacitor 40 c13 1 4.7 ? f buck 5 input capacitor 41 d6 1 diode bas3010-03lrh infineon sw5lx diode vpll 42 c20 1 2.2 ? f vpll output capacitor vrefddr 43 c18 1 100 nf vhalf 0.1 uf caps 44 c19 1 1.0 ? f vrefddr output capacitor 45 c17 1 100 nf vrefddr input capacitor table 132. 34709 bill of material (69) item reference quantity description vendor comments
analog integrated circuit device data ? 133 freescale semiconductor 34709 typical applications 8.3 34709 layout guidelines 8.3.1 general board recommendations 1. it is recommended to use an 4 layer board stack-up arranged as follows: ? high-current signal ?gnd ?signal ? high-current signal 2. allocate top and bottom pcb layers for power rout ing (high-current signals), copper-pour the unused area. 3. add one gnd inner layer to reduce current loops to the maximum between layers. 8.3.2 general routing requirements 1. some recommended things to keep in mind for manufacturability: ? via in pads require a 4.5 mil minimum annular ring. pad must be 9.0 mils larger than the hole ? max copper thickness for lines less than 5.0 mils wide is 0.6 oz copper ? minimum allowed spacing between line and hole pad is 3.5 mils ? minimum allowed spacing between line and line is 3.0 mils 2. care must be taken with swxfb pins traces. these signals are susceptible to noise and must be routed far away from power, clock, or high-power signals, like the ones on the swxin, swx, swxlx, swbstin, swbst, and swbstlx pins. vdac 46 q2 1 pnp nss12100uw3tcg pnp nss12100xv6t1g on semi vdac pnp - 500 w dissipation vdac pnp - 250 w dissipation - alternate 47 c22 1 2.2 ? f vdac output capacitor vusb2 48 q1 1 pnp nss12100uw3tcg pnp nss12100xv6t1g on semi vusb2 pnp - 500 w dissipation vusb2 pnp - 250 w dissipation - alternate 49 c21 1 2.2 ? f vusb2 output capacitor vusb 50 c29 1 2.2 ? f vusb output capacitor vgen1 51 c23 1 2.2 ? f vgen1 output capacitor vgen2 52 q3 1 pnp nss12100uw3tcg pnp nss12100xv6t1g on semi vgen2 pnp - 500 w dissipation vgen2 pnp - 250 w dissipation - alternate 53 c24 1 2.2 ? f vgen2 output capacitor notes 69. freescale does not assume liability, endorse, or warrant components from exte rnal manufacturers that are referenced in circu it drawings or tables. while freescale offers component recommendations in this configur ation, it is the customer?s responsibility to validate their application. table 132. 34709 bill of material (69) item reference quantity description vendor comments
analog integrated circuit device data ? freescale semiconductor 134 34709 typical applications 3. shield feedback traces of the switching regulators and keep them as short as possible (trace them on the bottom so the ground and power planes shield these traces). 4. avoid coupling trace between important signal/low noise supplies (like vrefcore, vcore, vcoredig) from any switching node (i.e. sw1alxx, sw2lx, sw3lx , sw4alx, sw4blx, sw5lx, and swbstlx). 5. make sure that all components related to an specific block are referenced to the corresponding ground, e.g. all components related to the sw1 converter must referenced to gndsw1a1 and gndsw1a2. 8.3.3 parallel routing requirements 1. spi/i 2 c signal routing: ? clk is the fastest signal of the system, so it must be given special care. here are some tips for routing the communication signals: ? to avoid contamination of these delicate signals by nearby high-power or high-frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. make sure the ground plane is uniform throughout the whole signal trace length. figure 25. recommended shielding for critical signals. ? these signals can be placed on an outer layer of the board to reduce their capacitance in respect to the ground plane. ? the crystal connected to the xtal1 and xtal2 pins must not have a ground plane directly below. ? the following are clock signals: clk, clk32k, clk32kmcu, xtal1, and xtal2. these signals must not run parallel to each other, or in the same routing layer. if it is necessary to run clock signals parallel to each other, or parallel to any ot her signal, then follow a max parallel rule as follows: ? up to one inch parallel length ? 25 mil minimum separation ? up to two inches parallel length ? 50 mil minimum separation ? up to three inches parallel length ? 100 mil minimum separation ? up to four inches parallel length ? 250 mil minimum separation ? care must be taken with these signals not to contaminate analog signals, as they are high-frequency signals. another good practice is to trace them perpendicularly on different layers , so there is a minimum area of proximity between signals. 8.3.4 switching regulator layout recommendations 1. per design, the 34709 is designed to operate with only one input bulk capacitor. however, it is recommended to add a high-frequency filter input capacitor (cin_hf), to filter out any noise at the regulator input. this capacitor should be in the range of 100 nf and should be placed right next to or under the ic, closest to the ic pins. 2. make high-current ripple traces low inductance (short, high w/l ratio). 3. make high-current traces wide or copper islands. 4. make high-current traces symetrical for dual?phase regul ators (sw1, sw4).
analog integrated circuit device data ? 135 freescale semiconductor 34709 typical applications figure 26. generic buck regulator architecture figure 27. recommended layout for switching regulators. 8.4 thermal considerations 8.4.1 rating data the thermal rating data of the packages has been simulated with the results listed in table 5 . junction to ambient thermal resistance nomenclatu re: the jedec specification reserves the symbol r ja or ja (theta-ja) strictly for junction-to-ambient thermal resistance on a 1s test board in natural convection environment. r jma or jma ? (theta-jma) will be used for both junction-t o-ambient on a 2s2p test board in natural convection and for ju nction-to-ambient wi th diver controller swxvin swxlx swxfb c out c in l gndswx swx v bp compensation c in_hf d
analog integrated circuit device data ? freescale semiconductor 136 34709 typical applications forced convection on both 1s and 2s2p test boards. it is antici pated that the generic name, theta-ja, will continue to be commo nly used. the jedec standards can be consulted at http://www.jedec.org/ 8.4.2 estimation of junction temperature an estimation of the chip junction temperature tj can be obtained from the equation t j = t a + (r ja x p d ) with t a = ambient temperature for the package in c r ? ja = junction to ambient thermal resistance in c/w p d = power dissipation in the package in w the junction to ambient thermal resistance is an industry standa rd value that provides a quick and easy estimation of thermal performance. unfortunately, there are two values in comm on usage: the value determined on a single layer board r ja and the value obtained on a four layer board r jma . actual application pcbs show a performance close to the simulated four layer board value although this may be somewhat degraded in case of sign ificant power dissipated by other components placed close to the device. at a known board temperature, the junction temperature t j is estimated using the following equation t j = t b + (r jb x p d ) with t b = board temperature at the package perimeter in c r jb = junction to board thermal resistance in c/w p d = power dissipation in the package in w when the heat loss from the package case to the air can be i gnored, acceptable predictions of junction temperature can be made. see functional block description for more details on thermal management.
analog integrated circuit device data ? 137 freescale semiconductor 34709 packaging 9 packaging the 34709 is offered in an 130 balls, 8.0x8.0 mm, 0.5 mm pitch mapbga package. 9.1 package mechanical dimensions package dimensions are provided in package drawings. to find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing?s document number. dimensions shown are provided for referenc e only (for layout and design, refer to the package outline drawing listed in the following figures). table 133. package drawing information package suffix package outline drawing number 130-pin mapbga (8 x 8), 0.5 mm vk 98asa00333d
analog integrated circuit device data ? freescale semiconductor 138 34709 packaging figure 28. 8 x 8 package mechanical dimension vk suffix 130-pin 98asa00333d revision 0
analog integrated circuit device data ? 139 freescale semiconductor 34709 packaging figure 29. 8 x 8 package mechanical dimension vk suffix 130-pin 98asa00333d revision 0
analog integrated circuit device data ? freescale semiconductor 140 34709 reference section 10 reference section table 134. mc34709 reference documents reference description 34709fs freescale fact sheet 34709er freescale errata
analog integrated circuit device data ? 141 freescale semiconductor 34709 revision history 11 revision history revision date description of changes 1.0 8/2012 ? initial release ? corrected doc number to mc34709, corrected part number pc34709vk ? removed freescale confidential proprietary on page 1
document number: mc34709 rev. 1.0 8/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fa bricate any integrat ed circuits on the information in this document. freescale reserves the right to make chang es without further not ice to any products herein. freescale makes no warranty, re presentation, or guarantee regarding the suitability of its products fo r any particular purpose, nor does freescale assume any liability arising out of the application or us e of any product or circ uit, and specifically disclaims any and all liability, including wi thout limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in differ ent applications, and ac tual performance may vary over time. all operating parameters, in cluding ?typicals,? must be validated for each customer application by customer?s te chnical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservice s/freescale/docs/ter msandconditions.htm freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, mobilegt, powerquicc, qoriq, qorivva, starcore, and symphony are trademarks of freescale semico nductor, inc., reg. u.s. pat. & tm. off. ? airfast, beekit, beestack, co ldfire+, corenet, flexis, ma gniv, mxc, platform in a package, processor expert, qoriq qonv erge, quicc engine, ready play, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

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