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W9961CF h.263/h.261 video codec - 1 - W9961CF h.263/h.261 video codec version 1.0 april, 1999
W9961CF - 2 - copyright by winbond electronics corp., all rights reserved. the information in this document has been carefully checked and is believed to be correct as of the date of publication. winbond electronics corp. reserves the right to make changes in the product or specification, or both, presented in this publication at any time without notice. winbond assumes no responsibility or liability arising from the specification listed herein. winbond makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patents, trademark, copyright, or rights of third parties. no license is granted by implication or other under any patent or patent rights of winbond electronics corp. all other trademarks and registered trademarks are the property of their respective holders.
W9961CF - 3 - t a b l e o f c o n t e n t s 1 general description ..................................................................................................................... 7 2 features ............................................................................................................................... ................ 8 3 pin configuration ........................................................................................................................ 10 4 pin description ............................................................................................................................... 11 4.1 p in d efinition ............................................................................................................................... ......... 11 4.2 p in l ist ............................................................................................................................... .................... 17 4.3 p ower o n r eset i nitialization ............................................................................................................. 22 5 system diagram ............................................................................................................................. 24 6 block diagram ............................................................................................................................... 26 7 functional description ............................................................................................................ 27 7.1 vpre p rocessor ............................................................................................................................... ..... 27 7.2 v ideo c odec ............................................................................................................................... ............ 28 7.2.1 video coding ............................................................................................................ ........................ 28 7.2.1.1 i-pictures intra coding .............................................................................................................................28 7.2.1.2 p-pictures inter coding ............................................................................................................................29 7.2.1.3 p-pictures intra coding ............................................................................................................................29 7.2.2 video decoding .......................................................................................................... ...................... 29 7.3 vpost p rocessor ............................................................................................................................... .. 30 7.3.1 video post-processing ....................................................................................................................... 30 7.3.2 display control ......................................................................................................... ....................... 31 7.3.3 video output control ........................................................................................................................ 31 7.3.3.1 hue, saturation, contrast, and brightness adjustments ................................................................................31 7.3.3.2 video output interface ............................................................................................................................... ..32 7.4 risc m icroprocessor ........................................................................................................................... 35 7.4.1 risc pipeline stages .................................................................................................... .................... 35 7.4.2 address spaces ............................................................................................................................... .. 36 7.4.2.1 program memory address space ..................................................................................................................36 7.4.2.2 data memory address space .......................................................................................................................36 7.4.3 risc registers.......................................................................................................... ........................ 38 7.4.3.1 general registers ..................................................................................................... ...................................38 7.4.3.2 shadow registers ............................................................................................................................... .........38 7.4.4 risc interrupt handling ................................................................................................................... 39 7.5 intc (i nterrupt c ontroller ).............................................................................................................. 41 7.6 t imer ............................................................................................................................... ....................... 43 7.7 fdma c ontroller ............................................................................................................................... .44 7.7.1 fdma transfer modes ..................................................................................................................... 45 7.7.2 fdma transfer types ....................................................................................................................... 45
W9961CF - 4 - 7.7.3 fdma programming ........................................................................................................................ 45 7.8 h ost i nterface c ontroller ................................................................................................................. 48 7.8.1 pci address spaces .......................................................................................................................... 48 7.8.2 pci interrupt control ....................................................................................................................... 48 7.9 dram c ontroller ............................................................................................................................... 50 7.9.1 video memory arbitration ................................................................................................................ 50 7.9.2 dram interface.......................................................................................................... ...................... 51 7.10 isa- like b us i nterface and gpio s ..................................................................................................... 52 7.10.1 isa-like bus interface ................................................................................................. .................... 52 7.10.2 gpio ............................................................................................................................... ............... 52 7.11 pll (p hase l ocked l oop ).................................................................................................................... 53 8 electrical characteristics .................................................................................................. 54 8.1 a bsolute m aximum r atings ................................................................................................................. 54 8.2 dc c haracteristics .............................................................................................................................. 5 4 8.2.1 dac dc characteristics ................................................................................................................... 54 8.2.2 digital dc characteristics .............................................................................................. ................. 58 8.3 ac c haracteristics .............................................................................................................................. 5 9 8.3.1 dac ac characteristics .................................................................................................. ................. 59 8.3.2 pll ac characteristics .................................................................................................................... 59 8.3.3 reset timing ac characteristics......................................................................................... ........... 60 8.3.4 clock ac characteristics................................................................................................ .................. 60 8.3.5 input timing ac characteristics......................................................................................... .............. 61 8.3.6 output timing ac characteristics .................................................................................................... 62 9 package spec. ............................................................................................................................... ... 64 10 ordering information ............................................................................................................. 65
W9961CF - 5 - l i s t o f f i g u r e s f igure 3.1 W9961CF p in c onfiguration .................................................................................................... 10 f igure 5.1 W9961CF-b ased s tand - alone v ideophone s ystem d iagram ................................................. 24 f igure 6.1 W9961CF b lock d iagram ......................................................................................................... 26 f igure 7.1 vpre p rocessor b lock d iagram ............................................................................................. 27 f igure 7.2 v ideo c odec b lock d iagram .................................................................................................... 28 f igure 7.3 vpost p rocessor b lock d iagram ........................................................................................... 30 f igure 7.4 t ypical t hree - window d isplay for v ideo c onferencing a pplications ................................ 31 f igure 7.5 h ue , s aturation , c ontrast , and b rightness c ontrols ........................................................ 32 f igure 7.6 risc m icroprocessor b lock d iagram .................................................................................... 35 f igure 7.7 p rogram m emory a ddress s pace ............................................................................................. 37 f igure 7.8 d ata m emory a ddress s pace ................................................................................................... 37 f igure 7.9 risc g eneral r egisters ........................................................................................................... 38 f igure 7.10 intc b lock d iagram .............................................................................................................. 41 f igure 7.11 t imer b lock d iagram .............................................................................................................. 43 f igure 7.12 fdma c ontroller b lock d iagram ....................................................................................... 44 f igure 7.13 b lock t ransfer m ode with b lock a ddressing ..................................................................... 46 f igure 7.14 d emand t ransfer m ode with l inear a ddressing ................................................................. 47 f igure 7.15 h ost i nterface c ontroller b lock d iagram ........................................................................ 48 f igure 7.16 dram c ontroller b lock d iagram ....................................................................................... 50 f igure 7.17 pll b lock d iagram ................................................................................................................. 53 f igure 8.1 525- line (ntsc/pal-m) y (l uminance ) o utput w aveform ................................................... 55 f igure 8.2 625- line (pal-b, d, g, h, n) y (l uminance ) o utput w aveform ............................................ 55 f igure 8.3 525- line (ntsc/pal-m) c (c hrominance ) o utput w aveform .............................................. 56 f igure 8.4 625- line (pal-b, d, g, h, n) c (c hrominance ) o utput w aveform ....................................... 56 f igure 8.5 525- line (ntsc/pal-m) c omposite v ideo o utput w aveform ............................................... 57 f igure 8.6 625- line (pal-b, d, g, h, n) c omposite v ideo o utput w aveform ........................................ 57 f igure 8.7 reset t iming ............................................................................................................................ 60 f igure 8.8 c lock w aveform ....................................................................................................................... 60 f igure 8.9 i nput t iming ............................................................................................................................... 61 f igure 8.10 o utput t iming .......................................................................................................................... 62 f igure 9.1 208l qfp (28x28 mm footprint 2.6 mm ) d imensions ................................................................ 64
W9961CF - 6 - l i s t o f t a b l e s t able 4.1 W9961CF p in l ist ........................................................................................................................ 17 t able 4.2 W9961CF p ower o n r eset d efinitions ..................................................................................... 22 t able 7.1 W9961CF v ideo o utput m odes ................................................................................................. 32 t able 7.2 W9961CF v ideo o utput i nterface p in a ssignment ................................................................. 34 t able 7.3 d ata m emory a ddress m apping ................................................................................................ 37 t able 7.4 risc i nterrupt v ectors ............................................................................................................ 39 t able 7.5 i nterrupt c hannels ................................................................................................................... 41 t able 7.6 fdma c hannels ......................................................................................................................... 44 t able 7.7 pci i nterrupt c hannels ............................................................................................................ 48 t able 7.8 sdram and edo dram i nterface s ignals ............................................................................ 51 t able 7.9 isa- like b us a ccess m odes ........................................................................................................ 52 t able 8.1 a bsolute m aximum r atings ....................................................................................................... 54 t able 8.2 dac dc c haracteristics ........................................................................................................... 54 t able 8.3 d igital dc c haracteristics ....................................................................................................... 58 t able 8.4 dac ac c haracteristics ........................................................................................................... 59 t able 8.5 tv m odes r esolution and c lock r ate ..................................................................................... 59 t able 8.6 pll ac c haracteristics ............................................................................................................ 59 t able 8.7 reset t iming .............................................................................................................................. 6 0 t able 8.8 c lock ac c haracteristics ......................................................................................................... 60 t able 8.9 pciclk-r eferenced i nput t iming ac c haracteristics ........................................................... 61 t able 8.10 smclk-r eferenced i nput t iming ac c haracteristics .......................................................... 61 t able 8.11 viclk-r eferenced i nput t iming ac c haracteristics ........................................................... 62 t able 8.12 pciclk-r eferenced o utput t iming ac c haracteristics ...................................................... 62 t able 8.13 smclk-r eferenced o utput t iming ac c haracteristics ...................................................... 62 t able 8.14 pclk-r eferenced o utput t iming ac c haracteristics .......................................................... 63
W9961CF - 7 - 1 g e n e r a l d e s c r i p t i o n the W9961CF is a highly integrated single chip video codec provided by winbond electronics corp. the W9961CF performs video compression and decompression fully compliant with itu-t h.263 and h.261 standards for video conferencing. working in conjunction with the high performance 32-bit risc, w90220cf, the W9961CF is aimed to provide a complete video solution that supports both the h.324 international standard for video conferencing over regular telephone lines (public switched telephone network, or pstn) as well as the h.320 international standard for isdn video conferencing. moreover, the W9961CF integrates a high quality ntsc/pal tv encoder to directly interface to tv or lcd, eliminating the need for a separate tv encoder for stand-alone or set-top videophone. to achieve high performance video coding and decoding, many hardware engines are integrated in the W9961CF, which perform motion estimation and motion compensation, discrete cosine transform (dct) and inverse discrete cosine transform (idct), quatization and inverse quantization, zig-zag scan, variable length encoding and variable length decoding (vld), etc. a high performance 16-bit risc with 5kx22 bits program memory (pm) and 1kx16 bits data memory (dm) is also integrated for h.263/h.261 coding/decoding control and intelligent frame rate control. there are three picture formats supported by the w9961 encoder and decoder: sub-qcif, qcif, and cif. the W9961CF, when operated at 70 mhz clock frequency, is capable to encode/decode sub- qcif, qcif, or cif at 30 fps. the W9961CF can accept ntsc or pal video, square, or rectangular pixels, and convert to sub- qcif, qcif, or cif format. a two-dimensional noise reduction filter is integrated to reduce noise and improve coding efficiency. built-in cropping window control and arbitrary scaling in both the horizontal and vertical directions can serve as the digital pan and zoom over a user-specified region for camera control. in the video post-processing, the W9961CF supports two movable and arbitrarily scaleable windows with picture-in-picture (pip) feature for remote and local view video. a built-in post deblocking filter is used to reduce visible artifacts of remote view from video compression. the local view video can be mirrored or unmirrored. a display controller is built-in with 4-/8-/16-bit color modes for background or on-screen-display (osd). a high quality ntsc/pal tv encoder is also integrated to directly interface to tv or lcd. an on-chip dram controller is used to interface to sdram or edo dram through 32-bit data bus. the W9961CF is a 3.3 v device with ttl-compatible 3.3 v or 5.0 v i/o, and is packaged in 208-pin pqfp.
W9961CF - 8 - 2 f e a t u r e s v i d e o c o d e c ? fully compliant with itu-t international standards h.263 and h.261 ? encodes/decodes in sub-qcif (128x96), qcif (176x144), or cif (352x288) picture format ? encodes/decodes sub-qcif/qcif/cif at 30 frames per second (fps) ? supports both integer search and half-pixel search motion estimation ? supports several h.263 version 2 preferred modes including annex d unrestricted motion vectors (with uui = 1) annex j deblocking filter annex k slice structured mode annex l supplemental enhancement information (full-frame freeze only) annex t modified quantization v i d e o p r e - p r o c e s s i n g ? direct connect to digital camera through 8- or 16-bit data bus ? glueless interface to ntsc/pal tv decoder ? input video format compliant with ycbcr 4:2:2 ccir 601 standard ? built-in two-dimensional noise reduction filter to reduce noise and improve coding efficiency ? built-in cropping and arbitrary scaling for digital pan and zoom camera control v i d e o p o s t - p r o c e s s i n g ? built-in two moveable and arbitrarily scalable video windows with picture-in-picture (pip) ? built-in post deblocking filter to reduce visible artifacts of remote view from video compression ? the local view can be mirrored or unmirrored ? built-in display controller with 4-/8-/16-bit color modes for background or on-screen-display (osd) ? built-in ntsc/pal tv encoder with three 9-bit dacs for direct tv output ? built-in 3-line 1d/2d flicker-free filter for best text quality ? supports three composite video, one s-video and one composite video, or one rgb output
W9961CF - 9 - ? hue, saturation, contrast, and brightness adjustments i s a - l i k e i n t e r f a c e a n d g p i o s ? direct connect to dspg ct802x-series audio processor through 8-bit isa-like interface ? provides several general purpose i/o ports which can be configured as serial ports, keypad control, button control, remote control, etc. h o s t i n t e r f a c e ? direct connect to winbond w902x0-series cpu through 32-bit pci bus ? pci 2.1 compliant m e m o r y i n t e r f a c e ? supports sdram or 1-cycle edo dram at 70 mhz maximum clock frequency ? supports 32-bit dram interface in 1, 2 or 4 mbytes configuration b u i l t - i n p r o g r a m m a b l e p h a s e - l o c k e d l o o p ( p l l ) c l o c k s y n t h e s i z e r o p e r a t i n g f r e q u e n c y i s 7 0 m h z w i t h v i d e o i n p u t f r e q u e n c y o f 1 3 . 5 m h z ( t y p i c a l ) , v i d e o o u t p u t f r e q u e n c y o f 2 7 . 0 m h z , a n d p c i c l o c k f r e q u e n c y o f 3 3 m h z 3 . 3 v d e v i c e w i t h t t l - c o m p a t i b l e 3 . 3 v o r 5 . 0 v i / o f a b r i c a t e d i n a d v a n c e d 0 . 3 5 u m t l m t e c h n o l o g y 2 0 8 l q f p p a c k a g e
W9961CF - 10 - 3 p i n c o n f i g u r a t i o n the W9961CF is packaged in a 208l qfp. the pin configuration is shown in figure 3.1. W9961CF (top view) ma0 v d d 5 v 55 1 0 a d 3 1 a d 3 0 v s s b m d 2 3 v d d b p 3 y 4 p 2 y 5 g p i o 4 u v 0 u v 1 d e m m d 2 0 m d 1 9 m d 2 1 m d 2 4 m d 2 5 m d 2 6 m d 2 2 m d 2 7 m d 2 8 m d 2 9 m d 3 0 m d 3 1 v s s b g p i o 0 g p i o 1 g p i o 2 v d d i g p i o 3 v s s i u v 2 u v 3 u v 4 u v 5 u v 6 u v 7 y 1 v d d b y 0 y 2 y 3 y 6 y 7 v s h s v i c l k v s s b p 0 p 1 h s y n c v s s b a d 2 9 a d 2 8 v d d b a d 2 7 a d 2 6 a d 2 5 a d 2 4 c / b e 3 # i d s e l a d 2 3 a d 2 2 a d 2 1 a d 2 0 a d 1 9 a d 1 8 a d 1 7 a d 1 6 v d d i c / b e 2 # f r a m e # v s s i i r d y # t r d y # v s s b d e v s e l # s t o p # v d d b p e r r # s e r r # p a r c / b e 1 # a d 1 5 a d 1 4 a d 1 3 a d 1 2 a d 1 1 a d 1 0 a d 9 a d 8 v s s b c / b e 0 # a d 7 a d 6 a d 5 a d 4 a d 3 a d 2 a d 1 a d 0 v s y n c 5 1 2 0 1 5 2 5 3 0 3 5 4 0 4 5 5 0 1 0 5 1 1 0 1 1 5 1 2 0 1 2 5 1 3 0 1 3 5 1 4 0 1 4 5 1 5 0 1 5 5 60 65 70 75 80 85 90 95 100 205 200 195 190 185 180 175 170 165 160 ma1 ma2 ma3 ma4 vssb ma5 ma6 vddb ma7 ma8 ma9 ma10 ba vssb smclk vssi scas# vddi sras# oe#/cke we# cas0#/dqm0 cas1#/dqm1 vssb ras0#/cs0# md0 md1 md2 vddb md3 md4 md5 md6 md7 md8 md9 vssb md10 md11 md12 md13 md14 md15 cas2#/dqm2 cas3#/dqm3 vddb ras1#/cs1# vssb md16 md17 md18 p5 p4 p7 p6 vddi pclk cp1/y/g cp2/c/b vref cp0/r extvref rset comp dacavss vdd5v dacavdd sd1 sd0 sd3 sd2 sd4 vssb sd6 sd5 voclk sd7 sa1 sa0 sa2 vssi vddb sa3 sa5 sa4 sa6 vssb sa8 sa7 sa10 sa9 sa12 sa11 srd# eint# pllavdd swr# mclk pllavss inta# voclk/2 pciclk rst# f i g u r e 3 . 1 w 9 9 6 1 c f p i n c o n f i g u r a t i o n
W9961CF - 11 - 4 p i n d e s c r i p t i o n the following tables provide a brief description of each pin on the W9961CF. the following signal type definitions are used in these descriptions: i input pin iu input pin with internal pull-up resistor b bi-directional input/output pin o output pin ts tri-state output pin sts sustained tri-state pin. must drive it high for at least one pci clock before letting it float. a analog pin p power supply pin g ground pin # active low 4 . 1 p i n d e f i n i t i o n p c i b u s i n t e r f a c e ( 4 8 p i n s ) p i n n a m e p i n n u m b e r t y p e d e s c r i p t i o n ad[31:0] 1, 2, 4, 5, 7- 10, 13-20, 35-42, 45-52 b multiplexed system address and data bus. the address phase is the clock cycle in which frame# is asserted. data is transferred during those clocks where both irdy# and trdy# are asserted. c/be[3:0]# 11, 22, 34, 44 i multiplexed bus command and byte enables. during the address phase of a transaction, c/be[3:0]# define the bus command. during the data phase c/be[3:0]# are used as byte enables. par 33 ts parity. it is even parity across ad31-ad0 and c/be[3:0]#. frame# 23 i cycle frame. asserted to indicate a bus transaction is beginning. trdy# 26 sts target ready. a data phase is completed on any clock both trdy# and irdy# are sampled asserted. irdy# 25 i initiator ready. a data phase is completed on any clock both irdy# and trdy# are sampled asserted.
W9961CF - 12 - inta# 206 ts interrupt request. asserted low, level sensitive. stop# 29 sts stop. asserted to request the master to stop the current transaction. devsel# 28 sts device select. asserted to indicate the W9961CF has decoded its address as the target of the current access. idsel 12 i initialization device select. used as chip select during configuration read and write transactions. perr# 31 sts parity error. it is only for the reporting of data parity errors during the pci transactions. the W9961CF cannot report a perr# until it has claimed the access by asserting devsel# and completed a data phase. serr# 32 ts system error. it is for reporting address parity errors, or any other system error where the result will be catastrophic. pciclk 208 i pci system clock. up to 33 mhz for W9961CF. rst# 207 i system reset. v i d e o m e m o r y i n t e r f a c e ( 5 5 p i n s ) p i n n a m e p i n n u m b e r t y p e d e s c r i p t i o n md[31:0] 120-115,113- 109, 107, 106, 104-102, 96- 91, 89-83, 81- 79 b data bus. note: md[15:0] are also used as the system configuration strapping bits, providing system configuration and setup information upon power-on or reset. ma[10:0] 65-62, 60, 59, 57-53 o address bus. note: for sdram, ma[10:0] are sampled during the active command (row address ma[10:0]) and read/write command (column address ma[7:0], with ma10 defining auto precharge) to select one location out of the 512k available in the respective bank. ma10 is sampled during a precharge command to determine if all banks are to be precharged (ma10 high). ras[1:0]# cs[1:0]# 100, 78 o edo dram: row address strobes. sdram: chip select. cs[1:0]# enable the command decoder
W9961CF - 13 - for each external memory bank. cas[3:0]# dqm[3:0] 98, 97, 76, 75 o edo dram: column address strobes. sdram: input/output mask. dqm[3:0] are input mask signals for write accesses and output enable signals for read accesses. dqm0 corresponds to md[7:0]; dqm1 corresponds to md[15:8]; dqm2 corresponds to md[23:16]; dqm3 corresponds to md[31:24]. oe# cke 73 o edo dram: output enable. sdram: clock enable. cke activates the smclk signal. the sdram enters precharge power-down to deactivate the input and output buffers, excluding cke, for maximum power saving when cke is low coincident with a nop. we# 74 o edo dram: write enable. sdram: command input. sras#, scas#, and we# (along with cs#) define the command being entered. sras# 72 o edo dram: not used. sdram: command input. sras#, scas#, and we# (along with cs#) define the command being entered. scas# 70 o edo dram: not used. sdram: command input. sras#, scas#, and we# (along with cs#) define the command being entered. ba 66 o edo dram: not used. sdram: bank address input. ba defines to which internal bank the active, read, write or precharge command is being applied. ba is also used to program the 12th bit of the mode register. smclk 68 o edo dram: not used. sdram: clock. i n p u t v i d e o i n t e r f a c e ( 1 9 p i n s ) p i n n a m e p i n n u m b e r t y p e d e s c r i p t i o n
W9961CF - 14 - y[7:0] 146-139 i digital y (luminance) inputs in 16-bit mode, or digital yuv inputs in 8-bit mode. uv[7:0] 137-130 iu digital uv (chrominance) inputs in 16-bit mode, or not used in 8-bit mode. hs 148 i horizontal sync. input. programmable polarity. vs 147 i vertical sync input. programmable polarity. viclk 149 i input video clock. o u t p u t v i d e o i n t e r f a c e ( 2 0 p i n s ) p i n n a m e p i n n u m b e r t y p e d e s c r i p t i o n cp2 c b 163 o composite video mode: composite video output. s-video + composite video mode: chrominance output. rgb output mode: blue video output. cp1 y g 164 o composite video mode: composite video output. s-video + composite video mode: luminance output. rgb output mode: green video output. cp0 r 165 o composite video mode: composite video output. s-video + composite video mode: composite video output. rgb output mode: red video output. p[7:0] 151-154, 157- 160 b 8-bit ycbcr mode: digital ycbcr video output data. 8-bit rgb mode: digital rgb video output data. pclk 161 ts 8-bit ycbcr mode: 2 pixel clock output. 8-bit rgb mode: 2 3 pixel clock output. hsync 155 ts horizontal sync.
W9961CF - 15 - vsync 156 ts vertical sync. dem 128 b data enable control signal for lcd interface. vref 166 a voltage reference. a 0.1uf bypass capacitor should always be connected between this pin and tvavdd, with short leads and in close proximity to the device pins. rset 167 a reference resistor. a resistor should be connected from this pin to tvavss to control the full-scale current value. extvref 168 a external vref mode: external voltage reference (analog input). an external voltage reference must supply this pin with a 1.235 v (typical) reference. a 0.1uf bypass capacitor should always be connected between this pin and tvavdd. internal vref mode: a 0.1uf bypass capacitor should always be connected between this pin and tvavdd. comp 170 a compensation pin. a 0.1uf bypass capacitor should always be connected between this pin and tvavdd, with short leads and in close proximity to the device pins. voclk 182 i output video clock. a stable 27 mhz reference clock input. i s a - l i k e b u s i n t e r f a c e a n d g p i o p o r t s ( 2 9 p i n s ) p i n n a m e p i n n u m b e r t y p e d e s c r i p t i o n sd[7:0] 181-178, 176- 174, 172 b data bus. isa-like data bus to interface with the audio processor. sa[12:0] 198-192, 190, 189, 187, 186, 184, 183 b address bus. they are output pins in normal operation (pwon_14-12 = 111), while serve as address inputs when in the internal ram/rom test mode (pwon_14-12 111). swr# 201 b i/o write. it is output pin in normal operation (pwon_14-12 = 111), while serves as write input when in the internal ram/rom test mode (pwon_14-12 111). srd# 200 b i/o read. it is output pin in normal operation (pwon_14-12 = 111), while serves as read input when in the internal ram/rom test mode (pwon_14-12 111). eint# 199 iu interrupt request input.
W9961CF - 16 - gpio[4:0] 122-125, 127 b general purpose input/out ports. with internal pull-up resistor. c l o c k i n t e r f a c e ( 2 p i n s ) p i n n a m e p i n n u m b e r t y p e d e s c r i p t i o n voclk/2 205 ts voclk by 2. a stable 13.5 mhz clock output. mclk 204 iu external mclk mode: main clock input. internal mclk mode: not used. p o w e r a n d g r o u n d ( 3 5 p i n s ) p i n n a m e p i n n u m b e r t y p e d e s c r i p t i o n vddb 6, 30, 61, 82, 99, 114, 138, 188 p buffer power supply. provides isolated power to the input and output buffers for improved noise immunity. +3.3 v 0.3 v. vdd5v 105, 173 p 5v buffer power supply. provides 5v power to the input and output buffers for 5v input tolerance. +5.0 v 0.25 v. vssb 3, 27, 43, 58, 67, 77, 90, 101, 108, 121, 150, 177, 191 g buffer ground. vddi 21, 71, 126, 162 p core power supply. +3.3 v 0.3 v. vssi 24, 69, 129, 185 g core ground. dacavdd 171 p dac analog power supply. provides isolated power to the dac analog ckts for improved noise immunity. +3.3 v 0.3 v. dacavss 169 g dac analog ground. pllavdd 202 p pll analog power supply. provides isolated power to the pll analog ckts for improved noise immunity. +3.3 v 0.3 v. pllavss 203 g pll analog ground.
W9961CF - 17 - 4 . 2 p i n l i s t t a b l e 4 . 1 w 9 9 6 1 c f p i n l i s t n u m b e r n a m e t y p e p u l l - u p i o h ( m a ) i o l ( m a ) l o a d ( p f ) 1 ad31 b ? 3 850 2 ad30 b ? 3 850 3 vssb g 4 ad29 b ? 3 850 5 ad28 b ? 3 850 6 vddb p 7 ad27 b ? 3 850 8 ad26 b ? 3 850 9 ad25 b ? 3 850 10 ad24 b ? 3 850 11 c/be3# i 12 idsel i 13 ad23 b ? 3 850 14 ad22 b ? 3 850 15 ad21 b ? 3 850 16 ad20 b ? 3 850 17 ad19 b ? 3 850 18 ad18 b ? 3 850 19 ad17 b ? 3 850 20 ad16 b ? 3 850 21 vddi p 22 c/be2# i 23 frame# i 24 vssi g 25 irdy# i 26 trdy# sts ? 3 850 27 vssb g 28 devsel# sts ? 3 850 29 stop# sts ? 3 850 30 vddb p 31 peer# sts -3 8 50 32 serr# ts -2 4 50 33 par ts ? 3 850 34 c/be1# i 35 ad15 b ? 3 850 36 ad14 b ? 3 850 37 ad13 b ? 3 850
W9961CF - 18 - 38 ad12 b ? 3 850 39 ad11 b ? 3 850 40 ad10 b ? 3 850 41 ad9 b ? 3 850 42 ad8 b ? 3 850 43 vssb g 44 c/be0# i 45 ad7 b ? 3 850 46 ad6 b ? 3 850 47 ad5 b ? 3 850 48 ad4 b ? 3 850 49 ad3 b ? 3 850 50 ad2 b ? 3 850 51 ad1 b ? 3 850 52 ad0 b ? 3 850 53 ma0 o ? 3 850 54 ma1 o ? 3 850 55 ma2 o ? 3 850 56 ma3 o ? 3 850 57 ma4 o ? 3 850 58 vssb g 59 ma5 o ? 3 850 60 ma6 o ? 3 850 61 vddb p 62 ma7 o ? 3 850 63 ma8 o ? 3 850 64 ma9 o ? 3 850 65 ma10 o ? 3 850 66 ba o ? 3 850 67 vssb g 68 smclk o ? 6 16 50 69 vssi g 70 scas# o -3 8 50 71 vddi p 72 sras# o -3 8 50 73 oe#/cke o ? 3 850 74 we# o ? 3 850 75 cas0#/dqm0 o ? 3 850 76 cas1#/dqm1 o ? 3 850 77 vssb g 78 ras0#/cs0 o ? 3 850 79 md0 b ? 3 850
W9961CF - 19 - 80 md1 b ? 3 850 81 md2 b ? 3 850 82 vddb p 83 md3 b ? 3 850 84 md4 b ? 3 850 85 md5 b ? 3 850 86 md6 b ? 3 850 87 md7 b ? 3 850 88 md8 b ? 3 850 89 md9 b ? 3 850 90 vssb g 91 md10 b ? 3 850 92 md11 b ? 3 850 93 md12 b ? 3 850 94 md13 b ? 3 850 95 md14 b ? 3 850 96 md15 b ? 3 850 97 cas2#/dqm2 o ? 3 850 98 cas3#/dqm3 o ? 3 850 99 vddb p 100 ras1#/cs1 o ? 3 850 101 vssb g 102 md16 b ? 3 850 103 md17 b ? 3 850 104 md18 b ? 3 850 105 vdd5v p 106 md19 b ? 3 850 107 md20 b ? 3 850 108 vssb g 109 md21 b ? 3 850 110 md22 b ? 3 850 111 md23 b ? 3 850 112 md24 b ? 3 850 113 md25 b ? 3 850 114 vddb p 115 md26 b ? 3 850 116 md27 b ? 3 850 117 md28 b ? 3 850 118 md29 b ? 3 850 119 md30 b ? 3 850 120 md31 b ? 3 850 121 vssb g
W9961CF - 20 - 122 gpio0 b ? 2 425 123 gpio1 b ? 2 425 124 gpio2 b ? 2 425 125 gpio3 b ? 2 425 126 vddi p 127 gpio4 b ? 2 425 128 dem b ? 3 850 129 vssi g 130 uv0 iu 131 uv1 iu 132 uv2 iu 133 uv3 iu 134 uv4 iu 135 uv5 iu 136 uv6 iu 137 uv7 iu 138 vddb p 139 y0 i 140 y1 i 141 y2 i 142 y3 i 143 y4 i 144 y5 i 145 y6 i 146 y7 i 147 vs i 148 hs i 149 viclk i 150 vssb g 151 p0 b ? 3 850 152 p1 b ? 3 850 153 p2 b ? 3 850 154 p3 b ? 3 850 155 hsync ts ? 3 850 156 vsync ts ? 3 850 157 p4 b ? 3 850 158 p5 b ? 3 850 159 p6 b ? 3 850 160 p7 b ? 3 850 161 pclk ts ? 3 850 162 vddi p 163 cp2/c/b o 164 cp1/y/g o
W9961CF - 21 - 165 cp0/r o 166 vref a 167 rset a 168 extvref a 169 dacavss g 170 comp a 171 dacavdd p 172 sd0 b -2 4 25 173 vdd5v p 174 sd1 b -2 4 25 175 sd2 b -2 4 25 176 sd3 b -2 4 25 177 vssb g 178 sd4 b -2 4 25 179 sd5 b -2 4 25 180 sd6 b -2 4 25 181 sd7 b -2 4 25 182 voclk i 183 sa0 b -2 4 25 184 sa1 b -2 4 25 185 vssi g 186 sa2 b -2 4 25 187 sa3 b -2 4 25 188 vddb p 189 sa4 b -2 4 25 190 sa5 b -2 4 25 191 vssb g 192 sa6 b -2 4 25 193 sa7 b -2 4 25 194 sa8 b -2 4 25 195 sa9 b -2 4 25 196 sa10 b -2 4 25 197 sa11 b -2 4 25 198 sa12 b -2 4 25 199 eint# iu 200 srd# b -2 4 25 201 swr# b -2 4 25 202 pllavdd p 203 pllavss g 204 mclk iu 205 voclk/2 ts ? 3 830 206 inta# ts ? 3 830 207 rst# i 208 pciclk i
W9961CF - 22 - 4 . 3 p o w e r o n r e s e t i n i t i a l i z a t i o n during system reset and power up, state of the memory data lines md[15:0] are latched into the W9961CF s internal configuration registers as video subsystem configuration information. since each md[15:0] pin is internally pulled up on their i/o buffers, no external pull-up resistor is required. a 4.7k ohm resistor to ground is recommended for pull-down. table 4.2 shows the system power on reset configuration definitions. 1 is the default value for each bit. t a b l e 4 . 2 w 9 9 6 1 c f p o w e r o n r e s e t d e f i n i t i o n s m d b i t ( s ) d e f i n i t i o n v a l u e f u n c t i o n c o n t r o l r e g . md[0] video memory type 0 1 edo dram sdram pwon_0 md[1] dram size 0 1 256kx16/32 dram 1mx16 dram pwon_1 md[3:2] analog video output mode 0x 10 11 rgb out, tv encoder is off composite video s-video + composite video pwon_3-2 md[5:4] tv system 00 01 10 11 reserved pal-m pal-b, d, g, h, n ntsc pwon_5-4 md[6] cp2/c/b dac control 0 1 off on pwon_6 md[7] cp1/y/g dac control 0 1 off on pwon_7 md[8] cp0/r dac control 0 1 off on pwon_8 md[9] vref control 0 1 external vref internal vref pwon_9 md[10] input video mode 0 1 8-bit mode 16-bit mode pwon_10 md[11] internal mclk select 0 1 from external mclk pin from internal pll pwon_11 md[14:12] test mode 000 001 010 pm test (5k 22 bits) dm test (1k 16 bits) reserved pwon_14-12
W9961CF - 23 - 011 100 101 110 111 palette ram test (256 18 bits) dto rom test (256 16 bits) dac test reserved normal operation md[15] digital video output mode 0 1 8-bit ycbcr 8-bit rgb pwon_15 note 1. pm, dm, palette ram, and dto rom are tested through a 13-bit address bus, 22-bit data bus, and read/write signals depicted in the following: test mode address data read write pm (5k 22) sa[12:0] p[7:0], dem, gpio[4:0], sd[7:0] srd# swr# dm (1k 16) sa[9:0] p[1:0], dem, gpio[4:0], sd[7:0] srd# swr# palette ram (256 18) sa[7:0] p[3:0], dem, gpio[4:0], sd[7:0] srd# swr# dto rom (256 16) sa[7:0] p[1:0], dem, gpio[4:0], sd[7:0] srd# note 2. for dac test, the external sa[8:0] pins are copied and sent directly to the inputs of cp2/c/b, cp1/y/g, and cp0/r dacs to control the dac output. sa[8:0] 9-bit input data for dac test voclk 2 clock for dac output
W9961CF - 24 - 5 s y s t e m d i a g r a m W9961CF h.263/h.261 d i g i t a l c a m e r a l c d (composite or 8-bit rgb) t v (composite or/and s-video) m o n i t o r (rgb) w90220cf h.223/h.245 g.723.1 s p e a k e r m i c r o p h o n e v i d e o m e m o r y 1/2/4 mbytes sdram or edo dram k e y p a d , c o n t r o l b u t t o n s m o d e m v.34/v.80 t e l e p h o n e l i n e s y s t e m b o o t r o m a u d i o c o d e c h a n d s e t s y s t e m m e m o r y 4 mbytes edo dram ycbcr 4:2:2 gpios/isa-like bus f i g u r e 5 . 1 w 9 9 6 1 c f - b a s e d s t a n d - a l o n e v i d e o p h o n e s y s t e m d i a g r a m
W9961CF - 25 - figure 5.1 shows an example system diagram for an h.324-compliant stand-alone videophone. for live video input, a digital camera, or an ntsc/pal camera connected to a tv decoder, is fed into the W9961CF in ycbcr 4:2:2 format through 16- or 8-bit data bus. the input video is cropped and scaled to sub-qcif, qcif, or cif format as the local view video. the W9961CF compresses the local view video according to h.263 for h.324 (or h.261 for h.320) and the resultant compressed video stream is transferred and multiplexed with compressed audio stream by the w90220cf. then the w90220cf performs multiplex/control according to h.223/h.245 for h.324 (or h.221/h.242/h.230 for h.320) and transmits the bit stream to the pstn through v.34/v.80 modem for h.324 (or isdn network for h.320). for the receipt of combined video/audio from the remote end, the h.324-compliant (or h.320- compliant) bit stream enters the system through a v.34/v.80 modem for h.324 (or isdn circuit for h.320), where the w90220cf performs demultiplex/control and separates the stream into two compressed streams. the W9961CF decompresses the video stream according to h.263 for h.324 (or h.261 for h.320) and produces the remote view video. the decompressed remote view video and/or the local view video can be overlaid with graphical background or on-screen-display (osd) and output to lcd (in ntsc/pal composite video or rgb format), tv (in ntsc/pal composite video or s-video format), or monitor (in rgb format). the W9961CF can also performs post deblocking filtering to reduce artifacts caused by compression/decompression for the remote view video, and the local view video can be mirrored or unmirrored. for audio processing, the near-end audio is compressed and the remote-end audio stream is decompressed by the w90220cf according to g.723.1 for h.324 (or g.711/g.722/g.728 for h.320). the w90220cf also performs acoustical echo cancellation (aec) between the speaker and microphone to prevent howling. a/d conversion for microphone or handset transmitter input, and d/a conversion to drive the speaker and/or handset receiver are performed by the audio codec.
W9961CF - 26 - 6 b l o c k d i a g r a m v i d e o i n ycbcr 4:2:2 v p r e p r o c e s s o r d r a m c o n t r o l l e r / d m a c o n t r o l l e r v i d e o c o d e c h o s t i n t e r f a c e c o n t r o l l e r r i s c m i c r o p r o c e s s o r i s a - l i k e i n t e r f a c e a n d g p i o s v p o s t p r o c e s s o r h o s t c p u v i d e o m e m o r y l c d t v m o n i t o r a u d i o , k e y p a d , b u t t o n s W9961CF t i m e r i n t c p l l m c l k f i g u r e 6 . 1 w 9 9 6 1 c f b l o c k d i a g r a m the block diagram for the W9961CF is shown in figure 6.1. please refer to next chapter for detailed functional description.
W9961CF - 27 - 7 f u n c t i o n a l d e s c r i p t i o n 7 . 1 v p r e p r o c e s s o r c r o p p i n g f t d o w n - s c a l i n g c a p t u r e f i f o v p r e - i n f i f o u p - s c a l i n g p r e - f i l t e r v p r e - o u t f i f o v i c l k y [ 7 : 0 ] , u v [ 7 : 0 ] h s , v s v i d e o m e m o r y l o c a l v i e w f o r d i s p l a y l o c a l v i e w f o r e n c o d i n g y c b c r 4 : 2 : 2 y c b c r 4 : 2 : 0 f i g u r e 7 . 1 v p r e p r o c e s s o r b l o c k d i a g r a m the vpre processor generates two video streams from the input video: the local view video for display and the local view video for encoding. the input video is cropped, down-scaled, and stored into the video memory as the local view video for display that is real-time at 30 fps. built-in cropping window control and arbitrary down-scaling in both the horizontal and vertical directions can serve as the digital pan and zoom over a user-specified region for camera control. the local view video for encoding is generated from the local view video for display through the pre- filter and/or up-scaling. up-scaling is needed to vertically up-scale a 240-line video to a 288-line video when encoding in cif format by using an ntsc camera. pre-filter is an adaptive 3 3 low-pass filter which can detect noise induced from the video input device and remove it. since h.263/h.261 uses motion estimation and dct for compression, the coding efficiency can be improved significantly by using the pre-filtered video whose most noise is removed.
W9961CF - 28 - 7 . 2 v i d e o c o d e c d c t q i q i d c t z z v l e i z z v l d m u x m c ( m o t i o n c o m p e n s a t i o n ) m e ( m o t i o n e s t i m a t i o n ) m u x 0 1 0 1 0 v i d e o m e m o r y p r e v i o u s r e c o n s t r u c t e d p i c t u r e c u r r e n t r e c o n s t r u c t e d p i c t u r e v i d e o m e m o r y e n c o d i n g b i t s t r e a m b u f f e r d e c o d i n g b i t s t r e a m b u f f e r v i d e o m e m o r y l o c a l v i e w f o r e n c o d i n g 0 : i n t r a 1 : i n t e r d c t e n g i n e d b f f i g u r e 7 . 2 v i d e o c o d e c b l o c k d i a g r a m 7 . 2 . 1 v i d e o c o d i n g the coding mode in which temporal prediction is applied is called inter; the coding mode is called intra if no temporal prediction is applied. the W9961CF supports both intra and inter coding modes. the intra coding mode can be signaled at the picture level (intra for i-pictures or inter for p-pictures) or at the macroblock level in p-pictures. 7 . 2 . 1 . 1 i - p i c t u r e s i n t r a c o d i n g i-pictures require no motion estimation or compensation. each macroblock is dct transformed at first. dct coefficients are quantized (q), zig-zag scanned (zz), variable-length encoder (vle) coded, and stored into the video memory. within each macroblock, processing is performed on 8 8 blocks.
W9961CF - 29 - the quantized blocks are also inverse quantized (iq) and transformed into the spatial domain by an inverse dct (idct). this operation yields a copy of the encoded picture as it will be seen by the decoder. that copy is then stored into the video memory and will be used for future predictive coding. since the vle operation is lossless, there is no need to include the vle unit in the feedback path. 7 . 2 . 1 . 2 p - p i c t u r e s i n t e r c o d i n g p-pictures macroblocks may be coded by intra or inter coding mode. for each macroblock in the current p-picture, the motion estimation is performed on the luminance (y) macroblock. a full search or fast search is made with integer pixel displacement in the y component at first. the comparisons are made between the incoming macroblock and the displaced macroblock in the previous reconstructed picture. the encoder makes a decision on whether to use intra or inter prediction in the coding after the integer pixel motion estimation. if intra mode is chosen, no further operation is necessary for the motion search. we will describe p-picture intra coding in the following section 7.2.1.3. if inter mode is chosen the motion search continues with half-pixel search around the integer pixel motion vector, mv0, position. after the half-pixel search, the best match motion vector is coded using a variable-length encoder (vle), and stored into the video memory. motion vector is included for all inter macroblocks and consists of horizontal and vertical components, both measured in half pixel units. p-pictures inter coding does not code the picture macroblocks directly. instead it codes the prediction errors. for each inter coding macroblock in the current picture, the best match macroblock in the previous reconstructed picture is loaded into the mc and half-pixel motion compensation is performed according to the motion vector. after half-pixel motion compensation, the two macroblocks are subtracted to produce prediction errors (their difference) which will be dct transformed. dct coefficients are quantized, zig-zag scanned, coded using a variable-length encoder, and stored into the video memory. the quantized blocks are also inverse quantized and transformed into the spatial domain by an inverse dct. the idct results and the previous reconstructed blocks are added and stored into the video memory as the current reconstructed picture for future predictive coding. 7 . 2 . 1 . 3 p - p i c t u r e s i n t r a c o d i n g if intra mode is chosen for current p-pictures macroblock, no further half-pixel motion search is performed and no motion vector is coded. each intra macroblock is coded as that for i-pictures intra coding. 7 . 2 . 2 v i d e o d e c o d i n g video decoding operation is very similar to the feedback loop of the video coding. after optional error correction, the compressed bit stream is processed by the variable length decoder (vld). the decoded data are parsed, inverse zig-zag scanned (izz), and then processed by an inverse quantizer and an inverse dct. depending on the transmission mode (intra or inter), macroblocks from the previous reconstructed picture may also be added to the current data to form the reconstructed picture. for each intra-coded macroblock of i-pictures or p-pictures, no motion compensation is performed. the idct results are stored into the video memory as reconstructed picture.
W9961CF - 30 - for each inter-coded macroblock of p-pictures, the macroblock pointed to by the motion vector in the previous reconstructed picture is loaded into the mc and half-pixel motion compensation is performed according to the motion vector. the half-pixel motion compensated results and the idct results are added and then stored into the video memory as reconstructed picture. 7 . 3 v p o s t p r o c e s s o r d i s p l a y f i f o v p g p o v e r l a y p o s t - f i l t e r a d j u s t m e n t t v e n c o d e r c s c y u v t o r g b m u x d a c d a c d a c v i d e o m e m o r y d i s p l a y c o n t r o l l e r c p 0 / r c p 1 / y / g c p 2 / c / b v s y n c h s y n c p [ 7 : 0 ] p c l k d e m f i g u r e 7 . 3 v p o s t p r o c e s s o r b l o c k d i a g r a m the vpost processor performs three main functions: video post-processing, display control, and video output control. 7 . 3 . 1 v i d e o p o s t - p r o c e s s i n g video post-processing includes post-filter and video processor (vp). the post-filter is performed on the luminance component and is used to reduce blocking artifacts and mosquito noise, and also for edge enhancement of the decoded remote view video. a 5 3 block classified filer (bcf) is implemented to calculate local mean and local variance of the processed pixel at first. depending on the local mean and local variance the processed pixel is classified as low-variance, middle-variance, or high-variance pixel. for low-variance pixels, a low-pass filter is applied to remove the blocking artifacts. for middle-variance pixels, the local mean is used in stead to remove the mosquito noise. edge enhancement is performed for the high-variance pixels. video processor is used to up-scale or down-scale the video for display. both local view and remote view video can be arbitrarily up-scaled up to full-screen size, or down-scaled to 1/2 of its original size, horizontally and/or vertically. either the local view video or remote view video can be up-scaled by using two-dimensional bilinear interpolation for better video quality. 1/2 down-scaling can be used in
W9961CF - 31 - picture-in-picture display where the local view video may be in cif format for encoding and in qcif format for display. 7 . 3 . 2 d i s p l a y c o n t r o l display control includes display controller, graphics processor (gp), and overlay function. the display controller generates horizontal and vertical timings for display. the graphics processor accesses the background data and on-screen-display data from the video memory, and converts it to ycbcr format for overlaying with the video data. the graphics data can be in 16-color, 256-color, or 565 high-color format, where a built-in color look-up-table (lut) is used to transform the pseudo color data (16- and 256-color modes) to true color data. an advanced two- dimensional 3-line flicker-free filter is also incorporated to eliminate the annoying artifacts induced by graphics lines on interlaced tv. the flicker-free filter takes effect on the original rgb data. background and on-screen-display graphics data, after processed by the graphics processor, are overlaid with the video data by using window key and color key. for example, a typical three-window display is shown in figure 7.4. r e m o t e v i e w v i d e o l o c a l v i e w v i d e o o n - s c r e e n d i s p l a y d e f i n e d b y w i n d o w k e y 1 d e f i n e d b y w i n d o w k e y 2 b a c k g r o u n d f i g u r e 7 . 4 t y p i c a l t h r e e - w i n d o w d i s p l a y f o r v i d e o c o n f e r e n c i n g a p p l i c a t i o n s 7 . 3 . 3 v i d e o o u t p u t c o n t r o l the vpost incorporates a tv encoder, color space conversion (csc), and three 9-bit dacs for direct interface with tv, lcd, and crt monitor. before the tv encoder block, an adjustment block is used for adjusting hue, saturation, contrast, and brightness. 7 . 3 . 3 . 1 h u e , s a t u r a t i o n , c o n t r a s t , a n d b r i g h t n e s s a d j u s t m e n t s
W9961CF - 32 - figure 7.5 illustrates a typical circuit for enabling adjustment of contrast and brightness for y component, and hue and saturation for cbcr components. the brightness is adjusted after the contrast adjustment to avoid introducing a varying dc offset due to adjusting the contrast. hue adjustment is implemented by mixing the cb and cr data: cb = cb cos + cr sin cr = cr cos ? cb sin where is the desired hue angle. an 11-bit hue adjustment value is used to allow adjustments from 0 to 360 , in increments of 0.176 . y + - 16 contrast value brightness value 16 y ? c r 128 hue value s i n 128 saturation value c r ? c b ? + - + - + - c b c o s f i g u r e 7 . 5 h u e , s a t u r a t i o n , c o n t r a s t , a n d b r i g h t n e s s c o n t r o l s 7 . 3 . 3 . 2 v i d e o o u t p u t i n t e r f a c e the built-in tv encoder supports worldwide video standards, including ntsc, pal-b, d, g, h, n, and pal-m. the W9961CF supports two digital video output modes (8-bit ycbcr and 8-bit rgb) and three analog video output modes (rgb, composite, and s-video + composite) as shown in table 7.1. up to one digital video and one analog video can be output simultaneously. table 7.2 shows pinout definitions of the video output interface. t a b l e 7 . 1 w 9 9 6 1 c f v i d e o o u t p u t m o d e s p w o n _ 1 5 p w o n _ 3 - 2 d i g i t a l v i d e o o u t p u t m o d e a n a l o g v i d e o o u t p u t m o d e 0 0x 8-bit ycbcr rgb 0 10 8-bit ycbcr composite 0 11 8-bit ycbcr s-video + composite
W9961CF - 33 - 1 0x 8-bit rgb rgb 1 10 8-bit rgb composite 1 11 8-bit rgb s-video + composite
W9961CF - 34 - t a b l e 7 . 2 w 9 9 6 1 c f v i d e o o u t p u t i n t e r f a c e p i n a s s i g n m e n t p w o n _ 1 5 , 3 - 2 0 0 x 0 1 0 0 1 1 1 0 x 1 1 0 1 1 1 pin 171 pclk pclk pclk pclk pclk pclk pin 170 ycbcr7 ycbcr7 ycbcr7 rgb7 rgb7 rgb7 pin 168 ycbcr6 ycbcr6 ycbcr6 rgb6 rgb6 rgb6 pin 167 ycbcr5 ycbcr5 ycbcr5 rgb5 rgb5 rgb5 pin 157 ycbcr4 ycbcr4 ycbcr4 rgb4 rgb4 rgb4 pin 154 ycbcr3 ycbcr3 ycbcr3 rgb3 rgb3 rgb3 pin 153 ycbcr2 ycbcr2 ycbcr2 rgb2 rgb2 rgb2 pin 152 ycbcr1 ycbcr1 ycbcr1 rgb1 rgb1 rgb1 pin 151 ycbcr0 ycbcr0 ycbcr0 rgb0 rgb0 rgb0 pin 156 vsync vsync vsync vsync vsync vsync pin 155 hsync hsync hsync hsync hsync hsync pin 128 dem dem dem pin 160 r cp0 cp0 r cp0 cp0 pin 159 g cp1 y g cp1 y pin 158 b cp2 c b cp2 c note 1. analog video output signals (cp0/r, cp1/y/g, and cp2/c/b) can be disabled by resetting pwon_8-6 to 000. note 2. digital video output signals (pclk, vsync, hsync, dem, and p[7:0]) can be disabled by resetting vpostcr_1 to 0 to tri-state these signals. note 3. p[7:0] and dem are re-defined for internal memory test and will not be tri-stated by vpostcr_1 when the chip is in test mode (pwon_14-12 111). note 4. pclk is derived from voclk as shown below: pclk voclk pclk voclk ff ff discr = = ? , _ , / if in 8 - bit ycbcr mode (pwon_15 = 0) if in 8 - bit rgb mode (pwon_15 = 1) 15 8 256 2
W9961CF - 35 - 7 . 4 r i s c m i c r o p r o c e s s o r p m 5 k x 2 2 p c c t l i n t c t l i n s t r u c t i o n d e c o d e r e x e c u t i o n g r 3 2 x 1 6 a l u w b a r b r i s c i n t e r f a c e d m 1 k x 1 6 v i d e o m e m o r y e n g i n e s h o s t i n t e r f a c e c o n t r o l l e r f i g u r e 7 . 6 r i s c m i c r o p r o c e s s o r b l o c k d i a g r a m the risc microprocessor provides the following: ? four-stage instruction pipeline ? 16-bit integer arithmetic logic unit (alu) ? 5k 22 bits program memory (pm) ? 1k 16 bits data memory (dm) ? 32 16 bits three-port (2-read/1-write) register file figure 7.6 is the block diagram of the risc microprocessor. 7 . 4 . 1 r i s c p i p e l i n e s t a g e s the risc has a four-stage instruction pipeline; each stage takes one mclk cycle. the four pipeline stages are: ? if - instruction fetch ? dec - instruction decoding ? exe - instruction execution ? wb - write back
W9961CF - 36 - once the pipeline has been filled, four instructions are executed simultaneously. the execution of each instruction takes at least four mclk cycles. an instruction can take longer, for example, if the required data is not in the dm, register file, or engine registers, the data must be retrieved from the video memory. 7 . 4 . 2 a d d r e s s s p a c e s the internal risc provides two address spaces: ? program memory (pm) address space ? data memory (dm) address space 7 . 4 . 2 . 1 p r o g r a m m e m o r y a d d r e s s s p a c e the pm address is 13 bits wide, and data is 22 bits wide. the built-in pm size is 5k 22 bits. figure 7.7 shows the pm address space. the risc always starts from pm address 0000h after it is enabled. 7 . 4 . 2 . 2 d a t a m e m o r y a d d r e s s s p a c e the dm address space is used for risc access to engine registers, internal dm, and external dram. all engine registers and internal dm can be accessed by the risc by using the dm address space. all dram data (maximum 4 mbytes), except the lower 1.5k words, can be accessed by the risc. the lower 1.5k words dram data can not be accessed by the risc because that the lower 1.5k dm address space is used for engine registers and internal dm accesses. figure 7.8 shows the dm address space. the dm address is 21 bits wide, and data is 16 bits wide. table 7.3 shows the 21-bit dm address, which is composed of a 5-bit segment register (dmsa) and a 16-bit address indicated by the load or store instruction. the 5-bit segment register is a write-only register which can be programmed through the segs imm5 instruction.
W9961CF - 37 - b o o t i n g 0000h 0001h 001fh i n t e r r u p t v e c t o r a d d r e s s s p a c e 0000h 0020h 13ffh 22 bits m a i n p r o g r a m f i g u r e 7 . 7 p r o g r a m m e m o r y a d d r e s s s p a c e 000000h 000600h 1fffffh 16 bits e x t e r n a l d r a m 0001ffh 000200h 0005ffh e n g i n e r e g i s t e r s i n t e r n a l d m f i g u r e 7 . 8 d a t a m e m o r y a d d r e s s s p a c e t a b l e 7 . 3 d a t a m e m o r y a d d r e s s m a p p i n g
W9961CF - 38 - 20 16 15 0 dmsa[4:0] 16-bit dm address indicated by the load or store instruction 7 . 4 . 3 r i s c r e g i s t e r s the internal risc provides the following registers: ? 32 16-bit general purpose registers ? 2 registers that hold the results of integer multiply and add (mula) and divide (div) operations ? 4 shadow registers that store current status at if stage (pc0), dec stage (ir0_l and ir0_h), and exe stage (mpz0) during a call procedure or an interrupt service. 7 . 4 . 3 . 1 g e n e r a l r e g i s t e r s the 32 general purpose registers provide general resources for all computation. figure 7.9 shows the 32 general registers (r0 ~ r31). r0 has assigned functions: when r0 is used as a source operand, it provides zero value, when r0 is used as the destination register, the result is discarded. r 0 r 1 r 2 r 0 r 3 0 r 3 1 . . . 1 5 0 f i g u r e 7 . 9 r i s c g e n e r a l r e g i s t e r s 7 . 4 . 3 . 2 s h a d o w r e g i s t e r s there are four shadow registers, pc0, ir0_l, ir0_h, and mpz0, which store current status at pipeline stages to eliminate the state save and restore time in a call subroutine or an interrupt service. the behavior of the shadow registers is described below. before entering call subroutine or interrupt service: current status at if/dec/exe pipeline stages are stored into shadow registers in one cycle. when executing ret instruction: contents of shadow registers are restored at if/dec/exe pipeline stages
W9961CF - 39 - depth of the shadow registers is two, which enables a nested interrupt in a call subroutine. 7 . 4 . 4 r i s c i n t e r r u p t h a n d l i n g there are 31 interrupt vectors stored on top of the pm, each points to the entry of an interrupt service routine. the first 15 interrupt vectors (0001h~00fh) are used for engine interrupts. the last 16 interrupt vectors (0010h~001fh) are used for dma tc interrupts. these interrupt vectors are shown in table 7.4. t a b l e 7 . 4 r i s c i n t e r r u p t v e c t o r s v e c t o r e n g i n e d e s c r i p t i o n 0000h main program starting address 0001h me me complete interrupt 0002h mc mc complete interrupt 0003h dct/idct (d) idct complete interrupt 0004h dct/idct (e) dct complete interrupt 0005h vpre video capture complete interrupt 0006h vpre pre-filter complete interrupt 0007h vle vle fifo full interrupt 0008h timer timer dtr interrupt 0009h timer timer etr interrupt 000ah timer timer tr interrupt 000bh vpost post-filter complete interrupt 000ch dbf deblocking filter complete interrupt 000dh vlpio vld complete interrupt 000eh vlpio bch frame un-lock, encode output fifo full, encode input fifo empty, or decode input fifo empty interrupt (note 1) 000fh vlpio vld run-level block error interrupt 0010h mc dma tc interrupt for mc input 0011h me dma tc interrupt for search window 0012h me dma tc interrupt for current macro block 0013h mc dma tc interrupt for mc output 0014h dct/idct dma tc interrupt for dct input 0015h dct/idct dma tc interrupt for idct output of decoding 0016h dct/idct dma tc interrupt for idct output of encoding 0017h vlpio dma tc interrupt for encoding bitstream 0018h vlpio dma tc interrupt for decoding bitstream 0019h vlpio dma tc interrupt for bitstream from pci fifo 001ah dbf dma tc interrupt for deblocking filter data in/out 001bh me dma tc interrupt for predicted macro block 001ah ~ 001fh reserved note 1. controlled by bits 11-8 of the pio control register (piocr). when an interrupt occurs, program counter jumps to the interrupt service routine pointed by the corresponding interrupt vector. risc also disables the other interrupt inputs and stores current program counter, instruction, and execution status at if, dec, and exe stages into the shadow registers.
W9961CF - 40 - in the interrupt service routine, the interrupt vector register (ivec) or fdma tc status register (tcsr) must be read at first to acknowledge the interrupt. at the end of the service routine, an ei instruction must be used to re-enable interrupt, then a ret instruction, which restores risc pipeline with the shadow registers, is used to return to the main program.
W9961CF - 41 - 7 . 5 i n t c ( i n t e r r u p t c o n t r o l l e r ) a n d r i s c i n t i r e q [ 1 5 : 0 ] i n t e r r u p t q u e u e i m s k a c k [ 1 5 : 0 ] i n t v e c [ 3 : 0 ] t r i g g e r t r i g [ 1 5 : 0 ] m u x m o d e t r i g _ a c k [ 1 5 : 0 ] f i g u r e 7 . 1 0 i n t c b l o c k d i a g r a m the interrupt controller provides 16 interrupt channels that are used for engine interrupts to the risc. it supports two interrupt modes: interrupt and trigger modes. in interrupt mode, the intc responds with acknowledgment signal when an interrupt is generated via ireq[15:0] by the engine, timer, or external interrupt from isa-like bus. in trigger mode, the risc first triggers a specific engine to operate via trig_ack[15:0] by programming the software trigger register (stg). once the engine completes operation, it interrupts the risc via ireq[15:0]. each channel can operate with only one specific mode as shown in table 7.5. the W9961CF can operate correctly only when the trigger mode register (tmod) is programmed with a 181fh or 185fh value. t a b l e 7 . 5 i n t e r r u p t c h a n n e l s c h a n n e l e n g i n e m o d e d e s c r i p t i o n 0 reserved 1 me trig trigger mb motion estimation 2 mc trig trigger current block motion compensation 3 dct/idct trig trigger current block idct 4 dct/idct trig trigger current block dct 5 vpre intr video capture complete interrupt 6 vpre trig/intr trigger pre-filter, or pre-filter complete interrupt (note 1) 7 vletco intr vle fifo full interrupt 8 timer intr timer dtr interrupt 9 timer intr timer etr interrupt a timer intr timer tr interrupt b vpost trig trigger post-filter c dbf trig trigger deblocking filter d vlpio intr vld complete interrupt e vlpio intr bch frame un-lock, encode output fifo full, encode input fifo empty, or decode input fifo empty interrupt (note 2)
W9961CF - 42 - f vlpio intr vld run-level block error interrupt note 1. pre-filter can be triggered automatically by the hardware (vccr_7 = 0, channel 6 must be in intr mode) or by the software (vccr_7 = 1, channel 6 must be in trig mode). note 2. controlled by bits 11-8 of the pio control register (piocr). all interrupt channels are maskable by the corresponding bits of the interrupt mask register (imsk). a 16-level interrupt queue is used to buffer interrupt from each channel. an interrupt to the risc will be generated with corresponding interrupt vector when the queue is not empty and the risc is not executing any interrupt service routine. in the interrupt service routine, the risc must read the interrupt vector register (ivec) at first to acknowledge the intc. once acknowledged, current interrupt status of the intc will be cleared and next interrupt request queued in the interrupt queue will be processed when the service routine is completed.
W9961CF - 43 - 7 . 6 t i m e r p r e - s c a l e r 1 / 2 ( n + 1 ) v o c l k e t r i n t e r r u p t t r c o u n t e r 1 6 - b i t t p c o m p a r a t o r e t r 8 - b i t c o u n t e r e t e r c o m p a r a t o r d t r 8 - b i t c o u n t e r d t e r c o m p a r a t o r d t r i n t e r r u p t t r i n t e r r u p t f i g u r e 7 . 1 1 t i m e r b l o c k d i a g r a m the timer provides a 16-bit tr counter for the picture clock frequency (pcf), an 8-bit etr counter for the encoding temporal reference, and an 8-bit dtr counter for the decoding temporal reference. a stable voclk with 27.0 mhz clock frequency is used as clock input for the timer. the picture clock frequency is generated according to the following equation: () () () pcf tp n =?+ + 1 2 1 for example, a picture clock frequency of 30000 / 1001 (approximately 29.97) pictures per second can be achieved by programming n = 04h and tp = 6df8h, and a picture clock frequency of 25 pictures per second can be achieved by programming n = 04h and tp = 83d5h.
W9961CF - 44 - 7 . 7 f d m a c o n t r o l l e r w r i t e d a t a s t a t e m a c h i n e q u e u e d r e q [ 1 1 : 0 ] m a s k s / w d m a a c k e n g t e m p r e a d d a t a v i d e o m e m o r y d a c k _ [ 1 1 : 0 ] f i g u r e 7 . 1 2 f d m a c o n t r o l l e r b l o c k d i a g r a m the fdma controller supports 12 channels that are used for direct memory access between video memory and hardware engines. the risc first sets up the fdma registers, which contain picture start, engine start, picture size, and transfer size. a 16-level request queue is used to buffer request from each fdma channel. once the dma transfer is complete, the controller interrupts the risc. in addition to accept requests from hardware engines, the fdma also responds to request that are initiated by software. software may initiate a dma service request by programming a channel value into the software fdma register. software fdma has the highest priority and will be serviced immediately when the fdma engine is ready. fdma channels are listed in table 7.6. t a b l e 7 . 6 f d m a c h a n n e l s c h a n n e l e n g i n e a d d r e s s i n g m o d e r / w d e s c r i p t i o n 0 mc w block in for mc 1 me w block in for search window of me 2 me w block in for current macro block 3 mc r block out for by-pass filter 4 dct/idct w block in for dct 5 dct/idct r block out for decoder re-construct 6 dct/idct r block out for encoder re-construct 7 pio linear demand w bch encoder bitstream in 8 pio linear demand w decoder bitstream in 9 pio linear demand r/w encoder bitstream in/out, bch out a dbf r/w deblocking filter data in/out b me r block out for predicted macro block note 1. r: engines to video memory; w: video memory to engines.
W9961CF - 45 - 7 . 7 . 1 f d m a t r a n s f e r m o d e s the fdma supports two transfer modes: block and demand. a 16-level request queue is used to buffer request from each fdma channel. each channel has associated with it a mask bit which can be set to disable the incoming dreq. an unrestricted mode is also supported when the picture start is out of picture boundary, where an edge pixel is used instead. in block transfer mode the fdma is activated by dreq to continue making transfers during the service until a tc is encountered. the fdma ignores dreq of that channel during the service. in demand transfer mode the fdma is activated by dreq to continue making transfers during the service until a tc is encountered, or until dreq goes inactive. thus transfers may continue until the hardware engine has exhausted its data capacity. after the hardware engine has had a chance to catch up, the fdma service is reestablished by means of a dreq. during the time between services, the intermediate values of address and word count are stored in the temporary registers. 7 . 7 . 2 f d m a t r a n s f e r t y p e s two transfer types are supported: read and write. read transfers move data from a hardware engine to video memory. write transfers move data from video memory to a hardware engine. 7 . 7 . 3 f d m a p r o g r a m m i n g the fdma supports two addressing modes: block and linear. normally, block addressing is used by block transfer modes, and linear addressing is by demand transfer modes. b l o c k t r a n s f e r m o d e w i t h b l o c k a d d r e s s i n g p r o g r a m m i n g refer to figure 7.13. programming sequence is: 1. fdma mode register: lin = 0, dmd = 0, r/w_ = 0 or 1 2. transfer size registers: ew = 3, eh = 3, transfer size = (ew + 1) (eh + 1) = 16 3. picture size registers: pw = 9, ph = 9 4. frame memory start address: fmsa = 64, physical memory start address (dword) = 64 64 / 4 = 1024 5. picture start registers: psx = 3, psy = 2 6. start to calculate finit = psy ( pw+1) + psx + fmsa = 2 ( 9+1 ) + 3 + 1024 = 1047 7. engine start registers: esx = 1, esy = 1 8. enable dmask d e m a n d t r a n s f e r m o d e w i t h l i n e a r a d d r e s s i n g p r o g r a m m i n g refer to figure 7.14. programming sequence is: 1. fdma mode register: lin = 1, dmd = 1, r/w_ = 0 or 1 2. transfer size registers: ew = 100, eh = 1, transfer size = eh 2 9 + (ew + 1) = 613 3. picture size registers: pw = 9, ph = 9 4. frame memory start address: fmsa = 64, physical memory start address (dword) = 64 64 / 4 = 1024 5. picture start registers: psx = 15, psy = 1 6. start to calculate finit = psy ( pw+1) + psx + fmsa = 1 ( 9+1 ) + 15 + 1024 = 1049
W9961CF - 46 - 7. engine start registers: esx = 0, esy = 0 8. enable dmask 0000 32 bits v i d e o m e m o r y (3,2) psy psx pw ph finit =1047 1050 1057 1060 1067 1070 1077 1080 p i c t u r e (1,1) esy esx ew+1 eh+1 e n g i n e (0,0) (9,9) 1047 2 3 1 1 1048 2 4 1 2 1049 2 5 1 3 1050 2 6 1 4 1057 3 3 2 1 1058 3 4 2 2 1059 3 5 2 3 1060 3 6 2 4 1067 4 3 3 1 1068 4 4 3 2 1069 4 5 3 3 1070 4 6 3 4 1077 5 3 4 1 1078 5 4 4 2 1079 5 5 4 3 1080 5 6 4 4 dram address picture x y engine x y dram address picture x y engine x y pw = 9 ph = 9 psx = 3 psy =2 ew = 3 eh = 3 esx = 1 esy = 1 f i g u r e 7 . 1 3 b l o c k t r a n s f e r m o d e w i t h b l o c k a d d r e s s i n g 0000 32 bits v i d e o m e m o r y finit =1049 1661 0 612 e n g i n e
W9961CF - 47 - f i g u r e 7 . 1 4 d e m a n d t r a n s f e r m o d e w i t h l i n e a r a d d r e s s i n g
W9961CF - 48 - 7 . 8 h o s t i n t e r f a c e c o n t r o l l e r p c i c o n f i g u r a t i o n p c i c o n t r o l i n t a # i n t e r r u p t r e q u e s t s p c i s l a v e c o n t r o l i n t e r r u p t c o n t r o l a d d r e s s d a t a m u x / d e m u x a d [ 3 1 : 0 ] p c i a d d r e s s p c i d a t a f i g u r e 7 . 1 5 h o s t i n t e r f a c e c o n t r o l l e r b l o c k d i a g r a m the W9961CF support a glueless interface for a 32-bit pci bus. the pci configuration register space occupies 256 bytes. the W9961CF supports or returns 0 for the first 64 bytes region. refer to section 8.1 for a detailed description of the pci configuration space supported by the W9961CF. 7 . 8 . 1 p c i a d d r e s s s p a c e s the W9961CF provides three addressing spaces starting at the base addresses specified in the pci base address 1, 2, and 3 registers. address space starting at base address 1 is used for pci accesses of W9961CF control registers, risc data memory, and risc program memory. address space starting at base address 2 is used for video memory accesses. address space starting at base address 3 is used for isa-like bus interface accesses. the W9961CF control registers, dm, pm, and video memory can be dword-accessed only, while the isa-like bus interface can be byte- accessed only. 7 . 8 . 2 p c i i n t e r r u p t c o n t r o l there are 16 interrupt sources which can generate inta# to pci bus. channels 0 ~ 11 are reserved for risc asserting interrupt to the host. channel 12 is used for the external isa-like bus interrupt. channel 14 is used for the fdma tc interrupt. channel 15 is used for the risc interrupt. all the 16 interrupt sources can be masked by programming a 1 to the corresponding bit of the xmsk register. when inta# is asserted by the W9961CF, the host has to read the xsts register to know which interrupt channel is active. t a b l e 7 . 7 p c i i n t e r r u p t c h a n n e l s c h a n n e l x i n t _ i n d e s c r i p t i o n 0 ~ 11 1 reserved for risc 12 extint external isa-like bus interrupt 13 not used
W9961CF - 49 - 14 tc_out fdma tc output 15 int intc interrupt
W9961CF - 50 - 7 . 9 d r a m c o n t r o l l e r m a m u x m s i g m d / b e m u x a r b i t r a t i o n & s t a t e m a c h i n e 2 0 - b i t a d d r e s s f r o m f d m a , r i s c , p c i , v p r e , v p o s t 3 2 - b i t d a t a a n d 4 - b i t b e s f r o m f d m a , r i s c , p c i , v p r e , v p o s t d r a m r e q u e s t / c y c l e f r o m / t o f d m a , r i s c , p c i , v p r e , v p o s t b a , m a [ 1 1 : 0 ] m d [ 3 1 : 0 ] r a s [ 1 : 0 ] # / c s [ 1 : 0 ] # , c a s [ 3 : 0 ] # / d q m [ 3 : 0 ] # , w e # , o e # / c k e , s r a s # , s c a s # , s m c l k m d i [ 3 1 : 0 ] f i g u r e 7 . 1 6 d r a m c o n t r o l l e r b l o c k d i a g r a m a 32-bit sdram or edo dram interface is supported for W9961CF. the dram controller serves as video memory arbiter and interface controller for video memory access. 7 . 9 . 1 v i d e o m e m o r y a r b i t r a t i o n the video memory arbiter helps to maximize performance by orchestrating memory access requests from internal engines. three priority levels are defined for these requests: ? first priority: dram refresh request, sdram mode register write request ? second priority: video capture request, graphics display request, va1 request, va2 request ? third priority: fdma request, risc request, pci request, pre-filter request, post-filter request first priority requests are for dram refresh and sdram mode control. second priority requests are for video input and video output, which should be real-time processed. a fifo status is provided by each request such that the dram controller arbitrates according to these fifo status to prevent any video data loss. third priority requests are for video coding/decoding and bitstream transfers. priorities of them can be either risc, pre-filter, fdma, post-filter, then pci access, or pci, risc, pre-filter, fdma, then post- filter access.
W9961CF - 51 - 7 . 9 . 2 d r a m i n t e r f a c e the dram controller provides many programmable controls for the dram operations which include: ? dram type: supports sdram and edo dram ? dram address: programmable 9-bit (256k edo dram), 10-bit (1m edo dram or 256k sdram), and 12-bit (1m sdram) address ? dram timing: adjustable trp, trcd, tras, and tcas timings ? dram refresh: 1 ~ 8 refresh cycles per scan line ? sdram read latency: 1 ~ 3 clocks ? sdram burst type: sequential or interleaved ? sdram burst length: 1, 2, 4, 8, or full page table 7.8 shows the interface signals for sdram and edo dram. t a b l e 7 . 8 s d r a m a n d e d o d r a m i n t e r f a c e s i g n a l s p i n n a m e 2 5 6 k e d o d r a m 1 m e d o d r a m 2 5 6 k s d r a m 1 m s d r a m md[31:0] md[31:0] md[31:0] md[31:0] md[31:0] ma[10:0] ma[8:0] ma[9:0] ma[8:0] ma[10:0] ba ba ba ras[1:0]#/cs[1:0]# ras[1:0]# ras[1:0]# cs[1:0]# cs[1:0]# cas[3:0]#/dqm[3:0] cas[3:0]# cas[3:0]# dqm[3:0] dqm[3:0] oe#/cke oe# oe# cke cke we# we# we# we# we# sras# sras# sras# scas# scas# scas# smclk smclk smclk
W9961CF - 52 - 7 . 1 0 i s a - l i k e b u s i n t e r f a c e a n d g p i o s 7 . 1 0 . 1 i s a - l i k e b u s i n t e r f a c e the isa-like bus provides a 13-bit address bus, an 8-bit data bus, one write strobe signal, one read strobe signal, and one interrupt input as interface with an external co-processor. it can be accessed directly by the host through pci bus, or indirectly by the host or risc via the isa-like bus control registers as described in table 7.9. the external interrupt input can be either level-triggered (isaint_2 = 1) or falling edge-triggered (isaint_2 = 0). t a b l e 7 . 9 i s a - l i k e b u s a c c e s s m o d e s m o d e a d d r e s s s p a c e d e s c r i p t i o n pci direct access ba3 000000h ~ 00003fh 64-byte address space, byte-access only. isa-like bus signals are automatically generated when a pci i/o read or write command to this address space is issued. pci indirect access ba1 0040h ~ 004ch 8k-byte address space. isa-like bus signals are generated via the isa-like bus control registers. risc indirect access risc dm 000010h ~ 000013h 8k-byte address space. isa-like bus signals are generated via the isa-like bus control registers. 7 . 1 0 . 2 g p i o the W9961CF provides 5 general purpose i/o ports. each gpio can be configured as an input or output port, depending on the corresponding bit of the gpio output enable register (gpiooe).
W9961CF - 53 - 7 . 1 1 p l l ( p h a s e l o c k e d l o o p ) 1 ( m + 1 ) p h a s e d e t e c t c h a r g e p u m p l o o p f i l t e r v c o 1 ( n 2 + 1 ) 1 2 k f r e f f o u t 1 2 n 1 f i g u r e 7 . 1 7 p l l b l o c k d i a g r a m the built-in pll frequency synthesizer is used to generate the internal mclk clock. a stable reference frequency is required by dividing voclk by 2 (voclk/2 with typical 13.5 mhz frequency) as the reference clock input for the pll. the output frequency resulting from a given set of parameters is specified by the following formula: f n m f out n k ref = +) (+) 221 12 1 ( where m is a 6-bit value that can be programmed with any integer value from 1 to 63, n1 is a 2-bit value that can be programmed with any integer value from 0 to 3, n2 is a 6-bit value that can be programmed with any integer value from 1 to 127, and k is a 2-bit value that can be programmed with any integer value from 0 to 3.
W9961CF - 54 - 8 e l e c t r i c a l c h a r a c t e r i s t i c s 8 . 1 a b s o l u t e m a x i m u m r a t i n g s t a b l e 8 . 1 a b s o l u t e m a x i m u m r a t i n g s ambient temperature 0 c to 70 c storage temperature -40 c to 125 c dc supply voltage -0.5v to 7v i/o pin voltage with respect to vss -0.5v to vdd + 0.5v 8 . 2 d c c h a r a c t e r i s t i c s 8 . 2 . 1 d a c d c c h a r a c t e r i s t i c s t a b l e 8 . 2 d a c d c c h a r a c t e r i s t i c s p a r a m e t e r m i n . t y p . m a x . u n i t power supply avdd, tvavdd 3.0 3.3 3.6 v dac coding binary tvdac resolution 9 9 9 bits integral linearity error 1 lsb differential linearity error 1 lsb gray scale error 5 %gray lsb size 69.1 a dac-to-dac matching 2 5 % output compliance -1.0 1.5 v gray scale current range 35 ma output impedance 10k ? output capacitance (f = 1 mhz; i out = 0 ma) 30 pf monotonicity guaranteed internal v ref 1.06 v power supply reject ratio (f = 1 khz) 0.5 %%avdd note 1. measured with vref = 1.06 v, rset = 100 ? .
W9961CF - 55 - l e v e l white yellow cyan green magenta red blue black blank sync m a v i r e d a c d a t a 26.68 1.000 100.0000 400 89.4550 370 72.3425 321 61.7972 291 45.7025 245 35.1575 215 18.0450 166 9.07 0.340 7.5000 136 7.60 0.285 0.0000 114 0.00 0.000 -40.0000 0 sync level blank level black level white level n o t e : nominal rset, 75 ? doubly-terminated load, with setup on. smpte 170m levels are assumed. 100% saturation color bars (100/7.5/100/7.5). f i g u r e 8 . 1 5 2 5 - l i n e ( n t s c / p a l - m ) y ( l u m i n a n c e ) o u t p u t w a v e f o r m l e v e l white yellow cyan green magenta red blue black blank sync m a v i r e d a c d a t a 26.68 1.000 100.0000 400 368 316 284 236 204 8.00 0.300 0.0000 120 8.00 0.300 0.0000 120 0.00 0.000 -43.0000 0 sync level blank level black level white level n o t e : nominal rset, 75 ? doubly-terminated load, with setup off. ccir 624 levels are assumed. 100% saturation color bars (100/0/100/0). 152 f i g u r e 8 . 2 6 2 5 - l i n e ( p a l - b , d , g , h , n ) y ( l u m i n a n c e ) o u t p u t w a v e f o r m
W9961CF - 56 - c o l o r cyan/red green/magenta yellow/blue burst high blank burst low yellow/blue green/magenta cyan/red m a v i r e d a c d a t a 28.21 1.058 58.5000 423 54.6000 41.4000 20.0000 313 0.0000 256 -20.0000 199 -41.4000 13.27 0.498 -54.6000 5.93 0.222 -58.5000 89 n o t e : nominal rset, 75 ? doubly-terminated load, with setup on. smpte 170m levels are assumed. 100% saturation color bars (100/7.5/100/7.5). yellow white cyan green magenta red blue black blank level 17.07 0.640 20.88 0.783 color burst (9 cycles) f i g u r e 8 . 3 5 2 5 - l i n e ( n t s c / p a l - m ) c ( c h r o m i n a n c e ) o u t p u t w a v e f o r m c o l o r cyan/red green/magenta yellow/blue burst high blank burst low yellow/blue green/magenta cyan/red m a v i r e d a c d a t a 28.88 1.083 63.2500 433 59.0500 44.7500 21.5000 316 0.0000 256 -21.5000 196 -44.7500 13.07 0.490 -59.0500 5.27 0.198 -63.2500 79 n o t e : nominal rset, 75 ? doubly-terminated load, with setup off. ccir 624 levels are assumed. 100% saturation color bars (100/0/100/0). yellow white cyan green magenta red blue black blank level 17.07 0.640 21.08 0.791 color burst (10 cycles) f i g u r e 8 . 4 6 2 5 - l i n e ( p a l - b , d , g , h , n ) c ( c h r o m i n a n c e ) o u t p u t w a v e f o r m
W9961CF - 57 - l e v e l white black blank sync m a v i r e d a c d a t a 26.68 1.000 100.0000 400 9.07 0.340 7.5000 136 7.60 0.285 0.0000 114 0.00 0.000 -40.0000 0 sync level blank level black level white level n o t e : nominal rset, 75 ? doubly-terminated load, with setup on. smpte 170m levels are assumed. 100% saturation color bars (100/7.5/100/7.5). peak chroma (high) 32.55 1.221 130.8333 488 burst low 3.80 0.143 -20.0000 57 burst high 11.41 0.423 20.0000 171 color burst (9 cycles) yellow white cyan green magenta red blue black peak chroma (low) 3.20 0.120 -23.3333 48 f i g u r e 8 . 5 5 2 5 - l i n e ( n t s c / p a l - m ) c o m p o s i t e v i d e o o u t p u t w a v e f o r m l e v e l white black blank sync m a v i r e d a c d a t a 26.68 1.000 100.0000 400 8.00 0.300 0.0000 120 8.00 0.300 0.0000 120 0.00 0.000 -43.0000 0 sync level blank level black level white level n o t e : nominal rset, 75 ? doubly-terminated load, with setup off. ccir 624 levels are assumed. 100% saturation color bars (100/0/100/0). peak chroma (high) 32.88 1.233 133.3333 493 burst low 4.00 0.150 -21.5000 60 burst high 12.01 0.450 21.5000 180 color burst (10 cycles) yellow white cyan green magenta red blue black peak chroma (low) 1.80 0.068 -33.3333 27 f i g u r e 8 . 6 6 2 5 - l i n e ( p a l - b , d , g , h , n ) c o m p o s i t e v i d e o o u t p u t w a v e f o r m
W9961CF - 58 - 8 . 2 . 2 d i g i t a l d c c h a r a c t e r i s t i c s t a b l e 8 . 3 d i g i t a l d c c h a r a c t e r i s t i c s s y m b o l p a r a m e t e r c o n d i t i o n s m i n . m a x . u n i t vdd5v 5v power supply 5.25 5.75 v vdd 3v power supply 3.0 3.6 v v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 v v ol output low voltage vss+0.4 v v oh output high voltage 2.4 v i il input low leakage current v in = 0.4v +70 a i ih input high leakage current v in = 2.4v -70 a i up pull-up current v in = 0v -133.2 -400.6 a c io pin capacitance 10 pf i dd active current f mclk = 70 mhz 500 ma
W9961CF - 59 - 8 . 3 a c c h a r a c t e r i s t i c s 8 . 3 . 1 d a c a c c h a r a c t e r i s t i c s t a b l e 8 . 4 d a c a c c h a r a c t e r i s t i c s p a r a m e t e r m i n . t y p . m a x . u n i t luminance bandwidth fin/2 mhz chrominance bandwidth 1.3 mhz hue accuracy 1.5 3 color saturation accuracy 1.5 3 % dac output delay 30 ns dac output rise/fall time 3ns dac output settling time 8ns input clock frequency (fin) 12.27 13.5 14.75 mhz t a b l e 8 . 5 t v m o d e s r e s o l u t i o n a n d c l o c k r a t e m o d e a c t i v e p i x e l s t o t a l p i x e l s t v c l o c k ntsc 720x485 858x525 13.5000 mhz pal-m 720x484 858x525 13.5000 mhz pal-b, d, g, h, n 720x576 864x625 13.5000 mhz 8 . 3 . 2 p l l a c c h a r a c t e r i s t i c s t a b l e 8 . 6 p l l a c c h a r a c t e r i s t i c s p a r a m e t e r m i n . t y p . m a x . u n i t input clock frequency 13.5 mhz input clock duty cycle 40 50 60 % mclk clock frequency 70 mhz mclk clock frequency error 0.5 % mclk clock duty cycle 40 50 60 %
W9961CF - 60 - 8 . 3 . 3 r e s e t t i m i n g a c c h a r a c t e r i s t i c s r s t # t rst t su t h m d [ 1 5 : 0 ] f i g u r e 8 . 7 r e s e t t i m i n g t a b l e 8 . 7 r e s e t t i m i n g s y m b o l p a r a m e t e r c o n d i t i o n s m i n . m a x . u n i t t rst reset pulse width 100 ns t su md[15:0] setup time 20 ns t h md[15:0] hold time 10 ns 8 . 3 . 4 c l o c k a c c h a r a c t e r i s t i c s t high t low t cyc 0.8 v 1.5 v 2.0 v f i g u r e 8 . 8 c l o c k w a v e f o r m t a b l e 8 . 8 c l o c k a c c h a r a c t e r i s t i c s s y m b o l p a r a m e t e r c o n d i t i o n s m i n . m a x . u n i t 1/t cyc pciclk frequency viclk frequency voclk frequency voclk/2 frequency 30 5 26.999 13.499 60 40 30 27.001 15.001 80 mhz mhz mhz mhz mhz
W9961CF - 61 - smclk frequency t high pciclk high time viclk high time voclk high time voclk/2 high time smclk high time pciclk = 33 mhz viclk = 13.5 mhz voclk = 27 mhz voclk/2 = 13.5 mhz smclk = 70 mhz 12 29.6 14.8 29.6 5.7 18 44.5 22.3 44.5 8.6 ns ns ns ns ns t low pciclk low time viclk low time voclk low time voclk/2 low time smclk low time pciclk = 33 mhz viclk = 13.5 mhz voclk = 27 mhz voclk/2 = 13.5 mhz smclk = 70 mhz 12 29.6 14.8 29.6 5.7 18 44.5 22.3 44.5 8.6 ns ns ns ns ns 8 . 3 . 5 i n p u t t i m i n g a c c h a r a c t e r i s t i c s c l k i n p u t t su t h 1.5 v 1.5 v 1.5 v input valid f i g u r e 8 . 9 i n p u t t i m i n g t a b l e 8 . 9 p c i c l k - r e f e r e n c e d i n p u t t i m i n g a c c h a r a c t e r i s t i c s s y m b o l p a r a m e t e r c o n d i t i o n s m i n . m a x . u n i t t su ad[31:0], c/be[3:0]#, frame#, irdy#, idsel 7ns t h ad[31:0], c/be[3:0]#, frame#, irdy#, idsel 7ns t a b l e 8 . 1 0 s m c l k - r e f e r e n c e d i n p u t t i m i n g a c c h a r a c t e r i s t i c s s y m b o l p a r a m e t e r c o n d i t i o n s m i n . m a x . u n i t t su md[15:0] , sd[7:0] setup time 0 ns t h md[15:0] , sd[7:0] hold time 7 ns
W9961CF - 62 - t a b l e 8 . 1 1 v i c l k - r e f e r e n c e d i n p u t t i m i n g a c c h a r a c t e r i s t i c s s y m b o l p a r a m e t e r c o n d i t i o n s m i n . m a x . u n i t t su y[7:0], uv[7:0], hs, vs 5 ns t h y[7:0], uv[7:0], hs, vs 5 ns 8 . 3 . 6 o u t p u t t i m i n g a c c h a r a c t e r i s t i c s c l k o u t p u t d e l a y t val 1.5 v 1.5 v t on t off t r i - s t a t e o u t p u t f i g u r e 8 . 1 0 o u t p u t t i m i n g t a b l e 8 . 1 2 p c i c l k - r e f e r e n c e d o u t p u t t i m i n g a c c h a r a c t e r i s t i c s s y m b o l p a r a m e t e r c o n d i t i o n s m i n . m a x . u n i t t val ad[31:0], trdy# 2 11 ns t on ad[31:0] 2 11 ns devsel#, trdy#, inta#, par, perr#, serr# 211ns t off ad[31:0] 28 ns devsel#, trdy#, inta#, par, perr#, serr# 28 ns t a b l e 8 . 1 3 s m c l k - r e f e r e n c e d o u t p u t t i m i n g a c c h a r a c t e r i s t i c s s y m b o l p a r a m e t e r c o n d i t i o n s m i n . m a x . u n i t t val md[15:0], ma[10:0], ba, ras[1:0]#/cs[1:0]#, cas[1:0]#/dqm[1:0], oe#/cke, we#, sras#, scas# 27ns sa[12:0], sd[7:0], srd#, swr# 2 11 ns t on md[15:0] 2 7 ns
W9961CF - 63 - t off md[15:0] 2 7 ns t a b l e 8 . 1 4 p c l k - r e f e r e n c e d o u t p u t t i m i n g a c c h a r a c t e r i s t i c s s y m b o l p a r a m e t e r c o n d i t i o n s m i n . m a x . u n i t t val hsync, vsync, p[7:0] 10 ns
W9961CF - 64 - 9 p a c k a g e s p e c . the W9961CF is packaged in a 208l qfp (28x28 mm footprint 2.6mm) as shown in figure 9.1. h d d e b e h e y a a s e a t i n g p l a n e l l 1 s e e d e t a i l f d e t a i l f c 1 a 2 1 5 2 5 3 1 0 4 1 0 5 1 5 6 1 5 7 2 0 8 0.10 010 10 0 0.004 1.30 0.70 30.90 30.90 0.50 30.60 30.60 0.30 30.30 30.30 0.051 0.028 1.217 1.217 0.020 1.205 1.205 0.012 1.193 1.193 0.50 28.13 28.13 0.25 0.25 3.35 3.68 28.00 28.00 3.23 27.87 27.87 0.10 0.15 3.10 0.10 1.107 1.107 0.010 0.010 0.132 0.145 1.102 1.102 0.127 0.020 1.097 1.097 0.004 0.006 0.122 0.004 s y m b o l m i n n o m m a x m a x n o m m i n d i m e n s i o n i n i n c h d i m e n s i o n i n m m a b c d e h d h e l y a a l 1 1 2 e 0.008 0.006 0.15 0.20 0.016 0.043 0.024 0.059 0.40 0.60 1.10 1.50 control dimensions are in mm f i g u r e 9 . 1 2 0 8 l q f p ( 2 8 x 2 8 m m f o o t p r i n t 2 . 6 m m ) d i m e n s i o n s
W9961CF - 65 - 1 0 o r d e r i n g i n f o r m a t i o n p a r t n u m b e r p a c k a g e W9961CF 208l qfp h e a d q u a r t e r s n o . 4 , c r e a t i o n r d . i i i , s c i e n c e - b a s e d i n d u s t r i a l p a r k , h s i n c h u , t a i w a n t e l : 8 8 6 - 3 - 5 7 7 0 0 6 6 f a x : 8 8 6 - 3 - 5 7 9 2 6 4 7 h t t p : / / w w w . w i n b o n d . c o m . t w / v o i c e & f a x - o n - d e m a n d : 8 8 6 - 2 - 7 1 9 7 0 0 6 t a i p e i o f f i c e 1 1 f , n o . 1 1 5 , s e c . 3 , m i n - s h e n g e a s t r d . , t a i p e i , t a i w a n t e l : 8 8 6 - 2 - 7 1 9 0 5 0 5 f a x : 8 8 6 - 2 - 7 1 9 7 5 0 2 w i n b o n d e l e c t r o n i c s ( h . k . ) l t d . r m . 8 0 3 , w o r l d t r a d e s q u a r e , t o w e r i i , 1 2 3 h o i b u n r d . , k w u n t o n g , k o w l o o n , h o n g k o n g t e l : 8 5 2 - 2 7 5 1 3 1 0 0 f a x : 8 5 2 - 2 7 5 5 2 0 6 4 w i n b o n d e l e c t r o n i c s n o r t h a m e r i c a c o r p . w i n b o n d m e m o r y l a b . w i n b o n d m i c r o e l e c t r o n i c s c o r p . w i n b o n d s y s t e m s l a b . 2 7 3 0 o r c h a r d p a r k w a y , s a n j o s e , c a 9 5 1 3 4 , u . s . a . t e l : 1 - 4 0 8 - 9 4 3 6 6 6 6 f a x : 1 - 4 0 8 - 9 4 3 6 6 6 8 n o t e : a l l d a t a a n d s p e c i f i c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e .

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