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T48C510 preliminary information rev. a2, 26-feb-01 1 (61) marc4 ? 4-bit mtp universal microcontroller the T48C510 is an multi time programmable (mtp) microcontroller which is pin and functionally compatible to the atmel wireless & microcontrollers? m44c510e mask programmable microcontroller. it contains eeprom, ram, up to 34 digital i/o pins, up to 10 maskable external interrupt sources, 4 maskable internal interrupts, a watchdog timer, interval timer, 2 x 8-bit multifunction timer/counter module and a versatile software configurable on-chip system clock module. features / benefits programmable system clock with prescaler and five different clock sources: ? up to 8-mhz crystal oscillator (system clock) ? 32-khz crystal oscillator ? rc-oscillator fully integrated ? rc-oscillator with external resistor adjustment ? external clock input wide supply-voltage range (2.4 v to 6.2 v) very low halt current 4 kbyte program eeprom, 256 x 4-bit ram 8 hard- and software interrupt priority levels up to 10 external and 4 internal interrupts , bitwise maskable with programmable priority level up to 34 i/o lines i/o ports ? bitwise configurable with combined inter- rupt handling (for serial i/o applications) 2 x 8-bit multifunction timer/counters coded reset and watchdog timer power-on reset and ?brown out? function various power-down modes efficient, hardware-controlled interrupt handling high-level programming language in qforth comprehensive library of useful routines windows 95/nt based development and programmer tools marc4 system clock timer/ counter timer 0 timer 1 master reset te port 0 port 1 port 5 port b sclin i/o bus eeprom ram 4-bit cpu core 4k x 8 bit 256 x 4 bit watch? dog i/o i/o i/o test sleep nrst v dd port 7 port a i/o port 4 i/o interrupt & reset prescaler av dd i/o i/o interrupt i/o interrupt port 6 real time clock oscin oscout melody & buzzer tim1 16536 i/o port c 4444 4 44 4 2 v ss config. eeprom pm figure 1. block diagram
T48C510 rev. a2, 26-feb-01 preliminary information 2 (61) ordering information extended type number package remarks T48C510 ? ils sso44 stick T48C510 ? ilq sso44 taped and reeled 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 sclin bpc 0 bp00 bp12 bp11 bp10 oscin oscout bp01 bp02 bp03 nrst v ss vdd bp43 bp42 bp41 bp40 bpb3 bpb2 bpb1 bpb0 bp70 bp71 bp72 bp73 bp53 bp52 bp51 bp50 tim1 bpa3 bpa2 bpa1 bpa0 te avdd bp61 bp60 21 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 23 24 41 42 43 44 bpc1 bp13 pm bpc3 bpc2 T48C510 figure 2. pin connections sso44-package table 1 pin description name function v dd power supply voltage +2.4 v to +6.2 v av dd analog power supply voltage +2.4 v to +6.2 v v ss circuit ground bp00 ? bp03 4 i/o lines of port 0 ? automatic nibblewise configurable / programmer interface bp10 ? bp13 4 i/o lines of port 1 ? automatic nibblewise configurable bp50 ? bp53 4 i/o lines of high current port 5 ? bitwise configurable bp70 ? bp73 4 i/o lines of high current port 7 ? bitwise configurable bpa0 ? bpa3 4 i/o lines of port a ? bitwise configurable, as inputs to a port monitor module and optional coded reset inputs bpb0 ? bpb3 4 i/o lines of port b ? bitwise configurable i/o and as inputs to a port monitor module bpc0 ? bpc3 4 i/o lines of port c ? bitwise configurable i/o bp60 ? bp61 2 i/o lines of port 6 ? bitwise configurable i/o or as external programmable interrupts bp40 (t0out0) i/o line bp40 of port 4 ? configurable or timer/counter i/o t0out0 bp41 (t0out1) i/o line bp41 of port 4 ? configurable or timer/counter i/o t0out1 bp42 (buz) high current i/o line bp42 of port 4 ? configurable or buzzer output buz bp43 (nbuz) high current i/o line bp43 of port 4 ? configurable or buzzer output nbuz tim1 dedicated i/o for timer 1 sclin external trimming resistor or external clock input oscin 32-khz quartz crystal or 4-mhz quartz crystal input pin oscout 32-khz quartz crystal or 4-mhz quartz crystal output pin te testmode input, used to control the production test modes (internal pull-down) nrst reset input (/output), a logic low on this pin resets the device. an internal watchdog or coded reset can cause a low pulse on this pin. pm mtp program mode enable pin (internal pull-down)
T48C510 preliminary information rev. a2, 26-feb-01 3 (61) table of contents 1 marc4 architecture 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 general description 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 components of marc4 core 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 eeprom 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 ram 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 registers 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 alu 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5 instruction set 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.6 i/o bus 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 interrupt structure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 hardware interrupts 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 software interrupts 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 hardware reset 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 clock generation 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 clock module 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 oscillator circuits and external clock input stage 14 . . . . . . . . . . . . . . . . . . . . . . . . rc-oscillator 1 fully integrated 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external input clock 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rc-oscillator 2 with external trimming resistor 14 . . . . . . . . . . . . . . . . . . . . . . . . . 4-mhz oscillator 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-khz oscillator 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . quartz oscillator configuration 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3 clock management register (cm) 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . system configuration register (sc) 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.4 power-down modes 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.5 clock monitor mode 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 peripheral modules 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 addressing peripherals 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 bidirectional ports 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 bidirectional port 0 and port 1 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 bidirectional port 5, port 7 and port c 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 bidirectional port a and port b with port monitor function 23 . . . . . . . . . . . . . . . . 2.2.4 bidirectional port 6 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 bidirectional port 4 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6 tim1 ? dedicated timer 1 i/o pin 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 interval timers / prescaler 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 interval timer registers 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 watchdog timer 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 timer/counter module (tcm) 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 general timer/counter control registers 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 timer/counter in 16-bit mode 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 timer 0 modes 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 timer 1 modes 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T48C510 rev. a2, 26-feb-01 preliminary information 4 (61) table of contents (continued) 2.6 buzzer module 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 mtp programming 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 noise considerations 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.1 noise immunity 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.2 electromagnetic emission 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 electrical characteristics 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 absolute maximum ratings 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 dc operating characteristics 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 ac characteristics 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 device information 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 pad layout 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 packaging 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 hardware options 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T48C510 preliminary information rev. a2, 26-feb-01 5 (61) 1 marc4 architecture ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ????????????????????? ?? ?? ?? instruction decoder ccr tos alu ram pc rp sp x y program 256 x 4-bit marc4 core clock reset sleep memory bus i/o bus instruction bus reset system clock interrupt controller on ? chip peripheral modules 94 8973 memory figure 3. marc4 core 1.1 general description the functionality, programming and pinning of the T48C510 is compatible with the m44c510e mask pro- grammable microcontroller from atmel wireless & microcontrollers. all on-chip modules are addressed and controlled with exactly the same programming code, so that a program targeted for the m44c510e can be read directly into the T48C510 and will operate in the same fashion. the marc4 microcontroller consists of an advanced stack based 4-bit cpu core and on-chip peripherals. the cpu is based on the harvard architecture with physi- cally separate program memory (eeprom) and data memory (ram). three independent buses, the instruc- tion bus, the memory bus and the i/o bus are used for parallel communication between eeprom, ram and peripherals. this enhances program execution speed by allowing both instruction prefetching, and a simultaneous communication to the on-chip peripheral circuitry. the extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast and efficient processing of hardware events. the marc4 is designed for the high-level programming language qforth. the core includes an expression and a return stack. this architecture allows high-level language pro- gramming without any loss in efficiency or code density. 1.2 components of marc4 core the core contains eeprom, ram, alu, a program counter, ram address registers, an instruction decoder and an interrupt controller. the following sections de- scribe each functional block in more detail: 1.2.1 eeprom the program memory (eeprom) is programmed with the customer application program. the eeprom is ad- dressed by a 12-bit wide program counter, thus predefining a maximum program bank size of 4 kbytes.
T48C510 rev. a2, 26-feb-01 preliminary information 6 (61) eeprom (4k x 8 bit) zero page fffh 1ffh 000h 1f0h 1f8h 010h 018h 000h 008h 020h 1e8h 1e0h scall addresses 140h 180h 040h 0c0h 008h $autosleep $reset int0 int1 int2 int3 int4 int5 int6 int7 1e0h 1c0h 100h 080h zero page 000h figure 4. eeprom map of T48C510 the lowest user eeprom address segment is taken up by a 512-byte zero page which contains predefined start addresses for interrupt service routines and special sub- routines accessible with single-byte instructions (scall). the corresponding memory map is shown in figure 4. look-up tables of constants can also be held in eeprom and are accessed via the marc4 ? s built-in table instruction. 1.2.2 ram the marc4 contains 256 x 4-bit wide static random access memory (ram). it is used for the expression stack, the return stack and data memory for variables and arrays. the ram is addressed by any of the four 8-bit wide ram address registers sp, rp, x and y. expression stack the 4-bit wide expression stack is addressed with the expression stack pointer (sp). all arithmetic, i/o and memory reference operations take their operands from, and return their result to the expression stack. the marc4 performs the operations with the top of stack items (tos and tos-1). the tos register contains the top element of the expression stack and works in the same way as an accumulator. this stack is also used for passing parameters between subroutines and as a scratch pad area for temporary storage of data. return stack the 12-bit wide return stack is addressed by the return stack pointer (rp). it is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. the return stack can also be used as a temporary storage area. the marc4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. the two stacks within the ram have a user- definable location and maximum depth. 1.2.3 registers the marc4 controller has seven programmable regis- ters and one condition code register. they are shown in figure 6. program counter (pc) the program counter (pc) is a 12-bit register that contains the address of the next instruction to be fetched from the eeprom. instructions currently being executed are de- coded in the instruction decoder to determine the internal micro operations. for linear code (no calls or branches) the program counter is incremented with every instruc- tion cycle. if a branch, call, return instruction or an interrupt is executed, the program counter is loaded with a new address. the program counter is also used with the table instruction to fetch 8-bit wide constants.
T48C510 preliminary information rev. a2, 26-feb-01 7 (61) ??? ??? ???? ???? ??????? ??????? ????? ????? ????? ????? ????? ????? ????? ??? ??? ram fch 00h autosleep ffh 03h 04h x y sp rp tos ? 1 expression stack return stack global variables ram address register: 07h (256 x 4-bit) global variables 4-bit tos tos ? 1 tos ? 2 30 sp expression stack return stack ????? ????? 0 11 12-bit rp v 94 8975 figure 5. ram map ram address registers the ram is addressed with the four 8-bit wide ram address registers: sp, rp, x and y. these registers allow access to any of the 256 ram nibbles. expression stack pointer (sp) the stack pointer (sp) contains the address of the next-to- top 4-bit item (tos-1) of the expression stack. the pointer is automatically preincremented if a nibble is moved onto the stack, or postdecremented if a nibble is removed from the stack. every postdecrement operation moves the item (tos-1) to the tos register before the sp is decremented. after a reset the stack pointer has to be initialized with ? >sp s0 ? to allocate the start address of the expression stack area. return stack pointer (rp) the return stack pointer points to the top element of the 12-bit wide return stack. the pointer automatically pre- increments if an element is moved onto the stack or it postdecrements if an element is removed from the stack. the return stack pointer increments and decrements in steps of 4. this means that every time a 12-bit element is stacked, a 4-bit ram location is left unwritten. these locations are used by the qforth compiler to allocate 4-bit variables. after a reset, the return stack pointer has to be initialized with ? >rp fch ? . ram address register ( x and y ) the x and y registers are used to address any 4-bit item in the ram. a fetch operation moves the addressed nibble onto the tos. a store operation moves the tos to the addressed ram location. by using either the preincrement or postdecrement, addressing mode arrays in the ram can be compared, filled or moved. top of stack ( tos ) the top of stack register is the accumulator of the marc4. all arithmetic/logic, memory reference and i/o operations use this register. the tos register receives data from the alu, eeprom, ram or i/o bus. condition code register ( ccr ) the 4-bit wide condition code register contains the branch, the carry and the interrupt-enable flag. these bits indicate the current state of the cpu. the ccr flags are set or reset by alu operations. the instructions set_bcf, tog_bf, ccr! and di allow direct manipulation of the condition code register. carry/borrow ( c ) the carry/borrow flag indicates that borrow or carry out of arithmetic logic unit ( alu ) occurred during the last arithmetic operation. during shift and rotate operations, this bit is used as a fifth bit. boolean operations have no affect on the c flag. branch ( b ) the branch flag controls the conditional program branch- ing. should the branch flag have been set by a previous instruction, a conditional branch will cause a jump. this flag is affected by arithmetical, logical, shift, and rotate operations. interrupt enable ( i ) the interrupt-enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. after a reset, or on executing the
T48C510 rev. a2, 26-feb-01 preliminary information 8 (61) di instruction, the interrupt-enable flag is reset, thus dis- abling all interrupts. the core will not accept any further interrupt requests until the interrupt-enable flag has been set again either by executing an ei, rti or sleep instruc- tion. tos ccr 0 3 0 3 0 7 0 7 7 0 11 rp sp x y pc ?? b i program counter return stack pointer expression stack pointer ram addr ess r egister (x) ram addr ess r egister (y) top of stack register condition code register carry / borrow branch interrupt enable reserved 0 7 00 c 0 figure 6. programming model
T48C510 preliminary information rev. a2, 26-feb-01 9 (61) 1.2.4 alu ?? ?? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ????? ????? ????? ????? ????? ????? ????? ????? ????? ???????? ???? ???? tos ? 1 ccr ram ???? ???? tos ? 2 sp tos ? 3 ????? ????? ????? ??????? ??????? ??????? tos alu tos ? 4 94 8977 figure 7. alu zero-address operations the 4-bit alu performs all the arithmetical, logical, shift and rotate operations with the top two elements of the ex- pression stack (tos and tos-1) and returns the result to the tos. the alu operations affect the carry/borrow and branch flag in the condition code register (ccr). 1.2.5 instruction set the marc4 instruction set is optimized for the high- level programming language qforth. many marc4 instructions are qforth words. this enables the com- piler to generate a fast and compact program code. the cpu has an instruction pipeline which allows the control- ler to prefetch an instruction from eeprom at the same time as the present instruction is being executed. the marc4 is a zero-address machine. the instructions con- tain only the operation to be performed and no source or destination address fields. the operations are implicitly performed on the data placed on the stack. there are one and two byte instructions which are executed within 1 to 4 machine cycles. a marc4 machine cycle is made up of two system clock (syscl) cycles. most of the instruc- tions are only one byte long and are executed in a single machine cycle. 1.2.6 i/o bus the i/o ports and the registers of the peripheral modules (timer 0, timer 1, interval timer, watchdog etc.) are i/o mapped. all communication between the core and the on- chip peripherals takes place via the i/o bus and the associated i/o control. with the marc4 in and out instructions, the i/o bus enables a direct read or write access to one of the 16 primary i/o addresses. more about the i/o access to the on-chip peripherals is described in the ? peripheral modules ? . the i/o bus is internal and is not accessible by the customer on the final micro- controller device, but is used as the interface for the marc4 emulation. 1.3 interrupt structure the marc4 can handle interrupts with eight different priority levels. they can be generated from the internal and external interrupt sources or by a software interrupt from the cpu itself. each interrupt level has a hard-wired priority and an associated vector for the service routine in the eeprom (see table 2, page 11). the programmer can postpone the processing of interrupts by resetting the in- terrupt enable flag (i) in the ccr. an interrupt occurrence will still be registered but the interrupt routine is only started after the i flag is set. all interrupts can be masked, and the priority individually software configured by pro- gramming the appropriate control register of the interrupting module (see section ? peripheral modules ? ).
T48C510 rev. a2, 26-feb-01 preliminary information 10 (61) 7 6 5 4 3 2 1 0 priority level int5 active int7 active ??????? ??????? int2 pending swi0 int2 active ??????? ??????? int0 pending int0 active int2 rti rti int5 int3 active int3 rti rti rti int7 time main / autosleep main / autosleep 94 8978 figure 8. interrupt handling interrupt processing for processing the eight interrupt levels, the marc4 in- cludes an interrupt controller with two 8-bit wide ? interrupt pending ? and ? interrupt active ? registers. the interrupt controller samples all interrupt requests during every non-i/o instruction cycle and latches these in the interrupt pending register. whenever an interrupt request is detected, the cpu interrupts the program currently being executed, on condition that no higher priority interrupt is present in the interrupt active register. if the interrupt-enable bit is set, the processor enters an inter- rupt acknowledge cycle. during this cycle a short call (scall) instruction is executed to the service routine and the current pc is saved on the return stack. an inter- rupt service routine is finished with the rti instruction. this instruction sets the interrupt-enable flag, resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. when the interrupt-enable flag is reset (triggering of interrupt routines is disabled), the execution of new interrupt service routines is inhibited, but not the logging of the interrupt requests in the inter- rupt pending register. the execution of the interrupt is then delayed until the interrupt-enable flag is set again. note that interrupts are only lost if an interrupt request oc- curs while the corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yet fin- ished). after a master reset (power-on, external or watchdog re- set), the interrupt-enable flag and the interrupt pending and interrupt active registers are all reset. interrupt latency the interrupt latency is the time from the occurrence of the interrupt to the interrupt service routine being acti- vated. in the marc4, this is extremely short and takes between 3 to 5 machine cycles depending on the state of the core.
T48C510 preliminary information rev. a2, 26-feb-01 11 (61) table 2 interrupt priority table interrupt priority eeprom address maskable interrupt opcode int0 lowest 040h yes c8h (scall 040h) int1 | 080h yes d0h (scall 080h) int2 | 0c0h yes d8h (scall 0c0h) int3 | 100h yes e8h (scall 100h) int4 | 140h yes e8h (scall 140h) int5 | 180h yes f0h (scall 180h) int6 1c0h yes f8h (scall 1c0h) int7 highest 1e0h yes fch (scall 1e0h) 1.3.1 hardware interrupts table 3 hardware interrupts interrupt possible interrupt priorities rst interrupt mask function source 0 1 2 3 4 5 6 7 register bit nrst external x ? ? low level active watchdog # ? ? 1/2 ? 2 sec. time out port a coded reset # ? ? level any inputs port a monitor * * * * paipr 3 any edge, any input port b monitor * * * * pbipr 3 any edge, any input port 60 external * * * * p6cr 1,0 any edge port 61 external * * * * p6cr 3,2 any edge interval timer inta * * itipr 0 1 of 8 frequencies (1 ? 128 hz) interval timer intb * * itipr 1 1 of 8 frequencies (8 ? 8192 hz) timer 0 * * * * t0cr 0 overflow/compare/ end measurement timer 1 * * * * t1cr 0 compare x = hardwired (neither optional or software configurable) # = configurable option (see ? hardware options ? ) * = software configurable (see ? peripheral modules ? section for further details) in the T48C510, there are eleven hardware interrupt sources which can be programmed to occupy a variety of priority levels. with the exception of the reset sources (rst), each source can be individually masked by mask bits in the corresponding control registers. an overview of the possible hardware configurations is shown in table 3. 1.3.2 software interrupts the program can generate interrupts using the software interrupt instruction (swi) which is supported in qforth by predefined macros named swi0...swi7. the software triggered interrupt operates in exactly the same way as any hardware triggered interrupt. the swi instruction takes the top two elements from the expression stack and writes the corresponding bits via the i/o bus to the interrupt pending register. thus, by using the swi instruction, interrupts can be re-prioritized or lower priority processes scheduled for later execution.
T48C510 rev. a2, 26-feb-01 preliminary information 12 (61) 1.4 hardware reset the master reset forces the cpu into a well-defined condition, is unmaskable and is activated independent of the current program state. it can be triggered by either initial supply power-up, a short collapse of the power sup- ply, a watchdog time out, activation of the nrst input or the occurrence of a coded reset on port a (see figure 9). a master reset activation will reset the interrupt enable flag, the interrupt pending registers, the interrupt active registers and initialize all on-chip peripherals. in this state all ports take on a high resistance input status with deacti- vated pullup and pulldown transistors (see figure 10). when the reset condition disappears, the hardware configuration previously programmed in the configuration eeprom (see mtp programming section) is loaded into the peripherals so that all port characteristics and pullup/ downs reflect the programmed configuration. this configuration period is immediately followed by a further reset delay time (approx. 80 ms), after which a short call instruction (opcode c1h) to the eeprom address 008h is performed. this activates the initialization routine $reset which in turn initializes all necessary ram variables, stack pointers and internal peripheral configuration registers. power-on reset the fully integrated power-on reset circuit ensures that the core is held in a reset state until the minimum operat- ing supply voltage has been reached. a reset condition is also generated should the supply voltage drop momentarily below the minimum operating supply. external reset (nrst) an external reset can be triggered with the nrst pin. to activate an external reset, the pin should be low for a minimum of 4 s. coded reset (port a) the coded reset circuit is connected directly to the port a terminals. by using the appropriate configuration, the user can define a hardwired code combination (e.g., all pins low) which, if occurring on the port a, will generate a reset in the same way as the nrst pin. table 4 multiple key reset options no_rst not used (default) rst2 bpa0 & bpa1 = low rst3 bpa0 & bpa1 & bpa2 = low rst4 bpa0 & bpa1 & bpa2 & bpa3 = low rst5 bpa0 & bpa1 = high rst6 bpa0 & bpa1 & bpa2 = high rst7 bpa0 & bpa1 & bpa2 & bpa3 = high note, that if this option is used, the reset is not maskable and will also trigger if the predefined code is written on to the port a by the cpu itself. care should also be taken not to generate an unwanted reset by inadvertently pass- ing through the reset code on input transitions. this applies especially if the pins have a high capacitive load. watchdog reset the watchdog ? s function can be enabled via a configura- tion option and triggers a reset with every watchdog counter overflow. to suppress the watchdog reset, the counter must be regularly reset by reading the watchdog timer register address (cwd). the cpu reacts in exactly the same manner as a reset stimulus from any of the above sources. port a port a i/o reset code cpu nrst v watch- power-on reset cpu reset rst pull-up code * time out v v wd reset * = configuration dog * dd ss dd reset delay timer figure 9. reset configuration/ start-up sequence
T48C510 preliminary information rev. a2, 26-feb-01 13 (61) reset configuration period power-on reset delay application program execution 250 sec 80 msec program defined input mode input mode input mode program defined no pullup/ pulldown new configuration old config. nrst port status pullup/ pulldown configuration device status new configuration 16539 no pullup/ -down figure 10. normal mode start-up 1.5 clock generation 1.5.1 clock module the clock module generates two clocks. the system clock (syscl) supplies the cpu and the peripherals while the lower frequency periphery sub-clock (subcl) supplies only the peripherals. the modes for clock sources are programmable with the os1-bit and os0-bit in the sc-register and the ccs-bit in the cm-register. the clock module includes 4 different internal oscillator types: two rc-oscillators, one 4-mhz crystal oscillator and one 32-khz crystal oscillator. the pins osc1 and osc2 provide the interface to connect a crystal either for the 4-mhz, or the 32-khz crystal oscillator. sclin can be used as an input for an external clock or for connecting an external trimming resistor for the rc-oscillator 2. all necessary components with the exception of the crystal and the trimming resistor are integrated on-chip. any one of these clock sources can be selected to generate the system clock (syscl). in applications that do not require exact timing, it is possible to use the fully integrated rc-oscillator 1 without any external components. the rc-oscillator 2 is more stable but the oscillator frequency must be trimmed with an external resistor attached between sclin and v dd . in this configuration, for system clock frequencies below 2 mhz, the rc-oscillator 2 frequency can be maintained to within a tolerance of 10% over the full operating temperature and voltage range. the clock module is programmable via software using the clock management register (cm) and the system configuration register (sc). the required oscillator configuration is selected with the os[1:0]-bits in the sc-register. a programmable 4-bit divider stage allows the adjustment of the system clock speed. a synchronization stage avoids any clock glitches which could be caused by clock source switching. the cpu always requires syscl clocks to execute instructions, process interrupts and enter or leave the sleep state. internal oscillators are, depending on the condition of the nstop-bit automatically stopped and started where necessary. special care must however be taken when using an external clock source which is gated by a one of the microcontroller port signals. this configu- ration can hang up if the external oscillator is switched off while the external clock source is still selected. it is there- fore advisable in such a case to switch first to the internal rc-oscillator 1 source using css-bit. the external source can then be reselected later when the external oscillator has again been restarted.
T48C510 rev. a2, 26-feb-01 preliminary information 14 (61) ext. clock exin exout stop rc oscillator2 rcout2 stop r trim 4 ? mhz oscillator 4out stop oscin oscout 32 ? khz oscillator 32out oscin oscout rc oscillator 1 rcout1 control stop in1 in2 /2 /2 /2 /2 divider chain sleep stop nstop ccs css1 css0 cm: os1 os0 subcl syscl sc: oscin oscout 32 khz sclin syscl max /8 syscl max /64 rc[1:0] sc: to cpu and timer/ counter figure 11. clock module table 5 clock modes mode clock source for syscl clock source for subcl os1 os0 ccs = 1 ccs = 0 ccs = 1 ccs = 0 1 1 1 rc-oscillator 1 (intern) external input clock syscl max /64 sclin / 128 2 0 1 rc-oscillator 1 (intern) rc-oscillator 2 with external trimming resistor syscl max /64 syscl max /64 3 1 0 rc-oscillator 1 (intern) 4-mhz oscillator syscl max /64 f xtal / 128 4 0 0 rc-oscillator 1 (intern) 32-khz oscillator 32 khz 1.5.2 oscillator circuits and external clock input stage rc-oscillator 1 fully integrated for timing insensitive applications, it is possible to use the fully integrated rc oscillator 1. this operates without any external components and thus saves on component costs. the rc-oscillator 1 frequency tolerance is better than 50% over the full temperature and voltage range. a reduction in the application operating supply voltage and temperature ranges will result in an improved fre- quency tolerance. for more detailed information see figures 55 ? 57. the basic center frequency of the rc-os- cillator 1 is programmable with the rc1 and the rc0-bits in the sc register. rc oscillator 1 rcout1 stop control rcout1 osc ? stop rc1 rc0 figure 12. rc-oscillator 1 external input clock the sclin pin can be driven by an external clock source provided it meets the specified input levels, duty cycle, rise and fall times. the maximum system clock frequency f sysclmax that the core can operate is f sclin /2 (see figure 13). ext. input clock exout stop ext. clock exout osc ? stop exin sclin figure 13. external input clock rc-oscillator 2 with external trimming resistor the rc-oscillator 2 is a high stability oscillator whereby the oscillator frequency can be trimmed with an external resistor connected between sclin and v dd . in this configuration, as long as the system clock frequency does not exceed 2 mhz, the rc-oscillator 2 frequency can be
T48C510 preliminary information rev. a2, 26-feb-01 15 (61) maintained stable to within a tolerance of 10% over the full operating temperature and voltage range. for example: a syscl max frequency of 2 mhz, can be obtained by connecting a resistor r ext = 150 k (see figures 14, 52, 53 and 54). rc oscillator 2 rcout2 stop rcout2 osc ? stop 13377 r trim sclin r ext v dd figure 14. rc-oscillator 2 4-mhz oscillator the integrated system clock oscillator requires an exter- nal crystal or ceramic resonator connected between the oscin and oscout pins to establish oscillation. all the necessary oscillator circuitry, with the exception of the actual crystal, resonator and the optional c3 and c4 are integrated on-chip. 4 ? mhz oscillator 4out stop 4out osc ? stop oscin oscout oscin oscout cer. res c3 c4 xtal figure 15. system clock oscillator 32-khz oscillator some applications require accurate long-term time keeping without putting excessive demands on the cpu or alternatively low resolution computing power. in this case, the on-chip ultra low power 32-khz crystal oscillator can be used to generate both the subcl and/or the syscl. in this mode, power consumption can be sig- nificantly reduced. the 32-khz crystal oscillator will remain operating (not stopped) during any cpu power- down/sleep mode. 32 ? khz oscillator 32out 32out oscin oscout oscin oscout xtal 32 khz figure 16. 32-khz crystal oscillator quartz oscillator configuration if the customer ? s application necessitates the use of a quartz crystal clock source and this requires capacitive trimming, the trimming capacitors are not integrated into the mtp unlike the m44c510e and should therefore be connected externally as descrete components between the respective quartz crystal terminals (oscin, oscout) and vss.
T48C510 rev. a2, 26-feb-01 preliminary information 16 (61) 1.5.3 clock management register (cm) the clock management register (cm) controls the system clock divider chain, as well as the peripheral clock in the power-down modes. auxiliary register address: ? e ? hex bit 3 bit 2 bit 1 bit 0 cm: nstop ccs css1 css0 reset value: 1111b nstop n ot stop peripheral clock nstop = 0, stops the peripheral clock (subcl) when the core is in sleep mode. the 32-khz crystal oscillator subcl clock cannot be stopped. nstop = 1, enables the peripheral clock (subcl) when the core in sleep mode ccs c ore c lock s elect ccs = 1, the internal rc-oscillator 1 generates syscl ccs = 0, the 4-mhz crystal oscillator, the 32-khz crystal oscillator, an external clock source or the rc-oscillator 2 (with the external resistor) will generate syscl dependent on the setting of os0 and os1 in the system configuration register css[1:0] c ore s peed s elect these two bits control the system clock divider chain auxiliary register address: ? e ? hex css1 css0 divider note 0 0 16 syscl max /8 0 1 8 syscl max /4 1 0 4 syscl max /2 1 1 2 reset value = syscl max system configuration register (sc) primary register address: ? e ? hex bit 3 bit 2 bit 1 bit 0 sc: write rc1 rc0 os1 os0 reset value: 1111b rc1, rc0 internal rc oscillator 1 frequency select (syscl max ) rc1 rc0 sysclmax @ 25 c, v dd = 5 v note 0 0 7.0 mhz (f irc0 ) 0 1 3.0 mhz (f irc1 ) 1 0 2.0 mhz (f irc2 ) 1 1 0.8 mhz (f irc3 ) reset value os1, os0 oscillator selection bits (in conjunction with the ccs-bit) ccs os1 os0 subcl system oscillator selection 0 1 1 external input clock at sclin 0 0 1 syscl max /64 rc-oscillator 2 with r ext 0 1 0 4-mhz crystal oscillator 0 0 0 32 khz 32-khz crystal oscillator 1 x x syscl max /64 or 32 khz rc-oscillator 1 if ccs = 0 in the cm-register, the rc-oscillator 1 is stopped.
T48C510 preliminary information rev. a2, 26-feb-01 17 (61) 1.5.4 power-down modes the T48C510 encorporates several modes which enable the power consumption to be tailored to a minimum with- out sacrificing computational power. when the controller exits the lowest priority interrupt task, it reverts to a sleep state. this is a cpu shutdown condition which is used to reduce average system power consumption where the cpu itself is only partially utilized. in sleep, the cpu clocking system is deactivated whereby the periph- erals and associated clock sources may remain active (standby mode) or they can also be halted (halt mode). in standby mode, the peripherals are able to continue op- eration and if required also generate interrupts which can, along with a reset reactivate the cpu to bring it out of the sleep state. sleep can only be maintained when none of the interrupt pending or active register bits are set. the application of the $autosleep routine ensures the correct function of the sleep mode. in both standby and active modes the current consump- tion is largely dependent on the frequency of the cpu system clock (syscl) and the supply voltage (v dd ). (see figures 50 and 51) while the halt mode current is merely controller static leakage current. selection of standby or halt mode is performed by the nstop bit in the clock managent register (cm). it should be noted that the low power 32-khz crystal oscillator, if enabled will always remain active in both standby and halt modes. table 6 power-down modes mode cpu core state nstop rc-oscillator 1 rc-oscillator 2 4-mhz oscillator 32-khz oscillator external input clock at sclin active run 1 run run enabled standby sleep 1 run run enabled halt sleep 0 stop run disabled 1.5.5 clock monitor mode 13387 syscl clocks nrst te bp11 oscillator supervisory mode normal operation bp10 subcl clocks figure 17. clock monitoring for trimming purposes, the T48C510 can be put into a clock monitor mode. by forcing the test input (te) high, the syscl clock will appear on bp11 (port 1, bit 1) and subcl clock on port bp10 (port 1, bit 0). on releasing the te pin, the bp10 and bp11 will resume their normal function (see figure 17).
T48C510 rev. a2, 26-feb-01 preliminary information 18 (61) 2 peripheral modules 2.1 addressing peripherals accessing the peripheral modules takes place via the i/o bus (see figure 18). the in or out instructions allow direct addressing of up to 16 i/o modules. a dual register addressing scheme has been adopted which addresses the ? primary register ? directly. to address the ? auxiliary reg- ister ? , the access must be switched with an ? auxiliary switching module ? . thus, a single in (or out) to the module address will read (or write) into the module pri- mary register. accessing the auxiliary register is performed with the same instruction preceded by writing the module address into the auxiliary switching module. byte-wide registers are accessed by multiple in (or out) instructions. extended addressing is used for more com- plex peripheral modules, with a larger number of registers. in this case, a bank of up to 16 subport registers are indirectly addressed with the subport address being initially written into the auxiliary register. please refer to the ? hardc510.scr ? hardware interface file as a pro- gramming guideline.
T48C510 preliminary information rev. a2, 26-feb-01 19 (61) aux. reg. subport 0 subport 1 subport fh subport eh i/o bus aux. reg. primary reg. bank of primary regs. primary reg. primary reg. (address pointer) auxiliary sw it ch module i n d i r e c t s u b p o r t a c c e s s d u a l r e g i s t e r a c c e s s s i n g l e r e g i s t e r a c c e s s to other modules module m1 module asw module m2 module m3 address(m2) address(asw) out aux._data address(m2) out prim._data address(m2) out (primary register write) prim._data address(m3) out (primary register write) addr.(m1) addr.(asw) out addr.(sport) addr.(m1) out 1 2 (subport register write) sport_data addr.(m1) out 3 4 5 6 1 2 3 4 7 7 5 6 exa mple of qf orth program code addr.(mx) = module mx address aux._data = data to be written into auxiliary register prim._data = data to be written into primary register. addr.(m1) addr.(asw) out addr.(sport) addr.(m1) out 1 2 (subport register read) addr.(m1) in address(m2) address(asw) out address(m2) in (auxiliary register rea d) 5 6 address(m2) in (primary register read) 4 address(m1) address(asw) out address(m1) in (auxiliary register rea d) 1 2 address(m3) in (primary register read) 7 addr.(asw) = auxiliary switch module address addr.(m1) addr.(asw) out addr.(sport) addr.(m1) out 1 2 (subport register write byte) sport_data(lo) addr.(m1) out 3 addr.(m1) addr.(asw) out addr.(sport) addr.(m1) out 1 2 (subport register read byte) addr.(m1) in 3 sport_data(hi) addr.(m1) out 3 addr.(m1) in 3 sport_data(lo) = data to be written into subport (low nibble) sport_data(hi) = data to be written into subport (high nibble) addr.(sport) = subport address address(m2) address(asw) out aux._data(lo) address(m2) out (auxiliary register write byte) 5 6 aux._data(hi) address(m2) out 6 aux._data (lo)= data to be written into auxiliary register (low nibble) aux._data (hi) = data to be written into auxiliary register(high nibble) 3 ( auxiliary register write ) 96 11522 figure 18. example of i/o addressing
T48C510 rev. a2, 26-feb-01 preliminary information 20 (61) table 7 T48C510 peripheral addresses port address name write /read reset value register function module type see page 0 p0dat w/r 1111b port 0 ? data register/input data m3 21 1 p1dat w/r 1111b port 1 ? data register/input data m3 21 2 paipr w 1111b port a ? interrupt priority register m2 22 aux. paicr w 1111b port a ? interrupt control register 22 3 cwd r ???? watchdog timer reset m3 29 pbipr w 1111b port b ? interrupt priority register m2 22 aux. pbicr w 1111b port b ? interrupt control register 22 4 p4dat w/r 1111b port 4 ? data register/pin data m2 20 aux. p4ddr w 1111b port 4 ? data direction register 21 5 p5dat w/r 1111b port 5 ? data register/pin data m2 20 aux. p5ddr w 1111b port 5 ? data direction register 21 6 p6dat w/r 0011b port 6 ? data register/pin data m2 25 aux p6cr w 1111 1111b port 6 ? control register (byte) 25 7 p7dat w/r 1111b port 7 ? data register/pin data m2 20 aux. p7ddr w 1111b port 7 ? data direction register 21 8 asw w 1111b auxiliary switch register asw 18 9 tcm w/r 1111b data to/from subport addressed by tcsub m1 18 aux. t0sr r 0000b timer 0 interrupt status register m1 35 tcsub w 1111b timer/counter subport address pointer m1 30/31 subport address 0 t0mo w 1111b timer 0 mode register m1 35 1 t0cr w 1111b timer 0 control register m1 36 2 t1mo w 1111b timer 1 mode register m1 43 3 t1cr w 1111b timer 1 control register m1 43/44 4 tcmo w 1111b timer/counter mode register m1 33 5 tcior w 1111b timer/counter i/o control register m1 32 6 tccr w 1111b timer/counter control register m1 31 7 tcip w 1111b timer/counter interrupt priority m1 32 8 t1cp w xxxx xxxxb timer 1 compare register (byte) m1 44 t1ca r xxxx xxxxb timer 1 capture register (byte) m1 9 t0cp w xxxx xxxxb timer 0 compare register (byte) m1 37 t0ca r xxxx xxxxb timer 0 capture register (byte) m1 a bzcr w 1111b buzzer control register m1 47 b-f ???? reserved a padat w/r 1111b port a ? data register/pin data m2 20 aux. paddr w 1111b port a ? data direction register 21 b pbdat w/r 1111b port b ? data register/pin data m2 20 aux. pbddr w 1111b port b ? data direction register 21 c pcdat w/r 1111b port c ? data register/pin data m2 20 aux. pcddr w 1111b port c ? data direction register 21 d ??? ??? ???? reserved e sc w 1111b system configuration register m2 16 aux. cm w/r 1111b clock management register 15 f itfsr w 1111b interval timer frequency select register m2 28 aux. itipr w 1111b interval timer interrupt priority register
T48C510 preliminary information rev. a2, 26-feb-01 21 (61) 2.2 bidirectional ports table 8 overview of port features port address 0 1 4 5 6 7 a b c number of bits 4 4 4 4 2 4 4 4 4 bitwise programmable direction no no yes yes yes yes yes yes yes output drivers configurable 1) no 2) yes yes yes yes yes yes yes yes dynamic pullup/ down typ. (ohm) 3) 500k 500k 500k 500k 500k 500k 500k 500k 500k static pullup/ down typ. (ohm) 4) none none 30k 30k 4k 30k 30k 30k 30k schmitt trigger inputs yes yes yes no yes no yes yes no additional functions timer 0 external interrupt port monitor/ coded reset port monitor 1) either ? open drain down ? , ? open drain up ? or cmos output configuration. 2) this output must always be cmos. 3) the dynamic pullup/down transistors are configurable and if selected, are only activated when the associated complementry dr iver transistor is off. ie. a dynamic pull up transistor is only active when the port is either in input mode (both drivers off) or when a log ical 1 is written to the port pad (low driver off) in output mode. (figure 20) 4) the static pullup/down transitors are configurable and if selected, are always active independant of the port direction or dr iven state. (figure 20) for further data see section 3.2 . all ports (0, 1, 4, 5, 7, a, b and c with the exception of port 6) are 4 bits wide. port 6 has a data width of 2 bits (bit 0 and bit 1) only. the ports may be used for data input or output. all ports that can either directly or indirectly gen- erate an interrupt are equipped with schmitt-trigger inputs. a variety configurable options are available such as open drain, open source and full complementary out- puts as well as different types of pull-up and pull-down transistors. all port data registers (pxdat) are i/o mapped to the primary address register of the respective port address, and the port data direction register (pxddr) to the corresponding auxiliary register. all bidirectional ports except port 0 and port 1, include a bitwise- programmable data direction register (pxddr) which allows the individual programming of each port bit as input or output. it is also possible to read the pin condition when in output mode. this is a useful feature for self testing and for collision detection on wired-or bus systems. there are five different types of bidirectional ports: ports 0 and 1 ? 4-bit wide, bidirectional ports with au- tomatic full bus width direction switching. port 4 ? 4-bit wide, bitwise programmable bidirec- tional port also provides the i/o interface to timer 0 and the buzzer. ports 5, 7 and c ? 4-bit wide, bitwise programmable high drive i/o port. port 6 ? 2-bit wide, bitwise programmable bidirec- tional ports with optional static (4 k ) pull-up/-down and programmable interrupt logic. ports a and b ? 4-bit wide, bitwise programmable bidirectional ports with optional port monitor func- tion. port data register (pxdat) primary register address: ? port address ? hex bit 3 bit 2 bit 1 bit 0 pxdat pxdat3 pxdat2 pxdat1 pxdat0 reset value: 1111b bit 3 msb, bit 0 lsb, x port address
T48C510 rev. a2, 26-feb-01 preliminary information 22 (61) port data direction register (pxddr) auxiliary register address: ? port address ? hex bit 3 bit 2 bit 1 bit 0 pxddr pxddr3 pxddr2 pxddr1 pxddr0 reset value: 1111b table 9 port data direction register (pxddr) code: 3 2 1 0 function x x x 1 bpx0 in input mode x x x 0 bpx0 in output mode x x 1 x bpx1 in input mode x x 0 x bpx1 in output mode x 1 x x bpx2 in input mode x 0 x x bpx2 in output mode 1 x x x bpx3 in input mode 0 x x x bpx3 in output mode 2.2.1 bidirectional port 0 and port 1 in this port type, the data direction register is not indepen- dently software programmable because the direction of the complete port is switched automatically when an i/o instruction occurs (see figure 19). the port can be switched to output mode with an out instruction and to input with an in instruction. the data written to a port will be stored in the output data latches and appears immedi- ately at the port pin following the out instruction. after reset, all output latches are set to ? 1 ? and the ports are switched to input mode. an in instruction reads the condition of the associated pins. note: care must be taken when switching these bidirec- tional ports from output to input. the capacitive pin loading at this port, in conjunction with the high resis- tance pull-ups, may cause the cpu to read the contents of the output data register rather than the external input state. this can be avoided by using either of the following pro- gramming techniques: use two in instructions and drop the first data nibble. the first in switches the port from output to input and the drop removes the first invalid nibble. the second in reads the valid pin state. use an out instruction followed by an in instruction. with the out instruction, the capacitive load is charged or discharged depending on the optional pull-up /pull-down configuration. write a ? 1 ? for pins with pull-up resistors, and a ? 0 ? for pins with pull- down resistors. out in reset i/o bus d r s q q nq r master reset pxdaty *) configurable option (data out) (direction) port 1 only bpxy v dd * pull-up * pull-down * * v dd * figure 19. bidirectional ports 0 and 1
T48C510 preliminary information rev. a2, 26-feb-01 23 (61) 2.2.2 bidirectional port 5, port 7 and port c all bidirectional ports except port 0 and port 1, include a bitwise-programmable data direction register (pxddr) which allows the individual programming of each port bit as input or output. it also enables the reading of the pin condition in output mode. the bidirectional ports 5, 7 and c as well as port a and port b are equipped with the same standard i/o logic. however, port 5, port 7 and port c include standard cmos input stages, whereas port a, port b and all other digital signal pins have schmitt-trigger inputs. port 5 and port 7 have high current output drive capability for up to 20 ma @ 5 v. whereby the instantaneous sum of the out- put currents should not exceed 100 ma. master reset q q bpxy configurable option * * pxdaty pxddry i/o bus d i/o bus i/o bus * * pull-up pull-down v dd * static pull-up (data out) (direction) * s d * s v dd * static pull-down 30 k @ 5 v port a and port b with schmitt-trigger figure 20. bidirectional ports 5, 7, a, b and c 2.2.3 bidirectional port a and port b with port monitor function pxicr bpx3 bpx2 bpx1 bpx0 decoder connected to ports a and b (x = a or b) int5 int7 int3 int1 int5 int7 int3 int1 pxipr enx3 enx2 enx1 enx0 imax itrx prx1 prx2 00 01 10 11 prx1 prx2 16507 2 : 4 figure 21. port monitor module of port a and port b in addition to the standard i/o functions described in sec- tion 2.2.2, both port a (bpa3 ? bpa0) and port b (bpb3 ? bpb0) are equipped with schmitt-trigger inputs and a port monitor module. this module is connected across all four port pins (see figure 21) and is intended for monitor- ing those pins selected by control bits enx3 ? enx0 and generating an interrupt when the first pin leaves a prese- lected logical default idle state. this state is defined by control bit itrx . transitions on other pins will only cause an interrupt if the other pins have first returned to the idle state. this, for example is useful for interrupt initiated port scanning without the power consuming task of con- tinuously polling for port activity. using the port interrupt control register (pxicr), pins can be individually selected. a non-selected pin cannot generate an interrupt. the port interrupt priority register (pxipr) allows masking of each interrupt, definition of
T48C510 rev. a2, 26-feb-01 preliminary information 24 (61) the interrupt edge and programming of the interrupt priority levels. when programming or reprogramming ei- ther of the port monitor control registers, any previously generated interrupt on that port which has not yet been ac- knowledged by the cpu or an interrupt generated by the reprogramming itself is automatically cleared. port a can also be used for a configurable coded reset. for more in- formation see section 1.4 ? hardware reset ? . the port interrupt priority registers paipr and pbipr are i/o mapped to the the primary address registers of the port monitor module addresses ? 2 ? h and ? 3 ? h respec- tively. the port interrupt control registers paicr and pbicr are mapped to the corresponding auxiliary registers. port monitor interrupt priority register (pxipr) x = ? a ? (port a) or ? b ? (port b) (port a) primary register address: ? 2 ? hex (port b) primary register address: ? 3 ? hex bit 3 bit 2 bit 1 bit 0 pxipr imx itrx prx2 prx1 reset value: 1111b imx ? interrupt mask itrx ? interrupt transition prx2..1 ? interrupt priority code table 10 port monitor interrupt priority register (pxipr) code 3 2 1 0 function x x 0 0 port monitor interrupt priority 7 x x 0 1 port monitor interrupt priority 5 x x 1 0 port monitor interrupt priority 3 x x 1 1 port monitor interrupt priority 1 x 0 x x port monitor interrupt on falling edge x 1 x x port monitor interrupt on rising edge 0 x x x port monitor interrupt enabled 1 x x x port monitor interrupt disabled port monitor interrupt control register (pxicr) x = ? a ? (port a) or ? b ? (port b) (port a) auxiliary register address: ? 2 ? hex (port b) auxiliary register address: ? 3 ? hex bit 3 bit 2 bit 1 bit 0 pxicr enx3 enx2 enx1 enx0 reset value: 1111b enx3 ... 0 port monitor input enable code table 11 port monitor interrupt control register (pxicr) code 3 2 1 0 function x x x 0 bit 0 can generate an interrupt x x x 1 bit 0 cannot generate an interrupt x x 0 x bit 1 can generate an interrupt x x 1 x bit 1 cannot generate an interrupt x 0 x x bit 2 can generate an interrupt x 1 x x bit 2 cannot generate an interrupt 0 x x x bit 3 can generate an interrupt 1 x x x bit 3 cannot generate an interrupt
T48C510 preliminary information rev. a2, 26-feb-01 25 (61) 2.2.4 bidirectional port 6 master reset q v dd v dd bp6y configurable * * p6daty i/o bus d in enable i/o bus * * pull-up pull-down v dd * static pull-up (data out) * * s y = 0 or 1 strong 4k @ 5 v * v dd static pull-down strong 4k @ 5 v figure 22. bidirectional port 6 this 2-bit bidirectional port can be used as bitwise-pro- grammable i/o. the data is lsb aligned so that the two msb ? s will not appear on the port pins when written. the port pins can also be used as external interrupt inputs (see figures 22 and 23). both interrupts can be masked or inde- pendently configured to trigger on either edge. the interrupt priority levels are also configurable. the interrupt configuration and port direction is controlled by the port 6 control register (p6cr). an additional low resistance pull-up transistor (configurable option) pro- vides an internal bus pull-up for serial bus applications. in output mode (pxddr bit = 0), the respective port data register (pxdat) bit appears on the port pin, driven by an output port driver stage which can be configurable as open drain, or full complementary cmos. with an in instruction the actual pin state can be read back into the controller at any time without changing the port direc- tional mode. if the output port is configured as an open drain driver, the controller is able to receive the external data on this pin without switching into input mode as long as the output transistor is switched off. in input mode (pxddr bit = 1), the output driver stage is deactivated, so that an in instruction will directly read the pin state which can be driven from an external source. in this case, the state of the port data register (pxdat), although not appearing at the pin itself, remains unchanged. high resistance configurable pull-up or pull- down transistors are automatically switched onto the port pin in input mode. the port data register is written to the respective port address with an out instruction. the port 6 data register (p6dat) is i/o mapped to the primary address register of address ? 6 ? hex and the port 6 control register (p6cr) to the corresponding auxiliary register. the p6cr is a byte wide register and is written by writing the low nibble first and then the high nibble (see section 2.1 ? addressing peripherals ? ).
T48C510 rev. a2, 26-feb-01 preliminary information 26 (61) port 6 data register (p6dat) primary register address: ? 6 ? hex bit 3 bit 2 bit 1 bit 0 p6dat not used not used p6dat1 p6dat0 reset value: xx11b the unused bits 2 and 3 are ? 0 ? , if read. port 6 control register (p6cr) auxiliary register address: ? 6 ? hex bit 3 bit 2 bit 1 bit 0 p6cr first write cycle p61im2 p61im1 p60im2 p60im1 reset value: 1111b bit 7 bit 6 bit 5 bit 4 second write cycle p61pr2 p61pr1 p60pr2 p60pr1 reset value: 1111b p6xim2, p6xim1 ? port 6x interrupt mode/direction code p6xpr2, p6xpr1 ? bp6x interrupt priority code table 12 port 6 control register (p6cr) auxiliary address: ? 6 ? hex first write cycle second write cycle code 3 2 1 0 function code 3 2 1 0 function x x 1 1 bp60 in input mode ? interrupt disabled x x 1 1 bp60 set to priority 1 x x 0 1 bp60 in input mode ? rising edge interrupt x x 1 0 bp60 set to priority 3 x x 1 0 bp60 in input mode ? falling edge interrupt x x 0 1 bp60 set to priority 5 x x 0 0 bp60 in output mode ? interrupt disabled x x 0 0 bp60 set to priority 7 1 1 x x bp61 in input mode ? interrupt disabled 1 1 x x bp61 set to priority 0 0 1 x x bp61 in input mode ? rising edge interrupt 1 0 x x bp61 set to priority 2 1 0 x x bp61 in input mode ? falling edge interrupt 0 1 x x bp61 set to priority 4 0 0 x x bp61 in output mode ? interrupt disabled 0 0 x x bp61 set to priority 6
T48C510 preliminary information rev. a2, 26-feb-01 27 (61) bidir. port in_enable data in p6cr: bp60 bidir. port in_enable data in bp61 cr0 decode decode decode decode int6 int4 int2 int0 int7 int5 int3 int1 i/o bus cr7 cr6 0 1 0 0 0 1 11 int6 int4 int2 int0 cr5 cr4 0 1 0 0 0 1 11 int7 int5 int3 int1 cr3 cr2 0 1 0 0 0 1 11 dir. int edge int disabled dir. dir. edge edge mask mask cr1 cr0 out yes ? yes in ? in in no no cr7 cr6 cr5 cr4 cr3 cr2 cr1 96 11526 figure 23. port 6 external interrupts 2.2.5 bidirectional port 4 the bidirectional port 4 is both a bitwise configurable i/o port and provides the external pins for both the timer 0 and the internal buzzer generator. as an i/o port, it per- forms in exactly the same way as bidirectional port 5, 7, a, b and c (see figure 20). two additional multiplexers allow data and port direction control to be passed over to other internal modules (timer 0 or buzzer). each of the four port 4 pins can be individually switched by the timer/counter i/o register (tcio). figure 24 shows the internal interfaces to port 4. master reset q v dd v dd bp4y configurable option * * p4daty i/o bus d i/o bus i/o bus * * pull-up pull-down (data out) * * s p4ddry s q d tcioy t0out (direction) tdir t0in v dd * * pull-up v dd static pull-down static 30 k @ 5 v figure 24. bidirectional port 4
T48C510 rev. a2, 26-feb-01 preliminary information 28 (61) 2.2.6 tim1 ? dedicated timer 1 i/o pin t1in (timer 1 input) t1out (timer 1 output) t1dir (direction control) v dd v dd tim1 configurable options * * * * pull-up pull-down * * figure 25. bidirectional pin tim1 tim1 is a dedicated bidirectional i/o stage for signal communication to and from the timer 1 in the timer/ counter module (see figure 25). it has no i/o bus interface and is not directly accessible from the cpu. the direction control is performed from the timer/counter configura- tion registers. 2.3 interval timers / prescaler the interval timers are based on a frequency divider for generating two independent time base interrupts. it is driven by subcl generated by the clock module (see fig- ure 11 ) and consists of a 15-stage binary divider and two programmable multiplexers for selecting the appropriate interrupt frequencies for each interrupt source (see fig- ure 26). each multiplexer is completely independent and is controlled by the common interval timer frequency select register (itfsr). buffer registers store the respec- tive frequency select codes and ensure complete programming independence of each interrupt channel. interrupt masking and programming of the interrupt priority levels is performed with the aid of the interval timer interrupt priority register (itipr). subcl ck 8092hz 4096hz 2048hz 1024hz 256hz 128hz 64hz 32hz 8hz 4hz 2hz 1hz 1hz 0h 1h 2h 3h 4h 5h 6h 7h 2hz 4hz 8hz 16hz 16hz 32hz 64hz 128hz 8hz 8h 9h ah bh ch dh eh fh 16hz 64hz 256hz 1024hz 2048hz 4096hz 8192hz itfsr fs1 fs2 fs3 fs0 buffer buffer itipr mia pra prb mib inta 8:1 mux intb 8:1 mux int5 int1 int6 int2 r 15-stage binary counter 2 2 222 2 22 2 22 2 222 345678 9 10 11 12 13 14 15 (e.g. subcl = 32 khz) 96 11530 figure 26. interval timers / prescaler
T48C510 preliminary information rev. a2, 26-feb-01 29 (61) 2.3.1 interval timer registers the interval timer frequency select register (itfsr) is i/o mapped to the primary address register of the pre- scaler/ interval timer address ( ? f ? hex) and the interval timer interrupt priority register (itipr) to the corre- sponding auxiliary register. the interrupt masks mia and mib enable interrupt masking of inta and intb respec- tively. each interrupt source can be programmed with pra and prb to one of two interrupt priority levels. dis- abling both interrupts resets the interval timer. interval timer interrupt priority register (itipr) auxiliary register address (write only): ? f ? hex bit 3 bit 2 bit 1 bit 0 itipr prb pra mib mia reset value: 1111b prb ? priority select interval timer interrupt intb pra ? priority select interval timer interrupt inta mib ? mask interval timer interrupt intb mia ? mask interval timer interrupt inta table 13 interval timer interrupt priority register (itipr) code 3 2 1 0 function x x 1 1 reset prescaler and halt x x x 1 interrupt a disabled x x x 0 interrupt a enabled x x 1 x interrupt b disabled x x 0 x interrupt b enabled x 1 x x interrupt a => priority 1 x 0 x x interrupt a => priority 5 1 x x x interrupt b => priority 2 0 x x x interrupt b => priority 6 interval timer frequency select register (itfsr) primary register address (write only): ? f ? hex bit 3 bit 2 bit 1 bit 0 itfsr fs3 fs2 fs1 fs0 reset value: 1111b fs3 ... 0 ? frequency select code table 14 interval timer frequency select register (itfsr) code 3 2 1 0 function subcl divide by subcl = 32 khz code 3 2 1 0 function subcl divide by subcl = 32 khz 0 0 0 0 inta 2 15 select 1 hz 1 0 0 0 intb 2 12 select 8 hz 0 0 0 1 2 14 select 2 hz 1 0 0 1 2 11 select 16 hz 0 0 1 0 2 13 select 4 hz 1 0 1 0 2 9 select 64 hz 0 0 1 1 2 12 select 8 hz 1 0 1 1 2 7 select 256 hz 0 1 0 0 2 11 select 16 hz 1 1 0 0 2 5 select 1024 hz 0 1 0 1 2 10 select 32 hz 1 1 0 1 2 4 select 2048 hz 0 1 1 0 2 9 select 64 hz 1 1 1 0 2 3 select 4096 hz 0 1 1 1 2 8 select 128 hz 1 1 1 1 2 2 select 8192 hz the control bit fs3 determines whether the inta or the intb buffer register is loaded with the select code (fs2 ? fs0). this allows independent programming of interval times for inta and intb.
T48C510 rev. a2, 26-feb-01 preliminary information 30 (61) 2.4 watchdog timer 17-stage binary counter subcl ck rrrrrrrrrrrrrrrr r read wdres v * watchdog enable * * * * configurable option 2 nrst master reset dd 14 2 15 2 16 figure 27. watchdog timer the watchdog timer is a 17-stage binary divider clocked by subcl generated within the clock module (see fig- ures 11 and 27). it can only be enabled as a configurable option whereby it must be periodically reset from the ap- plication program. the program cannot disable the watchdog. if the cpu find itself for an extended length of time in sleep mode or in a section of program that in- cludes no watchdog reset, then the watchdog will overflow, thus forcing the nrst pin low. this initiates a master reset. the timeout period can be set to 0.5, 1 or 2 seconds (if subcl = 32 khz) by using a configurable op- tion. to reset the watchdog, the program must perform an in- instruction on the address cwd ( ? 3 ? hex). no relevant data is received. the operation is therefore normally fol- lowed by a drop to flush the data from the stack. 2.5 timer/counter module (tcm) the tcm consists of two timer/counter blocks (timer 0 and timer 1) which can be used separately, or together as a single 16-bit counter/timer (see figures 28 and 30). each timer can be supplied by various internal or external clock sources. these can be selected and divided under program control using the timer/counter control register (tccr), the timer 0 control register (t0cr) and the timer 1 control register (t1cr). capture and compare registers (t0ca,t1ca,t0cp and t1cp) not only allow event counting, but also the generation of various timed output waveforms including programmable frequencies, modulated melody tones, pulse w idth modulated (pwm) and pulse density modulated (pdm) output signals. when in one of these signal generation modes, the capture register acts as timer shadow register, the current timer state is freezed whenever read by the cpu. the timer 0 is further equipped for performing a variety of time mea- surement operations. in this mode the capture register is used together with the gating logic for performing asynchronous, externally triggered snapshot measure- ments. these measurements include single input pulse width and period measurements and also dual input phase and positional measurement. the mode configuration is set in the timer 0 and timer 1 mode registers (t0mo and t1mo). each timer represents a single maskable interrupt source (t0int and t1int), the priority of which can be config- ured under program control. a timer 0 interrupt can be caused by any of three conditions (overflow, compare or end-of-measurement). the associated status register (t0sr) differentiates between these. a status register is not necessary in the timer 1 as an interrupt is caused only on a compare condition.
T48C510 preliminary information rev. a2, 26-feb-01 31 (61) 13909 ck prescaler rst gating control mux 4:1 mux 8:1 clock control up/down up/down counter t0ca compare t0cp reload control t0cr t0mo reset capture register compare register output control t0sr status register end ? of ? measu ? rement overflow int. enable int output control t1cp compare up/down counter t1ca compare register reload control carry t1mo clock control reset capture register mux 2:1 mux 8:1 t1cr rst prescaler ck mux 4:1 16 ? bit mode int int. enable tccr tcmo t0out0 t1out t0in1 t0in0 syscl subcl subcl syscl t1in t0out1 t0out0 t0int t1int t1out timer 0 timer 1 < = cpu read/write registers overflow figure 28. timer/counter module
T48C510 rev. a2, 26-feb-01 preliminary information 32 (61) 2.5.1 general timer/counter control registers with the exception of the timer 0 interrupt status regis- ter (t0sr), all the timer/counter registers are indirectly addressed using extended addressing as described in the section ? addressing peripherals ? . an overview of all reg- ister and subport addresses is shown in table 7. the timer/counter auxiliary register (tcsub) holds the sub- port address of the particular register about to be accessed. care has to be taken to ensure that this subport access se- quence is not interrupted. please refer to the ? hardc510.scr ? hardware interface file as a program- ming guideline. timer/counter clock control register (tccr) subport address (indirect write access): ? 6 ? hex of port address ? 9 ? hex bit 3 bit 2 bit 1 bit 0 tccr t1cl2 t1cl1 t0cl2 t0cl1 reset value: 1111b t0cl2, t0cl1 ? timer 0 clock source select t1cl2, t1cl1 ? timer 1 clock source select table 15 timer/counter clock control register (tccr) code 3 2 1 0 function direction (tdir) bp40* tim1 x x 0 0 timer 0 clock = subcl out x x x 0 1 timer 0 clock = syscl out x x x 1 0 timer 0 clock = timer1 output (t1out connected internally) out x x x 1 1 timer 0 clock = t0in0 ( bp40*) in x 0 0 x x timer 1 clock = subcl x out 0 1 x x timer 1 clock = syscl x out 1 0 x x timer 1 clock = timer 0 output (t0out0 connected internally) x out 1 1 x x timer 1 clock = tim1 x in * if tcio0 = low (connects timer 0 to port 4) the timer/counter clock control register (tccr) controls the clock source to both timer 0 and timer 1 prescalers. if an external clock source (on bp40 or tim1) is selected, then the corresponding port direction is automatically switched to input mode (see figure 27). note: the tcio0 bit must be set low for the bp40 external timer/counter access.
T48C510 preliminary information rev. a2, 26-feb-01 33 (61) timer/counter interrupt priority register (tcip) the timer/counter interrupt priority register (tcip) is used to configure the timer 0 and timer 1 interrupt priority levels. subport address (indirect write access): ? 7 ? hex of port address ? 9 ? hex bit 3 bit 2 bit 1 bit 0 tcip t1ip2 t1ip11 t0ip2 t0ip1 reset value: 1111b t0ip2, t0ip1 ? timer 0 interrupt priority code t1ip2, t1ip1 ? timer 1 interrupt priority code table 16 timer/counter interrupt priority register (tcip) code 3 2 1 0 function x x 1 1 timer 0 interrupt priority 1 x x 1 0 timer 0 interrupt priority 3 x x 0 1 timer 0 interrupt priority 5 x x 0 0 timer 0 interrupt priority 7 1 1 x x timer 1 interrupt priority 0 1 0 x x timer 1 interrupt priority 2 0 1 x x timer 1 interrupt priority 4 0 0 x x timer 1 interrupt priority 6 timer/counter i/o control register (tcior) subport address (indirect write access): ? 5 ? hex of port adddress ? 9 ? hex bit 3 bit 2 bit 1 bit 0 tcior tcio3 tcio2 tcio1 tcio0 reset value: 1111b tcio3...0 ? timer / counter i/0 mode select table 17 timer/counter i/o control register (tcior) code 3 2 1 0 function x x x 1 bp40 ? standard port mode x x x 0 bp40 ? timer 0 clock input (t0in0) or timer 0 output (t0out0) x x 1 x bp41 ? standard port mode x x 0 x bp41 ? timer 0 gate input (t0in1) or timer 0 output (t0out1) x 1 x x bp42 ? standard port mode x 0 x x bp42 ? buzzer output (buz) 1 x x x bp43 ? standard port mode 0 x x x bp43 ? buzzer output (nbuz) by using the timer/counter i/o control register (tcior) the program can configure the respective port 4 pins as either standard data i/o ports or as external signal ports for the t imer 0 and buzzer. the timer 1 uses a dedi- cated i/o pin tim1, whose direction is controlled solely by the tccr (see figure 29). it should be noted that if a tcior bit is set low, then the corresponding port data direction register (p4ddr) bit no longer influences the port direction. in the case of bp40 and bp41, the port direction is then controlled entirely by the timer/counter configuration registers (tccr,t0mo), while pins bp42 and bp43 become unidirectional buzzer outputs.
T48C510 rev. a2, 26-feb-01 preliminary information 34 (61) bp40 buzzer buz nbuz timer 0 t0in0 t0in1 t0out0 t0out1 timer 1 t1in t1out p4dat0 p4ddr0 bp41 p4dat1 p4ddr1 bp42 p4dat2 p4ddr2 bp43 tim1 tccr tccr tcio0 pwm,pdm melody,counter t0mo to cpu select ext. clock select ext. clock 96 11533 to cpu tcio1 to cpu tcio2 ? 0 ? p4dat3 p4ddr3 to cpu tcio3 ? 0 ? figure 29. timer/counter and buzzer external interface timer/counter mode register (tcmo) subport address (indirect write access): ? 4 ? hex of port address ? 9 ? hex bit 3 bit 2 bit 1 bit 0 tcmo t0ninv tc8 t1rst t0rst reset value: 1111b t0ninv ? timer 0 output (bp41) appears non-inverted at bp40 tc8 ? timer/counter in 8-/16-bit mode t1stp ? timer 1 stop/run t0stp ? timer 0 stop/run table 18 timer/counter mode register (tcmo) code 3 2 1 0 function x x x 0 timer 0 running x x x 1 timer 0 halted x x 0 x timer 1 running x x 1 x timer 1 halted x 0 x x timer/counter in 16-bit mode x 1 x x timer/counter in 8-bit mode 0 x x x inverted output bp41 appears on bp40 (bp40 = not bp41) 1 x x x non-inverted output bp41 appears on bp40 (bp40 = bp41)
T48C510 preliminary information rev. a2, 26-feb-01 35 (61) 2.5.2 timer/counter in 16-bit mode prescaler counter counter prescaler carry comparator compare register compare register comparator overflow/compare compare interrupt to tim1 8bit/16bit mux 96 11549 timer 0 timer 1 figure 30. 16-bit mode in 16-bit mode, timer 0 and timer 1 are cascaded thus forming a 16-bit counter (see figure 30) whereby, irre- spective of the state of t imer 0 interrupt mask bit (t0im), the timer 1 counts both timer 0 overflow and compares interrupt events. these are generated according to the state of the timer 0 mode register as described in the t0mo table. the comparators are also cascaded so that when both timer 0 and timer 1 match their respective compare registers, the timer 1 generates both an output signal and a compare interrupt (if unmasked). in measurement modes, only timer 0 capture register is loaded with timer 0 ? s contents on an end-of-measure- ment event. timer 1 capture register operates solely as a shadow register. there is no 16-bit capture operation, so the user program must check if timer 1 has incremented between reading the lower and higher byte. likewise, there is no automatic suppression of spurious interrupts which could conceivably be generated between writing timer 0 and timer 1 compare registers. 2.5.3 timer 0 modes the timer 0 mode configuration is defined in the timer 0 mode register (t0mo). the available modes and the effect on the t imer 0 interrupt and interrupt flags is shown below. in all modes except the position measurement mode, timer 0 acts as an up-counter, the related clock fre- quency being defined by the selected clock source and the prescaler division factor. the counter can be reset and halted at any time by the t0rst bit of the tcmo register which also resets all the interrupt status flags and capture registers. whenever port 4 bp40 and bp41 pins are re- quired for timer 0 i/o, then the appropriate tcior enable bit must be set low. in this case, the port direction switching is handled automatically by the hardware. in modes where the bp40 is not used as a timer clock input or as a melody envelope output, the bp40 outputs the same signal as that appearing on bp41. with the help of the t0ninv bit of the timer/counter mode register (tcmo), the bp41 output can be inverted so that bp40 and bp41 form a differential output stage which can be used for directly driving piezo buzzers or small stepper motors.
T48C510 rev. a2, 26-feb-01 preliminary information 36 (61) timer 0 mode register (t0mo) subport address (indirect write access): ? 0 ? hex of port adress ? 9 ? hex bit 3 bit 2 bit 1 bit 0 t0mo t0mo3 t0mo2 t0mo1 t0mo0 reset value: 1111b t0mo3 ... 0 ? timer 0 mode code table 19 timer 0 mode register (t0mo) code 3 2 1 0 function assuming tcior1=tcior0=low interrupt set / t0sr affected bp40 (*3) bp41 cmp ofl eom 0 0 0 0 reserved ? ? ? 0 0 0 1 reserved ? ? ? 0 0 1 0 modulated melody mode envelope (out) tone (out) y/y y/y n/n 0 0 1 1 melody mode tone (out) tone (out) y/y y/y n/n 0 1 0 0 counter-auto reload (50% duty cycle) toggle (out) /clock (in) toggle (out) y/y y/y n/n 0 1 0 1 counter-free running (50% duty cycle) toggle (out) /clock (in) toggle (out) n/y y/y n/n 0 1 1 0 pulse density modulation pdm (out) /clock (in) pdm (out) n/y y/y n/n 0 1 1 1 pulse width modulation pwm (out) /clock (in) pwm (out) n/y y/y n/n 1 0 0 0 phase measurement signal 1 (in) signal 2 (in) n/n y/y y/y 1 0 0 1 position measurement signal 1 (in) signal 2 (in) (*1) (*2) n/n 1 0 1 0 low pulse width measurement clock (in) signal (in) n/y y/y y/y 1 0 1 1 high pulse width measurement clock (in) signal (in) n/y y/y y/y 1 1 0 0 counter- auto reload (strobe) strobe (out) /clock (in) strobe (out) y/y y/y n/y 1 1 0 1 counter-free running (strobe) strobe (out) /clock (in) strobe (out) n/y y/y n/y 1 1 1 0 period measurement (rising edge) clock (in) signal (in) n/y y/y y/y 1 1 1 1 period measurement (falling edge) clock (in) signal (in) n/y y/y y/y *1 note: the compare interrupt/status flag can only be set when counting up. *2 note: the overflow interrupt/status flag is set on both an overflow or an underflow. *3 note: the bp40 signals can be inverted if t0ninv=0 (tcmo register) timer 0 interrupt status register (t0sr) auxiliary register address (read access): ? 9 ? hex bit 3 bit 2 bit 1 bit 0 t0sr not used t0eom t0ofl t0cmp reset value: x000b note: the status register is reset automatically when read and also when timer 0 is reset. t0eom ? timer 0 end of measurement status flag t0ofl ? timer 0 overflow status flag t0cmp ? timer 0 compare status flag
T48C510 preliminary information rev. a2, 26-feb-01 37 (61) table 20 timer 0 interrupt status register (t0sr) code 3 2 1 0 function x x x 1 timer 0 compare has occurred (timer 0 = t0cp) x x 1 x timer 0 overflow or underflow has occurred x 1 x x timer 0 measurement completed the interrupt flags will be set whenever the associated condition occurs irrespective of whether the corresponding inter- rupt is triggered. therefore, the status flags are still set if the interrupt condition occurs when the interrupt is masked. to see exactly when the flags are set, see t0mo control code table 18. reading from the timer/counter auxiliary register will access the timer 0 interrupt status register (t0sr). timer 0 control register (t0cr) the t0cr is responsible for the predivision of the selected timer 0 input clock (see tccr). it can be divided or used directly as clock for the up/down counter. bit 0 is the mask bit for the timer 0 interrupt. subport address (indirect write access): ? 1 ? hex of port address ? 9 ? hex bit 3 bit 2 bit 1 bit 0 t0cr t0fs3 t0fs2 t0fs1 t0im reset value: 1111b t0fs3 ... 1 ? timer 0 prescaler division factor code t0im ? timer 0 interrupt mask table 21 timer 0 control register (t0cr) code 3 2 1 0 function x x x 1 timer 0 interrupt disabled x x x 0 timer 0 interrupt enabled 0 0 0 x timer 0 prescaler divide by 256 0 0 1 x timer 0 prescaler divide by 128 0 1 0 x timer 0 prescaler divide by 64 0 1 1 x timer 0 prescaler divide by 32 1 0 0 x timer 0 prescaler divide by 16 1 0 1 x timer 0 prescaler divide by 8 1 1 0 x timer 0 prescaler divide by 4 1 1 1 x timer 0 prescaler bypassed
T48C510 rev. a2, 26-feb-01 preliminary information 38 (61) timer 0 compare register (t0cp) ? byte write subport address (indirect write access): ? 9 ? hex of port address ? 9 ? hex bit 3 bit 2 bit 1 bit 0 t0cp first write cycle t0cp3 t0cp2 t0cp1 t0cp0 reset value: xxxxb bit 7 bit 6 bit 5 bit 4 second write cycle t0cp7 t0cp6 t0cp5 t0cp4 reset value: xxxxb t0cp3 ... t0cp0 ? timer 0 compare register data (low nibble) ? first write cycle t0cp7 ... t0cp4 ? timer 0 compare register data (high nibble) ? second write cycle the compare register t0cp is 8-bit wide and must be accessed as byte wide subport (see section ? addressing peripher- als). first of all, the data is written low nibble and is then followed by the high nibble. any timer interrupts are automatically suppressed until the complete compare value has been transferred. timer 0 capture register (t0ca) ? byte read subport address (indirect read access): ? 9 ? hex of port address ? 9 ? hex bit 7 bit 6 bit 5 bit 4 t0ca first read cycle t0ca7 t0ca6 t0ca5 t0ca4 reset value: xxxxb bit 3 bit 2 bit 1 bit 0 second read cycle t0ca3 t0ca2 t0ca1 t0ca0 reset value: xxxxb t0ca7. .. t0ca4 ? timer 0 capture register data (high nibble) ? first read cycle t0ca3 ... t0ca0 ? timer 0 capture register data (low nibble) ? second read cycle note: if the timer is read (in pdm mode only) the bit order will appear reversed, so that t0ca0 =msb, t0ca1=msb-1 .... t0ca6=lsb+1, t0ca7 = lsb. the 8-bit capture register t0ca is read as byte wide subport. note, however, unlike the writing to the compare register, the high nibble is read first followed by the low nibble. the 8-bit timer state is captured on reading the first nibble and held until the complete byte has been read. during this transfer, the timer is free to continue counting.
T48C510 preliminary information rev. a2, 26-feb-01 39 (61) timer 0 free running counter modes (strobe and 50% duty cycle) in the free running counter mode, timer 0 can be used as an event counter for summing external event pulses on bp40, or as a timer with an internal time-based clock. when enabled, the counter will count up generating an output signal on bp41 whenever the counter contents match the compare register (see figure 31). this signal can appear either as a strobe pulse or as a simple toggling of the output state (50% duty cycle) depending on the timer mode. interrupts (if not masked) are generated every 256 clocks on the overflow condition. the current counter state can be read at any time by reading the capture register,. the compare register has no effect on the counter cycle time and will not influence interrupts. timer clock t0out1 (bp41) overflow interrupt timer = compare register (= 4) timer resets on overflow 0 4 255 timer state strobe 50% duty cycle 1 2 35 6 4 1 2 35 6 0 255 255 4 1 2 35 6 0 ?? ? ? 96 11534 figure 31. timer 0 free running counter mode timer 0 counter reload modes (strobe and 50% duty cycle) as in the free running mode, the counter can also be clocked from either an external signal on bp40 or from an internal clock source. in this mode, the counter repetition period is completely defined by the contents of the compare register (t0cp) (see figure 32). the counter counts up with the selected clock frequency. when it reaches the value held in the compare register, the counter then returns to the zero state. at the same time, depending on the selected timer mode, the bp41 either toggles or generates a strobe pulse. if the timer 0 interrupt is unmasked, a compare interrupt is also generated. the resultant output frequency f out = f in /2*(n+1) where n = compare value (n = 1 ? 255). timer clock t0out1 (bp41) compare interrupt timer = compare register (= 7) resets timer 0 7 timer state 0 50% duty cycle strobe 4 1 2 35 6 7 0 4 1 2 35 6 7 0 4 1 2 35 6 ?? ?? ?? ?? ? ? 96 11535 figure 32. timer 0 counter reload mode
T48C510 rev. a2, 26-feb-01 preliminary information 40 (61) melody mode (with/without modulation) the non-modulated melody mode is identical to the auto- reload counter (50% duty cycle) mode. the melody tone frequency appearing on bp41 and/or bp40 is determined in exactly the same way as the value written into the comparator register. in the modulated melody mode, the T48C510 generates two output signals, a melody tone and an envelope pulse (see figure 33). the tone frequency output on bp41 is generated in exactly the same way as in the simple melody mode. while the envelope pulse on bp40 is a single pulse, of a clock period in duration which appears shortly after loading the compare value into the compare register. in this mode, an analog switch is activated between the bp40 and bp41 outputs (see figure 34). with the external capacitor connected, the resultant signal on bp41 exhibits a melody chime effect with an exponential decay. timer clock t0out0 (bp40) compare interrupt timer = compare register resets timer 0 7 timer state 0 t0out1 (bp41) new value (=7) loaded into compare register 4 1 2 35 6 0 7 4 1 2 35 6 0 7 4 1 2 35 6 0 7 4 1 2 35 6 7 4 1 2 35 6 96 11538 figure 33. modulated melody mode t0out0 t0out1 v analog switch modulated melody mode bp41 bp40 t0out0 (melody output) t0out1 (envelope) bp40 bp41 v 10...47uf r (optional) piezo buzzer v dd ss dd v ss 96 11539 figure 34. modulated melody output circuit
T48C510 preliminary information rev. a2, 26-feb-01 41 (61) timer 0 pulse width modulation mode a pulse width modulated (pwm) signal exhibits a fixed repetition frequency and a variable mark space ratio. it is often used as a simple method for d/a conversion, where the high period is proportional to the digital value to be converted. therefore by connecting a simple low-pass rc network to the pwm signal, the analog value can be retrieved. timer 0 generates the pwm signal by comparing the state of the free running up counter with the contents of the compare register (see figure 35). if the result is less than the compare register value, then the bp41 output is high. if the result is greater or equal to the compare register value, then the bp41 output is set low. thus, the high phase of the pwm signal is directly proportional to the compare register contents. a total of 256 possible discrete mark space ratios can be generated ranging from a continuous low signal over a variable pulse width signal to a continuous high signal. the pwm signal has a repetition period of 256 clocks, an interrupt (if unmasked) being generated on every overflow event. care should be taken if the syscl clock is used as the pwm clock source because it may stop if the cpu goes into sleep mode (see section 1.5.4 power-down modes). ? ?? ?? timer clock t0out1 (bp41) overflow interrupt timer = compare register (= 4) 04 255 timer state t_hi t_low t_hi = (comparator value)*clock period t_low = (255 ? comparator value)*clock period 1 2 3 255 04 1 3 255 04 1 3 96 11540 figure 35. timer 0 pulse width modulation pulse density modulation mode pulse density modulation (pdm) is also used for simple d/a conversion. unlike the pwm signal,where the high and low signal phases are always continuous during a single repetition cycle, the pdm distributes these evenly as a series of pulses (see figure 36). this has the advantage that, if used together with an rc smoothing filter for d/a conversion, either the ripple is less than the pwm, or, for a corresponding ripple error, the filter components can be smaller or the clock frequency lower. to generate the pdm output on bp41, the pulse density is controlled by the contents of the compare register in the same way as the pwm generation. each of the pulses has a width equal to the counter clock period. pwm=0.25 pdm=0.25 pwm=0.75 pdm=0.75 repetition period 96 11541 figure 36. an example 4-bit pwm/pdm comparison
T48C510 rev. a2, 26-feb-01 preliminary information 42 (61) period measurement modes (rising and falling edge) during the period measurement mode, the counter counts the number of either internal or external clocks in one period of the bp41 input signal (see figure 37). dependent on the mode chosen, this will be from rising edge to the next rising edge or conversely, falling edge to the following falling edge. on the trigger edge, the counter state is loaded into the capture register and subsequently reset. the measured value remains in the capture register until overwritten by the following measured value. interrupts can be generated by either an overflow condition or an end-of-measurement (eom) event. an ? eom ? event signals the cpu that a new measured value is present in the capture register and can be read, if required. t0in1 (bp41) t_period ? eom ? interrupt captures and resets timer falling edge triggered t_period rising edge triggered 96 11542 figure 37. period measurement pulse width measurement modes (high and low) in this mode, the selected clock source is gated to the counter for the duration of each input pulse received on bp41 (see figure 38). whether the measurement takes place during the high or low phase depends on the selected mode. at the end of each pulse, the counter state is loaded into the capture register and subsequently reset. interrupts can be gen- erated by either an overflow condition or an end-of-measurement (eom) event. an ? eom ? event signals the cpu that a new measured value is present in the capture register can be read, if required. t0in1 (bp41) t_low t_high ? eom ? interrupt captures and resets timer 96 11543 figure 38. pulse width measurement
T48C510 preliminary information rev. a2, 26-feb-01 43 (61) phase measurement mode this mode allows the timer 0 to measure the phase misalignment between two 1:1 mark space ratio input signals con- nected to the bp40 and bp41 pins (see figure 39). the counter clock is gated with the phase misalignment period (tp), during which time the counter increments with the selected clock frequency. this misalignment period is defined as the period during which bp40 is high and bp41 is low. capturing and resetting of the counter always takes place on the rising edge of bp41. the measured value remains in the capture register until overwritten by the next measurement. interrupts can be generated by either an overflow condition or an end-of-measurement ( ? eom ? ) event. an ? eom ? event signals the cpu that a new measured value is present in the capture register and can be read, if required. t0in1 (bp41) t0in0 (bp40) ? eom ? interrupt tp tp tp captures & resets timer 96 11544 figure 39. phase measurement position measurement mode this mode is intended for the evaluation of positional sensors with biphase output signals. figure 40 illustrates a typical positional sensor system which delivers both incremental positional stepping signals and also directional information. the direction can be deduced from the relative phase of the two signals. therefore if bp40 is high on the rising edge of bp41, the moving mask travels to the left and if it is low then it travels to the right. the direction (left/right) informa - tion is used to set the direction of the up/down counter which enables the bp40 pulses to be counted. assuming that the system has been reset on a reference position, the counter will always hold the absolute current position of the mov- ing mask. this can be read by the cpu if necessary. this mode is the only one in which the counter is allowed to decrement. therefore, in this case it is possible for both an underflow or an overflow to occur. the overflow interrupt (if unmasked) will trigger on either of these conditions while the compare interrupt on the other hand will only trigger if the counter is counting upwards. to differentiate between an overflow or underflow, the compare value can be set to ? 0 ? hex, for example. an overflow would then set both the overflow and compare status flags while an underflow sets the overflow status flag only. t0in1 (bp41) t0in0 (bp40) typical sensor light light static mask moving mask t0in0 t0in1 left movement right movement timer n n+1 n+2 n+3 n n ? 1n ? 2n ? 3 96 11545 figure 40. position measurement mode
T48C510 rev. a2, 26-feb-01 preliminary information 44 (61) 2.5.4 timer 1 modes the timer 1 is aimed at performing event counting and timing functions (see figure 28). it has, unlike the timer 0, no gated clock or externally triggered capture modes. the counter counts up with an internal or external clock, depending on the state of the timer 1 control reg- ister (t1cr) and the timer/counter clock control register (tccr) and generates a compare interrupt whenever the counter matches the timer 1 compare regis- ter. this is the only timer 1 interrupt source. masking can be performed using the mask bit in the timer 1 control register (t1cr) and priority can be defined in the t imer/ counter interrupt priority register (tcip). the tim1 pin is used by the timer 1 either as clock/event input or timer output. i/o control of the timer 1 pin tim1 is controlled entirely by the hardware, therefore if the tim1 is selected as an external clock or event source (in the tccr), there can be no timer 1 signal output. in this case, the timer would be used solely to generate interrupts. in autostop operation, the timer 1 will halt both itself and timer 0 whenever the timer 1 compare value is reached. this feature can be used for example to generate an exact burst of pulses. both timers will remain stopped until restarted. restarting is performed in the normal way by setting the appropriate control bits in the timer/counter mode register (tcm0). timer 1 mode register (t1mo) subport address (indirect write address): ? 2 ? hex of port address ? 9 ? hex bit 3 bit 2 bit 1 bit 0 t1mo t1mo3 t1mo2 t1mo1 t1mo0 reset value: 1111b t1mo3 ... 0 ? timer 1 mode control table 22 timer 1 mode register (t1mo) code 3 2 1 0 function compare interrupt x x 0 0 counter free running (50% duty cycle) yes x x 0 1 counter auto reload (50% duty cycle) yes x x 1 0 pulse width modulation yes x x 1 1 counter auto-reload (strobe output) yes x 0 x x increment on falling edge of clock ? x 1 x x increment on rising edge of clock ? 1 x x x normal operation (no autostop) yes 0 x x x autostop operation (timer 1 stops timer 2) yes timer 1 control register (t1cr) the t1cr is responsible for the predivision of the selected timer 1 input clock (see tccr). it can be divided or used directly as clock for the up counter. bit 0 is the mask bit for the timer 1 interrupt. subport address (indirect write access): ? 3 ? hex of port adress ? 9 ? hex bit 3 bit 2 bit 1 bit 0 t1cr t1fs3 t1fs2 t1fs1 t1im reset value: 1111b t1fs3 ... 1 ? timer 1 prescaler division factor code t1im ? timer 1 interrupt mask
T48C510 preliminary information rev. a2, 26-feb-01 45 (61) table 23 timer 1 control register (t1cr) code 3 2 1 0 function x x x 1 timer 1 interrupt disabled x x x 0 timer 1 interrupt enabled 0 0 0 x timer 1 prescaler divide by 256 0 0 1 x timer 1 prescaler divide by 128 0 1 0 x timer 1 prescaler divide by 64 0 1 1 x timer 1 prescaler divide by 32 1 0 0 x timer 1 prescaler divide by 16 1 0 1 x timer 1 prescaler divide by 8 1 1 0 x timer 1 prescaler divide by 4 1 1 1 x timer 1 prescaler bypassed timer 1 compare register (t1cp) ? byte write subport address (indirect write access): ? 8 ? hex of port address ? 9 ? hex bit 3 bit 2 bit 1 bit 0 t1cp first write cycle t1cp3 t1cp2 t1cp1 t1cp0 reset value: xxxxb bit 7 bit 6 bit 5 bit 4 second write cycle t1cp7 t1cp6 t1cp5 t1cp4 reset value: xxxxb t1cp3 ... t1cp0 ? timer 1 compare register data (low nibble) ? first write cycle t1cp7. .. t1cp4 ? timer 1 compare register data (high nibble) ? second write cycle the compare register t1cp is 8 bits wide and must be accessed as byte wide subport (see section ? addressing peripher- als ? ). the data is written low nibble first, followed by high nibble. any timer interrupts are automatically suppressed until the complete compare value has been transferred. timer 1 capture register (t1ca) ? byte read subport address (indirect read access): ? 8 ? hex of port address ? 9 ? hex bit 7 bit 6 bit 5 bit 4 t1ca first read cycle t1ca7 t1ca6 t1ca5 t1ca4 reset value: xxxxb bit 3 bit 2 bit 1 bit 0 second read cycle t1ca3 t1ca2 t1ca1 t1ca0 reset value: xxxxb t1ca7 ... t1ca4 ? timer 1 capture register data (high nibble) ? first read cycle t1ca3 ... t1ca0 ? timer 1 capture register data (low nibble) ? second read cycle the 8-bit capture register t1ca is read as byte-wide subport. note, however, unlike the writing to the compare register, the high nibble is read first followed by low nibble. the 8-bit timer state is captured on reading the first nibble and held until the complete byte has been read. during this transfer, the timer is free to continue counting. the previous capture value will be held until the timer is restarted again.
T48C510 rev. a2, 26-feb-01 preliminary information 46 (61) timer 1 counter free running (50% duty cycle) in the free running counter mode, the counter counts up with either an internal or external clock and cycles through all 256 timer states. on the clock following a match between the compare register (t1cr) and the counter, a compare interrupt (if unmasked) is generated and the tim1 pin is toggled (see figure 40). timer clock t1out (tim1) compare interrupt timer = compare register (= 4) 04 255 timer state 1 2 35 6 4 1 2 35 6 0 255 255 4 1 2 35 6 0 (clock set to rising edge) ? ?? ?? 50% duty cycle 96 11546 figure 41. timer 1 counter free running (50% duty cycle) timer 1 counter auto reload (strobe and 50% duty cycle) in the auto-reload mode, the counter counts up with either an internal or external clock. on the clock cycle following a match between the compare register (t1cr) and the counter, a compare interrupt (if unmasked) is generated. the tim1 output is either strobed or toggled and the counter reset (see figure 42). therefore, the counter cycle period is defined by the contents of the compare register. in 50% duty cycle mode the frequency of tim1 is: f tim1 = f in /2(n+1) where the compare value (n) =1 ... 255. timer clock t1out (tim1) compare interrupt timer = compare register (= 7) resets timer 0 7 timer state 0 50% duty cycle strobe 4 1 2 35 6 7 0 4 1 2 35 6 7 0 4 1 2 35 6 ? ?? ? (clock set to neg. edge) 96 11547 figure 42. timer 1 counter auto reload
T48C510 preliminary information rev. a2, 26-feb-01 47 (61) timer 1 pulse width modulation the timer 1 generates the pwm signal by comparing the state of the free running up counter with the contents of the compare register (see figure 43). if the result is less or equal to the compare register value, then the tim1 output is high. if the result is greater than the compare register value, then the tim1 output is set low. thus, the high phase of the pwm signal is directly proportional to the compare register contents. a total of 256 possible discrete mark space ratios can be generated ranging from a continuous low signal over a variable pulse width signal. the pwm signal has a repetition period of 256 clock periods, an interrupt (if unmasked) being generated on every compare event. care should be taken if syscl is used as the pwm clock source. the pwm output may stop if the cpu goes into sleep depending on the prog ramming of the nstop bit in the cm-register. using this mode of operation recommends to set the bit nstop =1. ? ?? ?? timer clock t1out (tim1) timer = compare register (=4) 04 255 timer state compare interrupt t_hi t_low t_hi = (comparator value)*clock period t_low = (256-comparator value)* clock period 1 2 3 255 04 1 3 255 04 1 3 2 2 96 11548 figure 43. timer 1 pulse width modulation 2.6 buzzer module the buzzer is a 4 stage frequency divider which divides the subcl and depending on the state of the buzzer control register (bzcr) can output one of four frequencies. an external piezo or buzzer can be driven by the complementary buzzer outputs (buz and nbuz) which are directed to port 4 (bp42 and bp43) under control of the timer/counter i/o register (tcior) as shown in figure 28. when the buzzer is switched off, both of the buzzer outputs take up the same logical state. this is controlled by the bzop bit of the bzcr. subcl ck bzcr bzof bzfs2 bzop r 4 stage divider subcl (32 khz) subcl / 4 (8 khz) subcl / 8 (4 khz) subcl / 16 (2 khz) bzfs1 r r r buz nbuz 4 :1 mux 96 11550 figure 44. buzzer module
T48C510 rev. a2, 26-feb-01 preliminary information 48 (61) buzzer control register (bzcr) subport address (indirect write access): ? a ? hex of port adress ? 9 ? hex bit 3 bit 2 bit 1 bit 0 bzcr bzfs2 bzfs1 bzop bzof reset value: 1111b bzfs2, bzfs2 ? buzzer frequency select code bzop ? buzzer output stop state bzof ? buzzer off/on table 24 buzzer control register (bzcr) code 3 2 1 0 function x x x 0 buzzer on x x x 1 buzzer off x x 0 x buzzer output stop state: bp42 = bp43 = low x x 1 x buzzer output stop state: bp42 = bp43 = high 0 0 x x buzzer frequency: 32 khz (= subcl) 0 1 x x buzzer frequency: 8 khz (= subcl / 4) 1 0 x x buzzer frequency: 4 khz (= subcl / 8) 1 1 x x buzzer frequency: 2 khz (= subcl / 16) buz nbuz buz nbuz buzzer off bzop=1 bzop=0 96 11551 figure 45. buzzer waveform
T48C510 preliminary information rev. a2, 26-feb-01 49 (61) 2.7 mtp programming in circuit programmer (icp) target programmer interface (tpi) 16541 figure 46. programmer system to accomodate the application program and the associ- ated hardware option configuration, the T48C510 is equipped with 2 on-chip eeprom memory blocks. these are written via a 6-signal target programmer inter- face (tpi), comprising of 2 power lines (vdd and vss), a programm mode signal (pm) and 3 data lines which are multiplexed onto 3 of the T48C510 functional pins ? bp00, bp01 and bp02 (see figure 47). for setting up the required hardware options and downloading these along with the application program into the T48C510, the cus- tomer can be supplied with a dedicated pc based programmer software operating under windows95/98 or nt and an in circuit programmer unit (icp). the icp is connected to the pc via a standard pc serial interface port and to the target device or application board (for in sys- tem programming) via the tpi flat band cable. table 25 target programmer interface signals tpi connector pin pin name T48C510 function 1 pm programming mode input 2 vdd +5 volt supply 3 bp02 port02 (clock) input 4 bp01 port01 (data ) input 5 bp00 port00 (data ) output 6 vss ground supply 7 n/c not connected 8 n/c not connected 9 n/c not connected 10 n/c not connected the state of the T48C510 pm pin defines the mtp opera- tional mode ie. pm = high (program mode), pm = low (normal operation mode) while the 3 tpi data lines are used to serially load or read the customer ? s data into or out of the T48C510. application program the programmer software requires only the customer ? s binary *.hex file which is generated by the marc4 pro- gram compiler and also provides the primary data base for emulation. this is displayed on the screen as an editable hexadecimal memory map. contents of an already pro- grammed device can be read back and displayed an the same hex. form provided that the device ? s ? read lock ? has not been set. a ? read lock ? protected device, if read will appear to be full of f hex . hardware configuration all hardware configurations are set up within the soft- ware ? s intuitive user interface by selecting the required options from the masks provided. the available configur- able hardware options are similar to those of the m44c510e (see ? hardware options ? section). these ef- fect primarily port configurations, watchdog and coded reset settings. the port driver strengths, although mask programmable in the m44c510e are not configurable in the mtp ? all output drivers being internally ? hardwired ? to the default ? standard drive ? strength. read lock protection the programmer software encorporates a so called ? read lock ? which can be set by the user. this is provided for customer security purposes and inhibits the reading of the customer ? s application program by unauthorized per- sons. if set, the ? read lock ? sets a hardware key in the mtp eeprom which disables reading of the program/ configuration data. it should be noted that this is a ? read lock ? and not a ? write lock ? , so even if the lock is set, it is still possible to overwrite the customer data with new program code. in-system programming for ? in-system programming ? , the application circuit board must be fitted with a 10-pin male connector to acco- modate the tpi connector. to ensure conflict-free access to the target T48C510 tpi related pins (bp00, bp01, bp02 and pm) it is recommended that these are equipped with jumpers (j5, j4, j3 and j1) to avoid signal contention with other on board drivers sources. ( see figure 47). how- ever, if these can be overdriven, or if the port 0 is not used in the application, then the jumpers can be omitted or re- placed by isolating resistors. prior to connecting the tpi, all other application power supply sources should be dis- connected from the application circuit board. should
T48C510 rev. a2, 26-feb-01 preliminary information 50 (61) other on board components either present an excessive power supply load or be unable to withstand the icp 5-volt supply voltage, then the vdd power line should also be jumpered (j2). during the programming operation all ports are set into input mode, with the previously programmed pullup/pull- downs transitors deactivated. in normal operational mode, the pm pin is strapped to ground and the port 0 reverts to a port function as de- scribed in section 2.2.1. j1 bp70 bp71 bp72 bp60 bpb3 bpb2 bpb1 bp73 pm sclin bp61 bpb0 vss bp53 bp51 bp50 vdd bp43 bp52 bp00 tim1 te bp13 bp12 bp11 bp10 bp42 bp41 bp03 bp02 bp01 bp40 oscout nrst bpa0 bpa1 bpa2 bpa3 oscin avdd bpc2 bpc3 bpc0 bpc1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 23 24 25 j2 j3 j4 j5 vss n.c. n.c. n.c. n.c. 1 2 3 4 5 6 7 8 9 10 * * * * * *optional jumpers vss programmer interface bp00 bp01 bp02 vdd application: T48C510 20 21 figure 47. in-system programming 2.8 noise considerations when designing the microcontroller based application, several factors should be taken into consideration to increase noise immunity and reduce electromagnetic emission (eme). many such potential problems can be avoided by careful layout of the printed circuit board (pcb). the pcb contains many parasitic components which at first sight are not apparent. pcb tracks can act as antennas or as coupling capacitors. long stretches of parallel tracks and long high frequency signal lines should thus be avoided wherever possible to minimise the chance of picking up or transmitting unwanted signals. 2.8.1 noise immunity the following guidelines will increase system noise im- munity: unconnected inputs should not be left open. if port pins are not required then it is recommended to set pullup or pulldown option on these pins. special care should be taken when laying out the pcb that interrupt, reset and clock signal lines are kept short and are carefully shielded or have sufficient spacing from other on board noise generating sources. a quartz crystal should always be directly located immediately next to the microcontroller crystal oscillator terminals (oscin and oscout), the connections being always very short. this avoids not only signal coupling onto the c lock source but can also reduces eme.
T48C510 preliminary information rev. a2, 26-feb-01 51 (61) pcb ? s should where economically possible be equipped with adequate ground planes. the microcontroller power supply should be decoupled with an electrolytic capacitance (approx. 10 f) in parallel with a ceramic capacitance (approx.100 nf) situated as close to the micro- controller device as possible. 2.8.2 electromagnetic emission electromagnetic emmision is caused by rapidly changing electrical current (di/dt) in long antenna like connection lines and cables. this can result in electrical interference on other telecommunication devices. these current spikes are more often than not present in the system power supply lines and driver signal lines. the following guide will help to reduce eme: keep the length of pcb current switching signal tracks to a minimum.. adopt a pcb star power routing system connected at one point. many of the microcontroller port outputs can be con- figured with several drive strengths. this means that a high drive output will switch a signal faster than for example standard drive output. the resulting change in current in the signal and power lines will also in- crease, causing an increase in eme. so wherever speed and drive current is not necessary the ports should be configured with the lowest drive possible. if possible, write the application program to avoid multiple outputs switching at any instant. cables can be equipped with ferrite rings to slow cur- rent spikes or the system can be encased in a grounded conducting casing. 3 electrical characteristics 3.1 absolute maximum ratings voltages are given relative to v ss . parameters symbol value unit supply voltage v dd ? 0.3 to + 7.0 v input voltage (on any pin) v in v ss ? 0.3 v in v dd +0.3 v output short circuit duration t short indefinite s operating temperature range t amb ? 40 to +85 c storage temperature range t stg ? 65 to +150 c thermal resistance (sso44) r thja 110 k/w soldering temperature (t 10 s) t sld 260 c stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at any condition above those indicated in the operational section of these specification is not implied. exposure to absolute maximum rating condition for an extended period may affect device reliability. all inputs and outputs are protected against high electrostatic voltages (4kv, hbm) or electric fields. however, precautions to minimize the build-up of electrostatic charges during handling are recommended. reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. v dd ). 3.2 dc operating characteristics supply voltage v dd = 5 v, v ss = 0 v, t amb = ? 40 to 85 c unless otherwise specified. typical values relate to v dd = 5 v, t amb = 25 c and are for reference only. parameters test conditions / pins symbol min. typ. max. unit power supply supply voltage v dd 2.2 6.2 v active current cpu running testrom @syscl_irc3 i dd 200 500 a
T48C510 rev. a2, 26-feb-01 preliminary information 52 (61) unit max. typ. min. symbol test conditions / pins parameters quotient i dd /syscl_ir3 cpu running testrom @syscl_irc3 i ddq 0.25 0.5 a/khz halt current cpu in sleep mode, nstop = 0 i halt 0.1 0.5 a power-on reset threshold voltage por threshold voltage v por 0.8 1.0 1.5 v schmitt-trigger input voltage: (all inputs except port 5, 7 and c) negative-going threshold voltage v dd = 2.4 to 6.2 v v t ? v ss 0.4 v dd v positive-going threshold voltage v dd = 2.4 to 6.2 v v t+ 0.55 v dd v dd v hysteresis (vt+ ? vt ? ) v dd = 2.4 to 6.2 v v h 0.1 v dd input pins: nrst and te input voltage low v dd = 2.4 to 6.2 v v il v ss 0.2 v dd v input voltage high v dd = 2.4 to 6.2 v v ih 0.8 v dd v dd v input nrst with pull-up resistor input low current v dd = 2.4 v, v il = v ss v dd = 5.0 v i il ? 1.0 ? 5 ? 1.5 ? 10 ? 3.0 ? 18 a a input te with pull-down resistor input high current v dd = 5.0 v i ih 1 1.4 2 ma all bidirectional ports and tim1 input voltage low v dd = 2.4 to 6.2 v v il v ss 0.2 v dd v input voltage high v dd = 2.4 to 6.2 v v ih 0.8 v dd v dd v dynamic input low cur- rent (pull-up) v dd = 2.4 v, v il = v ss v dd = 5.0 v i il ? 1.0 ? 5 ? 1.5 ? 10 ? 3.0 ? 18 a a dynamic input high cur- rent (pull-down) v dd = 2.4 v, v ih = v dd v dd = 5.0 v i ih 1.0 5 1.5 10 2.5 18 a a output low current v dd = 2.4 v v ol = 0.2*v dd v dd = 5.0 v i ol 1 6 2 9 4 13 ma ma output high current v dd = 2.4 v v oh = 0.8*v dd v dd = 5.0 v i oh ? 1 ? 6 ? 2 ? 8 ? 4 ? 13 ma ma bidirectional port bp4, bp5, bp7, bpa, bpb and bpc input low current static pull-up (30 k ) v dd = 2.4 v v dd = 5.0 v i il i il ? 15 ? 100 ? 25 ? 150 ? 45 ? 220 a a input high current static pull-down (30 k ) v dd = 2.4 v v dd = 5.0 v i ih i ih 15 100 25 150 45 220 a a bidirectional port bp60 and br61 input low current static pull-up (4 k ) v dd = 2.4 v v dd = 5.0 v i il i il ? 0.2 ? 1 ? 0.3 ? 1.35 ? 0.5 ? 2 ma ma input high current static pull-down (4 k ) v dd = 2.4 v, v il = v ss v dd = 5.0 v i ih i ih 0.15 1 0.25 1.4 0.5 2 ma ma note: the total sum of all port static output currents must not exceed 100 ma. the sum of all port currents switched at any instant (di/ dt) must not exceed 30 ma.
T48C510 preliminary information rev. a2, 26-feb-01 53 (61) 3.3 ac characteristics supply voltage v dd = 2.4 to 6.2 v, v ss = 0 v, t amb = ? 40 to 85 c unless otherwise specified. typical values relate to v dd = 5 v, t amb = 25 c and are for reference only. parameters test conditions / pins symbol min. typ. max. unit reset timing power-on reset delay v dd v por t por 80 ms nrst input low time t nrst 4 s interrupt request input timing int. request low time t irl 50 ns int. request high time t irh 50 ns internal rc oscillator (for additional characteristics see figures 55 to 57) standby current of irc0 cpu in sleep mode, sc = 0011b, cm = 1100b i irc0 300 500 a syscl_irc0 cpu active, sc = 0011b, cm = 1100b f syscl 3.5 7.0 10.5 mhz standby current of irc1 cpu in sleep mode, sc = 0111b, cm = 1101b i irc1 150 250 a syscl_irc1 cpu active, sc = 0111b, cm = 1101b f syscl 1.9 3.0 4.5 mhz standby current of irc2 cpu in sleep mode, sc = 1011b, cm = 1110b i irc2 100 150 a syscl_irc2 cpu active, sc = 1011b, cm = 1110b f syscl 1.4 2.0 3.0 mhz standby current of irc3 cpu in sleep mode, sc = 1111b, cm = 1111b i irc3 40 70 a syscl_irc3 cpu active, sc = 1111b, cm = 1111b f syscl 0.60 0.80 1.3 mhz stability v dd = 5 v 20 % df/f 0 ? 5 % system clock crystal/ceramic oscillator (for additional characteristics see figures 49) standby current cpu in sleep mode, 4-mhz crystal active i xtal 125 a start-up time v dd = 2.4 v t startup 8 10 ms stability v dd = 3 v to 5.5 v df/f 0 0.3 0.5 ppm rc oscillator ? external resistor (for additional characteristics see figures 52 to 54) standby current cpu in sleep mode, r ext = 150 k ( i xrc 125 a frequency cpu active, r ext = 150 k f syscl 1.8 2.0 2.2 mhz stability v dd = 2.4 v to 5.5 v df/f 0 ? 10 %
T48C510 rev. a2, 26-feb-01 preliminary information 54 (61) ac characteristics (continued) parameters test conditions / pins symbol min. typ. max. unit 32-khz crystal oscillator active current cpu active/running i dd32k 10 a halt current cpu in sleep mode i haltx 1.0 1.5 a start-up time v dd = 2.4 v t startup 1.5 s stability av dd = 100 mv df/f 0 0.1 0.3 ppm external clock input at sclin, tim1 and t0in sclin input clock f sclin = 2 f syscl cpu active, v dd > 2.4 v rise/fall time < 50 ns, see figure 47 f syscl 4 8 mhz tim1, t0in input frequ. rise/fall time < 30 ns f in 10 mhz eeprom program/ configuration memory number of programming cycles n 1000 cycles crystal characteristics parameters test conditions / pins symbol min. typ. max. unit 32-khz crystal crystal frequency f x 32.768 khz series resistance rs 30 50 k static capacitance c0 1.5 pf dynamic capacitance c1 3 ff load capacitance c l 8 10 12.5 pf system clock crystal crystal frequency f x 1.5 4 8 mhz series resistance rs 30 50 static capacitance c0 2 4.5 pf dynamic capacitance c1 3 15 ff l c1 rs c0 oscin oscout equivalent circuit figure 48. crystal equivalent circuit 0.0010 0.0100 0.1000 1.0000 10.0000 100.0000 0123456 f syscl ( mhz ) v dd ( v ) f sysclmax f sysclmin figure 49. worst case minimum/ maximum system frequency (using external rc or crystal oscillator)
T48C510 preliminary information rev. a2, 26-feb-01 55 (61) 0.01 0.10 1.00 10.00 100.00 1000.00 10000.00 10 100 1000 10000 f syscl ( khz ) dd v dd = 3 v t amb = 25 c 100% active standby halt figure 50. i dd = f (f syscl ) 0.1 1.0 10.0 100.0 1000.0 10000.0 10 100 1000 10000 f syscl ( khz ) dd v dd = 5 v t amb = 25 c 100% active standby halt figure 51. i dd = f (f syscl ) 1900 1950 2000 2050 2100 2150 2200 ? 40 ? 20 0 20 40 60 80 100 t amb ( c ) v dd = 5 v v dd = 3 v 16512 f ( khz ) syscl r ext = 150 k figure 52. f syscl = f (t amb ); external rc 100 1000 10000 10 100 1000 r ext ( k ) f ( khz ) syscl v dd = 5 v t amb = 25 c figure 53. f syscl = f (r ext) 0 1000 2000 3000 4000 5000 6000 1.5 2.5 3.5 4.5 5.5 6.5 v dd ( v ) rext = 47 k rext = 150 k rext = 477 k f ( khz ) syscl t amb = 25 c figure 54. f syscl = f (v dd , r ext ) 0 1000 2000 3000 4000 5000 6000 7000 1.5 2.5 3.5 4.5 5.5 6.5 v dd ( v ) f irc3 f ( khz ) syscl f irc2 f irc1 f irc0 t amb = 25 c figure 55. f syscl = f (v dd ); internal rc
T48C510 rev. a2, 26-feb-01 preliminary information 56 (61) 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 ? 40 ? 20 0 20 40 60 80 100 t amb ( c ) f irc3 16514 v dd = 3 v f ( khz ) syscl f irc2 f irc1 f irc0 figure 56. f syscl = f (t amb ) 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 ? 40 ? 20 0 20 40 60 80 100 t amb ( c ) f irc3 16515 v dd = 5 v f ( khz ) syscl f irc2 f irc1 f irc0 figure 57. f syscl = f (t amb ) ? 12 ? 10 ? 8 ? 6 ? 4 ? 2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i ( ma ) v dd ? v oh ( v ) oh v dd = 3 v 16518 figure 58. typical high output driver 0 2 4 6 8 10 12 14 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i ( ma) v ol ( v ) ol v dd = 3 v 16516 figure 59. typical low output driver 0 5 10 15 20 25 30 35 012345 i ( ma) v ol ( v ) ol v dd = 5 v 16517 figure 60. typical low output driver ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 012345 i ( ma ) v dd ? v oh ( v ) oh v dd = 5 v 16519 figure 61. typical high output driver
T48C510 preliminary information rev. a2, 26-feb-01 57 (61) 4 device information 4.1 pad layout 17 11 16 10 8 7 6 5 4 12 1 2 3 9 44 13 14 15 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 43 42 41 40 mask/chip id T48C510 oscin avdd bpc2 bpc3 bpb0 bpb1 bpb2 bpb3 bp60 bp61 sclin bpc1 tim1 bp00 bp01 bp02 bp03 bp40 bp41 bp42 bp43 vdd oscout bpa2 bp12 bp10 bpc0 bpa0 bpa3 bpa1 nrst bp13 te bp1 1 pm bp70 bp53 bp51 bp73 bp71 bp72 bp52 vss bp50 die size: 2.99 x 4.30 mm standard pad size: 96 x 96 m pad size (vss): 246 x 96 m thickness: 480 25 m ( 19 1 mil ) figure 62. pad layout table 26 pad coordinates pad no. name x-coord. y-coord pad no. name x-coord. y-coord. 1 sclin 113.80 353.95 23 te 3861.80 2678.70 2 bp61 113.80 503.95 24 bpc1 3939.70 2374.60 3 bp60 113.80 744.40 25 tim1 3939.70 2134.15 4 bpb3 113.80 984.85 26 bp00 3939.70 1744.20 5 bpb2 113.80 1225.30 27 bp01 3939.70 1594.20 6 bpb1 113.80 1465.75 28 bp02 3939.70 1444.20 7 bpb0 113.80 1706.20 29 bp03 3939.70 1294.20 8 bpc3 113.80 1946.65 30 bp40 3939.70 1144.20 9 bpc2 113.80 2187.10 31 bp41 3939.70 903.75 10 avdd 113.80 2426.65 32 bp42 3939.70 663.30 11 oscin 113.80 2576.65 33 bp43 3939.70 422.85 12 oscout 421.80 2678.70 34 vdd 3939.70 147.90 13 nrst 571.80 2678.70 35 bp50 3590.95 146.45 14 bpa0 721.80 2678.70 36 bp51 3350.50 146.45 15 bpa1 962.25 2678.70 37 bp52 3110.05 146.45 16 bpa2 1202.70 2678.70 38 bp53 2869.60 146.45 17 bpa3 1443.15 2678.70 39 vss 2474.15 146.45 18 bp10 2659.55 2678.70 40 bp70 1431.05 146.45 19 bp11 2900.00 2678.70 41 bp71 1190.60 146.45 20 bp12 3140.45 2678.70 42 bp72 950.15 146.45 21 bp13 3380.90 2678.70 43 bp73 709.70 146.45 22 bpc0 3621.35 2678.70 44 vss 469.25 146.45
T48C510 rev. a2, 26-feb-01 preliminary information 58 (61) 4.2 packaging 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 sclin bpc0 bp00 bp12 bp11 bp10 oscin oscout bp01 bp02 bp03 nrst vss vdd bp43 bp42 bp41 bp40 bpb3 bpb2 bpb1 bpb0 bp70 bp71 bp72 bp73 bp53 bp52 bp51 bp50 tim1 bpa3 bpa2 bpa1 bpa0 te avdd bp61 [inty] bp60 [intx] 21 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 23 24 41 42 43 44 bpc1 bp13 vss bpc3 bpc2 T48C510 figure 63. pin connections sso44-package 13040 technical drawings according to din specifications package sso44 dimensions in mm 0.25 0.10 0.3 0.8 18.05 17.80 16.8 2.35 9.15 8.65 7.50 7.30 10.50 10.20 0.25 44 23 1 22
T48C510 preliminary information rev. a2, 26-feb-01 59 (61) 5 hardware options the following list shows all the T48C510 hardware options that can be programmed into the configuration eeprom. spd ? > strong static pull-down, spu ? > strong static pull-up port 0 output standard drive bp00 cmos pull-up bp01 cmos pull-up bp02 cmos pull-up bp03 cmos pull-up port 1 output standard drive bp10 cmos pull-up open drain [n] pull-down open drain [p] bp11 cmos pull-up open drain [n] pull-down open drain [p] bp12 cmos pull-up open drain [n] pull-down open drain [p] bp13 cmos pull-up open drain [n] pull-down open drain [p] port 4 output standard drive bp40 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bp41 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bp42 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bp43 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) port 5 output standard drive bp50 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bp51 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bp52 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bp53 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) port 7 output standard drive bp70 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bp71 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bp72 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bp73 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) port 6 output standard drive bp60 cmos pull-up open drain [n] pull-down open drain [p] spu (4 k ) spd (4 k ) bp61 cmos pull-up open drain [n] pull-down open drain [p] spu (4 k ) spd (4 k )
T48C510 rev. a2, 26-feb-01 preliminary information 60 (61) port a output standard drive bpa0 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bpa1 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bpa2 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bpa3 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) port b output standard drive bpb0 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bpb1 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bpb2 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bpb3 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) tim1 output standard drive cmos open drain [n] pull-up open drain [p] pull-down port c output standard drive bpc0 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bpc1 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bpc2 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bpc3 cmos pull-up open drain [n] pull-down open drain [p] spu (30 k ) spd (30 k ) bpa-reset no bpa0 & bpa1 = low bpa0 & bpa1 & bpa2 = low bpa0 & bpa1 & bpa2 & bpa3 = low bpa0 & bpa1 = high bpa0 & bpa1 & bpa2 = high bpa0 & bpa1 & bpa2 & bpa3 = high watchdog 1 / 2 s disabled 1 s 2 s oscin no integrated capacitance oscout no intergrated capacitance
T48C510 preliminary information rev. a2, 26-feb-01 61 (61) ozone depleting substances policy statement it is the policy of atmel germany gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (odss). the montreal protocol ( 1987) and its london amendments ( 1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. atmel germany gmbh has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2. class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency (epa) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c (transitional substances) respectively. atmel germany gmbh can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. 10. we reserve the right to make changes to improve technical design and may do so without further notice . parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use atmel wireless & microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify atmel wireless & microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. data sheets can also be retrieved from the internet: http://www.atmel ? wm.com atmel germany gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 (0)7131 67 2594, fax number: 49 (0)7131 67 2423

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