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1 sy87739l micrel, inc. m9999-062807 hbwhelp@micrel.com or (408) 955-1690 description ? ? ? ? ? protocol transparent fractional-n synthesizer from 10mhz to 729mhz from a single 27mhz reference oscillator ? ? ? ? ? generates exactly the correct frequency for common transport protocols with or without fec ? ? ? ? ? directly enables sy87721l cdr to lock onto any data rate within its range ? ? ? ? ? exceeds bellcore and itu jitter generation specifications ? ? ? ? ? programmable via microwire? interface ? ? ? ? ? available in 32-pin epad-tqfp package features protocol transparent 3.3v 10mhz to 729mhz fractional-n synthesizer sy87739l applications ? ? ? ? ? metro access system ? ? ? ? ? transponders ? ? ? ? ? multiplexers: access, add drop mux ? ? ? ? ? sonet/sdh/atm-based transmission systems, modules and test equipment ? ? ? ? ? broadband cross-connects ? ? ? ? ? fiber optic test equipment ? ? ? ? ? protocols supported: oc-1, oc-3, oc-12, oc-48, atm, gigabit ethernet, fast ethernet, fibre channel, 2x fibre channel, 1394, infiniband, proprietary optical transport rev.: e amendment: /0 issue date: june 2007 the sy87739l is a complete rate independent frequency synthesizer integrated circuit. from a single reference source, this device generates a differential pecl output frequency from 10mhz up to 729mhz. the sy87739l generates an exactly correct reference frequency for common data transport protocols. this is especially important in transponder applications, where a standards compliant protocol data unit must be generated downstream, even in the absence of any signal from the associated upstream interface. in addition, the sy87739l will generate exactly correct reference frequencies for common data transport protocols augmented by forward error correction codes. the sy87739l accepts configuration via a microwire? interface. for proprietary applications, the sy87739l generates reference frequencies guaranteed to enable the sy87721l cdr to lock to any possible baud rate from 28mbps to 2.7gbps. typical applications circuit typical performance anyclock and anyrate are registered trademarks of micrel, inc. microwire is a trademark of national semiconductor. 1, 9, 17, 18, 24 10, 25, 32 6 3 4 22 21 sy87739l refclk+ refclk- clkout+ clkout- 7814 v cc out out out in microcontroller progcs progsk progdi locked 31 30 26 25 2k 2k 0.1f 0.1f 121 121 121 121 fnvcf+ fnvcf- wrvcf+ wrvcf- saronix sel-2431c 27.0000mhz 8 1 v cc 7 14 0 1 2 3 4 5 6 0 100 200 300 400 500 600 700 800 rms jitter (ps) output frequency (mhz) cycle-to-cycle jitter vs. frequency
2 sy87739l micrel, inc. m9999-062807 hbwhelp@micrel.com or (408) 955-1690 package/ordering information nc nc fnvcf- fnvcf+ gnda wrvcf+ wrvcf- gnda nc nc nc gnd vcc locked nc nc vcca nc clkout+ clkout- nc nc vcco vcc vcca nc refclk+ refclk- nc progcs progdi progsk 32 31 30 29 28 27 26 25 9 10111213141516 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 epad-tqfp (h32-2) pin number pin name pin function 1, 24 vcca analog supply (power). set to same voltage as v cc . 2, 5, 11, 12, 13, nc no connect. these pins are to be left unconnected. 15, 16, 19, 20 23, 28, 29 3, 4 refclk reference clock input (differential pecl input): this is a clock derived from an oscillator or other sufficiently accurate frequency source. the frequency provided at this input determines, along with the programming, the output frequency at refout. micrel recommends using a 27.000mhz frequency source. 6 progcs program interface chip select (ttl input): this signal forms part of the microwire? interface. when active high, this signal permits the acquisition of serial data. a falling edge on this input causes sy87739l to re-acquire lock to a new frequency, based on the program downloaded to it. 7 progdi program interface data in (ttl input): one data bit is sampled on each rising edge of prgsk, while progcs is active high. 8 progsk program interface serial clock (ttl input): one bit of configuration data is read in each clock cycle. 9, 17, vcc supply (power): +3.15v to +3.45v. 10 gnd ground. 14 locked lock output (ttl output): this indicates proper operation of all the blocks in the clock synthesis chain. logic high indicates that sy87739l is generating the expected frequency at the clkout output. logic low indicates that one or more pll in the clock synthesis chain has yet to achieve proper lock. 18 vcco output supply (power). set to same voltage as v cc . 21, 22 clkout reference clock output (differential pecl output): this is the synthesized clock generated from refclk. it can be used to supply a reference clock to a data recovery device, such as micrel?s sy87721l. 25, 32 gnda analog ground. 26, 27 wrvcf wrapper filter (analog i/o): these pins connect to the output from the wrapper synthesizer charge pump, as well as the input to the corresponding vco. a filter network, as described below, converts the charge pump current to a voltage, and adjusts loop bandwidth. 30, 31 fnvcf fractional-n filter (analog i/o): these pins connect to the output from the fractional-n synthesizer charge pump, as well as the input to the corresponding voltage controlled oscillator (vco). a filter network, as described below, converts the charge pump current to a voltage, and adjusts loop bandwidth. pin description ordering information (1) package operating package lead part number type range marking finish sy87739lhi h32-2 industrial sy87739lhi sn-pb sy87739lhitr (2) h32-2 industrial sy87739lhi sn-pb sy87739lhy h32-2 industrial sy87739lhy with matte-sn pb-free bar line indicator pb-free sy87739lhytr (2, 3) h32-2 industrial sy87739lhy with matte-sn pb-free bar line indicator pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. 3. pb-free package is recommended for new designs.
3 sy87739l micrel, inc. m9999-062807 hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (note 1) supply voltage (v cc ) ................................... ?0.5v to +4.0v input voltage(v in ) ....................................... ?0.5v to v cc ecl output current (i out ) continuous .......................................................... 50ma surge .................................................................100ma lead temperature (soldering, 20 sec.) ...................... 260c storage temperature (t s ) ........................ ?65c to +150c operating ratings (note 2) supply voltage (v in ) ................................ +3.15v to +3.45v ambient temperature (t a ) ......................... ?40c to +85c junction temperature (t j ) ......................................... 125c package thermal resistance epad-tqfp ( ja ), (note 3) still-air .......................................................... 27.6c/w 500lfpm ........................................................ 20.7c/w v cc = v cco = v cca = 3.3v 5%; gnd = gnda = 0v; t a = ?40c to +85c symbol parameter condition min typ max units v cc power supply voltage 3.15 3.3 3.45 v i cc power supply current 210 280 ma dc electrical characteristics v cc = v cco = v cca = 3.3v 5%; gnd = gnda = 0v; t a = ?40c to +85c symbol parameter condition min typ max units v ih input high voltage v cc ?1.165 v cc ?0.880 v v il input low voltage v cc ?1.810 v cc ?1.475 v v oh output high voltage 50y to v cc ?2v v cc ?1.075 v cc ?0.830 v v ol output low voltage 50y to v cc ?2v v cc ?1.860 v cc ?1.570 v i il input low current v in = v il (min.), note 1, 2 ?1.5 a pecl dc electrical characteristics note 1. the refclk+ pin has a nominal 75ky pull-down resistor connected to ground. note 2. the reclk? pin has a nominal 75ky pull-down resistor connected to ground and a nominal 75ky pull-up resistor connected to v cc . v cc = v cco = v cca = 3.3v 5%; gnd = gnda = 0v; t a = ?40c to +85c symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v v oh output high voltage i oh = ?2ma 2.0 v v ol output low voltage i ol = 4ma 0.5 v i ih input high current v in = 2.7v, v cc = max. +20 a v in = v cc , v cc = max. +100 a i il input low current v in = 0.5v, v cc = max. ?300 a i os output short circuit current v out = 0v, (1 sec. max.) ?100 ?250 ma ttl dc electrical characteristics note 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operat ion is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximu m ratlng conditions for extended periods may affect device reliability. note 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. note 3. measured with die attach pad soldered to pcb, jedec standard multi-layer board.
4 sy87739l micrel, inc. m9999-062807 hbwhelp@micrel.com or (408) 955-1690 v cc = v cco = v cca = 3.3v 5%; gnd = gnda = 0v; t a = ?40c to +85c symbol parameter condition min typ max units t irf refclk input rise/fall times ? ? 2.0 ns t refpwh refclk pulse width high 5 ? ? ns t refpwl refclk pulse width low 5 ? ? ns t cssk progcs to progsk preset 100 ? ? ns t skcs progsk to progcs recovery 100 ? ? ns t skp progsk period 200 ? ? ns t skpwh progsk pulse width high 70 ? ? ns t skpwl progsk pulse width low 70 ? ? ns t dis progdi data setup 20 ? ? ns t dih progdi data hold 20 ? ? ns clkout duty cycle t clkpwh /(t clkpwh +t clkpwl ) 25 ? 75 % of ui clkout maximum frequency 729 ? ? mhz aquisition lock time 27mhz reference clock ? ? 0.1 sec fractional-n v co operating range 540 ? 729 mhz wrapper v co operating range 540 ? 729 mhz ac electrical characteristics timing waveforms t refpwl refclk t refpwh t clkpwl clkout progcs t skp t skpwh t skpwl t dis progsk progdi t dih t skcs t cssk valid valid valid t clkpwh
5 sy87739l micrel, inc. m9999-062807 hbwhelp@micrel.com or (408) 955-1690 functional description general the sy87739l anyclock? fractional-n synthesizer is used in serial data streaming applications, where the incoming data rate on a channel may vary, or where the incoming data rate on a channel is unknown ahead of time. in these situations, a valid output stream must still be generated even in the absence of any edges on the corresponding input stream. up until now, designers had to resort to sub-optimal solutions such as providing multiple reference oscillators. beyond the potential noise and emi issues, the designer has no way to future proof his circuit, as it would prove near impossible to pre-provision all the reference frequencies that might be needed after deployment, yet are unknown at this time. the sy87739l solves this problem by generating exact frequencies for common data streaming protocols, all from one 27mhz reference. if any of these protocols include overhead due to use of common digital wrappers, the sy87739l still generates the exact frequency required, including the overhead. besides generating reference rates for common protocols directly, the sy87739l also generates reference frequencies for micrel?s sy87721l cdr/cmu, such that it will reliably recover data at any rate between 28mbps and 2,700mbps without any gaps. a simple 3-wire microwire? bit-serial interface loads a configuration that describes the desired output reference frequency. all common microcontrollers support this microwire? interface. those microcontrollers that don?t support this interface in hardware can easily emulate the interface in firmware. the large set of possible frequencies that the sy87739l generates, are divided into three classes. first, the sets of frequencies that match a particular data streaming protocol are in the ?protocol? category. second, the set of frequencies that are guaranteed to be near enough to any arbitrary data rate such that the sy87721l will lock are in the ?picket fence? category. third, the set of frequencies that do not fit into either of the first two categories is in the third category, the sy87739l generates these important reference frequencies through two tandem pll circuits. the first pll uses a modified fractional-n approach to generate a rational ratio frequency. this pll is capable of generating all protocol data rates, except for those that include fec or digital wrapper overhead. a second, more traditional p/q synthesizer optionally adjusts the output frequency of the first, fractional-n synthesizer, to accommodate these fec or digital wrapper data rates. the bit serial interface conveys 32 bits of configuration data from a microcontroller to sy87739l. this simple interface consists of an active high chip select, a serial clock (2mhz or less) and a serial data input. each clock cycle one bit of configuration data transfers to sy87739l. circuit description the heart of sy87739l is its fractional-n synthesizer, as shown in figure 1. phase- frequency detector/ charge pump vco p p-1 mux control loop filter input reference frequency (f ref ) output frequency (f fnout ) figure 1. fractional-n synthesizer architecture the two dividers in the feedback path always differ by one count. that is, if one divider is set to divide by p = 5, then the other divider divides by p?1 = 4 . the mux choses between the two based on the control circuit. the idea behind the fractional-n approach is that every input reference edge is used. only those output edges that are nearest to an input edge get fed back to the phase- frequency comparator. in addition, the nearest output edges are chosen in such a way that the net offset, over a number of edges, zeroes out. it is the control circuit?s job to drive the mux such that only the ?correct? edges get fed back. in the above fractional-n circuit, if the output frequency should be, for example, 5 times the input frequency, then p is set to 5, and the control circuit sets the mux to only feed back the output of the p divider. if the output frequency should be, for example, 4 1 / 2 times the input frequency, then the control circuit alternates evenly between the p and the p?1 divider output. for every two input edges (one to compare against p, and another to compare against p?1), you will get 5 + 4 output edges, yielding an output frequency 9/2 the input frequency. whereas p sets the integer part of the multiplication factor from input to output frequency, the control circuit determines the fractional part. by mixing the output of the p and p?1 dividers correctly, the control circuit can fashion any output frequency from p?1 times the input to p times the input, as long as that ratio can be expressed as a ratio of integers.
6 sy87739l micrel, inc. m9999-062807 hbwhelp@micrel.com or (408) 955-1690 123412312341 123 1 figure 2. 11/3 example figure 2 shows an example generating an output frequency 3 2 / 3 times the input frequency. since the output frequency is between 3 and 4 times the input, p is set to 4. we need to select the p divider twice, and select the p?1 divider once. multiplying by 4 two times out of three, and multiplying by 3 one time out of three, averages to a multiplication of 3 2 / 3 . the top waveform is the reference input. the bottom waveform is the multiplied output. the waveform in the middle shows those edges from the output that most closely matches a corresponding reference waveform edge. the control circuit must generate a repeating pattern to the mux of something like ?101?, so that the p divider is selected twice, and the p?1 divider is selected once, every three reference edges. fractional-n phase-frequency detector this circuit, besides generating ?pump up? and ?pump down? signals, also generates delta phase signals for use by the lock detect circuit. this detector circuit also accepts a gating signal from the fractional-n control block. when gated, the phase detector generates neither pump up nor pump down pulses. fractional-n charge pump this circuit converts the ?pump up? and ?pump down? signals from the phase-frequency detector into current pulses. an external loop filter integrates these current pulses into a control voltage. charge pump current is selectable. this modifies loop gain as follows: during acquisition of the reference, the charge pump current is fixed at 20a. once the acquisition sequencer has completed center frequency trimming, then it changes the current of this charge pump to 50a. fractional-n vco this circuit converts the voltage integrated by the external loop filter into a digital clock stream. the frequency of this clock varies based on this control voltage. this vco has a coarse and a fine input, with a combined range of 540mhz to 729mhz. the coarse input trims the vco, as described below, so that its center frequency rests near the target frequency to generate. the fine adjustment forms part of the closed loop. vco gain is nominally 200mhz per volt. fractional-n p/p-1 divider this is the main divider for the fractional-n loop. the logical value of the output of the control block (figure 1) defines whether the divider divides by p (values shown in table 1) or by p?1. the expression for the fractional division becomes: f ractional division p ? q qq p?1 p?1 p = + () ? ? ? ? ? ? ? ? where q p is the number of reference clock periods during which the divider must divide by p and q p -1 is the number of reference clock periods during which the divider must divide by p?1. care should be exercised when selecting the value of p (table 1) so that the voltage-controlled oscillator (vco) of the fractional-n pll is not driven out of range. the following conditions must be met: f (min) f fractional division f (max) vco ref vco << f (min) f p ? q qq f (ma x) vco ref p?1 p?1 p vco << + () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? where, f vco (min) = 540mhz f vco (max) = 729mhz f ref = frequency of the reference clock. divsel3 divsel2 divsel1 divsel0 p 0 00017 0 00118 0 01019 0 01120 0 10021 0 10122 0 11023 0 11124 1 00025 1 00126 1 01027 1 01128 1 10029 1 10130 1 11031 1 11132 table 1. divsel divider setting
7 sy87739l micrel, inc. m9999-062807 hbwhelp@micrel.com or (408) 955-1690 fractional-n control this circuit controls the p/p?1 divider, selecting the appropriate divide ratio, either p or p?1, in the correct pattern. as explained in the example of figure 2 above, controlling the p/p?1 divider amounts to generating a repeating binary bit stream. in that example, a ?1? represents dividing by 4, and a ?0? represents dividing by 3. the full cycle, ?101?, says to divide by 4 twice, and to divide by 3 once. in the general case, the pattern ?101? need not change based on the p divider value. to multiply by 14/3 instead of 11/3, for example, the same ?101? pattern would be used, but we would alternate dividing by 5 and 4, instead of dividing by 4 and 3. the p value, in effect, represents the integer part of the multiplication factor. the repeating binary bit pattern really depends only on the number of times to divide by p, and the number of times to divide by p?1. we label the number of times to divide by p as q p , and the number of times to divide by p?1 as q p?1 . the fractional-n synthesizer generates its output frequency as per this formula: fp? q qq f fnout p?1 pp?1 re f = + ? ? ? ? ? ? ? ? in our figure two example, we multiply by 11/3, or 4 1 / 3 . matching against the formula, p = 4, q p?1 = 1, and q p =2. the sy87739l accepts q p and q p?1 values from its microwire? interface, where they exist as the 5-bit values ?qp? and ?qpm1.? both values are unsigned binary numbers. q p and q p-1 are both constrained to be 31 or less, and their sum is also constrained to be 31 or less. that means that the denominator in the above formula must be 31 or less. as would be expected from the formula, setting q p to zero causes frequency multiplication exactly by p?1. setting q p?1 to zero causes frequency multiplication exactly by p. the sy87739l behavior is undefined if both q p and q p?1 are both set to zero. in the general case, the length of the repeating binary bit pattern is q p + q p?1 . it consists of q p ?1?, and q p?1 ?0.? the sy87739l accomplishes this by implementing bresenham?s algorithm in hardware. to see how this works, we need a more complicated example. let?s say we need to multiply by 110/23, or 5 ? 5/23. in this example, p = 5, q p?1 = 5, and q p = 18. the na?ve approach would generate a bit pattern of: 11111 11111 11111 11100 000 the spaces between groups of five digits are added for readability only. this pattern is 23 bits long, with q p (that is, 18) ?1? and q p?1 (that is, 5) ?0?, so it will multiply correctly, but it doesn?t match p/p?1 divider edges to input edges in the best way possible. in fact, the best pattern, in terms of minimizing distance between divider and reference input edges, is: 11110 11110 1110 11110 1110 table 2 shows how bresenham?s algorithm works. the first column is an accumulator. it starts at zero, but otherwise takes the result from the fourth column of the previous row. the second column is the value to add to the accumulator at each step. in the general case, this is always q p?1 . the third column forms the sum. the fourth column takes the sum modulo (q p + q p?1 ). the last column is ?0? whenever the modulo changes the sum. note that the table has 23 rows, before the sum is zero, and the entire algorithm repeats itself. accum add sum modulo bit 05551 5 5 10 10 1 10 5 15 15 1 15 5 20 20 1 20 5 25 2 0 25771 7 5 12 12 1 12 5 17 17 1 17 5 22 22 1 22 5 27 4 0 45991 9 5 14 14 1 14 5 19 19 1 19 5 24 1 0 15661 6 5 11 11 1 11 5 16 16 1 16 5 21 21 1 21 5 26 3 0 35881 8 5 13 13 1 13 5 18 18 1 18 5 23 0 0 table 2. 5/23 example note that the sequence of bits in the last column, reading down, is the optimal pattern to generate. the choice of repeating bit pattern reduces jitter because a fractional-n synthesizer relies on edges temporarily not matching, but averaging out over some time interval. anything that reduces the timing disparity between edges arriving at the phase-frequency comparator will reduce jitter. center frequency trim this circuit block generates two identical reference voltages for the two vco on the sy87739l. this voltage pair can be digitally trimmed. trimming occurs under control of the acquisition sequencer, which trims for center frequency of the fractional-n synthesizer only. the wrapper synthesizer vco is matched to the fractional-n vco. both vco are fed
8 sy87739l micrel, inc. m9999-062807 hbwhelp@micrel.com or (408) 955-1690 the same coarse adjustment voltage, and so both center nominally at the same frequency. an 8-bit counter implements the voltage steps. the acquisition sequencer steps through this counter, which changes its voltage by about 12mv per step. the coarse input to the vco is nominally set at 500mhz per volt. the acquisition sequencer exercises the center frequency trim circuit so that the vco control voltage ends up within about 12mv of where it should be, were it exactly centered for the desired output frequency. lock detector the sy87739l ensures proper operation of both synthesizers by verifying that both pll have achieved lock. the locked output asserts active high only when this is the case, that is, both pll are locked. the sy87739l implements a digital lock detector that is both simple and robust. each phase-frequency detector provides a charge pump output that is the logical or of pump up and pump down pulses. the lock detect circuit processes this charge pump output with a pulse width discriminator. once each reference clock rising edge, the discriminator will produce a pulse, only if the phase difference between the feedback divider and the reference input is too large. these pulses are subsequently processed digitally. a pll that is out of lock, is declared to be in lock only if 256 consecutive reference clocks have no large phase errors, as reported by the pulse width discriminator. any large phase error event, even a single one, that arrives before lock is declared, will reset the circuit. once in lock, a pll is declared out of lock if more large- phase-difference than small-phase-difference events occur that is, if over time, a net of 256 large-phase-difference events occur. that is accomplished by counting up when large-phase-difference events occur and counting down in the case of small-phase events. wrapper synthesizer the frequency generated by the fractional-n pll is further processed by a more classical pll circuit, as shown in figure 3. phase- frequency detector/ charge pump vco m n loop filter output frequency (f wrout ) input frequency (f fnout ) figure 3. wrapper architecture this circuit further modifies the frequency generated by the fractional-n loop. this comes in handy where digital wrapper and/or fec is implemented. the wrapper synthesizer generates just a few ratios near 1. the wrapper modifies the frequency based on the values of m and n, the dividers, as per: 5 40mhz f n m f n m p? q qq wrout fnout p?1 p?1 p == + ? ? ? ? ? ? ? ? f 729mhz ref wrapper phase-frequency detector this circuit generates pump up and pump down signals for the charge pump, and also generates delta phase for the lock detector. wrapper charge pump this circuit converts the pump signals from the phase- frequency detector into current pulses. charge pump current is fixed at about 20a. an external loop filter integrates these current pulses into a control voltage. wrapper vco this circuit matches the fractional-n vco in construction and operation, so that the center frequency trim circuit can center both the fractional-n vco and the wrapper vco at about the same frequency. wrapper m divider this circuit forms the denominator of the ratio by which the wrapper synthesizer modifies the fractional-n output frequency. the division ratio is selected via microwire?, as the 3-bit mdivsel register, as per table 3 . mdivsel2 mdivsel1 mdivsel0 divisor 00016 00116 01018 01117 10031 10114 11032 11115 table 3. mdivsel divisor control the divisors are in two sets. the first set consists of the divisors 14, 15, 16, 17, and 18. the second set consists of 31 and 32. both m and n must be chosen from the same set. for example, an n divisor of 31 and an m divisor of 17 results in undefined behavior. the n m ? ? ? ? ? ? ratio must be kept smaller than 17 14 , that is, 18 14 is not allowed. wrapper n divider this circuit forms the numerator of the ratio by which the wrapper synthesizer modifies the fractional-n output frequency. the division ratio is selected via microwire?, as the 3-bit ndivsel register, as per table 4.
9 sy87739l micrel, inc. m9999-062807 hbwhelp@micrel.com or (408) 955-1690 ndivsel2 ndivsel1 ndivsel0 divisor 00016 00116 01018 01117 10031 10114 11032 11115 table 4. ndivsel divisor control p divider the output of the wrapper synthesizer is post divided down before appearing at the clkout pins. notice that, given the range of the wrapper vco (540mhz to 729mhz) and the maximum and minimum division ratios of the p divider (1 to 60, as shown in table 5), the minimum and maximum frequency of clkout is 10mhz and 729mhz respectively. postdivsel bit 43210 divisor 00000 1 00001 3 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14 01111 15 10000 16 10001 18 10010 20 10011 22 10100 24 10101 26 10110 28 10111 30 11000 32 11001 36 11010 40 11011 44 11100 48 11101 52 11110 56 11111 60 table 5. setting to program the division ratio of the p divider the divisor value is selected via microwire?. the 5-bit postdivsel register determines the divisor value. it is set as per table 5. the sy87739l does not guarantee a 50% duty cycle output. it is designed to provide well timed rising edges only. microwire? interface this standard bit-serial interface eases interfacing the sy87739l to microcontrollers. the sy87739l accepts one data bit on progdi per rising edge on progsk. the data is ignored when progcs is inactive low. when progcs is active high, bits are shifted into the sy87739l. the falling edge of progcs then initiates acquisition of the output frequency defined by the 32-bit program just loaded into the sy87739l. this means that, if the user wishes to re-acquire based on the same program, progcs needs to toggle high then low. programming to program the sy87739l to generate a certain frequency: 1. determine the required values of the programming parameters, as summarized in table 6. 2. set progcs active high. 3. shift in each of the 32 bits, as per table 6. the fields are loaded in sequence, from the first row to the last row. for each multi-bit field, the most significant bit is shifted in first. shift the bits in through progdi, clocking them with progsk edges. 4. set progcs inactive low. 5. wait for locked to assert high. field # bits reference preamble 4 always "0000" qp 5 section: gating the p/p-1 divider qpm1 5 section: gating the p/p-1 divider divsel 4 table 1 mfg. 3 always "000" postdivsel 5 table 5 ndivsel 3 table 4 mdivsel 3 table 3 table 6. programming sequence the sy87739l generates exact frequencies for common serial data streaming protocols. summary programming information appears in the next section. the sy87739l also enables micrel?s sy87721l anyrate? cdr to decode virtually anything within its range of operation, all from a 27.000mhz reference. details about how to program the sy87739l in the general case, including derivation of programs for both the standard protocols and the anyrate? application, appear in an applications note.
10 sy87739l micrel, inc. m9999-062807 hbwhelp@micrel.com or (408) 955-1690 standard protocol applications from a single 27.000mhz reference input, the sy87739l can generate exactly correct frequencies for at least the 18 protocols listed in table 7. this table also shows how to program the sy87739l for each protocol listed. this table assumes no digital wrapper. if your system includes such a wrapper, then modify the ndivsel and mdivsel bits accordingly. protocol sy87739l fout (mhz) programming bits etr 32 0000 10011 01000 0111 000 10010 101 101 oc-1 51.84 0000 00001 11000 0111 000 01100 101 101 fast ethernet 50 0000 00010 11001 1000 000 01101 101 101 fddi 125 0000 00100 10111 0111 000 00101 101 101 1/8 fibre channel 13.28125 0000 01011 00111 0111 000 11100 101 101 general 150 0000 00010 00111 0110 000 00100 101 101 oc-3/stm-1 155.52 0000 00001 11000 0111 000 00100 101 101 escon 50 0000 00010 11001 1000 000 01101 101 101 1/4 fibre channel 26.5625 0000 01011 00111 0111 000 10100 101 101 1/2 fibre channel 53.125 0000 01011 00111 0111 000 01100 101 101 oc-12/stm-4 622.08 0000 00011 11000 0111 000 00000 101 101 fibre channel 106.25 0000 01011 00111 0111 000 00110 101 101 gigabit ethernet 156.25 0000 00100 10111 0111 000 00100 101 101 d1 video 69 0000 00001 00000 0110 000 01001 101 101 hdtv 92.8125 0000 00001 01111 1000 000 00111 101 101 infiniband 125 0000 00100 10111 0111 000 00100 101 101 2x fibre channel 212.5 0000 01011 00111 0111 000 00011 101 101 oc-48/stm-16 155.52 0000 00001 11000 0111 000 00100 101 101 oc-48/stm-16 622 0000 00001 11000 0111 000 00000 101 101 table 7. protocol listings loop filter values each pll in the sy87739l adjusts its loop gain through an external loop filter. figure 4 shows micrel?s recommended values for these. fncvf+ or w rvcf+ fncvf ? or wrvcf ? 2k ? 0.1 f figure 4. recommended loop filter values
11 sy87739l micrel, inc. m9999-062807 hbwhelp@micrel.com or (408) 955-1690 demux tclk 4, 5, 8, 10 bits 4, 5, 8, 10 bits rclk rdata sy87724l post amp tia pin diode fiber laser diode fiber sy889x3 cmu cdr sy87721l anyrate ? ref_clk lock one ref_osc sy87739l sy889x2 anyclock? laser diode driver fractional-n synthesizer mux p 8 bits system block diagram
12 sy87739l micrel, inc. m9999-062807 hbwhelp@micrel.com or (408) 955-1690 functional block diagram phase- frequency detector charge pump vco center frequency trim p/(p-1) divider lock detector fn delta phase locked fn vcf loop filter m divider phase- frequency detector charge pump vco wr delta phase fine wr vcf loop filter fractional-n control n divider clkout p divider microwire? interface aquisition sequencer progcs progdi progsk refclk part number function data sheet link sy87739l-eval fractional-n synthesizer evaluation board www.micrel.com/product-info/eval_boards.shtml related product and support documentation
13 sy87739l micrel, inc. m9999-062807 hbwhelp@micrel.com or (408) 955-1690 package ep- exposed pa d die compside island heat dissipation heavy copper plane heavy copper plane v ee v ee heat dissipation pcb thermal consideration for 32-pin epad-tqfp package 32-pin epad-tqfp 7mm x 7mm (die up) (h32-2) rev. 01 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant inj ury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or systems is at purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2006 micrel, incorporated.

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