1 tm fn4029.5 hip5010, HIP5011 7v, 17a synchrofet? complementary drive synchronous half-bridge designed with the p6 and pentium? in mind, the intersil synchrofet? family provides a new approach for implementing a synchronous rectified buck switching regulator. the synchrofet replaces two power dmoss, a schottky diode, two gate drivers and synchronous control circuitry. the complementary drive circuit turns the upper fet on and the lower fet off when the input from the pwm is high. when the input from the pwm goes low the upper fet turns off and the lower fet turns on. the HIP5011 has a pwm pin that inverts the relationship from the input to phase. this architecture allows the designer to utilize a low cost single-ended pwm controller in either a current or voltage mode configuration. the synchrofet operates in continuous conduction mode reducing emi constraints and enabling high bandwidth operation. several features ensure easy start-up. first, the supply currents stay below specification as the supply voltages ramp up; no unexpected surges occur that might perturb a soft-start or deplete a charge-pump. second, any power-up sequence of the v cc , v in , or pwm pins can be used without causing large currents. third, the chip operates when v cc is greater than 2v so v cc can be created from a charge pump powered from v in . features ? complementary drive, half-bridge power nmos ? use with low-cost single-output pwm controllers ? improve efficiency over conventional buck converter with schottky clamp ? minimum deadtime provided by adaptive shoot-through protection eliminates external schottky ? grounded case for low emi and simple heatsinking ? low operating current ? frequency exceeding 1mhz ? dual polarity input options ? all pins surge protected applications ?5v to 3.3v synchronous buck converters ? pentium and p6 power supplies ? powerpc ? power supplies ? bus terminations (btl and gtl) ? drive 5v motors directly from microprocessor typical application block diagram pentium? is a registered trademark of intel corporation. powerpc? is a trademark of international business machines. synchrofet? is a trademark of intersil corporation. pinouts hip5010is1, HIP5011is1 (sip - vertical) top view hip5010is, HIP5011is (sip - gullwing) top view 1 phase 2v in 3v cc 4 5 pwm (hip5010), pwm (HIP5011) 6v in 7 phase gnd (tab) front rows = pins 1, 3, 5, 7 back rows = pins 2, 4, 6 1 phase 2v in 3v cc 4 5 pwm (hip5010), pwm (HIP5011) 6v in 7 phase gnd (tab) ordering information part number temp. range ( o c) package pkg. no. hip5010is -40 to 85 7 ld gullwing sip z7.05b hip5010is1 -40 to 85 7 ld staggered vertical sip z7.05c HIP5011is -40 to 85 7 ld gullwing sip z7.05b HIP5011is1 -40 to 85 7 ld staggered vertical sip z7.05c +12v +3.3v phase pwm v in v cc control +5v hip5010 pwm controller synchronous rectified buck converter gnd data sheet march 1996 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 non-inverting synchrofet block diagram hip5010 driver driver v in phase gnd v cc buffer pwm v cc adaptive shoot-through protection inverting synchrofet block diagram HIP5011 driver driver v in phase gnd v cc buffer pwm v cc adaptive shoot-through protection hip5010, HIP5011
3 absolute maximum ratings thermal information (typical) supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16v input voltage v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7v i phase, i vin, i gnd (t j = 25 o c) . . . . . . . . . . . 17a (repetitive peak) i phase, i vin, i gnd (t j = 150 o c) . . . . . . . . . . 15a (repetitive peak) pwm input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4v to +16v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . .class 3 (4kv) lead temperature (soldering 10s) (lead tips only) . . . . . . 300 o c storage temperature range . . . . . . . . . . . . . . . . . . -65 o c to 150 o c junction temperature range . . . . . . . . . . . . . . . . . -40 o c to 150 o c operating conditions supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . +12v, 20% input voltage vin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 5.5v supply voltage, vcc, minimum for charge-pumped start-up .+4.0v package jc ?? ja ( o c/w) ? ( o c/w)01233 ??? soic (ib) . . . 26 63 45 42 41 35 sip (is). . . . . 2 55 30 25 24 18 sip (is1). . . . 2 - - --- ? versus additional square inches of 1 ounce copper on the printed circuit board . ?? jc is measured to pin 12 for the soic. printed circuit board had 1 square inch of copper. for sip packages value shown is typical with an infinite heat sink. ??? 200 linear feet per minute of air flow. i phase .sips:11.5a(rms), 11.2a(dc); soic:7.4a(rms), 7.4a(dc) i vin . . . sips:10.0a(rms), 8.5a(dc); soic:6.4a(rms), 6.4a(dc) i gnd . . . . .sips:8.5a(rms), 6.0a(dc); soic:5.4a(rms), 5.4a(dc) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied. electrical specifications parameters symbol test conditions t j = 25 o c t j = - 40 o c t j = 150 o c units min typ max min max r ds(on) upper mosfet r dsu v cc = 12v, v in = 5v - 34 39 - 65 m ? r ds(on) lower mosfet r dsl v cc = 12v, v in = 5v - 36 42 - 68 m ? v in operating current i vino v in = 5v, no load, 500khz - 5 8 - 10 ma v in quiescent current i vin pwm or pwm = v cc or gnd - 0.1 10 - 100 a v cc operating current i cco v cc = 12v, 500khz - 8 12 - 15 ma v cc quiescent current (hip5010) i ccih pwm = v cc -80- -400 a v cc quiescent current (hip5010) i ccil pwm = gnd - 0.1 10 - 100 a v cc quiescent current (HIP5011) i ccnih pwm = v cc - 0.1 10 - 100 a v cc quiescent current (HIP5011) i ccnil pwm = gnd - 140 - - 400 a low level pwm input voltage v il -1.8- 1 - v high level pwm input voltage v ih -2.1- - 3 v pwm input voltage hysteresis v ihys -0.3---v input pulldown resistance (hip5010) r pwm -220-100400k ? input pullup resistance (HIP5011) r pwm -220-100400k ? switching specifications parameters symbol test conditions t j = 25 o c t j = - 40 o c t j = 150 o c units min typ max min max upper device turn-off delay t phl v cc = 12v, i phase = -1a - 30 50 - 80 ns lower device turn-off delay t plh v cc = 12v, i phase = +1a - 30 50 - 80 ns dead time t dt v cc = +12v, i phase = -1a -10---ns phase rise-time t r v cc = 12v, i phase = -1a -20---ns phase fall-time t f v cc = 12v, i phase = +1a -20---ns hip5010, HIP5011
4 timing diagram pin descriptions symbol description v cc positive supply to control logic and gate drivers. de-couple this pin to gnd. v in fet switch input voltage. de-couple this pin to gnd. tie all v in terminals together. phase output. tie all phase terminals together. pwm (hip5010) pwm (HIP5011) single ended control input. this input connects to the pwm controller output. gnd system ground. 12v 2v 12v 0v 2v 0v 5v 4.5v 2.5v 0.5v 0v -0.5v t phl t plh t f t r t dt pwm (hip5010) pwm (HIP5011) phase note: i phase = +1a for t plh and t f , i phase = -1a for t phl , t dt , and t r . figure 1. hip5010, HIP5011
5 typical performance curves figure 2. i cco vs frequency figure 3. i vino vs frequency figure 4. r dsu vs v cc figure 5. r dsl vs v cc figure 6. r dsu or r dsl vs temperature 0 100 200 300 400 500 600 700 800 900 1000 frequency (khz) i cco (ma) 20 18 16 14 12 10 8 6 4 2 0 0 100 200 300 400 500 600 700 800 900 1000 frequency (khz) i vino (ma) 6.0 5.5 5.0 4.5 3.5 3.0 2.5 2.0 1.5 1.0 0 456789101112 v cc (v) r dsu (m ? ) 120 110 100 90 80 70 60 50 40 30 20 13 14 15 16 v in = 5v v in = 3.3v 456789101112 v cc (v) r dsl (m ? ) 120 110 100 90 80 70 60 50 40 30 20 13 14 15 16 v in = 5v and 3.3v -40 -20 0 20 40 60 80 100 120 140 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 temperature ( o c) r dsu or r dsl (normalized) hip5010, HIP5011
6 hip5010, HIP5011 single-in-line plastic packages (sip) e c2 a l2 d l b l1 c d1 e1 0.350 0.609 -a- -c- 0.006 -b- 0.004 0.00 - 0.0098 back view 0.450 land pattern 0.010 (0.25) b a m m cm e (0.15) heatslug plane (0.00 - 0.25) (0.10) (15.46) min (11.43) min (8.89) min 0.129 (3.27) typ 0.030 (0.76) typ e pin #1 0 o - 8 o l3 z7.05b 7 lead plastic single-in-line package surface mount ?gullwing? lead form symbol inches millimeters notes min max min max a 0.170 0.180 4.32 4.57 - c2 0.048 0.055 1.22 1.39 5 d 0.350 0.370 8.89 9.39 - e 0.395 0.405 10.04 10.28 - d1 0.310 - 7.88 - - e1 0.310 - 7.88 - - l 0.549 0.569 13.95 14.45 - l1 0.068 0.088 1.72 2.24 - l2 0.045 0.055 1.15 1.40 - l3 0.030 bsc 0.76 bsc 4 b 0.028 0.034 0.71 0.86 5, 6, 7 c 0.018 0.024 0.46 0.60 5 e 0.050 bsc 1.27 bsc - rev. 2 12/95 notes: 1. these package dimensions are within allowable dimensions of jedec mo-169ac, issue a. 2. controlling dimension: inch. 3. dimensioning and tolerance per ansi y14.5m-1982. 4. gauge plane l3 is parallel to heatslug plane. 5. dimensions include lead finish. 6. leads are not allowed above the datum . 7. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum ?b? by more than 0.003?? (0.08mm). -b-
7 hip5010, HIP5011 single-in-line plastic packages (sip) e b header -a- e a d1 d ?p -b- e2 e1 0.010 (0.25) a b m m 7 places l bottom l1 e 1 e 2 c 0.024 (0.61) a m all leads f 0.006 (0.15) l h h h h h l l l e 3 z7.05c 7 lead plastic single-in-line package staggered vertical lead form symbol inches millimeters notes min max min max a 0.170 0.180 4.32 4.57 - b 0.028 0.034 0.71 0.86 3, 4 c 0.018 0.024 0.46 0.60 3 d 0.395 0.405 10.04 10.28 - d1 0.198 0.202 5.03 5.13 - e 0.595 0.605 15.11 15.37 - e1 0.350 0.370 8.89 9.39 - e2 0.110 bsc 2.79 bsc e 0.050 bsc 1.27 bsc - e1 0.200 bsc 5.08 bsc - e2 0.169 bsc 4.29 bsc - e3 0.300 bsc 7.62 bsc - f 0.048 0.055 1.22 1.39 3 l 0.150 0.176 3.81 4.47 - l1 0.600 0.620 15.24 15.74 - ?p 0.147 0.152 3.73 3.86 3 rev. 1 4/98 notes: 1. controlling dimension: inch. 2. dimensioning and tolerancing per ansi y14.5m-1982. 3. dimensions include lead finish. 4. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall not cause lead width to exceed maxi- mum ?b? by more than 0.003 inches (0.08mm).
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