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page 1 m32c/83 group (m32c/83, m32c/83t) single-chip 16/32-bit cmos microcomputer 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r rej03b0013-0141 rev.1.41 jan. 31, 2006 1. overview the m32c/83 group (m32c/83, m32c/83t) microcomputer is a single-chip control unit that utilizes high- performance silicon gate cmos technology with the m32c/80 series cpu core. the m32c/83 group (m32c/83, m32c/83t) is available in 144-pin and 100-pin plastic molded lqfp/qfp packages. with a 16-mbyte address space, this microcomputer combines advanced instruction manipulation capabili- ties to process complex instructions by less bytes and execute instructions at higher speed. it includes a multiplier and dmac adequate for office automation, communication devices and industrial equipments, and other high-speed processing applications. 1.1 applications automobiles, audio, cameras, office equipment, communications equipment, portable equipment, etc.
page 2 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 1.2 performance overview tables 1.1 and 1.2 list performance overview of the m32c/83 group (m32c/83, m32c/83t). table 1.1 m32c/83 group (m32c/83, m32c/83t) performance (144-pin package) characteristic performance m32c/83 m32c/83t cpu basic instructions 108 instructions minimum instruction execution time 31.3 ns (f(bclk)=32 mhz, v cc =4.2 to 5.5 v) (3) 31.3 ns (f(bclk)=32 mhz, v cc =4.2 to 5.5 v) (3) 50 ns (f(bclk)=20 mhz, v cc =3.0 to 5.5 v) operating mode single-chip mode, memory expansion single-chip mode mode and microprocessor mode address space 16 mbytes memory capacity see table 1.3 peripheral i/o port 123 i/o pins and 1 input pin function multifunction timer timer a: 16 bits x 5 channels, timer b: 16 bits x 6 channels three-phase motor control circuit intelligent i/o time measurement function: 16 bits x 12 channels waveform generating function: 16 bits x 28 channels communication function (clock synchronous serial i/o, clock asynchronous se- rial i/o, hdlc data processing, clock synchronous variable length serial i/o, iebus (1) , 8-bit or 16-bit clock synchronous serial i/o) serial i/o 5 channels clock synchronous serial i/o, clock asynchronous serial i/o, iebus (1) , i 2 c bus (2) can module 1 channel supporting can 2.0b specification a/d converter 10-bit a/d converter: 2 circuit, 34 channels d/a converter 8 bits x 2 channels dmac 4 channels dmac ii can be activated by all peripheral function interrupt sources immediate transfer, calculation transfer and chain transfer functions dram cas before ras refresh, self-reflesh, edo, ep crc calculation circuit crc-ccitt x/y converter 16 bits x 16 bits watchdog timer 15 bits x 1 channel (with prescaler) interrupt 42 internal and 8 external sources, 5 software sources, interrupt priority level: 7 clock generation circuit 4 circuits main clock oscillation circuit(*), sub clock oscillation circuit(*), on-chip oscillator, pll frequency synthesizer (*)equipped with a built-in feedback resistor. ceramic resonator or crystal oscilla- tor must be connected externally oscillation stop detect function main clock oscillation stop detect function electrical supply voltage 4.2 to 5.5 v (f(bclk)=32 mhz) 4.2 to 5.5 v (f(bclk)=32 mhz) charact- 3.0 to 5.5 v (f(bclk)=20 mhz, through vdc) eristics 3.0 to 3.6 v (f(bclk)=20 mhz, not through vdc) power consumption 41 ma (v cc =5 v, f(bclk)=32 mhz) 41 ma (v cc =5 v, f(bclk)=32 mhz) 38 ma (v cc =5 v, f(bclk)=30 mhz) 38 ma (v cc =5 v, vf(bclk)=30 mhz) 26 ma (v cc =3.3 v, f(bclk)=20 mhz) 470 a (v cc =5 v, f(x cin )=32 khz, 470 a (v cc =5 v, f(x cin )=32 khz, in wait mode) in wait mode) 0.4 a (v cc =5 v, stop mode) 340 a (v cc =3.3 v, f(x cin )=32 khz, through vdc, in wait mode) 5.0 a (v cc =3.3 v, f(x cin )=32 khz, not through vdc, in wait mode) 0.4 a (v cc =5 v, stop mode) 0.4 a (v cc =3.3 v, stop mode) flash program/erase supply voltage 3.3 0.3 v or 5.0 0.5 v 5.0 0.5 v memory program and erase endurance 100 times operating ambient temperature ?0 to 85 o c, ?0 to 85 o c (optional) ?0 to 85 o c (t version) package 144-pin plastic molded lqfp notes: 1. iebus is a trademark of nec electronics corporation. 2. i 2 c bus is a trademark of koninklijke philips electronics n. v. 3. contact our sales office if 30-mhz or higher frequency is required. all options are on a request basis.
page 3 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m table 1.2 m32c/83 group (m32c/83, m32c/83t) performance (100-pin package) characteristic performance m32c/83 m32c/83t cpu basic instructions 108 instructions minimum instruction execution time 31.3 ns (f(bclk) = 32 mhz, v cc = 4.2 to 5.5 v) 31.3 ns (f(bclk) = 32 mhz, v cc =4.2 to 5.5 v) 50 ns (f(bclk) = 20 mhz, v cc = 3.0 to 5.5 v) operating mode single-chip mode, memory expansion single-chip mode mode and microprocessor mode address space 16 mbytes memory capacity see table 1.3 peripheral i/o port 87 i/o pins and 1 input pin function multifunction timer timer a: 16 bits x 5 channels, timer b: 16 bits x 6 channels three-phase motor control circuit intelligent i/o time measurement function: 16 bits x 5 channels waveform generating function: 16 bits x 10 channels communication function (clock synchronous serial i/o, clock asynchronous se- rial i/o, hdlc data processing, clock synchronous variable length serial i/o, iebus (1) ) serial i/o 5 channels clock synchronous serial i/o, clock asynchronous serial i/o, iebus (1) , i 2 c bus (2) can module 1 channel supporting can 2.0b specification a/d converter 10-bit a/d converter: 2 circuits, 26 channels d/a converter 8 bits x 2 channels dmac 4 channels dmac ii can be activated by all peripheral function interrupt sources immediate transfer, calculation transfer and chain transfer functions crc calculation circuit crc-ccitt x/y converter 16 bits x 16 bits watchdog timer 15 bits x 1 channel (with prescaler) interrupt 42 internal and 8 external sources, 5 software sources interrupt priority level: 7 clock generation circuit 4 circuits main clock oscillation circuit(*), sub clock oscillation circuit(*), on-chip oscillator, pll frequency synthesizer (*)equipped with a built-in feedback resistor. ceramic resonator or crystal oscillator must be connected externally oscillation stop detect function main clock oscillation stop detect function electrical supply voltage 4.2 to 5.5 v (f(bclk)=32 mhz) 4.2 to 5.5 v (f(bclk)=32 mhz) charact- 3.0 to 5.5 v (f(bclk)=20 mhz, through vdc) eristics 3.0 to 3.6 v (f(bclk)=20 mhz, not through vdc) power consumption 41 ma (v cc =5 v, f(bclk)=32 mhz) 41 ma (v cc =5 v, f(bclk)=32 mhz) 38 ma (v cc =5 v, f(bclk)=30 mhz) 38 ma (v cc =5 v, vf(bclk)=30 mhz) 26 ma (v cc =3.3 v, f(bclk)=20 mhz) 470 a (v cc =5 v, f(x cin )=32 khz, 470 a (v cc =5 v, f(x cin )=32 khz, in wait mode) in wait mode) 0.4 a (v cc =5 v, stop mode) 340 a (v cc =3.3 v, f(x cin )=32 khz, through vdc, in wait mode) 5.0 a (v cc =3.3 v, f(x cin )=32 khz, not through vdc, in wait mode) 0.4 a (v cc =5 v, stop mode) 0.4 a (v cc =3.3 v, stop mode) flash program/erase supply voltage 3.3 0.3 v or 5.0 0.5 v 5.0 0.5 v memory program and erase endurance 100 times operating ambient temperature ?0 to 85 o c, ?0 to 85 o c (optional) ?0 to 85 o c (t version) package 100-pin plastic molded lqfp/qfp notes: 1. iebus is a trademark of nec electronics corporation. 2. i 2 c bus is a trademark of koninklijke philips electronics n. v. 3. contact our sales office if 30-mhz or higher frequency is required. all options are on a request basis.
page 4 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 1.3 block diagram figure 1.1 shows a block diagram of the m32c/83 group (m32c/83, m32c/83t) microcomputer. figure 1.1 m32c/83 group (m32c/83, m32c/83t) block diagram port p0 port p1 port p2 port p3 port p4 port p5 port p6 port p7 port p15 port p14 port p13 port p12 port p10 port p9 port p8 p8 5 port p11 r0h r0l r1h r1l r2 r3 a0 a1 fb sb notes: 1. ports p11 to p15 are provided only in the 144-pin package. 2. included only in the 144-pin package. 3. can be used only in the 144-pin package. flg intb isp usp pc svf svp vct multiplier m32c/80 series cpu core clock generation circuit x in - x out x cin - x cout on-chip oscillator pll frequency synthesizer a/d converter: 2 circuits standard: 18 inputs (2) maximum: 34 inputs (2) uart/clock synchronous serial i/o: 5 channels x/y converter: 16 bits x 16 bits crc calculation circuit (ccitt): x 16 +x 12 +x 5 +1 timer (16 bits) timer a: 5 channels timer b: 6 channels three-phase motor control circuit watchdog timer (15 bits) d/a converter (8 bits x 2 channels) intelligent i/o ( 4 groups ) peripheral functions rom ram memory 8788 5 (note1) 88 7 8888888 8 dmac dmacii dramc can module time measurement: 12 channels (2) wave generating: 28 channels (2) communication functions: clock synchronous serial i/o, uart, iebus, hdlc data processing, 8-bit or 16-bit clock synchronous serial i/o (3)
page 5 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 1.4 product information table 1.3 lists the product information. figure 1.2 shows the product numbering system. table 1.3 m32c/83 group (1) (m32c/83) as of january, 2006 table 1.3 m32c/83 group (2) (t version, m32c/83t) as of january, 2006 r e b m u n e p y te p y t e g a k c a p m o r y t i c a p a c m a r y t i c a p a c s k r a m e r p g j f 5 3 8 0 3 m) a - q 6 p 4 4 1 ( a - a k 4 4 1 0 p q l p k 2 1 5k 1 3y r o m e m h s a l f p g j f 3 3 8 0 3 m) a - q 6 p 0 0 1 ( a - b k 0 0 1 0 p q l p p f j f 3 3 8 0 3 m) a - s 6 p 0 0 1 ( a - b j 0 0 1 0 p q r p r e b m u n e p y te p y t e g a k c a p m o r y t i c a p a c m a r y t i c a p a c s k r a m e r j f 3 3 8 0 3 mtp g) a - q 6 p 0 0 1 ( a - b k 0 0 1 0 p q l pk 2 1 5k 1 3 y r o m e m h s a l f n o i s r e v t y t i l i b a i l e r - h g i h ( 5 8 o ) n o i s r e v c package type: fp = package prqp0100jb-a (100p6s-a) gp = package plqp0100kb-a (100p6q-a) package plqp0144ka-a (144p6q-a) rom capacity: j = 512 kbytes memory type: f = flash memory version m30 83 3 f j gp m32c/83 group m16c family ram capacity, pin count, etc. (value itself has no specific meaning) classification: blank = general industrial use t = t version please contact our sales office for v version information. figure 1.2 product numbering system
page 6 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m srxd4 / sda4 / txd4 / anex1 / p9 6 clk4 / anex0 / p9 5 ss4 / rts4 / cts4 / tb4 in / da1 / p9 4 ss3 / rts3 / cts3 / tb3 in / da0 / p9 3 ie out / istxd2 / outc2 0 / srxd3 / sda3 / txd3 / tb2 in / p9 2 ie in / isrxd2 / stxd3 / scl3 / rxd3 / tb1 in / p9 1 clk3 / tb0 in / p9 0 p14 6 p14 5 p14 4 outc1 7 / inpc1 7 / p14 3 outc1 6 / inpc1 6 / p14 2 outc1 5 / p14 1 outc1 4 / p14 0 byte cnvss v cont / x cin / p8 7 x cout / p8 6 reset x out vss x in vcc nmi / p8 5 int2 / p8 4 can in / int1 / p8 3 isrxd3 / outc3 2 / can out / int0 / p8 2 istxd3 / outc3 0 / u / ta4 in / p8 1 be0 in / isrxd0 / inpc0 2 / u / ta4 out / p8 0 can in / isclk0 / outc0 1 / inpc0 1 / ta3 in / p7 7 can out / be0 out / istxd0 / outc0 0 / inpc0 0 / ta3 out / p7 6 be1 in / isrxd1 / outc1 2 / inpc1 2 / w / ta2 in / p7 5 isclk1 / outc1 1 / inpc1 1 / w / ta2 out / p7 4 be1 out / istxd1 / outc1 0 / ss2 / rts2 / cts2 / v / ta1 in / p7 3 clk2 / v / ta1 out / p7 2 (3) ie in / isrxd2 / outc2 2 / stxd2 / scl2 / rxd2 / ta0 in / tb5 in / p7 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 50 49 48 47 46 45 44 43 42 41 40 39 38 37 56 55 54 53 52 51 62 61 60 59 58 57 68 67 66 65 64 63 72 71 70 69 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 131 132 133 134 135 136 137 138 139 140 141 142 143 144 125 126 127 128 129 130 119 120 121 122 123 124 113 114 115 116 117 118 109 110 111 112 m32c/83 group (m32c/83, m32c/83t) plqp0144ka-a (144p6q-a) p1 1 / d 9 p1 2 / d 10 p1 3 / d 11 p1 4 / d 12 p1 5 / d 13 / int3 p1 6 / d 14 / int4 p1 7 / d 15 / int5 p2 0 / a 0 ( / d 0 ) / an2 0 p2 1 / a 1 ( / d 1 ) / an2 1 p2 2 / a 2 ( / d 2 ) / an2 2 p2 3 / a 3 ( / d 3 ) / an2 3 p2 4 / a 4 ( / d 4 ) / an2 4 p2 5 / a 5 ( / d 5 ) / an2 5 p2 6 / a 6 ( / d 6 ) / an2 6 p2 7 / a 7 ( / d 7 ) / an2 7 vss p3 0 / a 8 ( ma 0 ) ( / d 8 ) vcc p12 0 / outc3 0 / istxd3 p12 1 / outc3 1 / isclk3 p12 2 / outc3 2 / isrxd3 p12 3 / outc3 3 p12 4 / outc3 4 p3 1 / a 9 ( ma 1 ) ( / d 9 ) p3 2 / a 10 ( ma 2 ) ( / d 10 ) p3 3 / a 11 ( ma 3 ) ( / d 11 ) p3 4 / a 12 ( ma 4 ) ( / d 12 ) p3 5 / a 13 ( ma 5 ) ( / d 13 ) p3 6 / a 14 ( ma 6 ) ( / d 14 ) p3 7 / a 15 ( ma 7 ) ( / d 15 ) p4 0 / a 16 ( ma 8 ) p4 1 / a 17 ( ma 9 ) vss p4 2 / a 18 ( ma 10 ) vcc p4 3 / a 19 ( ma 11 ) d 8 / p1 0 an0 7 / d 7 / p0 7 an0 6 / d 6 / p0 6 an0 5 / d 5 / p0 5 an0 4 / d 4 / p0 4 p11 4 outc1 3 / p11 3 be1 in / isrxd 1 / outc1 2 / inpc1 2 / p11 2 isclk1 / outc1 1 / inpc1 1 / p11 1 be1 out / istxd1 / outc1 0 / p11 0 an0 3 / d 3 / p0 3 an0 2 / d 2 / p0 2 an0 1 / d 1 / p0 1 an0 0 / d 0 / p0 0 inpc0 7 / an15 7 / p15 7 inpc0 6 / an15 6 / p15 6 outc0 5 / inpc0 5 / an15 5 / p15 5 outc0 4 / inpc0 4 / an15 4 / p15 4 inpc0 3 / an15 3 / p15 3 be0 in / isrxd0 / inpc0 2 / an15 2 / p15 2 isclk0 / outc0 1 / inpc0 1 / an15 1 / p15 1 vss be0 out / istxd0 / outc0 0 / inpc0 0 / an15 0 / p15 0 vcc ki 3 / an 7 / p10 7 ki 2 / an 6 / p10 6 ki 1 / an 5 / p10 5 ki 0 / an 4 / p10 4 an 3 / p10 3 an 2 / p10 2 an 1 / p10 1 avss an 0 / p10 0 v ref avcc stxd4 / scl4 / rxd4 / ad trg / p9 7 p4 4 / cs3 / a 20 (ma 12 ) p4 5 / cs2 / a 21 p4 6 / cs1 / a 22 p4 7 / cs0 / a 23 p12 5 / outc3 5 p12 6 / outc3 6 p12 7 / outc3 7 p5 0 / wrl / wr / casl p5 1 / wrh / bhe / cash p5 2 / rd / dw p5 3 / clk out / bclk / ale p13 0 / outc2 4 p13 1 / outc2 5 vcc p13 2 / outc2 6 vss p13 3 / outc2 3 p5 4 / hlda / ale p5 5 / hold p5 6 / ale / ras p5 7 / rdy p13 4 / outc2 0 / istxd2 / ie out p13 5 / outc2 2 / isrxd2 / ie in p13 6 / outc2 1 / isclk2 p13 7 / outc2 7 p6 0 / cts0 / rts0 / ss0 p6 1 / clk0 p6 2 / rxd0 / scl0 / stxd0 p6 3 / txd0 / sda0 / srxd0 p6 4 (1) p6 5 / clk1 vss p6 6 / rxd1 / scl1 / stxd1 vcc p6 7 / txd1 / sda1 / srxd1 p7 0 (2, 3) notes: 1. p6 4 / cts1 / rts1 / ss1 / outc21 / isclk2 2. p7 0 / ta0out / txd2 / sda2 / srxd2 / outc20 / istxd2 / ieout 3. p7 0 and p7 1 are ports for the n-channel open drain output. 1.5 pin assignment figures 1.3 to 1.5 show pin assignments (top view). figure 1.3 pin assignment for 144-pin package
page 7 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 byte cnv ss x cin /v cont x cout reset x out v ss x in v cc v cc v ss p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 p14 6 p14 5 p14 4 p14 3 p14 2 p14 1 p14 0 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 p13 7 nmi int2 int1 int0 tb4 in tb3 in tb2 in tb1 in tb0 in ta4 in /u ta4 out /u ta3 in ta3 out ta2 in /w ta2 out /w ta1 in /v ta1 out /v tb5 in /ta0 in ta0 out txd4/sda4/srxd4 clk4 cts4/rts4/ss4 cts3/rts3/ss3 txd3/sda3/srxd3 rxd3/scl3/stxd3 clk3 can in can out can in can out cts2/rts2/ss2 clk2 rxd2/scl2/stxd2 txd2/sda2/srxd2 txd1/sda1/srxd1 rxd1/scl1/stxd1 clk1 cts1/rts1/ss1 txd0/sda0/srxd0 rxd0/scl0/stxd0 clk0 cts0/rts0/ss0 outc2 0 /ie out /istxd2 ie in /isrxd2 inpc1 7 /outc1 7 inpc1 6 /outc1 6 outc1 5 outc1 4 outc3 2 /isrxd3 outc3 0 /istxd3 inpc0 2 /isrxd0/be0 in inpc0 1 /outc0 1 /isclk0 inpc0 0 /outc0 0 /istxd0/be0 out inpc1 2 /outc1 2 /isrxd1/be1 in inpc1 1 /outc1 1 /isclk1 outc1 0 /istxd1/be1 out outc2 2 /isrxd2/ie in outc2 0 /istxd2/ie out outc2 1 /isclk2 outc2 7 anex1 anex0 da1 da0 intelligent i/o pin bus control pin (1) analog pin interrupt pin pin no control pin port timer pin uart/can pin notes: 1. bus control pins in m32c/83t cannot be used. table 1.4 pin characteristics for 144-pin package
page 8 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 v ss v cc v cc v ss v cc v ss p13 6 p13 5 p13 4 p5 7 p5 6 p5 5 p5 4 p13 3 p13 2 p13 1 p13 0 p5 3 p5 2 p5 1 p5 0 p12 7 p12 6 p12 5 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p12 4 p12 3 p12 2 p12 1 p12 0 p3 0 p2 7 p2 6 p2 5 timer pin uart/can pin outc2 1 /isclk2 outc2 2 /isrxd2/ie in outc2 0 /istxd2/ie out outc2 3 outc2 6 outc2 5 outc2 4 outc3 7 outc3 6 outc3 5 outc3 4 outc3 3 outc3 2 /isrxd3 outc3 1 /isclk3 outc3 0 /istxd3 an2 7 an2 6 an2 5 rdy ale/ras hold hlda/ale clk out /bclk/ale rd/dw wrh/bhe/cash wrl/wr/casl cs0/a 23 cs1/a 22 cs2/a 21 cs3/a 20 (ma 12 ) a 19 (ma 11 ) a 18 (ma 10 ) a 17 (ma 9 ) a 16 (ma 8 ) a 15 (ma 7 )(/d 15 ) a 14 (ma 6 )(/d 14 ) a 13 (ma 5 )(/d 13 ) a 12 (ma 4 )(/d 12 ) a 11 (ma 3 )(/d 11 ) a 10 (ma 2 )(/d 10 ) a 9 (ma 1 )(/d 9 ) a 8 (ma 0 )(/d 8 ) a 7 (/d 7 ) a 6 (/d 6 ) a 5 (/d 5 ) intelligent i/o pin bus control pin (1) analog pin interrupt pin pin no control pin port notes: 1. bus control pins in m32c/83t cannot be used. table 1.4 pin characteristics for 144-pin package (continued)
page 9 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 v ss v cc av ss v ref av cc p2 4 p2 3 p2 2 p2 1 p2 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 p0 7 p0 6 p0 5 p0 4 p11 4 p11 3 p11 2 p11 1 p11 0 p0 3 p0 2 p0 1 p0 0 p15 7 p15 6 p15 5 p15 4 p15 3 p15 2 p15 1 p15 0 p10 7 p10 6 p10 5 p10 4 p10 3 p10 2 p10 1 p10 0 p9 7 int5 int4 int3 ki 3 ki 2 ki 1 ki 0 timer pin rxd4/scl4/stxd4 an2 4 an2 3 an2 2 an2 1 an2 0 an0 7 an0 6 an0 5 an0 4 an0 3 an0 2 an0 1 an0 0 an15 7 an15 6 an15 5 an15 4 an15 3 an15 2 an15 1 an15 0 an 7 an 6 an 5 an 4 an 3 an 2 an 1 an 0 ad trg a 4 (/d 4 ) a 3 (/d 3 ) a 2 (/d 2 ) a 1 (/d 1 ) a 0 (/d 0 ) d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bus control pin (1) analog pin interrupt pin pin no outc1 3 inpc1 2 /outc1 2 /isrxd1/be1 in inpc1 1 /outc1 1 /isclk1 outc1 0 /istxd1/be1 out inpc0 7 inpc0 6 inpc0 5 /outc0 5 inpc0 4 /outc0 4 inpc0 3 inpc0 2 /isrxd0/be0 in inpc0 1 /outc0 1 /isclk0 inpc0 0 /outc0 0 /istxd0/be0 out control pin port uart/can pin intelligent i/o pin notes: 1. bus control pins in m32c/83t cannot be used. table 1.4 pin characteristics for 144-pin package (continued)
page 10 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 srxd4 / sda4 / txd4 / anex1 / p9 6 clk4 / anex0 / p9 5 ss4 / rts4 / cts4 / tb4 in / da1 / p9 4 ss3 / rts3 / cts3 / tb3 in / da0 / p9 3 ie out / istxd2 / outc2 0 / srxd3 / sda3 / txd3 / tb2 in / p9 2 ie in / isrxd2 / stxd3 / scl3 / rxd3 / tb1 in / p9 1 clk3 / tb0 in / p9 0 byte cnvss v cont / x cin / p8 7 x cout / p8 6 reset x out vss x in vcc nmi / p8 5 int2 / p8 4 can in / int1 / p8 3 isrxd3 / outc3 2 / can out / int0 / p8 2 istxd3 / outc3 0 / u / ta4 in / p8 1 be0 in / isrxd0 /inpc0 2 / u / ta4 out / p8 0 can in / isclk0 / outc0 1 / inpc0 1 / ta3 in / p7 7 can out / be0 out / istxd0 / outc0 0 / inpc0 0 / ta3 out / p7 6 be1 in / isrxd1 / outc1 2 / inpc1 2 / w / ta2 in / p7 5 isclk1 / outc1 1 / inpc1 1 / w / ta2 out / p7 4 be1 out / istxd1 / outc1 0 / ss2 / rts2 / cts2 / v / ta1 in / p7 3 clk2 / v / ta1 out / p7 2 (3) ie in / isrxd2 / outc2 2 / stxd2 / scl2 / rxd2 / ta0 in / tb5 in / p7 1 (3) ie out / istxd2 / outc2 0 / srxd2 / sda2 / txd2 / ta0 out / p7 0 p4 4 / cs3 / a 20 (ma 12 ) p4 5 / cs2 / a 21 p4 6 / cs1 / a 22 p4 7 / cs0 / a 23 p5 0 / wrl / wr / casl p5 1 / wrh / bhe / cash p5 2 / rd / dw p5 3 / clk out / bclk / ale p5 4 / hlda / ale p5 5 / hold p5 6 / ale / ras p5 7 / rdy p6 0 / cts0 / rts0 / ss0 p6 1 / clk0 p6 2 / rxd0 / scl0 / stxd0 p6 3 / txd0 / sda0 / srxd0 p6 4 (1) p6 5 / clk1 p6 6 / rxd1 / scl1 / stxd1 p6 7 / txd1 / sda1 / srxd1 p1 0 / d 8 p1 1 / d 9 p1 2 / d 10 p1 3 / d 11 p1 4 / d 12 p1 5 / d 13 / int3 p1 6 / d 14 / int4 p1 7 / d 15 / int5 p2 0 / a 0 ( / d 0 ) / an2 0 p2 1 / a 1 ( / d 1 ) / an2 1 p2 2 / a 2 ( / d 2 ) / an2 2 p2 3 / a 3 ( / d 3 ) / an2 3 p2 4 / a 4 ( / d 4 ) / an2 4 p2 5 / a 5 ( / d 5 ) / an2 5 p2 6 / a 6 ( / d 6 ) / an2 6 p2 7 / a 7 ( / d 7 ) / an2 7 vss p3 0 / a 8 ( ma 0 ) ( / d 8 ) vcc p3 1 / a 9 ( ma 1 ) ( / d 9 ) p3 2 / a 10 ( ma 2 ) ( / d 10 ) p3 3 / a 11 ( ma 3 ) ( / d 11 ) p3 4 / a 12 ( ma 4 ) ( / d 12 ) p3 5 / a 13 ( ma 5 ) ( / d 13 ) p3 6 / a 14 ( ma 6 ) ( / d 14 ) p3 7 / a 15 ( ma 7 ) ( / d 15 ) p4 0 / a 16 ( ma 8 ) p4 1 / a 17 ( ma 9 ) p4 2 / a 18 ( ma 10 ) p4 3 / a 19 ( ma 11 ) d 7 / an0 7 / p0 7 d 6 / an0 6 / p0 6 d 5 / an0 5 / p0 5 d 4 / an0 4 / p0 4 d 3 / an0 3 / p0 3 d 2 / an0 2 / p0 2 d 1 / an0 1 / p0 1 d 0 / an0 0 / p0 0 ki 3 / an 7 / p10 7 ki 2 / an 6 / p10 6 ki 1 / an 5 / p10 5 ki 0 / an 4 / p10 4 an 3 / p10 3 an 2 / p10 2 an 1 / p10 1 avss an 0 / p10 0 v ref avcc (2) p9 7 m32c/83 group (m32c/83, m32c/83t) prqp0100jb-a (100p6s-a) notes: 1. p6 4 / cts1 / rts1 / ss1 / outc2 1 / isclk2 2. p9 7 / ad trg / rxd4 / stxd4 / scl4 3. p7 0 and p7 1 are ports for the n-channel open drain output. figure 1.4 pin assignment for 100-pin package
page 11 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 30 29 28 27 26 76 77 78 79 80 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 ss4 / rts4 / cts4 / tb4 in / da1 / p9 4 ss3 / rts3 / cts3 / tb3 in / da0 / p9 3 ie out / istxd2 / outc2 0 / srxd3 / sda3 / txd3 / tb2 in / p9 2 ie in / isrxd2 / stxd3 / scl3 / rxd3 / tb1 in / p9 1 clk3 / tb0 in / p9 0 byte cnvss v cont / x cin / p8 7 x cout / p8 6 reset x out vss x in vcc nmi / p8 5 int2 / p8 4 can in / int1 / p8 3 isrxd3 / outc3 2 / can out / int0 / p8 2 istxd3 / outc3 0 / u / ta4 in / p8 1 be0 in / isrxd0 /inpc0 2 / u / ta4 out / p8 0 can in / isclk0 / outc0 1 / inpc0 1 / ta3 in / p7 7 can out / be0 out / istxd0 / outc0 0 / inpc0 0 / ta3 out / p7 6 be1 in / isrxd1 / outc1 2 / inpc1 2 / w / ta2 in / p7 5 isclk1 / outc1 1 / inpc1 1 / w / ta2 out / p7 4 be1 out / istxd1 / outc1 0 / ss2 / rts2 / cts2 / v / ta1 in / p7 3 p4 2 / a 18 ( ma 10 ) p4 3 / a 19 ( ma 11 ) p4 4 / cs3 / a 20 (ma 12 ) p4 5 / cs2 / a 21 p4 6 / cs1 / a 22 p4 7 / cs0 / a 23 p5 0 / wrl / wr / casl p5 1 / wrh / bhe / cash p5 2 / rd / dw p5 3 / clk out / bclk / ale p5 4 / hlda / ale p5 5 / hold p5 6 / ale / ras p5 7 / rdy p6 0 / cts0 / rts0 / ss0 p6 1 / clk0 p6 2 / rxd0 / scl0 / stxd0 p6 3 / txd0 / sda0 / srxd0 p6 4 (1) p6 5 / clk1 p6 6 / rxd1 / scl1 / stxd1 p6 7 / txd1 / sda1 / srxd1 p7 0 (2, 4) p7 1 (3, 4) p7 2 / ta1 out / v / clk2 p1 3 / d 11 p1 4 / d 12 p1 5 / d 13 / int3 p1 6 / d 14 / int4 p1 7 / d 15 / int5 p2 0 / a 0 ( / d 0 ) / an2 0 p2 1 / a 1 ( / d 1 ) / an2 1 p2 2 / a 2 ( / d 2 ) / an2 2 p2 3 / a 3 ( / d 3 ) / an2 3 p2 4 / a 4 ( / d 4 ) / an2 4 p2 5 / a 5 ( / d 5 ) / an2 5 p2 6 / a 6 ( / d 6 ) / an2 6 p2 7 / a 7 ( / d 7 ) / an2 7 vss p3 0 / a 8 ( ma 0 ) ( / d 8 ) vcc p3 1 / a 9 ( ma 1 ) ( / d 9 ) p3 2 / a 10 ( ma 2 ) ( / d 10 ) p3 3 / a 11 ( ma 3 ) ( / d 11 ) p3 4 / a 12 ( ma 4 ) ( / d 12 ) p3 5 / a 13 ( ma 5 ) ( / d 13 ) p3 6 / a 14 ( ma 6 ) ( / d 14 ) p3 7 / a 15 ( ma 7 ) ( / d 15 ) p4 0 / a 16 ( ma 8 ) p4 1 / a 17 ( ma 9 ) d 10 / p1 2 d 9 / p1 1 d 8 / p1 0 d 7 / an0 7 / p0 7 d 6 / an0 6 / p0 6 d 5 / an0 5 / p0 5 d 4 / an0 4 / p0 4 d 3 / an0 3 / p0 3 d 2 / an0 2 / p0 2 d 1 / an0 1 / p0 1 d 0 / an0 0 / p0 0 ki 3 / an3 7 / p10 7 ki 2 / an3 6 / p10 6 ki 1 / an3 5 / p10 5 ki 0 / an3 4 / p10 4 an3 3 / p10 3 an3 2 / p10 2 an3 1 / p10 1 avss an3 0 / p10 0 v ref avcc stxd4 / scl4 / rxd4 / ad trg / p9 7 srxd4 / sda4 / txd4 / anex1 / p9 6 clk4 / anex0 / p9 5 m32c/83 group (m32c/83, m32c/83t) plqp0100kb-a (100p6q-a) notes: 1. p6 4 / cts1 / rts1 / ss1 / outc2 1 / isclk2 2. p7 0 / ta0 out / txd2 / sda2 / srxd2 / outc2 0 / istxd2 / ie out 3. p7 1 / ta0 in / tb5 in / rxd2 / scl2 / stxd2 / outc2 2 / isrxd2 / ie in 4. p7 0 and p7 1 are ports for the n-channel open drain output. figure 1.5 pin assignment for 100-pin package
page 12 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 byte cnv ss x cin /v cont x cout reset x out v ss x in v cc p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 p4 7 p4 6 p4 5 p4 4 nmi int2 int1 int0 tb4 in tb3 in tb2 in tb1 in tb0 in ta4 in /u ta4 out /u ta3 in ta3 out ta2 in /w ta2 out /w ta1 in /v ta1 out /v tb5 in /ta0 in ta0 out txd4/sda4/srxd4 clk4 cts4/rts4/ss4 cts3/rts3/ss3 txd3/sda3/srxd3 rxd3/scl3/stxd3 clk3 can in can out can in can out cts2/rts2/ss2 clk2 rxd2/scl2/stxd2 txd2/sda2/srxd2 txd1/sda1/srxd1 rxd1/scl1/stxd1 clk1 cts1/rts1/ss1 txd0/sda0/srxd0 rxd0/scl0/stxd0 clk0 cts0/rts0/ss0 outc2 0 /ie out /istxd2 ie in /isrxd2 outc3 2 /isrxd3 outc3 0 /istxd3 inpc0 2 /isrxd0/be0 in inpc0 1 /outc0 1 /isclk0 inpc0 0 /outc0 0 /istxd0/be0 out inpc1 2 /outc1 2 /isrxd1/be1 in inpc1 1 /outc1 1 /isclk1 outc1 0 /istxd1/be1 out outc2 2 /isrxd2/ie in outc2 0 /istxd2/ie out outc2 1 /isclk2 anex1 anex0 da1 da0 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 rdy ale/ras hold hlda/ale clk out /bclk/ale rd/dw wrh/bhe/cash wrl/wr/casl cs0/a 23 cs1/a 22 cs2/a 21 cs3/a 20 (ma 12 ) package pin no fp gp control pin port timer pin uart/can pin intelligent i/o pin bus control pin (1) analog pin interrupt pin notes: 1. bus control pins in m32c/83t cannot be used. table 1.5 pin characteristics for 100-pin package
page 13 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 v cc v ss av ss v ref av cc p4 3 p4 2 p4 1 p4 0 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p0 1 p0 0 p10 7 p10 6 p10 5 p10 4 p10 3 p10 2 p10 1 p10 0 p9 7 timer pin uart/can pin an2 7 an2 6 an2 5 an2 4 an2 3 an2 2 an2 1 an2 0 an0 7 an0 6 an0 5 an0 4 an0 3 an0 2 an0 1 an0 0 an 7 an 6 an 5 an 4 an 3 an 2 an 1 an 0 ad trg a 19 (ma 11 ) a 18 (ma 10 ) a 17 (ma 9 ) a 16 (ma 8 ) a 15 (ma 7 )(/d 15 ) a 14 (ma 6 )(/d 14 ) a 13 (ma 5 )(/d 13 ) a 12 (ma 4 )(/d 12 ) a 11 (ma 3 )(/d 11 ) a 10 (ma 2 )(/d 10 ) a 9 (ma 1 )(/d 9 ) a 8 (ma 0 )(/d 8 ) a 7 (/d 7 ) a 6 (/d 6 ) a 5 (/d 5 ) a 4 (/d 4 ) a 3 (/d 3 ) a 2 (/d 2 ) a 1 (/d 1 ) a 0 (/d 0 ) d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 intelligent i/o pin bus control pin (1) analog pin interrupt pin int5 int4 int3 ki 3 ki 2 ki 1 ki 0 rxd4/scl4/stxd4 fp gp package pin no control pin port notes: 1. bus control pins in m32c/83t cannot be used. table 1.5 pin characteristics for 100-pin package (continued)
page 14 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m apply 3.0 to 5.5v to both v cc pin. apply 0v to the v ss pin. (1) supplies power to the a/d converter. connect the av cc pin to v cc and the av ss pin to v ss ___________ the microcomputer is in a reset state when "l" is applied to the reset pin switches processor mode. connect the cnv ss pin to v ss to start up in single- chip mode or to v cc to start up in microprocessor mode switches data bus width in external memory space 3. the data bus is 16 bits wide when the byte pin is held "l" and 8 bits wide when it is held "h". set to either. connect the byte pin to v ss to use the microcomputer in single-chip mode inputs and outputs data (d 0 to d 7 ) while accessing an external memory space with separate bus inputs and outputs data (d 8 to d 15 ) while accessing an external memory space with 16-bit separate bus outputs address bits a 0 to a 22 outputs inversed address bit a 23 inputs and outputs data (d 0 to d 7 ) and outputs 8 low-order address bits (a 0 to a 7 ) by time-sharing while accessing an external memory space with multiplexed bus inputs and outputs data (d 8 to d 15 ) and outputs 8 middle-order address bits (a 8 to a 15 ) by time-sharing while accessing an external memory space with 16-bit multiplexed bus _______ _______ outputs cs0 to cs3 that are chip-select signals specifying an external space ________ _________ ______ ________ _____ ________ _________ outputs wrl, wrh, (wr, bhe) and rd signals. wrl and wrh can be ______ _______ switched with wr and bhe by program ________ _________ _____ wrl, wrh and rd selected: if external data bus is 16 bits wide, data is written to an even address in ________ external memory space when wrl is held "l". _________ data is written to an odd address when wrh is held "l". _____ data is read when rd is held "l". ______ ________ _____ wr, bhe and rd selected: ______ data is written to external memory space when wr is held "l". _____ data in an external memory space is read when rd is held "l". ________ an odd address is accessed when bhe is held "l". ______ ________ _____ select wr, bhe and rd for external 8-bit data bus. ale is a signal latching the address __________ the microcomputer is placed in a hold state while the hold pin is held "l" outputs an "l" signal while the microcomputer is placed in a hold state ________ bus is placed in a wait state while the rdy pin is held "l" when dram area is accessed, outputs column and row addresses by time-sharing. ______ __________ __________ the dw signal becomes "l" when data is written to the dram area. casl and cash are __________ signals indicating the timing to latch column addresses. the casl signal becomes "l" when __________ an even address is accessed. the cash signal becomes "l" when an odd address is ________ accessed. ras is a signal latching row addresses. v cc v ss av cc av ss ____________ reset cnv ss byte d 0 to d 7 d 8 to d 15 a 0 to a 22 ______ a 23 a 0 /d 0 to a 7 /d 7 a 8 /d 8 to a 15 /d 15 ______ ______ cs0 to cs3 ________ ______ wrl / wr _________ ________ wrh / bhe _____ rd ale __________ hold __________ hlda ________ rdy ma 0 to ma 12 ______ dw __________ casl __________ cash ________ ras power supply analog power supply reset input cnv ss input to switch external data bus width (2) bus control pins (2) dram bus control pin (2) i i i i i i/o i/o o o i/o i/o o o o i o i o o i : input o : output i/o : input and output notes: 1. apply 4.2 to 5.5v to the v cc pin when using m32c/83t. 2. bus control pins in m32c/83t cannot be used. classsfication symbol i/o type function 1.6 pin description table 1.6 pin description (100-pin and 144-pin packages)
page 15 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m x in x out x cin x cout v cont bclk clk out ________ ________ int0 to int5 _______ nmi _____ _____ ki 0 to ki 3 ta0 out to ta4 out ta0 in to ta4 in tb0 in to tb5 in ___ ___ u, u, v, v, ___ w, w _________ ________ cts0 to cts4 _________ _________ rts0 to rts4 clk0 to clk4 rxd0 to rxd4 txd0 to txd4 sda0 to sda4 scl0 to scl4 main clock input main clock output sub clock input sub clock output low-pa ss filter connect pin for pll frequency synthesizer pin bclk output (1) clock output ______ int interrupt input _______ nmi interrupt input key input interrupt timer a timer b three-phase motor control timer output serial i/o i 2 c mode i o i o o o i i i i/o i i o i o i/o i o i/o i/o pins for the main clock oscillation circuit. connect a ceramic resonator or crystal oscillator between x in and x out . to apply external clock, apply it to x in and leave x out open i/o pins for the sub clock oscillation circuit. connect a crystal oscillator between x cin and x cout . to apply external clock, apply it to x cin and leave x cout open connects the low-pass filter to the vcont pin when using the pll fre- quency synthesizer. connect p8 6 to vss to stabilize the pll frequency. outputs bclk signal outputs the clock having the same frequency as f c , f 8 or f 32 ______ input pins for the int interrupt _______ input pin for the nmi interrupt input pins for the key input interrupt i/o pins for the timer a0 to a4 (ta0 out is a pin for the n-channel open drain output.) input pins for the timer a0 to a4 input pins for the timer b0 to b5 output pins for the three-phase motor control timer input pins for data transmission control output pins for data reception control inputs and outputs the transfer clock inputs serial data outputs serial data (txd2 is a pin for the n-channel open drain output.) inputs and outputs serial data (sda2 is a pin for the n-channel open drain output.) inputs and outputs the transfer clock (scl2 is a pin for the n-channel open drain output.) i : input o : output i/o : input and output note: 1. bus control pins in m32c/83t cannot be used. classsfication symbol i/o type function table 1.6 pin description (100-pin and 144-pin packages) (continued)
page 16 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m stxd0 to stxd4 srxd0 to srxd4 _______ _______ ss0 to ss4 v ref an 0 to an 7 an0 0 to an0 7 an2 0 to an2 7 an15 0 to an15 7 ___________ ad trg anex0 anex1 da0, da1 inpc0 0 to inpc0 2 inpc0 3 to inpc0 7 (1) inpc1 1 to inpc1 2 inpc1 6 to inpc1 7 (1) outc0 0 to outc0 2 outc0 4 to outc0 5 (1) outc1 0 to outc1 2 outc1 3 to outc1 7 (1) outc2 0 to outc2 2 outc2 3 to outc2 7 (1) outc3 0 to outc3 2 outc3 1 , outc3 3 to outc3 7 (1) isclk0 to isclk2 isclk3 (1) isrxd0 to isrxd3 istxd0 to istxd3 be0 in, be1 in be0 out, be1 out ie in ie out can in can out serial i/o special function reference voltage input a/d converter d/a converter intelligent i/o can outputs serial data when slave mode is selected inputs serial data when slave mode is selected input pins to control serial i/o special function applies reference voltage to the a/d converter and d/a converter analog input pins for the a/d converter input pin for an external a/d trigger extended analog input pin for the a/d converter and output pin in external op-amp connection mode extended analog input pin for the a/d converter output pin for the d/a converter input pins for the time measurement function output pins for the waveform generating function (outc2 0 and outc2 2 assigned to p7 0 and p7 1 are pins for the n-channel open drain output.) inputs and outputs the clock for the intelligent i/o communication function inputs data for the intelligent i/o communication function outputs data for the intelligent i/o communication function inputs data for the intelligent i/o communication function outputs data for the intelligent i/o communication function inputs data for the intelligent i/o communication function outputs data for the intelligent i/o communication function input pin for the can communication function output pin for the can communication function o i i i i i i/o i o i o i/o i o i o i o i o i : input o : output i/o : input and output note: 1. available in the 144-pin package only. classsfication symbol i/o type function table 1.6 pin description (100-pin and 144-pin packages) (continued)
page 17 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m p0 0 to p0 7 p1 0 to p1 7 p2 0 to p2 7 p3 0 to p3 7 p4 0 to p4 7 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p9 0 to p9 7 p10 0 to p10 7 p11 0 to p11 4 p12 0 to p12 7 p13 0 to p13 7 p14 0 to p14 6 p15 0 to p15 7 (1) p8 0 to p8 4 p8 6 , p8 7 p8 5 i/o i/o i/o i 8-bit i/o ports for cmos. each port can be programmed for input or output under the control of the direction register. an input port can be set, by program, for a pull-up resistor available or for no pull-up resister available in 4-bit units (p7 0 and p7 1 are ports for the n-channel open drain output.) i/o ports having equivalent functions to p0 i/o ports having equivalent functions to p0 _______ _______ shares a pin with nmi. nmi input state can be got by reading p8 5 i : input o : output i/o : input and output note: 1. available in the 144-pin package only. classsfication symbol i/o type function i/o ports input port table 1.6 pin description (144-pin package only) (continued)
page 18 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 2. central processing unit (cpu) figure 2.1 shows the cpu registers. a register bank comprises 8 registers (r0, r1, r2, r3, a0, a1, sb and fb) out of 28 cpu registers. two sets of register banks are provided. figure 2.1 cpu register b23 r0h r0l r1h r1l r2 r3 b31 r2 r3 a0 a1 sb fb usp isp intb pc high-speed interrupt register b15 b0 b23 svf svp vct dmac associated register b7 b0 b23 dmd0 dct0 dct1 b15 drc0 drc1 dma0 dma1 dmd1 dra0 dra1 data register (1) address register (1) static base register (1) frame base register (1) user stack pointer interrupt stack pointer interrupt table register program counter flag save register pc save register vector register dma mode register dma transfer count register dma transfer count reload register dma memory address register dma sfr address register dma memory address reload register notes: 1. a register bank comprises these registers. two sets of register banks are provided. general register b15 b0 b15 b0 carry flag debug flag zero flag sign flag register bank flag overflow flag interrupt enable flag stack pointer select flag reserved space processor interrupt priority level reserved space flg flag register ipl u i o b s z d c b7 b8 dsa0 dsa1
page 19 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 2.1 general registers 2.1.1 data registers (r0, r1, r2 and r3) r0, r1, r2 and r3 are 16-bit registers for transfer, arithmetic and logic operations. r0 and r1 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r0 can be combined with r2 to be used as a 32-bit data register (r2r0). the same applies to r1 and r3. 2.1.2 address registers (a0 and a1) a0 and a1 are 24-bit registers for a0-/a1-indirect addressing, a0-/a1-relative addressing, transfer, arith- metic and logic operations. 2.1.3 static base register (sb) sb is a 24-bit register for sb-relative addressing. 2.1.4 frame base register (fb) fb is a 24-bit register for fb-relative addressing. 2.1.5 program counter (pc) pc, 24 bits wide, indicates the address of an instruction to be executed. 2.1.6 interrupt table register (intb) intb is a 24-bit register indicating the starting address of an interrupt vector table. 2.1.7 user stack pointer (usp), interrupt stack pointer (isp) the stack pointers (sp), usp and isp, are 24 bits wide each. the u flag is used to switch between usp and isp. refer to "2.1.8 flag register (flg)" for details on the u flag. set usp and isp to even addresses to execute an interrupt sequence efficiently. 2.1.8 flag register (flg) flg is a 16-bit register indicating a cpu state. 2.1.8.1 carry flag (c) the c flag indicates whether carry or borrow has occurred after executing an instruction. 2.1.8.2 debug flag (d) the d flag is for debug only. set to "0". 2.1.8.3 zero flag (z) the z flag is set to "1" when the value of zero is obtained from an arithmetic calculation; otherwise "0". 2.1.8.4 sign flag (s) the s flag is set to "1" when a negative value is obtained from an arithmetic calculation; otherwise "0".
page 20 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 2.1.8.5 register bank select flag (b) the register bank 0 is selected when the b flag is set to "0". the register bank 1 is selected when this flag is set to "1". 2.1.8.6 overflow flag (o) the o flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0". 2.1.8.7 interrupt enable flag (i) the i flag enables a maskable interrupt. an interrupt is disabled when the i flag is set to "0" and enabled when the i flag is set to "1". the i flag is set to "0" when an interrupt is acknowledged. 2.1.8.8 stack pointer select flag (u) isp is selected when the u flag is set to "0". usp is selected when this flag is set to "1". the u flag is set to "0" when a hardware interrupt is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.1.8.9 processor interrupt priority level (ipl) ipl, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. if a requested interrupt has greater priority than ipl, the interrupt is enabled. 2.1.8.10 reserved space when writing to a reserved space, set to "0". when read, its content is indeterminate. 2.2 high-speed interrupt registers registers associated with the high-speed interrupt are as follows. refer to 10.4 high-speed interrupt for details. - flag save register (svf) - pc save register (svp) - vector register (vct) 2.3 dmac-associated registers registers associated with dmac are as follows. refer to 12. dmac for details. - dma mode register (dmd0, dmd1) - dma transfer count register (dct0, dct1) - dma transfer count reload register (drc0, drc1) - dma memory address register (dma0, dma1) - dma sfr address register (dsa0, dsa1) - dma memory address reload register (dra0, dra1)
page 21 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 3. memory figure 3.1 shows a memory map of the m32c/83 group (m32c/83, m32c/83t). m32c/83 group (m32c/83, m32c/83t) provides 16-mbyte address space from addresses 000000 16 to ffffff 16 . the internal rom is allocated lower addresses beginning with address ffffff 16 . for example, a 64- kbyte internal rom is allocated addresses ff0000 16 to ffffff 16 . the fixed interrupt vectors are allocated addresses ffffdc 16 to ffffff 16 . it stores the starting address of each interrupt routine. refer to 10. interrupts for details. the internal ram is allocated higher addresses beginning with address 000400 16 . for example, a 10- kbyte internal ram is allocated addresses 000400 16 to 002bff 16 . besides storing data, it becomes stacks when the subroutine is called or an interrupt is acknowledged. sfr, consisting of control registers for peripheral functions such as i/o port, a/d conversion, serial i/o, and timers, is allocated addresses 000000 16 to 0003ff 16 . all addresses, which have nothing allocated within sfr, are reserved space and cannot be accessed by users. the special page vectors are allocated addresses fffe00 16 to ffffdb 16 . it is used for the jmps instruc- tion and jsrs instruction. refer to the renesas publication software manual for details. in memory expansion mode and microprocessor mode, some space are reserved and cannot be accessed by users. figure 3.1 memory map sfr internal ram reserved space external space (1) brk instruction overflow undefined instruction ffffff 16 nmi 000000 16 000400 16 007fff 16 008000 16 f00000 16 f80000 16 ffffff 16 reserved space (2) internal rom (3) special page vector table address match watchdog timer (4) reset notes: 1. in memory expansion and microprocessor modes 2. in memory expansion mode. this space becomes external space in microprocessor mode. 3. this space can be used in single-chip mode and memory expansion mode. this space becomes external space in microprocessor mode. 4. watchdog timer interrupt, oscillation stop detection interrupt, and low voltage detection interrupt share vectors. ffffdc 16 fffe00 16
page 22 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 0000 16 0001 16 0002 16 0003 16 1000 0000 2 (cnvss pin ="l") 0004 16 processor mode register 0 (1) pm0 0000 0011 2 (cnvss pin ="h") 0005 16 processor mode register 1 pm1 0x00 0000 2 0006 16 system clock control register 0 cm0 0000 x000 2 0007 16 system clock control register 1 cm1 0010 0000 2 0008 16 wait control register (2) wcr 1111 1111 2 0009 16 address match interrupt enable register aier xxxx 0000 2 000a 16 protect register prcr xxxx 0000 2 xxxx 1000 2 (byte pin ="l") 000b 16 external data bus width control register (2) ds xxxx 0000 2 (byte pin ="h") 000c 16 main clock division register mcd xxx0 1000 2 000d 16 oscillation stop detection register cm2 00 16 000e 16 watchdog timer start register wdts xx 16 000f 16 watchdog timer control register wdc 000x xxxx 2 0010 16 0011 16 address match interrupt register 0 rmad0 00 00 00 16 0012 16 0013 16 0014 16 0015 16 address match interrupt register 1 rmad1 00 00 00 16 0016 16 0017 16 vdc control register for pll plv xxxx xx01 2 0018 16 0019 16 address match interrupt register 2 rmad2 00 00 00 16 001a 16 001b 16 vdc control register 0 vdc0 00 16 001c 16 001d 16 address match interrupt register 3 rmad3 00 00 00 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 x: indeterminate blank spaces are reserved. no access is allowed. notes: 1. the pm00 and pm01 bits in the pm1 register maintain values set before reset even if software reset or watchdog timer reset i s performed. 2. these registers in m32c/83t cannot be used. 4. special function registers (sfr)
page 23 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0040 16 dram control register (1) dramcont xx 16 0041 16 dram refresh interval set register (1) refcnt xx 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 flash memory control register 0 fmr0 xx00 0001 2 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 x: indeterminate blank spaces are reserved. no access is allowed. notes: 1. these registers in m32c/83t cannot be used.
page 24 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 dma0 interrupt control register dm0ic xxxx x000 2 0069 16 timer b5 interrupt control register tb5ic xxxx x000 2 006a 16 dma2 interrupt control register dm2ic xxxx x000 2 006b 16 uart2 receive /ack interrupt control register s2ric xxxx x000 2 006c 16 timer a0 interrupt control register ta0ic xxxx x000 2 006d 16 uart3 receive /ack interrupt control register s3ric xxxx x000 2 006e 16 timer a2 interrupt control register ta2ic xxxx x000 2 006f 16 uart4 receive /ack interrupt control register s4ric xxxx x000 2 0070 16 timer a4 interrupt control register ta4ic xxxx x000 2 0071 16 uart0/uart3 bus conflict detect interrupt control register bcn0ic/bcn3ic xxxx x000 2 0072 16 uart0 receive/ack interrupt control register s0ric xxxx x000 2 0073 16 a/d0 conversion interrupt control register ad0ic xxxx x000 2 0074 16 uart1 receive/ack interrupt control register s1ric xxxx x000 2 0075 16 intelligent i/o interrupt control register 0 iio0ic xxxx x000 2 0076 16 timer b1 interrupt control register tb1ic xxxx x000 2 0077 16 intelligent i/o interrupt control register 2 iio2ic xxxx x000 2 0078 16 timer b3 interrupt control register tb3ic xxxx x000 2 0079 16 intelligent i/o interrupt control register 4 iio4ic xxxx x000 2 007a 16 int5 interrupt control register int5ic xx00 x000 2 007b 16 intelligent i/o interrupt control register 6 iio6ic xxxx x000 2 007c 16 int3 interrupt control register int3ic xx00 x000 2 007d 16 intelligent i/o interrupt control register 8 iio8ic xxxx x000 2 007e 16 int1 interrupt control register int1ic xx00 x000 2 intelligent i/o interrupt control register 10/ iio10ic 007f 16 xxxx x000 2 can interrupt 1 control register can1ic 0080 16 intelligent i/o interrupt control register 11/ iio11ic 0081 16 xxxx x000 2 can interrupt 2 control register can2ic 0082 16 0083 16 0084 16 0085 16 0086 16 a/d1 conversion interrupt control register ad1ic xxxx x000 2 0087 16 0088 16 dma1 interrupt control register dm1ic xxxx x000 2 0089 16 uart2 transmit /nack interrupt control register s2tic xxxx x000 2 008a 16 dma3 interrupt control register dm3ic xxxx x000 2 008b 16 uart3 transmit /nack interrupt control register s3tic xxxx x000 2 008c 16 timer a1 interrupt control register ta1ic xxxx x000 2 008d 16 uart4 transmit /nack interrupt control register s4tic xxxx x000 2 008e 16 timer a3 interrupt control register ta3ic xxxx x000 2 008f 16 uart2 bus conflict detect interrupt control register bcn2ic xxxx x000 2 x: indeterminate blank spaces are reserved. no access is allowed.
page 25 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 0090 16 uart0 transmit /nack interrupt control register s0tic xxxx x000 2 0091 16 uart1/uart4 bus conflict detect interrupt control register bcn1ic/bcn4ic xxxx x000 2 0092 16 uart1 transmit/nack interrupt control register s1tic xxxx x000 2 0093 16 key input interrupt control register kupic xxxx x000 2 0094 16 timer b0 interrupt control register tb0ic xxxx x000 2 0095 16 intelligent i/o interrupt control register 1 iio1ic xxxx x000 2 0096 16 timer b2 interrupt control register tb2ic xxxx x000 2 0097 16 intelligent i/o interrupt control register 3 iio3ic xxxx x000 2 0098 16 timer b4 interrupt control register tb4ic xxxx x000 2 0099 16 intelligent i/o interrupt control register 5 iio5ic xxxx x000 2 009a 16 int4 interrupt control register int4ic xx00 x000 2 009b 16 intelligent i/o interrupt control register 7 iio7ic xxxx x000 2 009c 16 int2 interrupt control register int2ic xx00 x000 2 intelligent i/o interrupt control register 9/ iio9ic 009d 16 xxxx x000 2 can interrupt 0 control register can0ic 009e 16 int0 interrupt control register int0ic xx00 x000 2 009f 16 exit priority control register rlvl xxxx 0000 2 00a0 16 interrupt request register 0 iio0ir 0000 000x 2 00a1 16 interrupt request register 1 iio1ir 0000 000x 2 00a2 16 interrupt request register 2 iio2ir 0000 000x 2 00a3 16 interrupt request register 3 iio3ir 0000 000x 2 00a4 16 interrupt request register 4 iio4ir 0000 000x 2 00a5 16 interrupt request register 5 iio5ir 0000 000x 2 00a6 16 interrupt request register 6 iio6ir 0000 000x 2 00a7 16 interrupt request register 7 iio7ir 0000 000x 2 00a8 16 interrupt request register 8 iio8ir 0000 000x 2 00a9 16 interrupt request register 9 iio9ir 0000 000x 2 00aa 16 interrupt request register 10 iio10ir 0000 000x 2 00ab 16 interrupt request register 11 iio11ir 0000 000x 2 00ac 16 00ad 16 00ae 16 00af 16 00b0 16 interrupt enable register 0 iio0ie 00 16 00b1 16 interrupt enable register 1 iio1ie 00 16 00b2 16 interrupt enable register 2 iio2ie 00 16 00b3 16 interrupt enable register 3 iio3ie 00 16 00b4 16 interrupt enable register 4 iio4ie 00 16 00b5 16 interrupt enable register 5 iio5ie 00 16 00b6 16 interrupt enable register 6 iio6ie 00 16 00b7 16 interrupt enable register 7 iio7ie 00 16 00b8 16 interrupt enable register 8 iio8ie 00 16 00b9 16 interrupt enable register 9 iio9ie 00 16 00ba 16 interrupt enable register 10 iio10ie 00 16 00bb 16 interrupt enable register 11 iio11ie 00 16 00bc 16 00bd 16 00be 16 00bf 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 26 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 00c0 16 xx 16 group 0 time measurement/waveform generating register 0 g0tm0/g0po0 00c1 16 xx 16 00c2 16 xx 16 group 0 time measurement/waveform generating register 1 g0tm1/g0po1 00c3 16 xx 16 00c4 16 xx 16 group 0 time measurement/waveform generating register 2 g0tm2/g0po2 00c5 16 xx 16 00c6 16 xx 16 group 0 time measurement/waveform generating register 3 g0tm3/g0po3 00c7 16 xx 16 00c8 16 xx 16 group 0 time measurement/waveform generating register 4 g0tm4/g0po4 00c9 16 xx 16 00ca 16 xx 16 group 0 time measurement/waveform generating register 5 g0tm5/g0po5 00cb 16 xx 16 00cc 16 xx 16 group 0 time measurement/waveform generating register 6 g0tm6/g0po6 00cd 16 xx 16 00ce 16 xx 16 group 0 time measurement/waveform generating register 7 g0tm7/g0po7 00cf 16 xx 16 00d0 16 group 0 waveform generating control register 0 g0pocr0 0x00 x000 2 00d1 16 group 0 waveform generating control register 1 g0pocr1 0x00 x000 2 00d2 16 group 0 waveform generating control register 2 g0pocr2 0x00 x000 2 00d3 16 group 0 waveform generating control register 3 g0pocr3 0x00 x000 2 00d4 16 group 0 waveform generating control register 4 g0pocr4 0x00 x000 2 00d5 16 group 0 waveform generating control register 5 g0pocr5 0x00 x000 2 00d6 16 group 0 waveform generating control register 6 g0pocr6 0x00 x000 2 00d7 16 group 0 waveform generating control register 7 g0pocr7 0x00 x000 2 00d8 16 group 0 time measurement control register 0 g0tmcr0 00 16 00d9 16 group 0 time measurement control register 1 g0tmcr1 00 16 00da 16 group 0 time measurement control register 2 g0tmcr2 00 16 00db 16 group 0 time measurement control register 3 g0tmcr3 00 16 00dc 16 group 0 time measurement control register 4 g0tmcr4 00 16 00dd 16 group 0 time measurement control register 5 g0tmcr5 00 16 00de 16 group 0 time measurement control register 6 g0tmcr6 00 16 00df 16 group 0 time measurement control register 7 g0tmcr7 00 16 00e0 16 xx 16 group 0 base timer register g0bt 00e1 16 xx 16 00e2 16 group 0 base timer control register 0 g0bcr0 00 16 00e3 16 group 0 base timer control register 1 g0bcr1 00 16 00e4 16 group 0 time measurement prescaler register 6 g0tpr6 00 16 00e5 16 group 0 time measurement prescaler register 7 g0tpr7 00 16 00e6 16 group 0 function enable register g0fe 00 16 00e7 16 group 0 function select register g0fs 00 16 00e8 16 xxxx xxxx 2 group 0 si/o receive buffer register g0rb 00e9 16 xx00 xxxx 2 00ea 16 group 0 transmit buffer/receive data register g0tb/g0dr xx 16 00eb 16 00ec 16 group 0 receive input register g0ri xx 16 00ed 16 group 0 si/o communication mode register g0mr 00 16 00ee 16 group 0 transmit output register g0to xx 16 00ef 16 group 0 si/o communication control register g0cr 0000 x000 2 x: indeterminate blank spaces are reserved. no access is allowed.
page 27 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 00f0 16 group 0 data compare register 0 g0cmp0 xx 16 00f1 16 group 0 data compare register 1 g0cmp1 xx 16 00f2 16 group 0 data compare register 2 g0cmp2 xx 16 00f3 16 group 0 data compare register 3 g0cmp3 xx 16 00f4 16 group 0 data mask register 0 g0msk0 xx 16 00f5 16 group 0 data mask register 1 g0msk1 xx 16 00f6 16 00f7 16 00f8 16 xx 16 group 0 receive crc code register g0rcrc 00f9 16 xx 16 00fa 16 00 16 group 0 transmit crc code register g0tcrc 00fb 16 00 16 00fc 16 group 0 si/o extended mode register g0emr 00 16 00fd 16 group 0 si/o extended receive control register g0erc 00 16 00fe 16 group 0 si/o special communication interrupt detect register g0irf 0000 00xx 2 00ff 16 group 0 si/o extended transmit control register g0etc 0000 0xxx 2 0100 16 xx 16 group 1 time measurement/waveform generating register 0 g1tm0/g1po0 0101 16 xx 16 0102 16 xx 16 group 1 time measurement/waveform generating register 1 g1tm1/g1po1 0103 16 xx 16 0104 16 xx 16 group 1 time measurement/waveform generating register 2 g1tm2/g1po2 0105 16 xx 16 0106 16 xx 16 group 1 time measurement/waveform generating register 3 g1tm3/g1po3 0107 16 xx 16 0108 16 xx 16 group 1 time measurement/waveform generating register 4 g1tm4/g1po4 0109 16 xx 16 010a 16 xx 16 group 1 time measurement/waveform generating register 5 g1tm5/g1po5 010b 16 xx 16 010c 16 xx 16 group 1 time measurement/waveform generating register 6 g1tm6/g1po6 010d 16 xx 16 010e 16 xx 16 group 1 time measurement/waveform generating register 7 g1tm7/g1po7 010f 16 xx 16 0110 16 group 1 waveform generating control register 0 g1pocr0 0x00 x000 2 0111 16 group 1 waveform generating control register 1 g1pocr1 0x00 x000 2 0112 16 group 1 waveform generating control register 2 g1pocr2 0x00 x000 2 0113 16 group 1 waveform generating control register 3 g1pocr3 0x00 x000 2 0114 16 group 1 waveform generating control register 4 g1pocr4 0x00 x000 2 0115 16 group 1 waveform generating control register 5 g1pocr5 0x00 x000 2 0116 16 group 1 waveform generating control register 6 g1pocr6 0x00 x000 2 0117 16 group 1 waveform generating control register 7 g1pocr7 0x00 x000 2 0118 16 group 1 time measurement control register 0 g1tmcr0 00 16 0119 16 group 1 time measurement control register 1 g1tmcr1 00 16 011a 16 group 1 time measurement control register 2 g1tmcr2 00 16 011b 16 group 1 time measurement control register 3 g1tmcr3 00 16 011c 16 group 1 time measurement control register 4 g1tmcr4 00 16 011d 16 group 1 time measurement control register 5 g1tmcr5 00 16 011e 16 group 1 time measurement control register 6 g1tmcr6 00 16 011f 16 group 1 time measurement control register 7 g1tmcr7 00 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 28 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 0120 16 xx 16 group 1 base timer register g1bt 0121 16 xx 16 0122 16 group 1 base timer control register 0 g1bcr0 00 16 0123 16 group 1 base timer control register 1 g1bcr1 00 16 0124 16 group 1 time measurement prescaler register 6 g1tpr6 00 16 0125 16 group 1 time measurement prescaler register 7 g1tpr7 00 16 0126 16 group 1 function enable register g1fe 00 16 0127 16 group 1 function select register g1fs 00 16 0128 16 xxxx xxxx 2 group 1 si/o receive buffer register g1rb 0129 16 xx00 xxxx 2 012a 16 group 1 transmit buffer/receive data register g1tb/g1dr xx 16 012b 16 012c 16 group 1 receive input register g1ri xx 16 012d 16 group 1 si/o communication mode register g1mr 00 16 012e 16 group 1 transmit output register g1to xx 16 012f 16 group 1 si/o communication control register g1cr 0000 x000 2 0130 16 group 1 data compare register 0 g1cmp0 xx 16 0131 16 group 1 data compare register 1 g1cmp1 xx 16 0132 16 group 1 data compare register 2 g1cmp2 xx 16 0133 16 group 1 data compare register 3 g1cmp3 xx 16 0134 16 group 1 data mask register 0 g1msk0 xx 16 0135 16 group 1 data mask register 1 g1msk1 xx 16 0136 16 0137 16 0138 16 xx 16 group 1 receive crc code register g1rcrc 0139 16 xx 16 013a 16 00 16 group 1 transmit crc code register g1tcrc 013b 16 00 16 013c 16 group 1 si/o extended mode register g1emr 00 16 013d 16 group 1 si/o extended receive control register g1erc 00 16 013e 16 group 1 si/o special communication interrupt detect register g1irf 0000 00xx 2 013f 16 group 1 si/o extended transmit control register g1etc 0000 0xxx 2 0140 16 xx 16 group 2 waveform generating register 0 g2po0 0141 16 xx 16 0142 16 xx 16 group 2 waveform generating register 1 g2po1 0143 16 xx 16 0144 16 xx 16 group 2 waveform generating register 2 g2po2 0145 16 xx 16 0146 16 xx 16 group 2 waveform generating register 3 g2po3 0147 16 xx 16 0148 16 xx 16 group 2 waveform generating register 4 g2po4 0149 16 xx 16 014a 16 xx 16 group 2 waveform generating register 5 g2po5 014b 16 xx 16 014c 16 xx 16 group 2 waveform generating register 6 g2po6 014d 16 xx 16 014e 16 xx 16 group 2 waveform generating register 7 g2po7 014f 16 xx 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 29 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 0150 16 group 2 waveform generating control register 0 g2pocr0 00 16 0151 16 group 2 waveform generating control register 1 g2pocr1 00 16 0152 16 group 2 waveform generating control register 2 g2pocr2 00 16 0153 16 group 2 waveform generating control register 3 g2pocr3 00 16 0154 16 group 2 waveform generating control register 4 g2pocr4 00 16 0155 16 group 2 waveform generating control register 5 g2pocr5 00 16 0156 16 group 2 waveform generating control register 6 g2pocr6 00 16 0157 16 group 2 waveform generating control register 7 g2pocr7 00 16 0158 16 0159 16 015a 16 015b 16 015c 16 015d 16 015e 16 015f 16 0160 16 xx 16 group 2 base timer register g2bt 0161 16 xx 16 0162 16 group 2 base timer control register 0 g2bcr0 00 16 0163 16 group 2 base timer control register 1 g2bcr1 00 16 0164 16 base timer start register btsr xxxx 0000 2 0165 16 0166 16 group 2 function enable register g2fe 00 16 0167 16 group 2 rtp output buffer register g2rtp 00 16 0168 16 0169 16 016a 16 group 2 si/o communication mode register g2mr 00xx x000 2 016b 16 group 2 si/o communication control register g2cr 0000 x000 2 016c 16 xx 16 group 2 si/o transmit buffer register g2tb 016d 16 xx 16 016e 16 xx 16 group 2 si/o receive buffer register g2rb 016f 16 xx 16 0170 16 xx 16 group 2 iebus address register iear 0171 16 xx 16 0172 16 group 2 iebus control register iecr 00xx x000 2 0173 16 group 2 iebus transmit interrupt cause detect register ietif xxx0 0000 2 0174 16 group 2 iebus receive interrupt cause detect register ierif xxx0 0000 2 0175 16 0176 16 0177 16 0178 16 input function select register ips 00 16 0179 16 017a 16 group 3 si/o communication mode register g3mr 00xx 0000 2 017b 16 group 3 si/o communication control register g3cr 0000 x000 2 017c 16 xx 16 group 3 si/o transmit buffer register g3tb 017d 16 xx 16 017e 16 xx 16 group 3 si/o receive buffer register g3rb 017f 16 xx 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 30 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 0180 16 xx 16 group 3 waveform generating register 0 g3po0 0181 16 xx 16 0182 16 xx 16 group 3 waveform generating register 1 g3po1 0183 16 xx 16 0184 16 xx 16 group 3 waveform generating register 2 g3po2 0185 16 xx 16 0186 16 xx 16 group 3 waveform generating register 3 g3po3 0187 16 xx 16 0188 16 xx 16 group 3 waveform generating register 4 g3po4 0189 16 xx 16 018a 16 xx 16 group 3 waveform generating register 5 g3po5 018b 16 xx 16 018c 16 xx 16 group 3 waveform generating register 6 g3po6 018d 16 xx 16 018e 16 xx 16 group 3 waveform generating register 7 g3po7 018f 16 xx 16 0190 16 group 3 waveform generating control register 0 g3pocr0 00 16 0191 16 group 3 waveform generating control register 1 g3pocr1 00 16 0192 16 group 3 waveform generating control register 2 g3pocr2 00 16 0193 16 group 3 waveform generating control register 3 g3pocr3 00 16 0194 16 group 3 waveform generating control register 4 g3pocr4 00 16 0195 16 group 3 waveform generating control register 5 g3pocr5 00 16 0196 16 group 3 waveform generating control register 6 g3pocr6 00 16 0197 16 group 3 waveform generating control register 7 g3pocr7 00 16 0198 16 xx 16 group 3 waveform generating mask register 4 g3mk4 0199 16 xx 16 019a 16 xx 16 group 3 waveform generating mask register 5 g3mk5 019b 16 xx 16 019c 16 xx 16 group 3 waveform generating mask register 6 g3mk6 019d 16 xx 16 019e 16 xx 16 group 3 waveform generating mask register 7 g3mk7 019f 16 xx 16 01a0 16 xx 16 group 3 base timer register g3bt 01a1 16 xx 16 01a2 16 group 3 base timer control register 0 g3bcr0 00 16 01a3 16 group 3 base timer control register 1 g3bcr1 00 16 01a4 16 01a5 16 01a6 16 group 3 function enable register g3fe 00 16 01a7 16 group 3 rtp output buffer register g3rtp 00 16 01a8 16 01a9 16 01aa 16 01ab 16 01ac 16 01ad 16 group 3 si/o communication flag register g3flg xxxx xxx0 2 01ae 16 01af 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 31 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 01b0 16 01b1 16 01b2 16 01b3 16 01b4 16 01b5 16 01b6 16 01b7 16 01b8 16 01b9 16 01ba 16 01bb 16 01bc 16 01bd 16 01be 16 01bf 16 01c0 16 xx 16 a/d1 register 0 ad10 01c1 16 xx 16 01c2 16 xx 16 a/d1 register 1 ad11 01c3 16 xx 16 01c4 16 xx 16 a/d1 register 2 ad12 01c5 16 xx 16 01c6 16 xx 16 a/d1 register 3 ad13 01c7 16 xx 16 01c8 16 xx 16 a/d1 register 4 ad14 01c9 16 xx 16 01ca 16 xx 16 a/d1 register 5 ad15 01cb 16 xx 16 01cc 16 xx 16 a/d1 register 6 ad16 01cd 16 xx 16 01ce 16 xx 16 a/d1 register 7 ad17 01cf 16 xx 16 01d0 16 01d1 16 01d2 16 01d3 16 01d4 16 a/d1 control register 2 ad1con2 x00x x000 2 01d5 16 01d6 16 a/d1 control register 0 ad1con0 00 16 01d7 16 a/d1 control register 1 ad1con1 xx00 0000 2 01d8 16 01d9 16 01da 16 01db 16 01dc 16 01dd 16 01de 16 01df 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 32 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 01e0 16 can0 message slot buffer 0 standard id0 c0slot0_0 xx 16 01e1 16 can0 message slot buffer 0 standard id1 c0slot0_1 xx 16 01e2 16 can0 message slot buffer 0 extended id0 c0slot0_2 xx 16 01e3 16 can0 message slot buffer 0 extended id1 c0slot0_3 xx 16 01e4 16 can0 message slot buffer 0 extended id2 c0slot0_4 xx 16 01e5 16 can0 message slot buffer 0 data length code c0slot0_5 xx 16 01e6 16 can0 message slot buffer 0 data 0 c0slot0_6 xx 16 01e7 16 can0 message slot buffer 0 data 1 c0slot0_7 xx 16 01e8 16 can0 message slot buffer 0 data 2 c0slot0_8 xx 16 01e9 16 can0 message slot buffer 0 data 3 c0slot0_9 xx 16 01ea 16 can0 message slot buffer 0 data 4 c0slot0_10 xx 16 01eb 16 can0 message slot buffer 0 data 5 c0slot0_11 xx 16 01ec 16 can0 message slot buffer 0 data 6 c0slot0_12 xx 16 01ed 16 can0 message slot buffer 0 data 7 c0slot0_13 xx 16 01ee 16 can0 message slot buffer 0 time stamp high-order c0slot0_14 xx 16 01ef 16 can0 message slot buffer 0 time stamp low-order c0slot0_15 xx 16 01f0 16 can0 message slot buffer 1 standard id0 c0slot1_0 xx 16 01f1 16 can0 message slot buffer 1 standard id1 c0slot1_1 xx 16 01f2 16 can0 message slot buffer 1 extended id0 c0slot1_2 xx 16 01f3 16 can0 message slot buffer 1 extended id1 c0slot1_3 xx 16 01f4 16 can0 message slot buffer 1 extended id2 c0slot1_4 xx 16 01f5 16 can0 message slot buffer 1 data length code c0slot1_5 xx 16 01f6 16 can0 message slot buffer 1 data 0 c0slot1_6 xx 16 01f7 16 can0 message slot buffer 1 data 1 c0slot1_7 xx 16 01f8 16 can0 message slot buffer 1 data 2 c0slot1_8 xx 16 01f9 16 can0 message slot buffer 1 data 3 c0slot1_9 xx 16 01fa 16 can0 message slot buffer 1 data 4 c0slot1_10 xx 16 01fb 16 can0 message slot buffer 1 data 5 c0slot1_11 xx 16 01fc 16 can0 message slot buffer 1 data 6 c0slot1_12 xx 16 01fd 16 can0 message slot buffer 1 data 7 c0slot1_13 xx 16 01fe 16 can0 message slot buffer 1 time stamp high-order c0slot1_14 xx 16 01ff 16 can0 message slot buffer 1 time stamp low-order c0slot1_15 xx 16 0200 16 xx01 0x01 2 (1) can0 control register 0 c0ctlr0 0201 16 xxxx 0000 2 (1) 0202 16 0000 0000 2 (1) can0 status register c0str 0203 16 x000 0x01 2 (1) 0204 16 00 16 (1) can0 extended id register c0idr 0205 16 00 16 (1) 0206 16 0000 xxxx 2 (1) can0 configuration register c0conr 0207 16 0000 0000 2 (1) 0208 16 00 16 1) can0 time stamp register c0tsr 0209 16 00 16 (1) 020a 16 can0 transmit error count register c0tec 00 16 (1) 020b 16 can0 receive error count register c0rec 00 16 (1) 020c 16 00 16 (1) can0 slot interrupt status register c0sistr 020d 16 00 16 (1) 020e 16 020f 16 x: indeterminate blank spaces are reserved. no access is allowed. notes: 1. values are obtained by setting the sleep bit in the c0slpr register to "1" (sleep mode exited) and supplying a clock to the can module after reset.
page 33 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 0210 16 00 16 (2) can0 slot interrupt mask register c0simkr 0211 16 00 16 (2) 0212 16 0213 16 0214 16 can0 error interrupt mask register c0eimkr xxxx x000 2 (2) 0215 16 can0 error interrupt status register c0eistr xxxx x000 2 (2) 0216 16 0217 16 can0 baud rate prescaler c0brp 0000 0001 2 (2) 0218 16 0219 16 021a 16 021b 16 021c 16 021d 16 021e 16 021f 16 0220 16 0221 16 0222 16 0223 16 0224 16 0225 16 0226 16 0227 16 0228 16 can0 global mask register standard id0 c0gmr0 xxx0 0000 2 (2) 0229 16 can0 global mask register standard id1 c0gmr1 xx00 0000 2 (2) 022a 16 can0 global mask register extended id0 c0gmr2 xxxx 0000 2 (2) 022b 16 can0 global mask register extended id1 c0gmr3 00 16 (2) 022c 16 can0 global mask register extended id2 c0gmr4 xx00 0000 2 (2) 022d 16 022e 16 022f 16 can0 message slot 0 control register / c0mctl0/ 0000 0000 2 (2) 0230 16 can0 local mask register a standard id0 c0lmar0 xxx0 0000 2 (2) can0 message slot 1 control register / c0mctl1/ 0000 0000 2 (2) 0231 16 can0 local mask register a standard id1 c0lmar1 xx00 0000 2 (2) can0 message slot 2 control register / c0mctl2/ 0000 0000 2 (2) 0232 16 can0 local mask register a extended id0 c0lmar2 xxxx 0000 2 (2) can0 message slot 3 control register / c0mctl3/ 00 16 (2) 0233 16 can0 local mask register a extended id1 c0lmar3 00 16 (2) can0 message slot 4 control register / c0mctl4/ 0000 0000 2 (2) 0234 16 can0 local mask register a extended id2 c0lmar4 xx00 0000 2 (2) 0235 16 can0 message slot 5 control register c0mctl5 00 16 (2) 0236 16 can0 message slot 6 control register c0mctl6 00 16 (2) 0237 16 can0 message slot 7 control register c0mctl7 00 16 (2) can0 message slot 8 control register / c0mctl8/ 0000 0000 2 (2) 0238 16 can0 local mask register b standard id0 c0lmbr0 xxx0 0000 2 (2) x: indeterminate blank spaces are reserved. no access is allowed. notes: 1. the banksel bit in the c0ctlr1 register switches functions for addresses 0220 16 to 023f 16 . 2. values are obtained by setting the sleep bit in the c0slpr register to "1" (sleep mode exited) and supplying a clock to the can module after reset. (note 1)
page 34 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset can0 message slot 9 control register / c0mctl9/ 0000 0000 2 (2) 0239 16 can0 local mask register b standard id1 c0lmbr1 xx00 0000 2 (2) can0 message slot 10 control register / c0mctl10/ 0000 0000 2 (2) 023a 16 can0 local mask register b extended id0 c0lmbr2 xxxx 0000 2 (2) can0 message slot 11 control register / c0mctl11/ 00 16 (2) 023b 16 can0 local mask register b extended id1 c0lmbr3 00 16 (2) can0 message slot 12 control register / c0mctl12/ 0000 0000 2 (2) 023c 16 can0 local mask register b extended id2 c0lmbr4 xx00 0000 2 (2) 023d 16 can0 message slot 13 control register c0mctl13 00 16 (2) 023e 16 can0 message slot 14 control register c0mctl14 00 16 (2) 023f 16 can0 message slot 15 control register c0mctl15 00 16 (2) 0240 16 can0 slot buffer select register c0sbs 00 16 (2) 0241 16 can0 control register 1 c0ctlr1 xx00 00xx 2 (2) 0242 16 can0 sleep control register c0slpr xxxx xxx0 2 0243 16 0244 16 00 16 (2) can0 acceptance filter support register c0afs 0245 16 01 16 (2) 0246 16 0247 16 0248 16 0249 16 024a 16 024b 16 024c 16 024d 16 024e 16 024f 16 0250 16 0251 16 0252 16 0253 16 0254 16 0255 16 0256 16 0257 16 0258 16 0259 16 025a 16 025b 16 025c 16 025d 16 025e 16 025f 16 0260 16 0261 16 to 02bf 16 x: indeterminate blank spaces are reserved. no access is allowed. notes: 1. the banksel bit in the c0ctlr1 register switches functions for addresses 0220 16 to 023f 16 . 2. values are obtained by setting the sleep bit in the c0slpr register to "1" (sleep mode exited) and supplying a clock to the can module after reset. (note 1)
page 35 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 02c0 16 xx 16 x0 register y0 register x0r,y0r 02c1 16 xx 16 02c2 16 xx 16 x1 register y1 register x1r,y1r 02c3 16 xx 16 02c4 16 xx 16 x2 register y2 register x2r,y2r 02c5 16 xx 16 02c6 16 xx 16 x3 register y3 register x3r,y3r 02c7 16 xx 16 02c8 16 xx 16 x4 register y4 register x4r,y4r 02c9 16 xx 16 02ca 16 xx 16 x5 register y5 register x5r,y5r 02cb 16 xx 16 02cc 16 xx 16 x6 register y6 register x6r,y6r 02cd 16 xx 16 02ce 16 xx 16 x7 register y7 register x7r,y7r 02cf 16 xx 16 02d0 16 xx 16 x8 register y8 register x8r,y8r 02d1 16 xx 16 02d2 16 xx 16 x9 register y9 register x9r,y9r 02d3 16 xx 16 02d4 16 xx 16 x10 register y10 register x10r,y10r 02d5 16 xx 16 02d6 16 xx 16 x11 register y11 register x11r,y11r 02d7 16 xx 16 02d8 16 xx 16 x12 register y12 register x12r,y12r 02d9 16 xx 16 02da 16 xx 16 x13 register y13 register x13r,y13r 02db 16 xx 16 02dc 16 xx 16 x14 register y14 register x14r,y14r 02dd 16 xx 16 02de 16 xx 16 x15 register y15 register x15r,y15r 02df 16 xx 16 02e0 16 xy control register xyc xxxx xx00 2 02e1 16 02e2 16 02e3 16 02e4 16 uart1 special mode register 4 u1smr4 00 16 02e5 16 uart1 special mode register 3 u1smr3 00 16 02e6 16 uart1 special mode register 2 u1smr2 00 16 02e7 16 uart1 special mode register u1smr 00 16 02e8 16 uart1 transmit/receive mode register u1mr 00 16 02e9 16 uart1 baud rate register u1brg xx 16 02ea 16 xx 16 uart1 transmit buffer register u1tb 02eb 16 xx 16 02ec 16 uart1 transmit/receive control register 0 u1c0 0000 1000 2 02ed 16 uart1 transmit/receive control register 1 u1c1 0000 0010 2 02ee 16 xx 16 uart1 receive buffer register u1rb 02ef 16 xx 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 36 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 02f0 16 02f1 16 02f2 16 02f3 16 02f4 16 uart4 special mode register 4 u4smr4 00 16 02f5 16 uart4 special mode register 3 u4smr3 00 16 02f6 16 uart4 special mode register 2 u4smr2 00 16 02f7 16 uart4 special mode register u4smr 00 16 02f8 16 uart4 transmit/receive mode register u4mr 00 16 02f9 16 uart4 baud rate register u4brg xx 16 02fa 16 xx 16 uart4 transmit buffer register u4tb 02fb 16 xx 16 02fc 16 uart4 transmit/receive control register 0 u4c0 0000 1000 2 02fd 16 uart4 transmit/receive control register 1 u4c1 0000 0010 2 02fe 16 xx 16 uart4 receive buffer register u4rb 02ff 16 xx 16 0300 16 timer b3, b4, b5 count start flag tbsr 000x xxxx 2 0301 16 0302 16 xx 16 timer a1-1 register ta11 0303 16 xx 16 0304 16 xx 16 timer a2-1 register ta21 0305 16 xx 16 0306 16 xx 16 timer a4-1 register ta41 0307 16 xx 16 0308 16 three-phase pwm control register 0 invc0 00 16 0309 16 three-phase pwm control register 1 invc1 00 16 030a 16 three-phase output buffer register 0 idb0 xx11 1111 2 030b 16 three-phase output buffer register 1 idb1 xx11 1111 2 030c 16 dead time timer dtt xx 16 030d 16 timer b2 interrupt generating frequency set counter ictb2 xx 16 030e 16 030f 16 0310 16 xx 16 timer b3 register tb3 0311 16 xx 16 0312 16 xx 16 timer b4 register tb4 0313 16 xx 16 0314 16 xx 16 timer b5 register tb5 0315 16 xx 16 0316 16 0317 16 0318 16 0319 16 031a 16 031b 16 timer b3 mode register tb3mr 00xx 0000 2 031c 16 timer b4 mode register tb4mr 00xx 0000 2 031d 16 timer b5 mode register tb5mr 00xx 0000 2 031e 16 031f 16 external interrupt cause select register ifsr 00 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 37 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 0320 16 0321 16 0322 16 0323 16 0324 16 uart3 special mode register 4 u3smr4 00 16 0325 16 uart3 special mode register 3 u3smr3 00 16 0326 16 uart3 special mode register 2 u3smr2 00 16 0327 16 uart3 special mode register u3smr 00 16 0328 16 uart3 transmit/receive mode register u3mr 00 16 0329 16 uart3 baud rate register u3brg xx 16 032a 16 xx 16 uart3 transmit buffer register u3tb 032b 16 xx 16 032c 16 uart3 transmit/receive control register 0 u3c0 0000 1000 2 032d 16 uart3 transmit/receive control register 1 u3c1 0000 0010 2 032e 16 xx 16 uart3 receive buffer register u3rb 032f 16 xx 16 0330 16 0331 16 0332 16 0333 16 0334 16 uart2 special mode register 4 u2smr4 00 16 0335 16 uart2 special mode register 3 u2smr3 00 16 0336 16 uart2 special mode register 2 u2smr2 00 16 0337 16 uart2 special mode register u2smr 00 16 0338 16 uart2 transmit/receive mode register u2mr 00 16 0339 16 uart2 baud rate register u2brg xx 16 033a 16 xx 16 uart2 transmit buffer register u2tb 033b 16 xx 16 033c 16 uart2 transmit/receive control register 0 u2c0 0000 1000 2 033d 16 uart2 transmit/receive control register 1 u2c1 0000 0010 2 033e 16 xx 16 uart2 receive buffer register u2rb 033f 16 xx 16 0340 16 count start flag tabsr 00 16 0341 16 clock prescaler reset flag cpsrf 0xxx xxxx 2 0342 16 one-shot start flag onsf 00 16 0343 16 trigger select register trgsr 00 16 0344 16 up-down flag udf 00 16 0345 16 0346 16 xx 16 timer a0 register ta0 0347 16 xx 16 0348 16 xx 16 timer a1 register ta1 0349 16 xx 16 034a 16 xx 16 timer a2 register ta2 034b 16 xx 16 034c 16 xx 16 timer a3 register ta3 034d 16 xx 16 034e 16 xx 16 timer a4 register ta4 034f 16 xx 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 38 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 0350 16 xx 16 timer b0 register tb0 0351 16 xx 16 0352 16 xx 16 timer b1 register tb1 0353 16 xx 16 0354 16 xx 16 timer b2 register tb2 0355 16 xx 16 0356 16 timer a0 mode register ta0mr 0000 0x00 2 0357 16 timer a1 mode register ta1mr 0000 0x00 2 0358 16 timer a2 mode register ta2mr 0000 0x00 2 0359 16 timer a3 mode register ta3mr 0000 0x00 2 035a 16 timer a4 mode register ta4mr 0000 0x00 2 035b 16 timer b0 mode register tb0mr 00xx 0000 2 035c 16 timer b1 mode register tb1mr 00xx 0000 2 035d 16 timer b2 mode register tb2mr 00xx 0000 2 035e 16 timer b2 special mode register tb2sc xxxx xxx0 2 035f 16 count source prescaler register (1) tcspr 0xxx 0000 2 0360 16 0361 16 0362 16 0363 16 0364 16 uart0 special mode register 4 u0smr4 00 16 0365 16 uart0 special mode register 3 u0smr3 00 16 0366 16 uart0 special mode register 2 u0smr2 00 16 0367 16 uart0 special mode register u0smr 00 16 0368 16 uart0 transmit/receive mode register u0mr 00 16 0369 16 uart0 baud rate register u0brg xx 16 036a 16 xx 16 uart0 transmit buffer register u0tb 036b 16 xx 16 036c 16 uart0 transmit/receive control register 0 u0c0 0000 1000 2 036d 16 uart0 transmit/receive control register 1 u0c1 0000 0010 2 036e 16 xx 16 uart0 receive buffer register u0rb 036f 16 xx 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 pll control register 0 plc0 0011 x100 2 0377 16 pll control register 1 plc1 xxxx 0000 2 0378 16 dma0 cause select register dm0sl 0x00 0000 2 0379 16 dma1 cause select register dm1sl 0x00 0000 2 037a 16 dma2 cause select register dm2sl 0x00 0000 2 037b 16 dma3 cause select register dm3sl 0x00 0000 2 037c 16 xx 16 crc data register crcd 037d 16 xx 16 037e 16 crc input register crcin xx 16 037f 16 x: indeterminate blank spaces are reserved. no access is allowed. notes: 1. the tcspr register maintains the values set before reset even if software reset or watchdog timer reset is performed.
page 39 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m address register symbol value after reset 0380 16 xx 16 a/d0 register 0 ad00 0381 16 xx 16 0382 16 xx 16 a/d0 register 1 ad01 0383 16 xx 16 0384 16 xx 16 a/d0 register 2 ad02 0385 16 xx 16 0386 16 xx 16 a/d0 register 3 ad03 0387 16 xx 16 0388 16 xx 16 a/d0 register 4 ad04 0389 16 xx 16 038a 16 xx 16 a/d0 register 5 ad05 038b 16 xx 16 038c 16 xx 16 a/d0 register 6 ad06 038d 16 xx 16 038e 16 xx 16 a/d0 register 7 ad07 038f 16 xx 16 0390 16 0391 16 0392 16 0393 16 0394 16 a/d0 control register 2 ad0con2 x000 0000 2 0395 16 0396 16 a/d0 control register 0 ad0con0 00 16 0397 16 a/d0 control register 1 ad0con1 00 16 0398 16 d/a register 0 da0 xx 16 0399 16 039a 16 d/a register 1 da1 xx 16 039b 16 039c 16 d/a control register dacon xxxx xx00 2 039d 16 039e 16 039f 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 40 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m <144-pin package> address register symbol value after reset 03a0 16 function select register a8 ps8 x000 0000 2 03a1 16 function select register a9 ps9 00 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 function select register c psc 00x0 0000 2 03b0 16 function select register a0 ps0 00 16 03b1 16 function select register a1 ps1 00 16 03b2 16 function select register b0 psl0 00 16 03b3 16 function select register b1 psl1 00 16 03b4 16 function select register a2 ps2 00x0 0000 2 03b5 16 function select register a3 ps3 00 16 03b6 16 function select register b2 psl2 00x0 0000 2 03b7 16 function select register b3 psl3 00 16 03b8 16 03b9 16 function select register a5 ps5 xxx0 0000 2 03ba 16 03bb 16 03bc 16 function select register a6 ps6 00 16 03bd 16 function select register a7 ps7 00 16 03be 16 03bf 16 03c0 16 port p6 register p6 xx 16 03c1 16 port p7 register p7 xx 16 03c2 16 port p6 direction register pd6 00 16 03c3 16 port p7 direction register pd7 00 16 03c4 16 port p8 register p8 xx 16 03c5 16 port p9 register p9 xx 16 03c6 16 port p8 direction register pd8 00x0 0000 2 03c7 16 port p9 direction register pd9 00 16 03c8 16 port p10 register p10 xx 16 03c9 16 port p11 register p11 xx 16 03ca 16 port p10 direction register pd10 00 16 03cb 16 port p11 direction register pd11 xxx0 0000 2 03cc 16 port p12 register p12 xx 16 03cd 16 port p13 register p13 xx 16 03ce 16 port p12 direction register pd12 00 16 03cf 16 port p13 direction register pd13 00 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 41 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m <144-pin package> address register symbol value after reset 03d0 16 port p14 register p14 xx 16 03d1 16 port p15 register p15 xx 16 03d2 16 port p14 direction register pd14 x000 0000 2 03d3 16 port p15 direction register pd15 00 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 pull-up control register 2 pur2 00 16 03db 16 pull-up control register 3 pur3 00 16 03dc 16 pull-up control register 4 pur4 xxxx 0000 2 03dd 16 03de 16 03df 16 03e0 16 port p0 register p0 xx 16 03e1 16 port p1 register p1 xx 16 03e2 16 port p0 direction register pd0 00 16 03e3 16 port p1 direction register pd1 00 16 03e4 16 port p2 register p2 xx 16 03e5 16 port p3 register p3 xx 16 03e6 16 port p2 direction register pd2 00 16 03e7 16 port p3 direction register pd3 00 16 03e8 16 port p4 register p4 xx 16 03e9 16 port p5 register p5 xx 16 03ea 16 port p4 direction register pd4 00 16 03eb 16 port p5 direction register pd5 00 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 pull-up control register 0 pur0 00 16 03f1 16 pull-up control register 1 pur1 xxxx 0000 2 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 port control register pcr xxxx xxx0 2 x: indeterminate blank spaces are reserved. no access is allowed.
page 42 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 12345678901234567890123456789012123456789012345678901234 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 12345678901234567890123456789012123456789012345678901234 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 12345678901234567890123456789012123456789012345678901234 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 12345678901234567890123456789012123456789012345678901234 <100-pin package> address register symbol value after reset 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 function select register c psc 0x00 0000 2 03b0 16 function select register a0 ps0 00 16 03b1 16 function select register a1 ps1 00 16 03b2 16 function select register b0 psl0 00 16 03b3 16 function select register b1 psl1 00 16 03b4 16 function select register a2 ps2 00x0 0000 2 03b5 16 function select register a3 ps3 00 16 03b6 16 function select register b2 psl2 00x0 0000 2 03b7 16 function select register b3 psl3 00 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 03c0 16 port p6 register p6 xx 16 03c1 16 port p7 register p7 xx 16 03c2 16 port p6 direction register pd6 00 16 03c3 16 port p7 direction register pd7 00 16 03c4 16 port p8 register p8 xx 16 03c5 16 port p9 register p9 xx 16 03c6 16 port p8 direction register pd8 00x0 0000 2 03c7 16 port p9 direction register pd9 00 16 03c8 16 port p10 register p10 xx 16 03c9 16 03ca 16 port p10 direction register pd10 00 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 x: indeterminate blank spaces are reserved. no access is allowed. notes: 1. set address spaces 03cb 16 , 03ce 16 and 03cf 16 to "ff 16 " in the 100-pin package. 2. address spaces 03a0 16 , 03a1 16 , 03b9 16 , 03bc 16 , 03bd 16 , 03c9 16 , 03cc 16 and 03cd 16 are not provided in the 100-pin package. 123456 1 2345 6 123456 1234 1234 (note 2) (note 2) (note 2) (note 2) (note 2) (note 1) (note 1)
page 43 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 123456789012345678901234567890121234567890123456789012345678901212345678901234567 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456 7 123456789012345678901234567890121234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 12345678901234567890123456789012123456789012345678901234 1 234567890123456789012345678901212345678901234567890123 4 1 234567890123456789012345678901212345678901234567890123 4 12345678901234567890123456789012123456789012345678901234 <100-pin package> address register symbol value after reset 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 pull-up control register 2 pur2 00 16 03db 16 pull-up control register 3 pur3 00 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 port p0 register p0 xx 16 03e1 16 port p1 register p1 xx 16 03e2 16 port p0 direction register pd0 00 16 03e3 16 port p1 direction register pd1 00 16 03e4 16 port p2 register p2 xx 16 03e5 16 port p3 register p3 xx 16 03e6 16 port p2 direction register pd2 00 16 03e7 16 port p3 direction register pd3 00 16 03e8 16 port p4 register p4 xx 16 03e9 16 port p5 register p5 xx 16 03ea 16 port p4 direction register pd4 00 16 03eb 16 port p5 direction register pd5 00 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 pull-up control register 0 pur0 00 16 03f1 16 pull-up control register 1 pur1 xxxx 0000 2 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 port control register pcr xxxx xxx0 2 x: indeterminate 123456 1 2345 6 123456 1234 1234 12345 12345 blank spaces are reserved. no access is allowed. notes: 1. set address spaces 03d2 16 and 03d3 16 to "ff 16 " in the 100-pin package. 2. set address spaces 03dc 16 to "00 16 " in the 100-pin package. 3. address spaces 03d0 16 and 03d1 16 are not provided in the 100-pin package. (note 3) (note 1) (note 2)
page 44 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 5. electrical characteristics 5.1 electrical characteristics (m32c/83) table 5.1 absolute maximum ratings l o b m y sr e t e m a r a pn o i t i d n o ce u l a vt i n u v c c e g a t l o v y l p p u sv c c v a = c c 0 . 6 o t 3 . 0 - v v a c c e g a t l o v y l p p u s g o l a n av c c v a = c c 0 . 6 o t 3 . 0 - v v i e g a t l o v t u p n iv n c , t e s e r s s 0 p , e t y b , 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 , 3 p 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 6 p , 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 - 8 p 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 , 3 1 p 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( v , f e r x , n i v o t 3 . 0 - c c 3 . 0 +v 7 p 0 7 p , 1 0 . 6 o t 3 . 0 -v v o e g a t l o v t u p t u o0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 - 5 p 7 6 p , 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 9 p - 7 , 0 1 p 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 - 4 1 p 6 5 1 p , 0 5 1 p - 7 ) 1 ( x , t u o v o t 3 . 0 - c c 3 . 0 +v d pn o i t a p i s s i d r e w o p c 5 2 = r p o t0 0 5w m r p o te r u t a r e p m e t t n e i b m a g n i t a r e p o o t 0 2 -5 8c g t s te r u t a r e p m e t e g a r o t s 0 5 1 o t 5 6 -c : s e t o n . e g a k c a p n i p - 4 4 1 e h t n i d e d i v o r p e r a 5 1 p o t 1 1 p . 1
page 45 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m table 5.2 recommended operating conditions (v cc = 3.0v to 5.5v at topr = ?20 to 85 o c) l o b m y sr e t e m a r a pd r a d n a t st i n u n i mp y tx a m v c c ) c d v h g u o r h t ( e g a t l o v y l p p u s 0 . 30 . 55 . 5v ) c d v h g u o r h t t o n ( e g a t l o v y l p p u s 0 . 33 . 36 . 3v v a c c e g a t l o v y l p p u s g o l a n a v c c v v s s e g a t l o v y l p p u s 0v v a s s e g a t l o v y l p p u s g o l a n a 0v v h i ) " h " ( h g i h t u p n i e g a t l o v 2 p 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 6 p , 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 - 8 p 7 ) 3 ( 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 - 3 1 p 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 4 ( x , n i v n c , t e s e r , s s e t y b , v 8 . 0 c c v c c v 7 p 0 7 p , 1 v 8 . 0 c c 0 . 6 0 p 0 0 p - 7 1 p , 0 1 p - 7 ) e d o m p i h c - e l g n i s n i (v 8 . 0 c c v c c v 0 p 0 0 p - 7 1 p , 0 1 p - 7 ) e d o m r o s e c o r p o r c i m d n a e d o m n o i s n a p x e y r o m e m n i ( v 5 . 0 c c v c c v v l i ) " l " ( w o l t u p n i e g a t l o v 2 p 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 - 8 p 7 ) 3 ( 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 - 3 1 p 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 4 ( x , n i v n c , t e s e r , s s e t y b , 0v 2 . 0 c c v 0 p 0 0 p - 7 1 p , 0 1 p - 7 ) e d o m p i h c - e l g n i s n i (0v 2 . 0 c c v 0 p 0 0 p - 7 1 p , 0 1 p - 7 ) e d o m r o s e c o r p o r c i m d n a e d o m n o i s n a p x e y r o m e m n i ( 0v 6 1 . 0 c c v i ) k a e p ( h o t u p t u o k a e p ) " h " ( h g i h t n e r r u c ) 2 ( 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 6 p , 0 - 6 p 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 - 1 1 p 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 4 ( 0 . 0 1 -a m i ) g v a ( h o t u p t u o e g a r e v a ) " h " ( h g i h t n e r r u c ) 1 ( 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 6 p , 0 - 6 p 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 - 1 1 p 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 4 ( 0 . 5 -a m i ) k a e p ( l o t u p t u o k a e p ) " l " ( w o l t n e r r u c ) 2 ( 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 6 p , 0 - 6 p 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 - 1 1 p 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 4 ( 0 . 0 1a m i ) g v a ( l o t u p t u o e g a r e v a ) " l " ( w o l t n e r r u c ) 1 ( 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 6 p , 0 - 6 p 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 - 1 1 p 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 4 ( 0 . 5a m x ( f n i )k c o l c n i a m t u p n i y c n e u q e r f c d v h g u o r h tv c c v 5 . 5 o t 2 . 4 = v c c v 3 . 4 o t 0 . 3 = 0 0 2 3 0 2 z h m z h m c d v h g u o r h t t o nv c c 6 . 3 o t 0 . 3 =00 2z h m x ( f n i c )y c n e u q e r f n o i t a l l i c s o k c o l c b u s 8 6 7 . 2 30 5z h k : s e t o n . s m 0 0 1 s i t n e r r u c t u p t u o e g a r e v a n e h w s e u l a v l a c i p y t . 1 i l a t o t . 2 ) k a e p ( l o 8 p , 2 p , 1 p , 0 p r o f 6 8 p , 7 . s s e l r o a m 0 8 e b t s u m 5 1 p d n a 4 1 p , 1 1 p , 0 1 p , 9 p , i l a t o t ) k a e p ( h o 8 p , 2 p , 1 p , 0 p r o f 6 8 p , 7 . s s e l r o a m 0 8 - e b t s u m 5 1 p d n a 4 1 p , 1 1 p , 0 1 p , 9 p , i l a t o t ) k a e p ( l o 8 p , 7 p , 6 p , 5 p , 4 p , 3 p r o f 0 8 p o t 4 . s s e l r o a m 0 8 e b t s u m 3 1 p d n a 2 1 p , i l a t o t ) k a e p ( h o 7 p , 6 p , 5 p , 4 p , 3 p r o f 2 7 p o t 7 8 p , 0 8 p o t 4 . s s e l r o a m 0 8 - e b t s u m 3 1 p d n a 2 1 p , . 3v h i v d n a l i 8 p r o f e c n e r e f e r 7 8 p n e h w s e i l p p a 7 . t r o p t u p n i e l b a m m a r g o r p a s a d e s u s i 8 p o t y l p p a t o n s e o d t i 7 x s a d e s u n i c . . y l n o e g a k c a p n i p - 4 4 1 e h t n i d e d i v o r p e r a 5 1 p o t 1 1 p . 4
page 46 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =5v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m table 5.3 electrical characteristics (v cc =4.2 to 5.5v, v ss =0v at topr= ?0 to 85 o c, f(x in )=32mh z unless otherwise specified) l o b m y sr e t e m a r a pn o i t i d n o cd r a d n a t st i n u n i mp y tx a m v h o ) " h " ( h g i h t u p t u o e g a t l o v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 , 9 p 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 , 3 1 p 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( i h o a m 5 - =0 . 2 - c c vv 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 , 9 p 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 , 3 1 p 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( i h o 0 0 2 - = a3 . 0 - c c v x t u o i h o a m 1 - =0 . 3v x t u o c d e i l p p a d a o l o n3 . 3v v l o ) " l " ( w o l t u p t u o e g a t l o v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 , 9 p 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 , 3 1 p 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( i l o a m 5 =0 . 2v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 , 9 p 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 , 3 1 p 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( i l o 0 0 2 = a5 4 . 0v x t u o i l o a m 1 =0 . 2v x t u o c d e i l p p a d a o l o n0v v + t v - - t s i s e r e t s y h0 a t , y d r , d l o h n i 4 a t - n i 0 b t , n i 5 b t - n i - 0 t n i , d a , 5 t n i g r t , 4 k l c - 0 k l c , 4 s t c - 0 s t c , 0 a t t u o 4 a t - t u o , 4 d x r - 0 d x r , 3 i k - 0 i k , i m n , 4 a d s - 0 a d s , 4 l c s - 0 l c s 2 . 00 . 1v t e s e r2 . 08 . 1v i h i ) " h " ( h g i h t u p n i t n e r r u c 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 7 9 p , 0 9 p - 7 , 0 1 p 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 , 4 1 p 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( x , n i v n c , t e s e r , s s , e t y b v i v 5 =0 . 5 a i l i ) " l " ( w o l t u p n i t n e r r u c 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 7 9 p , 0 9 p - 7 , 0 1 p 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 , 4 1 p 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( x , n i v n c , t e s e r , s s , e t y b v i v 0 =0 . 5 - a r p u l l u p e c n a t s i s e r p u - l l u p0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 , 9 p 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 , 3 1 p 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( v i v 0 =0 30 57 6 1k ? f r n i x e c n a t s i s e r k c a b d e e fx n i 5 . 1m ? f r n i c x e c n a t s i s e r k c a b d e e fx n i c 0 1m ? v m a r e g a t l o v y b d n a t s m a rc d v h g u o r h t5 . 2v i c c y l p p u s r e w o p t n e r r u c : s n o i t i d n o c t n e m e r u s a e m t u p t u o , e d o m p i h c - e l g n i s n i r e h t o d n a n e p o t f e l e r a s n i p v o t d e t c e n n o c e r a s n i p s s . x ( f n i , e v a w e r a u q s , z h m 2 3 = ) n o i s i v i d o n 0 44 5a m x ( f n i c , e t a t s t i a w a h t i w , z h k 2 3 = ) 5 2 = r p o tc 0 7 4 a 5 2 = r p o tk c o l c e h t n e h w c s p o t s 4 . 00 2 a : s e t o n . y l n o e g a k c a p n i p - 4 4 1 e h t n i d e d i v o r p e r a 5 1 p o t 1 1 p . 1
page 47 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =5v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m table 5.4 a/d conversion characteristics (v cc = av cc = v ref = 4.2 to 5.5v, vss = av ss = 0v at topr = 20 to 85 o c, f(x in ) = 32mh z unless otherwise specified) l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u n i mp y tx a m -n o i t u l o s e rv f e r v = c c 0 1s t i b l n ir o r r e y t i r a e n i l n o n l a r g e t n iv f e r v = c c v 5 = n a 0 n a o t 7 n a 0 x e n a , 1 x e 3 b s l b s l p m a - p o l a n r e t x e e d o m n o i t c e n n o c 7 b s l b s l l n dr o r r e y t i r a e n i l n o n l a i t n e r e f f i d 1 b s l -r o r r e t e s f f o 3 b s l -r o r r e n i a g 3 b s l r r e d d a l r e d d a l r o t s i s e rv f e r v = c c 80 4k ? t v n o c e m i t n o i s r e v n o c t i b - 0 1 1 . 2 s t v n o c e m i t n o i s r e v n o c t i b - 8 8 . 1 s t p m a s e m i t e l p m a s 2 . 0 s v f e r e g a t l o v e c n e r e f e r 2v c c v v a i e g a t l o v t u p n i g o l a n a 0v f e r v : s e t o n x ( f e d i v i d . 1 n i p e e k o t , z h m 6 1 g n i d e e c x e f i , ) . s s e l r o z h m 6 1 t a y c n e u q e r f d a l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u n i mp y tx a m -n o i t u l o s e r 8s t i b -y c a r u c c a e t u l o s b a 0 . 1% t u s e m i t p u t e s 3 s r o e c n a t s i s e r t u p t u o 40 10 2k ? i f e r v y l p p u s r e w o p e c n e r e f e r t n e r r u c t u p n i ) 1 e t o n (5 . 1a m : s e t o n e h t f o ) 1 , 0 = i ( r e t s i g e r i a d e h t . r e t r e v n o c a / d e n o g n i s u n e h w s t l u s e r t n e m e r u s a e m . 1 0 0 " o t t e s s i d e s u g n i e b t o n r e t r e v n o c a / d 6 1 . d e u l c x e s i r e t r e v n o c d / a e h t n i r e d d a l r o t s i s e r e h t . " i f e r v v o n ( " 0 " o t t e s s i r e t s i g e r 1 n o c i d a e h t n i t i b t u c v e h t f i n e v e s w o l f f e r . ) n o i t c e n n o c table 5.5 d/a conversion characteristics (v cc = v ref = 4.2 to 5.5v, v ss = av ss = 0v at topr = ?0 to 85 o c, f(x in ) = 32mh z unless otherwise specified) table 5.6 flash memory version electrical characteristics r e t e m a r a p d r a d n a t s t i n u n i mp y tx a m ) e g a p r e p ( e m i t m a r g o r p80 2 1s m ) k c o l b r e p ( e m i t e s a r e k c o l b0 50 0 6s m : s e t o n v . 1 c c s s e l n u , c 0 6 o t 0 = r p o t t a ) c d v h g u o r h t t o n ( v 6 . 3 o t 0 . 3 , ) c d v h g u o r h t ( v 5 . 5 o t 2 . 4 = d e i f i c e p s e s i w r e h t o
page 48 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =5v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c te m i t e l c y c t u p n i k c o l c l a n r e t x e 3 3s n w t ) h ( h t d i w e s l u p ) " h " ( h g i h t u p n i k c o l c l a n r e t x e 3 1s n w t ) l ( h t d i w e s l u p ) " l " ( w o l t u p n i k c o l c l a n r e t x e 3 1s n r te m i t e s i r k c o l c l a n r e t x e 5s n f te m i t l l a f k c o l c l a n r e t x e 5s n t ac1(rd db) = f (bclk) x 2 35 10 9 [ns] t ac2(rd db) = f (bclk) x 2 35 10 x m 9 [ns] (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states) t ac1(ad db) = f (bclk) 35 10 9 [ns] t ac2(ad db) = 35 10 x n 9 [ns] (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states) t ac3(rd db) = f (bclk) x 2 35 10 x m 9 [ns] (m=3 with 2 wait states and m=5 with 3 wait states) t ac3(ad db) = f (bclk) x 2 35 10 x n 9 [ns] (n=5 with 2 wait states and n=7 with 3 wait states) t ac4(ras db) = f (bclk) x 2 35 10 x m 9 [ns] (m=3 with 1 wait state and m=5 with 2 wait states) t ac4(cas db) = 35 10 x n 9 [ns] (n=1 with 1 wait state and n=3 when 2 wait states) t ac4(cad db) = f ( bclk ) 35 10 x l 9 [ns] (l=1 with 1 wait state and l=2 with 2 wait states) f (bclk) f (bclk) x 2 timing requirements (v cc = 4.2 to 5.5v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.7 external clock input table 5.8 memory expansion and microprocessor modes l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m 1 c a t ) b d - d r ( ) e t a t s t i a w o n h t i w , d r a d n a t s d r ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 1 c a t ) b d - d a ( ) e t a t s t i a w o n h t i w , d r a d n a t s s c , d r a d n a t s d a ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 2 c a t ) b d - d r ( ) e t a t s t i a w a h t i w , d r a d n a t s d r ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 2 c a t ) b d - d a ( ) e t a t s t i a w a h t i w , d r a d n a t s s c , d r a d n a t s d a ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 3 c a t ) b d - d r ( ) s u b d e x e l p i t l u m e h t h t i w e c a p s a g n i s s e c c a n e h w , d r a d n a t s d r ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 3 c a t ) b d - d a ( d e x e l p i t l u m e h t h t i w e c a p s a g n i s s e c c a n e h w , d r a d n a t s s c , d r a d n a t s d a ( e m i t s s e c c a t u p n i a t a d ) s u b ) 1 e t o n (s n 4 c a t ) b d - s a r ( ) e c a p s m a r d a g n i s s e c c a n e h w , d r a d n a t s s a r ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 4 c a t ) b d - s a c ( ) e c a p s m a r d a g n i s s e c c a n e h w , d r a d n a t s s a c ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 4 c a t ) b d - d a c ( ) e c a p s m a r d a g n i s s e c c a n e h w , d r a d n a t s d a c ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n u s t ) k l c b - b d ( e m i t p u t e s t u p n i a t a d 6 2s n u s t ) k l c b - y d r ( e m i t p u t e s t u p n i y d r 6 2s n u s t ) k l c b - d l o h ( e m i t p u t e s t u p n i d l o h 0 3s n h t ) b d - d r ( e m i t d l o h t u p n i a t a d 0s n h t ) b d - s a c ( e m i t d l o h t u p n i a t a d 0s n h t ) y d r - k l c b ( e m i t d l o h t u p n i y d r 0s n h t ) d l o h - k l c b ( e m i t d l o h t u p n i d l o h 0s n d t ) a d l h - k l c b ( e m i t y a l e d t u p t u o a d l h 5 2s n : s e t o n r e w o l r o e t a t s t i a w a t r e s n i . y c n c e u q e r f k l c b o t g n i d r o c c a , s n o i t a u q e g n i w o l l o f e h t m o r f d e n i a t b o e b n a c s e u l a v . 1 ( f , y c n e u q e r f n o i t a r e p o e h t k l c b . e v i t a g e n s i e u l a v d e t a l u c l a c e h t f i , )
page 49 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =5v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 1s n w t ) h a t ( i a t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 4s n w t ) l a t ( i a t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 4s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h a t ( i a t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 2s n w t ) l a t ( i a t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 2s n w t ) h a t ( i a t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 1s n w t ) l a t ( i a t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m w t ) h a t ( i a t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 1s n w t ) l a t ( i a t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) p u ( i a t t u o e m i t e l c y c t u p n i 0 0 0 2s n w t ) h p u ( i a t t u o h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 0 1s n w t ) l p u ( i a t t u o h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 0 1s n u s t ) n i t - p u ( i a t t u o e m i t p u t e s t u p n i 0 0 4s n h t ) p u - n i t ( i a t t u o e m i t d l o h t u p n i 0 0 4s n timing requirements (v cc = 4.2 to 5.5v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.9 timer a input (count source input in event counter mode) table 5.10 timer a input (gate input in timer mode) table 5.11 timer a input (external trigger input in one-shot timer mode) table 5.12 timer a input (external trigger input in pulse width modulation mode) table 5.13 timer a input (counter increment/decrement input in event counter mode)
page 50 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =5v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m timing requirements (v cc = 4.2 to 5.5v, v ss = 0v at topr = ?0 to 85 o c unless otherwise specified) table 5.14 timer b input (count source input in event counter mode) table 5.15 timer b input (pulse period measurement mode) table 5.16 timer b input (pulse width measurement mode) table 5.17 a/d trigger input table 5.18 serial i/o _______ table 5.19 external interrupt inti input l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) b t ( i b t n i ) e g d e e n o n o d e t n u o c ( e m i t e l c y c t u p n i 0 0 1s n w t ) h b t ( i b t n i ) e g d e e n o n o d e t n u o c ( h t d i w e s l u p ) " h " ( h g i h t u p n i 0 4s n w t ) l b t ( i b t n i ) e g d e e n o n o d e t n u o c ( h t d i w e s l u p ) " l " ( w o l t u p n i 0 4s n c t ) b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( e m i t e l c y c t u p n i 0 0 2s n w t ) h b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( h t d i w e s l u p ) " h " ( h g i h t u p n i 0 8s n w t ) l b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( h t d i w e s l u p ) " l " ( w o l t u p n i 0 8s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) b t ( i b t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h b t ( i b t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 2s n w t ) l b t ( i b t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) b t ( i b t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h b t ( i b t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 2s n w t ) l b t ( i b t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) d a ( d a g r t ) r e g g i r t - e r r o f d e r i u q e r ( e m i t e l c y c t u p n i 0 0 0 1s n w t ) l d a ( d a g r t h t d i w e s l u p ) " l " ( w o l t u p n i 5 2 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) k c ( e m i t e l c y c t u p n i i k l c 0 0 2s n w t ) h k c ( h t d i w e s l u p ) " h " ( h g i h t u p n i i k l c 0 0 1s n w t ) l k c ( h t d i w e s l u p ) " l " ( w o l t u p n i i k l c 0 0 1s n d t ) q - c ( e m i t y a l e d t u p t u o i d x t 0 8s n h t ) q - c ( e m i t d l o h i d x t 0s n u s t ) c - d ( e m i t p u t e s t u p n i i d x r 0 3s n h t ) q - c ( e m i t d l o h t u p n i i d x r 0 9s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m w t ) h n i ( h t d i w e s l u p ) " h " ( h g i h t u p n i i t n i 0 5 2s n w t ) l n i ( h t d i w e s l u p ) " l " ( w o l t u p n i i t n i 0 5 2s n
page 51 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =5v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m see figure 5.1 l o b m y sr e t e m a r a p t n e m e r u s a e m n o i t i d n o c d r a d n a t s t i n u n i mx a m d t ) d a - k l c b ( e m i t y a l e d t u p t u o s s e r d d a 8 1s n h t ) d a - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s s e r d d a 3 -s n h t ) d a - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o s s e r d d a 0s n h t ) d a - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o s s e r d d a ) 1 e t o n (s n d t ) s c - k l c b ( e m i t y a l e d t u p t u o l a n g i s t c e l e s - p i h c 8 1s n h t ) s c - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 3 -s n h t ) s c - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 0s n h t ) s c - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c ) 1 e t o n (s n d t ) e l a - k l c b ( e m i t y a l e d t u p t u o l a n g i s e l a 8 1s n h t ) e l a - k l c b ( e m i t d l o h t u p t u o l a n g i s e l a 2 -s n d t ) d r - k l c b ( e m i t y a l e d t u p t u o l a n g i s d r 8 1s n h t ) d r - k l c b ( e m i t d l o h t u p t u o l a n g i s d r 5 -s n d t ) r w - k l c b ( e m i t y a l e d t u p t u o l a n g i s r w 8 1s n h t ) r w - k l c b ( e m i t d l o h t u p t u o l a n g i s r w 3 -s n d t ) r w - b d ( ) d r a d n a t s r w ( e m i t y a l e d t u p t u o a t a d ) 1 e t o n (s n h t ) b d - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o a t a d ) 1 e t o n (s n w t ) r w ( h t d i w t u p t u o r w ) 1 e t o n (s n : s e t o n . y c n e u q e r f k l c b o t g n i d r o c c a , s n o i t a u q e g n i w o l l o f e h t m o r f d e n i a t b o e b n a c s e u l a v . 1 t d(db wr) = f (bclk) 10 9 20 [ns] t h(wr db) = f (bclk) x 2 10 9 10 [ns] t h(wr ad) = f (bclk) x 2 10 9 10 [ns] t h(wr cs) = f (bclk) x 2 10 9 10 [ns] t w(wr) = f (bclk) x 2 10 9 15 [ns] switching characteristics (v cc = 4.2 to 5.5v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.20 memory expansion mode and microprocessor mode (with no wait state)
page 52 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =5v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m l o b m y sr e t e m a r a p t n e m e r u s a e m n o i t i d n o c d r a d n a t s t i n u n i mx a m d t ) d a - k l c b ( e m i t y a l e d t u p t u o s s e r d d a 8 1s n h t ) d a - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s s e r d d a 3 -s n h t ) d a - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o s s e r d d a 0s n h t ) d a - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o s s e r d d a ) 1 e t o n (s n d t ) s c - k l c b ( e m i t y a l e d t u p t u o l a n g i s t c e l e s - p i h c 8 1s n h t ) s c - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 3 -s n h t ) s c - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 0s n h t ) s c - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c ) 1 e t o n (s n d t ) e l a - k l c b ( e m i t y a l e d t u p t u o l a n g i s e l a 8 1s n h t ) e l a - k l c b ( e m i t d l o h t u p t u o l a n g i s e l a 2 -s n d t ) d r - k l c b ( e m i t y a l e d t u p t u o l a n g i s d r 8 1s n h t ) d r - k l c b ( e m i t d l o h t u p t u o l a n g i s d r 5 -s n d t ) r w - k l c b ( e m i t y a l e d t u p t u o l a n g i s r w 8 1s n h t ) r w - k l c b ( e m i t d l o h t u p t u o l a n g i s r w 3 -s n d t ) r w - b d ( ) d r a d n a t s r w ( e m i t y a l e d t u p t u o a t a d ) 1 e t o n (s n h t ) b d - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o a t a d ) 1 e t o n (s n w t ) r w ( h t d i w t u p t u o r w ) 1 e t o n (s n : s e t o n . y c n e u q e r f k l c b o t g n i d r o c c a , s n o i t a u q e g n i w o l l o f e h t m o r f d e n i a t b o e b n a c s e u l a v . 1 [ns] (n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states) t d(db wr) = f (bclk) 10 x n 9 20 t h(wr db) = f (bclk) x 2 10 9 10 [ns] t h(wr ad) = f (bclk) x 2 10 9 10 [ns] t h(wr cs) = f (bclk) x 2 10 9 10 [ns] [ns] (n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states) t w( wr) = 10 x n 9 15 f (bclk) x 2 see figure 5.1 switching characteristics (v cc = 4.2 to 5.5v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.21 memory expansion mode and microprocessor mode (with a wait state, accessing an external memory)
page 53 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =5v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m l o b m y sr e t e m a r a p t n e m e r u s a e m n o i t i d n o c d r a d n a t s t i n u n i mx a m d t ) d a - k l c b ( e m i t y a l e d t u p t u o s s e r d d a 8 1s n h t ) d a - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s s e r d d a 3 -s n h t ) d a - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o s s e r d d a ) 1 e t o n (s n h t ) d a - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o s s e r d d a ) 1 e t o n (s n d t ) s c - k l c b ( e m i t y a l e d t u p t u o l a n g i s t c e l e s - p i h c 8 1s n h t ) s c - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 3 -s n h t ) s c - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c ) 1 e t o n (s n h t ) s c - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c ) 1 e t o n (s n d t ) d r - k l c b ( e m i t y a l e d t u p t u o l a n g i s d r 8 1s n h t ) d a - k l c b ( e m i t d l o h t u p t u o l a n g i s d r 5 -s n d t ) r w - k l c b ( e m i t y a l e d t u p t u o l a n g i s r w 8 1s n h t ) r w - k l c b ( e m i t d l o h t u p t u o l a n g i s r w 3 -s n d t ) r w - b d ( ) d r a d n a t s r w ( e m i t y a l e d t u p t u o a t a d ) 1 e t o n (s n h t ) b d - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o a t a d ) 1 e t o n (s n d t ) e l a - k l c b ( ) d r a d n a t s k l c b ( e m i t y a l e d t u p t u o l a n g i s e l a 8 1s n h t ) e l a - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s e l a 2 -s n d t ) e l a - d a ( ) d r a d n a t s s s e r d d a ( e m i t y a l e d t u p t u o l a n g i s e l a ) 1 e t o n (s n h t ) d a - e l a ( ) d r a d n a t s s s e r d d a ( e m i t d l o h t u p t u o l a n g i s e l a ) 1 e t o n (s n z d t ) d a - d r ( e m i t e c n a d e p m i - h g i h t u p t u o s s e r d d a 8s n : s e t o n . y c n e u q e r f k l c b o t g n i d r o c c a , s n o i t a u q e g n i w o l l o f e h t m o r f d e n i a t b o e b n a c s e u l a v . 1 t d(db wr) = 10 x m 9 25 [ns] (m=3 with 2 wait states and m=5 with 3 wait states) t h(rd ad) = f (bclk) x 2 10 9 10 [ns] t h(wr ad) = f (bclk) x 2 10 9 10 [ns] t h(rd cs) = f (bclk) x 2 10 9 10 [ns] t h(wr cs) = f (bclk) x 2 10 9 10 [ns] t h(wr db) = f (bclk) x 2 10 9 10 [ns] t d(ad ale) = f (bclk) x 2 10 9 20 [ns] t h(ale ad) = f ( bclk ) x 2 10 9 10 [ns] f (bclk) x 2 see figure 5.1 switching characteristics (v cc = 4.2 to 5.5v, v ss = 0v at topr = ?0 to 85 o c unless otherwise specified) table 5.22 memory expansion mode and microprocessor mode (with a wait state, accessing an external memory and selecting a space with the multiplexed bus)
page 54 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =5v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m l o b m y sr e t e m a r a p t n e m e r u s a e m n o i t i d n o c d r a d n a t s t i n u n i mx a m d t ) d a r - k l c b ( e m i t y a l e d t u p t u o s s e r d d a w o r 8 1s n h t ) d a r - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s s e r d d a w o r 3 -s n d t ) d a c - k l c b ( e m i t y a l e d t u p t u o s s e r d d a n m u l o c 8 1s n h t ) d a c - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s s e r d d a n m u l o c 3 -s n h t ) d a r - s a r ( t u p t u o s a r r e t f a e m i t d l o h t u p t u o s s e r d d a w o r ) 1 e t o n (s n d t ) s a r - k l c b ( ) d r a d n a t s k l c b ( e m i t y a l e d t u p t u o s a r 8 1s n h t ) s a r - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s a r 3 -s n t p r e m i t d l o h ) " h " ( h g i h s a r ) 1 e t o n (s n d t ) s a c - k l c b ( ) d r a d n a t s k l c b ( e m i t y a l e d t u p t u o s a c 8 1s n h t ) s a c - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s a c 3 -s n d t ) w d - k l c b ( ) d r a d n a t s k l c b ( e m i t y a l e d t u p t u o w d 8 1s n h t ) w d - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o w d 5 -s n u s t ) s a c - b d ( t u p t u o b d r e t f a e m i t p u t e s t u p t u o s a c ) 1 e t o n (s n h t ) b d - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s b d 7 -s n u s t ) s a r - s a c ( ) h s e r f e r ( t u p t u o s a r e r o f e b e m i t p u t e s t u p t u o s a c ) 1 e t o n (s n : s e t o n . y c n e u q e r f k l c b o t g n i d r o c c a , n o i t a u q e g n i w o l l o f e h t m o r f d e n i a t b o e b n a c s e u l a v . 1 t su(cas ras) = f (bclk) x 2 10 9 13 [ns] t h(ras rad) = f (bclk) x 2 10 9 13 [ns] t rp = f (bclk) x 2 10 x 3 9 20 [ns] t su(db cas) = f (bclk) 10 9 20 [ns] see figure 5.1 switching characteristics (v cc = 4.2 to 5.5v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.23 memory expansion mode and microprocessor mode (with a wait state, accessing an external memory and selecting the dram space)
page 55 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf p14 p13 p12 p15 p11 note 1 notes: 1. p11 to p15 are p rovided in the 144- p in p acka g e onl y . figure 5.1 p0 to p15 measurement circuit
page 56 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m figure 5.2 v cc =5v timing diagram (1) b c l k a l e - 2 n s . m i n r d 1 8 n s . m a x -5ns.min h i - z d b 0ns.min 0ns.min t d(bclk-ale) t h ( b c l k - a l e ) t s u( d b - b c l k ) t d ( b c l k - r d ) 26ns.min (1) c s i t d ( b c l k - c s ) 1 8 n s . m a x ( 1 ) a d i t h ( b c l k - a d ) -3ns.min t h ( b c l k - c s ) - 3n s . m i n b h e t c y c t d ( b c l k - a d ) 0 n s . m i n t ac1(ad-db) (2) w r , w r l , w r h 1 8 n s . m a x - 3 n s . m i n b c l k c s i t d ( b c l k - c s ) 1 8 n s . m a x a d i t d(bclk-ad) 1 8 n s . m a x t d ( b c l k - a l e ) -3ns.min - 3 n s . m i n tcyc bhe d b i t d(bclk-wr) a l e 18ns.max - 2 n s . m i n t h ( w r - d b ) ( 3 ) t d ( d b - w r ) = ( t c y c - 2 0 ) n s . m i n t h ( w r - d b ) = ( t c y c / 2 - 1 0 ) n s . m i n t h ( w r - a d ) = ( t c y c / 2 - 1 0 ) n s . m i n t h ( w r - c s ) = ( t c y c / 2 - 1 0 ) n s . m i n t w( w r ) = ( t c y c / 2 - 1 5 ) n s . m i n vcc=5v t h ( b c l k - r d ) t h(rd-db) t h(rd-ad) t h ( r d - c s ) t h(bclk-wr) t h(bclk-ale) t h ( b c l k - a d ) t h(bclk-cs) t h ( w r - c s ) ( 3 ) t h(wr-ad) (3) t w(wr) (3) t a c 1 ( r d - d b ) ( 2 ) 1 8 n s . m a x ( 1 ) re a d t i m i n g w r i t e t i m i n g ( w r i t t e n i n 2 c y c l e s w i t h n o w a i t s t a t e ) no t e s: 3 . va r i e s w i t h o p e r a t i o n f r e q u e n c y : m e a s u r e m e n t c o n d i t i o n s : v c c = 4 . 2 t o 5 . 5 v i n p u t h i g h a n d l o w v o l t a g e : v i h = 2 . 5 v , v i l = 0 . 8 v o u t p u t h i g h a n d l o w v o l t a g e : v o h = 2 . 0 v , v o l = 0 . 8 v m e m o r y ex p a ns i o n m o d e a n d m i c r o p r o c e s s o r m o d e ( w i t h n o w a i t s t a t e ) notes: 1. values guaranteed only when the microcomputer is used independently. a maximum of 35ns is guaranteed for t d(bclk-ad) +t su(db-bclk) . 2. varies with operation frequency: t ac1(rd-db) =(tcyc/2-35)ns.max t ac1(ad-db) =(tcyc-35)ns.max 18ns.max t d(db-wr) (3)
page 57 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m b c l k a l e 1 8 n s . m a x - 2 n s . m i n rd 1 8 n s . m a x - 5 n s . m i n h i - z d b 0ns.min t d ( b c l k - a l e ) t h ( b c l k - a l e ) t d ( b c l k - r d ) 26ns.min (1) t a c 2 ( r d - d b ) ( 2 ) c s i t d ( b c l k - c s ) 1 8 n s . m a x ( 1 ) a d i 1 8 n s . m a x ( 1 ) t h ( b c l k - a d ) - 3 n s . m i n t h ( b c l k - c s ) - 3 n s . m i n b h e t c y c t d ( b c l k - a d ) t a c 2 ( a d - d b ) ( 2 ) w r , w r l , w r h 1 8 n s . m a x b c l k c s i 1 8 n s . m a x adi 1 8 n s . m a x - 3 n s . m i n - 3 n s . m i n tcyc bhe d b i t d ( b c l k - w r ) a l e 18ns.max - 2 n s . m i n v c c = 5 v t h ( b c l k - r d ) t h ( r d - d b ) t s u ( d b - b c l k ) t h ( r d - c s ) 0 n s . m i n t d ( b c l k - c s ) t d ( b c l k - a d ) t d ( b c l k - a l e ) t h ( b c l k - a d ) t h ( b c l k - c s ) t h(wr-cs) (3) t d(db-wr) (3) t h(wr-db) (3) t h ( w r - a d ) ( 3 ) t d(db-wr) =(tcyc x n-20)ns.min (n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states) t h(wr-db) =(tcyc/2-10)ns.min t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min t w(wr) =(tcyc/2 x n-15)ns.min (n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states) n o t e s : 3. v a r i e s w i t h o p e r a t i o n f r e q u e n c y : m e a s u r e m e n t c o n d i t i o n s v c c = 4 . 2 t o 5 . 5 v i n p u t h i g h a n d l o w v o l t a g e : v i h = 2 . 5 v , v i l = 0. 8 v o u t p u t h i g h a n d l o w v o l t a g e : v o h = 2 . 0 v , v o l = 0 . 8 v t h(bclk-ale) r e a d t i m i n g w r i t e t i m i n g ( w r i t t e n i n 2 c y c l e s w i t h n o w a i t s t a t e ) m e m o r y e x p a n s i o n m o d e a n d m i c r o p r o c e s s o r m o d e ( w i t h a w a i t s t a t e ) t h ( r d - a d ) t w ( w r ) ( 3 ) t h(bclk-wr) 0ns.min n o t e s : 1 . v a l u e g u a r a n t e e d o n l y w h e n t h e m i c r o c o m p u t e r i s u s e d i n d e p e n d e n t l y . a ma x i m u m o f 3 5 n s i s g u a r a n t e e d f o r t d ( b c l k - a d ) + t s u ( d b - b c l k ) . 2 . v a r i e s w i t h o p e r a t i o n f r e q u e n c y : t a c 2 ( r d - d b ) = ( t c y c / 2 x m - 3 5 ) n s . m a x ( m = 3 w i t h 1 w a i t s t a t e , m = 5 w i t h 2 w a i t s t a t e s a n d m = 7 w i t h 3 w a i t s t a t e s . ) t a c 2 ( a d - d b ) = ( t c y c x n - 3 5 ) n s . m a x ( n = 2 w i t h 1 w a i t s t a t e , n = 3 w i t h 2 w a i t s t a t e s a n d n = 4 w i t h 3 w a i t s t a t e s . ) -3ns.min figure 5.3 v cc =5v timing diagram (2)
page 58 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m bclk csi 18ns.max adi 18ns.max rd 18ns.max -5ns.min t h(bclk-ad) -3ns.min -3ns.min bhe adi /dbi 0ns.min 18ns.max -3ns.min bclk csi 18ns.max adi 18ns.max -3ns.min -3ns.min tcyc bhe adi /dbi data output wr,wrl, wrh address address data input 26ns.min t d(bclk-rd) t h(wr-cs) (2) address t d(ad-ale) (2) address t su(db-bclk) t ac3(rd-db) (1) t dz(rd-ad) 8ns.max ale -2ns.min t d(bclk-ale) 18ns.max t d(ad-ale) =(tcyc/2-20)ns.min t h(ale-ad) =(tcyc/2-10)ns.min, t h(rd-ad) =(tcyc/2-10)ns.min, t h(rd-cs) =(tcyc/2-10)ns.min t ac3(rd-db) =(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states) t ac3(ad-db) =(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states) ale 18ns.max -2ns.min t d(bclk-ale) t h(ale-ad) (1) t d(ad-ale) =(tcyc/2-20)ns.min t h(ale-ad) =(tcyc/2-10)ns.min, t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min, t h(wr-db) =(tcyc/2-10)ns.min t d(db-wr) =(tcyc/2 x m-25)ns.min vcc=5v t d(bclk-cs) t d(ad-ale) (1) t h(ale-ad) (1) t h(bclk-rd) t h(rd-ad) (1) t h(rd-db) t d(bclk-ad) t h(bclk-cs) t h(rd-cs) (1) t d(bclk-wr) t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t h(bclk-ad) t h(bclk-cs) t h(wr-ad) (2) t d(db-wr) (2) t h(wr-db) (2) t h(bclk-ale) t h(bclk-ale) tcyc notes: 2. varies with operation frequency: measurement conditions: v cc =4.2 to 5.5v input high and low voltage: v ih =2.5v, v il =0.8v output high and low voltage: v o h =2. 0 v , v o l = 0 . 8 v notes: 1. varies with operation frequency: read timing write timing (written in 2 cycles with no wait state) memory expansion mode and microprocessor mode (with a wait state, when accessing an external memory and using the multiplexed bus) t ac3(ad-db) (1) figure 5.4 v cc =5v timing diagram (3)
page 59 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m bclk dw db mai vcc=5v ras casl cash hi-z t ac4(cas-db) (2) 18ns.max t h(bclk-cad) -3ns.min tcyc t d(bclk-rad) t ac4(ras-db) (2) row address column address t h(bclk-rad) -3ns.min 18ns.max (1) t d(bclk-cad) 18ns.max (1) t d(bclk-ras) 18ns.max (1) t d(bclk-cas) t h(ras-rad) (2) t rp (2) t ac4(cad-db) (2) t h(bclk-ras) -3ns.min t h(bclk-cas) -3ns.min 0ns.min t su(db-bclk) 26ns.min (1) t h(cas-db) measurement conditions: v cc =4.2 to 5.5v input high and low voltage: v ih =2.5v, v il =0.8v output high and low voltage: v oh =2.0v, v ol =0.8v read timing memory expansion mode and microprocessor mode (when accessing the dram area) notes: 1. values guaranteed only when the microcomputer is used independently. a maximum of 35ns is guaranteed for the following combinations. t d(bclk-ras) + t su(db-bclk) t d(bclk-cas) + t su(db-bclk) t d(bclk-cad) + t su(db-bclk) 2. varies with operation frequency: t ac4(ras-db) =(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states) t ac4(cas-db) =(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states) t ac4(cad-db) =(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states) t h(ras-rad) =(tcyc/2-13)ns.min t rp =(tcyc/2 x 3-20)ns.min figure 5.5 v cc =5v timing diagram (4)
page 60 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m bclk dw db mai t h(ras-rad) =(tcyc/2-13)ns.min t rp =(tcyc/2 x 3-20)ns.min t su(db-cas) =(tcyc-20)ns.min vcc=5v ras casl cash hi-z t h(bclk-db) -7ns.min 18ns.max t h(bclk-cad) -3ns.min tcyc t d(bclk-rad) t h(bclk-rad) -3ns.min 18ns.max t d(bclk-cad) 18ns.max t d(bclk-ras) 18ns.max t d(bclk-cas) t h(ras-rad) (1) t rp (1) 18ns.max t d(bclk-dw) t su(db-cas) (1) t h(bclk-ras) -3ns.min t h(bclk-cas) -3ns.min t h(bclk-dw) -5ns.min row address column address notes: 1. varies with operation frequency: measurement conditions: v cc =4.2 to 5.5v input high and low voltage: v ih =2.5v, v il =0.8v output high and low voltage: v oh =2.0v, v ol =0.8v write timing memory expansion mode and microprocessor mode (when accessing the dram area) figure 5.6 v cc =5v timing diagram (5)
page 61 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m tcyc 18ns.max t d(bclk-ras) 18ns.max t d(bclk-cas) t h(bclk-ras) -3ns.min t h(bclk-cas) -3ns.min t su(cas-ras) (1) 18ns.max t cyc t d(bclk-cas) t su(cas-ras) (2) t h(bclk-ras) -3ns.min t h(bclk-cas) -3ns.min 18ns.max t d(bclk-ras) bclk dw t su(cas-ras) =(tcyc/2-13)ns.min vcc=5v ras casl cash bclk dw t su(cas-ras) =(tcyc/2-13)ns.min ras casl cash notes : 1. varies with operation frequency: measurement conditions: v cc =4.2 to 5.5v input high and low voltage: v ih =2.5v, v il =0.8v output high and low voltage: v oh =2.0v, v ol =0.8v refresh timing (cas-before-ras refresh) memory expansion mode and microprocessor mode notes: 2. varies with operation frequency: refresh timing (self-refresh) figure 5.7 v cc =5v timing diagram (6)
page 62 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m t su(d c) tai in input tai out input in event counter mode tbi in input clki txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c q) t h(c d) t h(c q) t h(t in up) t su(up t in ) tai in input (when counting on the falling edge) tai in input (when counting on the rising edge) tai out input (counter increment/ decrement input) inti input ad trg input vcc=5v nmi input 2 clock cycles + 300ns ore more ("l" width) 2 clock cycles + 300ns or more figure 5.8 v cc =5v timing diagram (7)
page 63 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m t h(bclk hold) t su(hold bclk) t d(bclk hlda) t d(bclk hlda) hi z measurement conditions: v cc =4.2 to 5.5v input high and low voltage: v ih =4.0v, v il =1.0v output high and low voltage: v oh =2.5v, v ol =2.5v memory expansion mode and microprocessor mode bclk hold input hlda output p0, p1, p2, p3, p4, p5 0 to p5 2 (valid with a wait state or with no wait state) (valid only with a wait state) rdy input t su(rdy bclk) t h(bclk rdy) bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus) vcc=5v figure 5.9 v cc =5v timing diagram (8)
page 64 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =3.3v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m table 5.24 electrical characteristics (v cc =3.0 to 3.6v, v ss =0v at topr = 20 to 85 o c, f(x in )=20mh z unless otherwise specified) l o b m y sr e t e m a r a pn o i t i d n o cd r a d n a t st i n u n i mp y tx a m v h o ) " h " ( h g i h t u p t u o e g a t l o v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 , 9 p 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 , 3 1 p 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( i h o a m 1 - =6 . 0 - c c vv x t u o i h o a m 1 . 0 - =7 . 2v x t u o c d e i l p p a d a o l o n3 . 3v v l o ) " l " ( w o l t u p t u o e g a t l o v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 , 9 p 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 , 3 1 p 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( i l o a m 1 =5 . 0v x t u o i l o a m 1 . 0 =5 . 0v x t u o c d e i l p p a d a o l o n0v v + t v - - t s i s e r e t s y h0 a t , y d r , d l o h n i 4 a t - n i 0 b t , n i 5 b t - n i - 0 t n i , d a , 5 t n i g r t 0 a t , 4 k l c - 0 k l c , 4 s t c - 0 s t c , t u o - 4 a t t u o , 4 l c s - 0 l c s , 4 d x r - 0 d x r , 3 i k - 0 i k , i m n , 4 a d s - 0 a d s 2 . 00 . 1v t e s e r2 . 08 . 1v i h i ) " h " ( h g i h t u p n i t n e r r u c 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 7 9 p , 0 9 p - 7 , 0 1 p 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 , 4 1 p 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( x , n i v n c , t e s e r , s s , e t y b v i v 3 =0 . 4 a i l i ) " l " ( w o l t u p n i t n e r r u c 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 7 9 p , 0 9 p - 7 , 0 1 p 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 , 4 1 p 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( x , n i v n c , t e s e r , s s , e t y b v i v 0 =0 . 4 - a r p u l l u p e c n a t s i s e r p u - l l u p0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 , 9 p 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 , 3 1 p 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( v i v 0 =6 60 2 10 0 5k ? f r n i x e c n a t s i s e r k c a b d e e fx n i 0 . 3m ? f r n i c x e c n a t s i s e r k c a b d e e fx n i c 0 . 0 2m ? v m a r y b d n a t s m a r e g a t l o v c d v h g u o r h t5 . 2v c d v h g u o r h t t o n0 . 2v i c c y l p p u s r e w o p t n e r r u c : n o i t i d n o c t n e m e r u s a e m t u p t u o , e d o m p i h c - e l g n i s n i r e h t o d n a n e p o t f e l e r a s n i p v o t d e t c e n n o c e r a s n i p s s . x ( f n i , e v a w e r a u q s , z h m 0 2 = ) n o i s i v i d o n 6 28 3a m x ( f n i c , e t a t s t i a w a h t i w , z h k 2 3 = ) 5 2 = r p o t , c d v h g u o r h t t o nc 0 . 5 a x ( f n i c , e t a t s t i a w a h t i w , z h k 2 3 = ) 5 2 = r p o t , c d v h g u o r h tc 0 4 3 a 5 2 = r p o ts p o t s k c o l c e h t n e h w c 4 . 00 2 a : s e t o n . y l n o e g a k c a p n i p - 4 4 1 e h t n i d e d i v o r p e r a 5 1 p o t 1 1 p . 1
page 65 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =3.3v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m table 5.25 a/d conversion characteristics (v cc = av cc = v ref = 3.0 to 3.6 v, v ss = av ss = 0v at topr = 20 to 85 o c, f(x in ) = 20mh z unless otherwise specified) table 5.26 d/a conversion characteristics (v cc = v ref = 3.0 to 3.6v, v ss = av ss = 0v at topr = 20 to 85 o c, f(x in ) = 20mh z unless otherwise specified) l o b m y sr e t e m a r a p t n e m e r u s a e m n o i t i d n o c d r a d n a t s t i n u n i mp y tx a m -n o i t u l o s e rv f e r v = c c 0 1s t i b l n ir o r r e y t i r a e n i l n o n l a r g e t n i) t i b - 8 ( n o i t c n u f h & s o nv c c v = f e r v 3 . 3 =2 b s l l n dr o r r e y t i r a e n i l n o n l a i t n e r e f f i d) t i b - 8 ( n o i t c n u f h & s o n1 b s l -r o r r e t e s f f o) t i b - 8 ( n o i t c n u f h & s o n2 b s l -r o r r e n i a g) t i b - 8 ( n o i t c n u f h & s o n2 b s l r r e d d a l r e d d a l r o t s i s e rv f e r v = c c 80 4k ? t v n o c e m i t n o i s r e v n o c t i b - 8 9 . 4 s v f e r e g a t l o v e c n e r e f e r 0 . 3v c c v v a i e g a t l o v t u p n i g o l a n a 0v f e r v d l o h d n a e l p m a s : h & s : s e t o n x ( f e d i v i d . 1 n i p e e k o t , z h m 0 1 g n i d e e c x e f i , ) . s s e l r o z h m 0 1 t a y c n e u q e r f d a l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u n i mp y tx a m -n o i t u l o s e r 8s t i b -y c a r u c c a e t u l o s b a 0 . 1% t u s e m i t p u t e s 3 s r o e c n a t s i s e r t u p t u o 40 10 2k ? i f e r v t n e r r u c t u p n i y l p p u s r e w o p e c n e r e f e r) 1 e t o n (0 . 1a m : s e t o n t o n r e t r e v n o c a / d e h t f o ) 1 , 0 = i ( r e t s i g e r i a d e h t . r e t r e v n o c a / d e n o g n i s u n e h w s t l u s e r t n e m e r u s a e m . 1 0 0 " o t t e s s i d e s u g n i e b 6 1 . d e u l c x e s i r e t r e v n o c d / a e h t n i r e d d a l r o t s i s e r e h t . " i f e r v v o n ( " 0 " o t t e s s i r e t s i g e r 1 n o c i d a e h t n i t i b t u c v e h t f i n e v e s w o l f f e r . ) n o i t c e n n o c table 5.27 flash memory version electrical characteristics r e t e m a r a p d r a d n a t s t i n u n i mp y tx a m ) e g a p r e p ( e m i t m a r g o r p80 2 1s m ) k c o l b r e p ( e m i t e s a r e k c o l b0 50 0 6s m : s e t o n v . 1 c c s s e l n u , c 0 6 o t 0 = r p o t t a ) c d v h g u o r h t t o n ( v 6 . 3 o t 0 . 3 , ) c d v h g u o r h t ( v 5 . 5 o t 2 . 4 = d e i f i c e p s e s i w r e h t o
page 66 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =3.3v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m timing requirements (v cc = 3.0 to 3.6v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.28 external clock input table 5.29 memory expansion mode and microprocessor mode l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c te m i t e l c y c t u p n i k c o l c l a n r e t x e 0 5s n w t ) h ( h t d i w e s l u p ) " h " ( h g i h t u p n i k c o l c l a n r e t x e 2 2s n w t ) l ( h t d i w e s l u p ) " l " ( w o l t u p n i k c o l c l a n r e t x e 2 2s n r te m i t e s i r k c o l c l a n r e t x e 5s n f te m i t l l a f k c o l c l a n r e t x e 5s n t ac1(rd db) = f (bclk) x 2 35 10 9 [ns] t ac2(rd db) = f (bclk) x 2 35 10 x m 9 [ns] (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states) t ac1(ad db) = f (bclk) 35 10 9 [ns] t ac2(ad db) = 35 10 x n 9 [ns] (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states) t ac3(rd db) = f (bclk) x 2 35 10 x m 9 [ns] (m=3 with 2 wait states and m=5 with 3 wait states) t ac3(ad db) = f (bclk) x 2 35 10 x n 9 [ns] (n=5 with 2 wait states and n=7 with 3 wait states) t ac4(ras db) = f (bclk) x 2 35 10 x m 9 [ns] (m=3 with 1 wait state and m=5 with 2 wait states) t ac4(cas db) = 35 10 x n 9 [ns] (n=1 with 1 wait state and n=3 when 2 wait states) t ac4(cad db) = f ( bclk ) 35 10 x l 9 [ns] (l=1 with 1 wait state and l=2 with 2 wait states) f (bclk) f (bclk) x 2 l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m 1 c a t ) b d - d r ( ) e t a t s t i a w o n h t i w , d r a d n a t s d r ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 1 c a t ) b d - d a ( ) e t a t s t i a w o n h t i w , d r a d n a t s s c , d r a d n a t s d a ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 2 c a t ) b d - d r ( ) e t a t s t i a w a h t i w , d r a d n a t s d r ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 2 c a t ) b d - d a ( ) e t a t s t i a w a h t i w , d r a d n a t s s c , d r a d n a t s d a ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 3 c a t ) b d - d r ( ) s u b d e x e l p i t l u m e h t h t i w e c a p s a g n i s s e c c a n e h w , d r a d n a t s d r ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 3 c a t ) b d - d a ( e m i t s s e c c a t u p n i a t a d ) s u b d e x e l p i t l u m e h t h t i w e c a p s a g n i s s e c c a n e h w , d r a d n a t s s c , d r a d n a t s d a ( ) 1 e t o n (s n 4 c a t ) b d - s a r ( ) e c a p s m a r d a g n i s s e c c a n e h w , d r a d n a t s s a r ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 4 c a t ) b d - s a c ( ) e c a p s m a r d a g n i s s e c c a n e h w , d r a d n a t s s a c ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 4 c a t ) b d - d a c ( ) e c a p s m a r d a g n i s s e c c a n e h w , d r a d n a t s d a c ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n u s t ) k l c b - b d ( e m i t p u t e s t u p n i a t a d 0 3s n u s t ) k l c b - y d r ( e m i t p u t e s t u p n i y d r 0 4s n u s t ) k l c b - d l o h ( e m i t p u t e s t u p n i d l o h 0 6s n h t ) b d - d r ( e m i t d l o h t u p n i a t a d 0s n h t ) b d - s a c ( e m i t d l o h t u p n i a t a d 0s n h t ) y d r - k l c b ( e m i t d l o h t u p n i y d r 0s n h t ) d l o h - k l c b ( e m i t d l o h t u p n i d l o h 0s n d t ) a d l h - k l c b ( e m i t y a l e d t u p t u o a d l h 5 2s n : s e t o n r e w o l r o e t a t s t i a w a t r e s n i . y c n e u q e r f k l c b o t g n i d r o c c a , s n o i t a u q e g n i w o l l o f e h t m o r f d e n i a t b o e b n a c s e u l a v . 1 ( f , y c n e u q e r f n o i t a r e p o k l c b . e v i t a g e n s i e u l a v d e t a l u c l a c e h t f i , )
page 67 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =3.3v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m timing requirements (v cc = 3.0 to 3.6v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.30 timer a input (count source input in event counter mode) table 5.31 timer a input (gate input in timer mode) table 5.32 timer a input (external trigger input in one-shot timer mode) table 5.33 timer a input (external trigger input in pulse width modulation mode) table 5.34 timer a input (counter increment/decrement input in event counter mode) l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 1s n w t ) h a t ( i a t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 4s n w t ) l a t ( i a t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 4s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h a t ( i a t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 2s n w t ) l a t ( i a t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 2s n w t ) h a t ( i a t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 1s n w t ) l a t ( i a t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m w t ) h a t ( i a t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 1s n w t ) l a t ( i a t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) p u ( i a t t u o e m i t e l c y c t u p n i 0 0 0 2s n w t ) h p u ( i a t t u o h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 0 1s n w t ) l p u ( i a t t u o h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 0 1s n u s t ) n i t - p u ( i a t t u o e m i t p u t e s t u p n i 0 0 4s n h t ) p u - n i t ( i a t t u o e m i t d l o h t u p n i 0 0 4s n
page 68 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =3.3v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m timing requirements (v cc = 3.0 to 3.6v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.35 timer b input (count source input in event counter mode) table 5.36 timer b input (pulse period measurement mode) table 5.37 timer b input (pulse width measurement mode) table 5.38 a/d trigger input table 5.39 serial i/o _______ table 5.40 external interrupt inti input l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) b t ( i b t n i ) e g d e e n o n o d e t n u o c ( e m i t e l c y c t u p n i 0 0 1s n w t ) h b t ( i b t n i ) e g d e e n o n o d e t n u o c ( h t d i w e s l u p ) " h " ( h g i h t u p n i 0 4s n w t ) l b t ( i b t n i ) e g d e e n o n o d e t n u o c ( h t d i w e s l u p ) " l " ( w o l t u p n i 0 4s n c t ) b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( e m i t e l c y c t u p n i 0 0 2s n w t ) h b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( h t d i w e s l u p ) " h " ( h g i h t u p n i 0 8s n w t ) l b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( h t d i w e s l u p ) " l " ( w o l t u p n i 0 8s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) b t ( i b t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h b t ( i b t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 2s n w t ) l b t ( i b t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) b t ( i b t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h b t ( i b t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 2s n w t ) l b t ( i b t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) d a ( d a g r t ) r e g g i r t - e r r o f d e r i u q e r ( h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 0 1s n w t ) l d a ( d a g r t h t d i w e s l u p ) " l " ( w o l t u p n i 5 2 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) k c ( e m i t e l c y c t u p n i i k l c 0 0 2s n w t ) h k c ( h t d i w e s l u p ) " h " ( h g i h t u p n i i k l c 0 0 1s n w t ) l k c ( h t d i w e s l u p ) " l " ( w o l t u p n i i k l c 0 0 1s n d t ) q - c ( e m i t y a l e d t u p t u o i d x t 0 8s n h t ) q - c ( e m i t d l o h i d x t 0s n u s t ) c - d ( e m i t p u t e s t u p n i i d x r 0 3s n h t ) q - c ( e m i t d l o h t u p n i i d x r 0 9s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m w t ) h n i ( h t d i w e s l u p ) " h " ( h g i h t u p n i i t n i 0 5 2s n w t ) l n i ( h t d i w e s l u p ) " l " ( w o l t u p n i i t n i 0 5 2s n
page 69 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =3.3v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m l o b m y sr e t e m a r a p t n e m e r u s a e m n o i t i d n o c d r a d n a t s t i n u n i mx a m d t ) d a - k l c b ( e m i t y a l e d t u p t u o s s e r d d a 8 1s n h t ) d a - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s s e r d d a 0s n h t ) d a - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o s s e r d d a 0s n h t ) d a - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o s s e r d d a ) 1 e t o n (s n d t ) s c - k l c b ( e m i t y a l e d t u p t u o l a n g i s t c e l e s - p i h c 8 1s n h t ) s c - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 0s n h t ) s c - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 0s n h t ) s c - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c ) 1 e t o n (s n d t ) e l a - k l c b ( e m i t y a l e d t u p t u o l a n g i s e l a 8 1s n h t ) e l a - k l c b ( e m i t d l o h t u p t u o l a n g i s e l a 2 -s n d t ) d r - k l c b ( e m i t y a l e d t u p t u o l a n g i s d r 8 1s n h t ) d r - k l c b ( e m i t d l o h t u p t u o l a n g i s d r 3 -s n d t ) r w - k l c b ( e m i t y a l e d t u p t u o l a n g i s r w 8 1s n h t ) r w - k l c b ( e m i t d l o h t u p t u o l a n g i s r w 0s n d t ) r w - b d ( ) d r a d n a t s r w ( e m i t y a l e d t u p t u o a t a d ) 1 e t o n (s n h t ) b d - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o a t a d ) 1 e t o n (s n w t ) r w ( h t d i w t u p t u o r w ) 1 e t o n (s n : s e t o n . y c n e u q e r f k l c b e h t o t g n i d r o c c a s n o i t a u q e g n i w o l l o f e h t m o r f d e n i a t b o e b n a c s e u l a v . 1 t d(db wr) = f (bclk) 10 9 20 [ns] t h(wr db) = f (bclk) x 2 10 9 10 [ns] t h(wr ad) = f (bclk) x 2 10 9 10 [ns] t h(wr cs) = f (bclk) x 2 10 9 10 [ns] t w(wr) = f (bclk) x 2 10 9 15 [ns] see figure 5.1 switching characteristics (v cc = 3.0 to 3.6v, v ss = 0v at topr = 20 to 85 o c, unless otherwise specified) table 5.41 memory expansion mode and microprocessor mode (with no wait state)
page 70 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =3.3v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m l o b m y sr e t e m a r a p t n e m e r u s a e m n o i t i d n o c d r a d n a t s t i n u n i mx a m d t ) d a - k l c b ( e m i t y a l e d t u p t u o s s e r d d a 8 1s n h t ) d a - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s s e r d d a 0s n h t ) d a - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o s s e r d d a 0s n h t ) d a - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o s s e r d d a ) 1 e t o n (s n d t ) s c - k l c b ( e m i t y a l e d t u p t u o l a n g i s t c e l e s - p i h c 8 1s n h t ) s c - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 0s n h t ) s c - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 0s n h t ) s c - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c ) 1 e t o n (s n d t ) e l a - k l c b ( e m i t y a l e d t u p t u o l a n g i s e l a 8 1s n h t ) e l a - k l c b ( e m i t d l o h t u p t u o l a n g i s e l a 2 -s n d t ) d r - k l c b ( e m i t y a l e d t u p t u o l a n g i s d r 8 1s n h t ) d r - k l c b ( e m i t d l o h t u p t u o l a n g i s d r 3 -s n d t ) r w - k l c b ( e m i t y a l e d t u p t u o l a n g i s r w 8 1s n h t ) r w - k l c b ( e m i t d l o h t u p t u o l a n g i s r w 0s n d t ) r w - b d ( ) d r a d n a t s r w ( e m i t y a l e d t u p t u o a t a d ) 1 e t o n (s n h t ) b d - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o a t a d ) 1 e t o n (s n w t ) r w ( h t d i w t u p t u o r w ) 1 e t o n (s n : s e t o n . y c n e u q e r f k l c b o t g n i d r o c c a , s n o i t a u q e g n i w o l l o f e h t m o r f d e n i a t b o e b n a c s e u l a v . 1 [ns] (n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states) t d(db wr) = f (bclk) 10 x n 9 20 t h(wr db) = f (bclk) x 2 10 9 10 [ns] t h(wr ad) = f (bclk) x 2 10 9 10 [ns] t h(wr cs) = f (bclk) x 2 10 9 10 [ns] [ns] (n=1 with 1 wait state, n=3 with 2 wait states and n = 5with3waitstates) t w( wr) = 10 x n 9 15 f (bclk) x 2 see figure 5.1 switching characteristics (v cc = 3.0 to 3.6v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.42 memory expansion mode and microprocessor mode (with a wait state, accessing an external memory)
page 71 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =3.3v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m l o b m y sr e t e m a r a p t n e m e r u s a e m n o i t i d n o c d r a d n a t s t i n u n i mx a m d t ) d a - k l c b ( e m i t y a l e d t u p t u o s s e r d d a 8 1s n h t ) d a - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s s e r d d a 0s n h t ) d a - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o s s e r d d a ) 1 e t o n (s n h t ) d a - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o s s e r d d a ) 1 e t o n (s n d t ) s c - k l c b ( e m i t y a l e d t u p t u o l a n g i s t c e l e s - p i h c 8 1s n h t ) s c - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 0s n h t ) s c - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c ) 1 e t o n (s n h t ) s c - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c ) 1 e t o n (s n d t ) d r - k l c b ( e m i t y a l e d t u p t u o l a n g i s d r 8 1s n h t ) d a - k l c b ( e m i t d l o h t u p t u o l a n g i s d r 3 -s n d t ) r w - k l c b ( e m i t y a l e d t u p t u o l a n g i s r w 8 1s n h t ) r w - k l c b ( e m i t d l o h t u p t u o l a n g i s r w 0s n d t ) r w - b d ( ) d r a d n a t s r w ( e m i t y a l e d t u p t u o a t a d ) 1 e t o n (s n h t ) b d - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o a t a d ) 1 e t o n (s n d t ) e l a - k l c b ( ) d r a d n a t s k l c b ( e m i t y a l e d t u p t u o l a n g i s e l a 8 1s n h t ) e l a - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s e l a 2 -s n d t ) e l a - d a ( ) d r a d n a t s s s e r d d a ( e m i t y a l e d t u p t u o l a n g i s e l a ) 1 e t o n (s n h t ) d a - e l a ( ) d r a d n a t s s s e r d d a ( e m i t d l o h t u p t u o l a n g i s e l a ) 1 e t o n (s n z d t ) d a - d r ( e m i t e c n a d e p m i - h g i h t u p t u o s s e r d d a 8s n : s e t o n . y c n e u q e r f k l c b o t g n i d r o c c a , s n o i t a u q e g n i w o l l o f e h t m o r f d e n i a t b o e b n a c s e u l a v . 1 t d(db wr) = 10 x m 9 25 [ns] (m=3 with 2 wait states and m=5 with 3 wait states) t h(rd ad) = f (bclk) x 2 10 9 10 [ns] t h(wr ad) = f (bclk) x 2 10 9 10 [ns] t h(rd cs) = f (bclk) x 2 10 9 10 [ns] t h(wr cs) = f (bclk) x 2 10 9 10 [ns] t h(wr db) = f (bclk) x 2 10 9 10 [ns] t d(ad ale) = f (bclk) x 2 10 9 20 [ns] t h(ale ad) = f ( bclk ) x 2 10 9 10 [ns] f (bclk) x 2 see figure 5.1 switching characteristics (v cc = 3.0 to 3.6v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.43 memory expansion mode and microprocessor mode (with a wait state, accessing an external memory and selecting a space with the multiplexed bus)
page 72 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r v cc =3.3v ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m l o b m y sr e t e m a r a p t n e m e r u s a e m n o i t i d n o c d r a d n a t s t i n u n i mx a m d t ) d a r - k l c b ( e m i t y a l e d t u p t u o s s e r d d a w o r 8 1s n h t ) d a r - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s s e r d d a w o r 0s n d t ) d a c - k l c b ( e m i t y a l e d t u p t u o s s e r d d a n m u l o c 8 1s n h t ) d a c - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s s e r d d a n m u l o c 0s n h t ) d a r - s a r ( t u p t u o s a r r e t f a e m i t d l o h t u p t u o s s e r d d a w o r ) 1 e t o n (s n d t ) s a r - k l c b ( ) d r a d n a t s k l c b ( e m i t y a l e d t u p t u o s a r 8 1s n h t ) s a r - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s a r 0s n t p r e m i t d l o h ) " h " ( h g i h s a r ) 1 e t o n (s n d t ) s a c - k l c b ( ) d r a d n a t s k l c b ( e m i t y a l e d t u p t u o s a c 8 1s n h t ) s a c - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s a c 0s n d t ) w d - k l c b ( ) d r a d n a t s k l c b ( e m i t y a l e d t u p t u o w d 8 1s n h t ) w d - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o w d 3 -s n u s t ) s a c - b d ( t u p t u o b d r e t f a e m i t p u t e s t u p t u o s a c ) 1 e t o n (s n h t ) b d - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s b d 7 -s n u s t ) s a r - s a c ( ) h s e r f e r ( t u p t u o s a r e r o f e b e m i t p u t e s t u p t u o s a c ) 1 e t o n (s n : s e t o n . y c n e u q e r f k l c b e h t o t g n i d r o c c a , s n o i t a u q e g n i w o l l o f e h t m o r f d e n i a t b o e b n a c s e u l a v . 1 t su(cas ras) = f ( bclk ) x 2 10 9 13 [ns] t h(ras rad) = f (bclk) x 2 10 9 13 [ns] t rp = f (bclk) x 2 10 x 3 9 20 [ns] t su(db cas) = f (bclk) 10 9 20 [ns] see figure 5.1 switching characteristics (v cc = 3.0 to 3.6v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.44 memory expansion mode and microprocessor mode (with a wait state, accessing an external memory and selecting the dram area)
page 73 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m figure 5.10 v cc =3.3v timing diagram (1) bclk ale -2ns.min rd 18ns.max -3ns.min hi-z db 0ns.min 0ns.min t d(bclk-ale) t h(bclk-ale) t su(db-bclk) t d(bclk-rd) 30ns.min (1) csi t d(bclk-cs) 18ns.max (1) adi t h(bclk-ad) 0ns.min t h(bclk-cs) 0ns.min bhe tcyc t d(bclk-ad) 0ns.min t ac2(ad-db) (2) wr,wrl, wrh 18ns.max 0ns.min bclk csi t d(bclk-cs) 18ns.max adi t d(bclk-ad) 18ns.max t d(bclk-ale) 0ns.min 0ns.min tcyc bhe t d(db-wr) (1) dbi t d(bclk-wr) ale -2ns.min t h(wr-db) (1) t d(db-wr) =(tcyc-20)ns.min t h(wr-db) =(tcyc/2-10)ns.min t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min t w(wr) =(tcyc/2-15)ns.min vcc=3.3v t h(bclk-rd) t h(rd-db) t h(rd-ad) t h(rd-cs) t h(bclk-wr) t h(bclk-ale) t h(bclk-ad) t h(bclk-cs) t h(wr-cs) (1) t h(wr-ad) (1) t ac2(rd-db) (2) 18ns.max (1) read timing write timing notes: 1. varies with operation frequency. measurement conditions: v cc =3.0 to 3.6v input high and low voltage: v ih =1.5v, v il =0.5v output high and low voltage: v oh =1.5v, v ol =1.5v memory expansion mode and microprocessor mode (with no wait state) notes: 1. values guaranteed only when the microcomputer is used independently. a maximum of 35ns is guaranteed for t d(bclk-ad) +t su(db-bclk) . 2. varies with operation frequency: t ac2(rd-db) =(tcyc/2-35)ns.max t ac2(ad-db) =(tcyc-35)ns.max 18ns.max t w(wr) (1) 18ns.max
page 74 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m bclk ale 18ns.max -2ns.min rd 18ns.max -3ns.min hi-z db 0ns.min 0ns.min t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) 30ns.min (1) t ac2(rd-db) (2) csi t d(bclk-cs) 18ns.max (1) adi 18ns.max (1) t h(bclk-ad) 0ns.min t h(bclk-cs) 0ns.min bhe tcyc t d(bclk-ad) t ac2(ad-db) (2) wr,wrl, wrh 18ns.max 0ns.min bclk csi 18ns.max adi 18ns.max 0ns.min 0ns.min tcyc bhe dbi t d(bclk-wr) ale 18ns.max -2ns.min vcc=3.3v t h(bclk-rd) t h(rd-db) t h(rd-ad) t su(db-bclk) t h(rd-cs) 0ns.min t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t d(bclk-ale) t h(bclk-ad) t h(bclk-cs) t h(wr-cs) (1) t d(db-wr) (1) t h(wr-db) (1) t h(wr-ad) (1) t d(db-wr) =(tcyc x n-20)ns.min (n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states) t h(wr-db) =(tcyc/2-10)ns.min t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min t w(wr) =(tcyc/2 x n-15)ns.min (n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states ) notes: 1. varies with operation frequency. measurement conditions: v cc =3.0 to 3.6v input high and low voltage: v ih =1.5v, v il =0.5v output high and low voltage: v oh =1.5v, v ol =1.5v notes: 1. values guaranteed only when the microcomputer is used independently. a maximum of 35ns is guaranteed for t d(bclk-ad) +t su(db-bclk) . 2. varies with operation frequency. t ac2(rd-db) =(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states) t ac2(ad-db) =(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states) t h(bclk-ale) read timing write timing memory expansion mode and microprocessor mode (with a wait state) t w(wr) (1) figure 5.11 v cc =3.3v timing diagram (2)
page 75 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m bclk csi 18ns.max adi 18ns.max rd 18ns.max -3ns.min t h(bclk-ad) 0ns.min 0ns.min bhe adi /dbi 0ns.min 18ns.max 0ns.min bclk csi 18ns.max adi 18ns.max 0ns.min 0ns.min tcyc bhe adi /dbi data output wr,wrl, wrh address address data input 30ns.min t d(bclk-rd) t h(wr-cs) (1) address t d(ad-ale) (1) address t su(db-bclk) t ac3(rd-db) (1) t dz(rd-ad) 8ns.max ale -2ns.min t d(bclk-ale) 18ns.max ale -2ns.min t d(bclk-ale) t h(ale-ad) (1) vcc=3.3v t d(bclk-cs) t d(ad-ale) (1) t h(ale-ad) (1) t h(bclk-rd) t h(rd-ad) (1) t h(rd-db) t d(bclk-ad) t h(bclk-cs) t h(rd-cs) (1) t d(bclk-wr) t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t h(bclk-ad) t h(bclk-cs) t h(wr-ad) () t d(db-wr) (1) t h(wr-db) (1) t h(bclk-ale) t h(bclk-ale) tcyc notes: 1. varies with operation frequency. t d(ad-ale) =(tcyc/2-20)ns.min t h(ale-ad) =(tcyc/2-10)ns.min, t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min, t h(wr-db) =(tcyc/2-10)ns.min t d(db-wr) =(tcyc/2 x m-25)ns.min (m=3 with 2 wait states and m=5 with 3 wait states) measurement conditions: v cc =3.0 to 3.6v input high and low voltage: v ih =1.5v, v il =0.5v output high and low voltage: v oh =1.5v, v ol =1.5v notes: 1. varies with operation frequency. t d(ad-ale) =(tcyc/2-20)ns.min t h(ale-ad) =(tcyc/2-10)ns.min, t h(rd-ad) =(tcyc/2-10)ns.min, t h(rd-cs) =(tcyc/2-10)ns.min t ac3(rd-db) =(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states) t ac3(ad-db) =(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states) read timing write timing memory expansion mode and microprocessor mode (with a wait state, when accessing an external memory and using the multiplexed bus) 18ns.max t ac3(ad-db) (1) figure 5.12 v cc =3.3v timing diagram (3)
page 76 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m b c l k d w d b m a i v c c = 3 . 3 v r a s c a s l c a s h h i - z t a c 4 ( c a s - d b ) ( 2 ) 1 8n s . m a x ( 1 ) t h ( b c l k - c a d ) 0 n s . m i n t c y c t d ( b c l k - r a d ) t a c 4 ( r a s - d b ) ( 2 ) r o w a d d r e s s c o l u m n a d d r e s s t h ( b c l k - r a d ) 0 n s . m i n 1 8 n s . m a x ( 1 ) t d ( b c l k - c a d ) 1 8n s . m a x ( 1 ) t d ( b c l k - r a s ) 1 8n s . m a x ( 1 ) t d ( b c l k - c a s ) t h( r a s - r a d ) ( 1 ) t r p ( 2 ) t a c 4 ( c a d - d b ) ( 2 ) t h ( b c l k - r a s ) 0 n s . m i n t h ( b c l k - c a s ) 0n s . m i n 0 n s . m i n t s u ( d b - b c l k ) 30n s . m i n ( 1 ) t h ( c a s - d b ) m e a s u r e m e n t c o n d i t i o n s : v c c = 3 . 0 t o 3 . 6 v i n p u t h i g h a n d l o w v o l t a g e : v i h = 1 . 5 v , v i l = 0 . 5 v o u t p u t h i g h a n d l o w v o l t a g e : v o h = 1 . 5 v , v o l = 1 . 5 v r e a d t i m i n g m e m o r y ex p a ns i o n m o d e a n d m i c r o p r o c e s s o r m o d e ( w i t h 2 w a i t s t a t e s , w h e n a c c e s s i n g t h e d r a m a r e a ) n o t e s : 1 . v a l u e s g u a r a n t e e d o n l y w h e n t h e m i c r o c o m p u t e r i s u s e d i n d e p e n d e n t l y . a m a x i m u m o f 3 5 n s i s g u a r a n t e e d f o r t h e f o l l o w i n g s : t d ( b c l k - r a s ) + t s u ( d b - b c l k ) t d ( b c l k - c a s ) + t s u ( d b - b c l k ) t d ( b c l k - c a d ) + t s u ( d b - b c l k ) 2 . i t v a r i e s w i t h t h e o p e r a t i o n f r e q u e n c y . t a c 4 ( r a s - d b ) = ( t c y c / 2 x m - 3 5 ) n s . m a x ( m = 3 w i t h 1 w a i t s t a t e a n d m = 5 w i t h 2 w a i t s t a t e s ) t a c 4 ( c a s - d b ) = ( t c y c / 2 x n - 3 5 ) n s . m a x ( n = 1 w i t h 1 w a i t s t a t e a n d n = 3 w i t h 2 w a i t s t a t e s ) t a c 4 ( c a d - d b ) = ( t c y c x l - 3 5 ) n s . m a x ( l = 1 w i t h 1 w a i t s t a t e a n d l = 2 w i t h 2 w a i t s t a t e s ) t h ( r a s - r a d ) = ( t c y c / 2 - 1 3 ) n s . m i n t r p = ( t c y c / 2 x 3 - 2 0 ) n s . m i n figure 5.13 v cc =3.3v timing diagram (4)
page 77 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m bclk dw db mai vcc=3.3v ras casl cash hi-z t h(bclk-db) -7ns.min 18ns.max t h(bclk-cad) 0ns.min tcyc t d(bclk-rad) t h(bclk-rad) 0ns.min 18ns.max t d(bclk-cad) 18ns.max t d(bclk-ras) 18ns.max t d(bclk-cas) t rp (1) 18ns.max t d(bclk-dw) t su(db-cas) (1) t h(bclk-ras) 0ns.min t h(bclk-cas) -3ns.min t h(bclk-dw) 0ns.min row address column address notes: 1. varies with operation frequency. t h(ras-rad) =(tcyc/2-13)ns.min t rp =(tcyc/2 x 3-20)ns.min t su(db-cas) =(tcyc-20)ns.min measurement conditions: v cc =3.0 to 3.6v input high and low voltage: v ih =1.5v, v il =0.5v output high and low voltage: v oh =1.5v, v ol =1.5v write timing memory expansion mode and microprocessor mode (with 2 wait states, when accessing the dram area) t h(ras-rad) (1) figure 5.14 v cc =3.3v timing diagram (5)
page 78 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m figure 5.15 v cc =3.3v timing diagram (6) tcyc 18ns.max t d(bclk-ras) 18ns.max t d(bclk-cas) t h(bclk-ras) 0ns.min t h(bclk-cas) 0ns.min t su(cas-ras) (1) 18ns.max t cyc t d(bclk-cas) t su(cas-ras) (1) t h(bclk-ras) 0ns.min t h(bclk-cas) 0ns.min 18ns.max t d(bclk-ras) bclk dw vcc=3.3v ras casl cash bclk dw ras casl cash notes: 1. varies with operation frequency. t su(cas-ras) =(tcyc/2-13)ns.min measurement conditions: v cc =3.0 to 3.6v input high and low voltage: v ih =1.5v, v il =0.5v output high and low voltage: v oh =1.5v, v ol =1.5v refresh timing (cas-before-ras refresh) memory expansion mode and microprocessor mode notes: 1. varies with operation frequency. t su(cas-ras) =(tcyc/2-13)ns.min refresh timing (self-refresh)
page 79 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m t su(d c) tai in input tai out input in event counter mode tbi in input clki txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c q) t h(c d) t h(c q) t h(t in up) t su(up t in ) tai in input (when counting on falling edge) tai in input (when counting on rising edge) tai out input (counter increment/ decrement input) inti input ad trg input vcc=3.3v nmi input 2 clock cycles + 300ns or more 2 clock cycles + 300ns or more ("l" width) figure 5.16 v cc =3.3v timing diagram (7)
page 80 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m measurement conditions: vcc=3.0 to 3.6v input high and low voltage: v ih =2.4v, v il =0.6v output high and low voltage: v oh =1.5v, v ol =1.5v memory expansion mode and microprocessor mode bclk hold input hlda output p0, p1, p2, p3, p4, p5 0 to p5 2 (valid with a wait state and no wait state) (valid only with a wait state) rdy input t su(rdy bclk) t h(bclk rdy) bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus) hi z t h(bclk hold) t su(hold bclk) t d(bclk hlda) t d(bclk hlda) vcc=3.3v figure 5.17 v cc =3.3v timing diagram (8)
page 81 ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r 5.2 electrical characteristics (m32c/83t) table 5.45 absolute maximum ratings l o b m y sr e t e m a r a pn o i t i d n o ce u l a vt i n u v c c e g a t l o v y l p p u sv c c v a = c c 0 . 6 o t 3 . 0 - v v a c c e g a t l o v y l p p u s g o l a n av c c v a = c c 0 . 6 o t 3 . 0 - v v i e g a t l o v t u p n iv n c , t e s e r s s 0 p , e t y b , 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 , 3 p 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 6 p , 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 - 8 p 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 , 3 1 p 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( v , f e r x , n i v o t 3 . 0 - c c 3 . 0 +v 7 p 0 7 p , 1 0 . 6 o t 3 . 0 -v v o e g a t l o v t u p t u o0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 - 5 p 7 6 p , 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 9 p - 7 , 0 1 p 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 - 4 1 p 6 5 1 p , 0 5 1 p - 7 ) 1 ( x , t u o v o t 3 . 0 - c c 3 . 0 +v d pn o i t a p i s s i d r e w o p c 5 2 = r p o t0 0 4w m r p o te r u t a r e p m e t t n e i b m a g n i t a r e p o n o i s r e v to t 0 4 -5 8c g t s te r u t a r e p m e t e g a r o t s 0 5 1 o t 5 6 -c : s e t o n . e g a k c a p n i p - 4 4 1 e h t n i d e d i v o r p e r a 5 1 p o t 1 1 p . 1
page 82 ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r table 5.46 recommended operating conditions (v cc =4.2 to 5.5v, v ss =0v at topr = -40 to 85 o c (t version) unless otherwise specified) l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. p y t. x a m v c c e g a t l o v y l p p u s 2 . 40 . 55 . 5v v a c c e g a t l o v y l p p u s g o l a n a v c c v v s s e g a t l o v y l p p u s 0v v a s s e g a t l o v y l p p u s g o l a n a 0v v h i ) " h " ( h g i h t u p n i e g a t l o v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 6 p , 0 - 6 p 7 7 p , 2 7 p - 7 8 p , 0 8 p - 7 ) 3 ( 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 , 2 1 p 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 4 ( x , n i , v n c , t e s e r s s e t y b , v 8 . 0 c c v c c v 7 p 0 7 p , 1 v 8 . 0 c c 0 . 6 v l i ) " l " ( w o l t u p n i e g a t l o v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 6 p , 0 - 6 p 7 7 p , 0 7 p - 7 8 p , 0 8 p - 7 ) 3 ( 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 , 2 1 p 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 4 ( x , n i , v n c , t e s e r s s e t y b , 0v 2 . 0 c c v i ) k a e p ( h o t u p t u o k a e p ) " h " ( h g i h t n e r r u c ) 2 ( 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 6 p , 0 - 6 p 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 - 1 1 p 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 4 ( 0 . 0 1 -a m i ) g v a ( h o t u p t u o e g a r e v a ) " h " ( h g i h t n e r r u c ) 1 ( 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 6 p , 0 - 6 p 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 - 1 1 p 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 4 ( 0 . 5 -a m i ) k a e p ( l o w o l t u p t u o k a e p t n e r r u c ) " l " ( ) 2 ( 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 6 p , 0 - 6 p 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 - 1 1 p 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 4 ( 0 . 0 1a m i ) g v a ( l o t u p t u o e g a r e v a ) " l " ( w o l t n e r r u c ) 1 ( 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 6 p , 0 - 6 p 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 - 1 1 p 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 4 ( 0 . 5a m x ( f n i )t u p n i k c o l c n i a m y c n e u q e r f v c c v 5 . 5 o t 2 . 4 =02 3z h m x ( f n i c )y c n e u q e r f n o i t a l l i c s o k c o l c b u s 8 6 7 . 2 30 5z h k : s e t o n . s m 0 0 1 s i t n e r r u c t u p t u o e g a r e v a n e h w s e u l a v l a c i p y t . 1 i l a t o t . 2 ) k a e p ( l o 8 p , 2 p , 1 p , 0 p r o f 6 8 p , 7 . s s e l r o a m 0 8 e b t s u m 5 1 p d n a 4 1 p , 1 1 p , 0 1 p , 9 p , i l a t o t ) k a e p ( h o 8 p , 2 p , 1 p , 0 p r o f 6 8 p , 7 . s s e l r o a m 0 8 - e b t s u m 5 1 p d n a 4 1 p , 1 1 p , 0 1 p , 9 p , i l a t o t ) k a e p ( l o 8 p , 7 p , 6 p , 5 p , 4 p , 3 p r o f 0 8 p o t 4 . s s e l r o a m 0 8 e b t s u m 3 1 p d n a 2 1 p , i l a t o t ) k a e p ( h o 7 p , 6 p , 5 p , 4 p , 3 p r o f 2 7 p o t 7 8 p , 0 8 p o t 4 . s s e l r o a m 0 8 - e b t s u m 3 1 p d n a 2 1 p , . 3v h i v d n a l i 8 p r o f e c n e r e f e r 7 8 p n e h w s e i l p p a 7 . t r o p t u p n i e l b a m m a r g o r p a s a d e s u s i 8 p n e h w y l p p a t o n s e o d t i 7 x s a d e s u s i n i c . . y l n o e g a k c a p n i p - 4 4 1 e h t n i d e d i v o r p e r a 5 1 p o t 1 1 p . 4
page 83 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m v cc =5v table 5.47 electrical characteristics (v cc = 4.2 to 5.5 v, v ss = 0v at topr = 40 to 85 o c(t version), f(x in )=32mh z unless otherwise specified) l o b m y sr e t e m a r a pn o i t i d n o cd r a d n a t st i n u n i mp y tx a m v h o ) " h " ( h g i h t u p t u o e g a t l o v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 , 8 p 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 - 2 1 p 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( i h o a m 5 - =v c c 0 . 2 -v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 , 8 p 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 - 2 1 p 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( i h o 0 0 2 - = av c c 3 . 0 - x t u o i h o a m 1 - =0 . 3v x t u o c d e i l p p a d a o l o n3 . 3v v l o ) " l " ( w o l t u p t u o e g a t l o v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 8 p , 6 , 8 p 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 - 2 1 p 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( i l o a m 5 =0 . 2v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 8 p , 6 , 8 p 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 - 2 1 p 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( i l o 0 0 2 = a5 4 . 0v x t u o i l o a m 1 =0 . 2v x t u o c d e i l p p a d a o l o n0v v + t v - - t s i s e r e t s y h0 a t , y d r , d l o h n i 4 a t - n i 0 b t , n i 5 b t - n i , d a , 5 t n i - 0 t n i g r t - 0 k l c , 4 s t c - 0 s t c , 0 a t , 4 k l c t u o 4 a t - t u o - 0 d x r , 3 i k - 0 i k , i m n , 4 a d s - 0 a d s , 4 l c s - 0 l c s , 4 d x r 2 . 00 . 1v t e s e r 2 . 08 . 1v i h i ) " h " ( h g i h t u p n i t n e r r u c 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 7 9 p , 0 9 p - 7 , 0 1 p 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 - 3 1 p 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( x , n i , t e s e r , v n c s s e t y b , v i v 5 =0 . 5 a i l i ) " l " ( w o l t u p n i t n e r r u c 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 7 9 p , 0 9 p - 7 , 0 1 p 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 2 1 p - 7 3 1 p , 0 - 3 1 p 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( x , n i , t e s e r , v n c s s e t y b , v i v 0 =0 . 5 - a r p u l l u p e c n a t s i s e r p u - l l u p0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 , 8 p 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 1 1 p , 0 1 1 p - 4 2 1 p , 0 - 2 1 p 7 3 1 p , 0 3 1 p - 7 4 1 p , 0 4 1 p - 6 5 1 p , 0 5 1 p - 7 ) 1 ( v i v 0 =0 30 57 6 1k ? f r n i x e c n a t s i s e r k c a b d e e fx n i 5 . 1m ? f r n i c x e c n a t s i s e r k c a b d e e fx n i c 0 1m ? v m a r e g a t l o v y b d n a t s m a r 5 . 2v i c c y l p p u s r e w o p t n e r r u c : s n o i t i d n o c t n e m e r u s a e m t u p t u o , e d o m p i h c - e l g n i s n i r e h t o d n a n e p o t f e l e r a s n i p v o t d e t c e n n o c e r a s n i p s s x ( f n i , e v a w e r a u q s , z h m 2 3 = ) n o i s i v i d o n 0 44 5a m x ( f n i c , e t a t s t i a w a h t i w , z h k 2 3 = ) 5 2 = r p o tc 0 7 4 a s p o t s k c o l c e h t n e h w c 5 2 = r p o t 4 . 00 2 a : s e t o n . y l n o e g a k c a p n i p - 4 4 1 e h t n i d e d i v o r p e r a 5 1 p o t 1 1 p . 1
page 84 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m v cc =5v table 5.48 a/d conversion characteristics (v cc = av cc = v ref = 4.2 to 5.5v, vss = av ss = 0v at topr = 40 to 85 o c (t version), f(x in ) = 32mh z unless otherwise specified) table 5.49 d/a conversion characteristics (v cc = v ref = 4.2 to 5.5v, v ss = av ss = 0v at topr = 40 to 85 o c (t version), f(x in ) = 32mh z unless otherwise specified) table 5.50 flash memory version electrical characteristics l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u n i mp y tx a m -n o i t u l o s e rv f e r v = c c 0 1s t i b l n ir o r r e y t i r a e n i l n o n l a r g e t n iv f e r v = c c v 5 = n a 0 n a o t 7 n a 0 x e n a , 1 x e 3 b s l b s l p m a - p o l a n r e t x e e d o m n o i t c e n n o c 7 b s l b s l l n dr o r r e y t i r a e n i l n o n l a i t n e r e f f i d 1 b s l -r o r r e t e s f f o 3 b s l -r o r r e n i a g 3 b s l r r e d d a l r e d d a l r o t s i s e rv f e r v = c c 80 4k ? t v n o c e m i t n o i s r e v n o c t i b - 0 1 1 . 2 s t v n o c e m i t n o i s r e v n o c t i b - 8 8 . 1 s t p m a s e m i t e l p m a s 2 . 0 s v f e r e g a t l o v e c n e r e f e r 2v c c v v a i e g a t l o v t u p n i g o l a n a 0v f e r v : s e t o n x ( f e d i v i d . 1 n i p e e k o t , z h m 6 1 g n i d e e c x e f i , ) . s s e l r o z h m 6 1 t a y c n e u q e r f d a l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u n i mp y tx a m -n o i t u l o s e r 8s t i b -y c a r u c c a e t u l o s b a 0 . 1% t u s e m i t p u t e s 3 s r o e c n a t s i s e r t u p t u o 40 10 2k ? i f e r v y l p p u s r e w o p e c n e r e f e r t n e r r u c t u p n i ) 1 e t o n (5 . 1a m : s e t o n e h t f o ) 1 , 0 = i ( r e t s i g e r i a d e h t . r e t r e v n o c a / d e n o g n i s u n e h w s t l u s e r t n e m e r u s a e m . 1 0 0 " o t t e s s i d e s u g n i e b t o n r e t r e v n o c a / d 6 1 . d e u l c x e s i r e t r e v n o c d / a e h t n i r e d d a l r o t s i s e r e h t . " i f e r v v o n ( " 0 " o t t e s s i r e t s i g e r 1 n o c i d a e h t n i t i b t u c v e h t f i n e v e s w o l f f e r . ) n o i t c e n n o c r e t e m a r a p d r a d n a t s t i n u n i mp y tx a m ) e g a p r e p ( e m i t m a r g o r p80 2 1s m ) k c o l b r e p ( e m i t e s a r e k c o l b0 50 0 6s m : s e t o n v . 1 c c d e i f i c e p s e s i w r e h t o s s e l n u , c 0 6 o t 0 = r p o t t a v 5 . 5 o t 2 . 4 =
page 85 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m v cc =5v timing requirements (v cc = 4.2 to 5.5v, v ss = 0v at topr = 40 to 85 o c (t version) unless otherwise specified) table 5.51 external clock input l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c te m i t e l c y c t u p n i k c o l c l a n r e t x e 3 3s n w t ) h ( h t d i w e s l u p ) " h " ( h g i h t u p n i k c o l c l a n r e t x e 3 1s n w t ) l ( h t d i w e s l u p ) " l " ( w o l t u p n i k c o l c l a n r e t x e 3 1s n r te m i t e s i r k c o l c l a n r e t x e 5s n f te m i t l l a f k c o l c l a n r e t x e 5s n
page 86 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m v cc =5v l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 1s n w t ) h a t ( i a t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 4s n w t ) l a t ( i a t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 4s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h a t ( i a t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 2s n w t ) l a t ( i a t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 2s n w t ) h a t ( i a t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 1s n w t ) l a t ( i a t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m w t ) h a t ( i a t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 1s n w t ) l a t ( i a t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) p u ( i a t t u o e m i t e l c y c t u p n i 0 0 0 2s n w t ) h p u ( i a t t u o h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 0 1s n w t ) l p u ( i a t t u o h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 0 1s n u s t ) n i t - p u ( i a t t u o e m i t p u t e s t u p n i 0 0 4s n h t ) p u - n i t ( i a t t u o e m i t d l o h t u p n i 0 0 4s n timing requirements (v cc = 4.2 to 5.5v, v ss = 0v at topr = 40 to 85 o c (t version) unless otherwise specified) table 5.52 timer a input (count source input in event counter mode) table 5.53 timer a input (gate input in timer mode) table 5.54 timer a input (external trigger input in one-shot timer mode) table 5.55 timer a input (external trigger input in pulse width modulation mode) table 5.56 timer a input (counter increment/decrement input in event counter mode)
page 87 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m v cc =5v timing requirements (v cc = 4.2 to 5.5v, v ss = 0v at topr = 40 to 85 o c (t version) unless otherwise specified) table 5.57 timer b input (count source input in event counter mode) table 5.58 timer b input (pulse period measurement mode) table 5.59 timer b input (pulse width measurement mode) table 5.60 a/d trigger input table 5.61 serial i/o _______ table 5.62 external interrupt inti input l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) b t ( i b t n i ) e g d e e n o n o d e t n u o c ( e m i t e l c y c t u p n i 0 0 1s n w t ) h b t ( i b t n i ) e g d e e n o n o d e t n u o c ( h t d i w e s l u p ) " h " ( h g i h t u p n i 0 4s n w t ) l b t ( i b t n i ) e g d e e n o n o d e t n u o c ( h t d i w e s l u p ) " l " ( w o l t u p n i 0 4s n c t ) b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( e m i t e l c y c t u p n i 0 0 2s n w t ) h b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( h t d i w e s l u p ) " h " ( h g i h t u p n i 0 8s n w t ) l b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( h t d i w e s l u p ) " l " ( w o l t u p n i 0 8s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) b t ( i b t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h b t ( i b t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 2s n w t ) l b t ( i b t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) b t ( i b t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h b t ( i b t n i h t d i w e s l u p ) " h " ( h g i h t u p n i 0 0 2s n w t ) l b t ( i b t n i h t d i w e s l u p ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) d a ( d a g r t ) r e g g i r t - e r r o f d e r i u q e r ( e m i t e l c y c t u p n i 0 0 0 1s n w t ) l d a ( d a g r t h t d i w e s l u p ) " l " ( w o l t u p n i 5 2 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m c t ) k c ( e m i t e l c y c t u p n i i k l c 0 0 2s n w t ) h k c ( h t d i w e s l u p ) " h " ( h g i h t u p n i i k l c 0 0 1s n w t ) l k c ( h t d i w e s l u p ) " l " ( w o l t u p n i i k l c 0 0 1s n d t ) q - c ( e m i t y a l e d t u p t u o i d x t 0 8s n h t ) q - c ( e m i t d l o h i d x t 0s n u s t ) c - d ( e m i t p u t e s t u p n i i d x r 0 3s n h t ) q - c ( e m i t d l o h t u p n i i d x r 0 9s n l o b m y sr e t e m a r a p d r a d n a t s t i n u n i mx a m w t ) h n i ( h t d i w e s l u p ) " h " ( h g i h t u p n i i t n i 0 5 2s n w t ) l n i ( h t d i w e s l u p ) " l " ( w o l t u p n i i t n i 0 5 2s n
page 88 ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf p14 p13 p12 p15 p11 note 1 notes: 1. p11 to p15 are p rovided in the 144- p in p acka g e onl y . figure 5.18 p0 to p15 measurement circuit
page 89 ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r t su(d c) tai in input tai out input in event counter mode tbi in input clki txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c q) t h(c d) t h(c q) t h(t in up) t su(up t in ) tai in input (when counting on the falling edge) tai in input (when counting on the rising edge) tai out input (counter increment/ decrement input) inti input ad trg input vcc=5v nmi input 2 clock cycles + 300ns or more ("l" width) 2 clock cycles + 300ns or more figure 5.19 vcc = 5 v timing diagram(1)
page 90 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m package dimensions plq0144ka-a (144p6q-a) plastic 144pin 20 x 20 mm body lqfp terminal cross section b 1 c 1 b p c 1.0 0.125 0.20 1.25 1.25 0.08 0.20 0.145 0.09 0.27 0.22 0.17 max nom min dimension in millimeters symbol reference 20.1 20.0 19.9 d 20.1 20.0 19.9 e 1.4 a 2 22.2 22.0 21.8 22.2 22.0 21.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 p-lqfp144-20x20-0.50 1.2g mass[typ.] 144p6q-a / fp-144l / fp-144lv plqp0144ka-a renesas code jeita package code previous code f 1 36 37 72 73 108 109 144 * 1 * 2 * 3 x index mark y h e e d h d b p z d z e detail f c a l a 1 a 2 l 1 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. e 0.8 0.5 0.825 0.575 z e z d b p a 1 h e h d y 0.10 e 0.65 c 0 10 l 0.4 0.6 0.8 0 0.1 0.2 a 3.05 16.5 16.8 17.1 22.5 22.8 23.1 a 2 2.8 e 13.8 14.0 14.2 d 19.8 20.0 20.2 reference symbol dimension in millimeters min nom max 0.25 0.3 0.4 0.13 0.15 0.2 p-qfp100-14x20-0.65 1.6g mass[typ.] 100p6s-a prqp0100jb-a renesas code jeita package code previous code y index mark 100 81 80 51 50 31 30 1 f * 2 * 1 * 3 z e z d e b p a h d d e h e c detail f a 1 a 2 l include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. prqp0100jb-a (100p6s-a) plastic 100pin 14 x 20 mm body lqfp
page 91 1 9 f o 6 0 0 2 , 1 3 . n a j 1 4 . 1 . v e r 1 4 1 0 - 3 1 0 0 b 3 0 j e r ) t 3 8 / c 2 3 m , 3 8 / c 2 3 m ( p u o r g 3 8 / c 2 3 m terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark x 125 26 50 51 75 76 100 f * 1 *3 * 2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e plqp0100kb-a (100p6q-a) plastic 100pin 14 x 14 mm body lqfp
revision history m32c/83 group (m32c/83, m32c/83t) datasheet rev. date description page summary 1.10 2003-9 1.20 2003-12 1.30 2004-06 1.41 2006-01 - new document maximum operating frequency changed from 30 mhz to 32 mhz. overview, electrical characteristics table 1.1 m32c/83 group performance (144-pin package) table 1.2 m32c/83 group performance (100-pin package) table 5.2 recommended operating conditions table 5.3 electrical characteristics all pages words standardized: on-chip oscillator, a/d converter and d/a converter all pages m32c/83t version added; package code changed: 144p6q-a to plqp0144ka- a, 100p6q-a to plqp0100kb-a, 100p6s-a to prqp0100jb-a all pages word standardized: clock generation circuit , on-chip oscillator, a/d converter, d/a converter, xy conversion, low -power consumption overview 1 1.1 applications automobile added 2, 3 tables 1.1 and 1.2 m32c/83 group (m32c/83, m32c/83t) performance 5 table 1.3 m32c/83 group (1) (m32c/83) information updated table 1.3 m32c/83 group (2) (m32c/83t) m32c/83t product information added figure 1.2 product numbering system classification modified table 1.4 pin characteristics for 144-pin package note 1 added table 1.5 pin characteristics for 100-pin package note 1 added table 1.6 pin description modified, notes added memory 21 figure 3.1 memory map modified; note 2 modified, notes 3 and 4 added special function registers (sfr) 22 to 23 note 2 added reset 45 figure 5.2 reset sequence note 2 added electrical characteristics 46 table 5.3 electrical characteristics minimum standard values for v oh revised, values for i cc when f(x in )=32 mhz, square wave, no division revised, one condition of f(x in )=32 mhz, square wave, no division deleted 54 table 5.23 memory expansion mode and microprocessor mode symbols for row address output delay time and for row address output hold time (bclk standard) modified 62 _______ figure 5.8 v cc =5 v timing diagram (7) timing for nmi input added 64 table 5.24 electrical characteristics minimum standard value for v oh revised
revision history m32c/83 group (m32c/83, m32c/83t) datasheet rev. date description page summary 72 table 5.44 memory expansion mode and microprocessor mode symbols for row address output delay time and for row address output hold time (bclk standard) modified 79 _______ figure 5.8 v cc =3.3 v timing diagram (7) timing for nmi input added 81-89 5.2 electrical characteristics (m32c/83t) newly added
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