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revision date: mar 17, 2006 8 h8/3577 group , h8/3567 group hardware manual rev. 3.00 rej09b0303-0300 renesas 8-bit single-chip microcomputer h8 family/h8/300 series h8/3577 hd6433577 hd6473577 h8/3574 hd6433574 h8/3567 hd6433567 hd6473567 h8/3564 hd6433564 h8/3567u hd6433567u hd6473567u h8/3564u hd6433564u
rev. 3.00 mar 17, 2006 page ii of xxiv 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third- party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. keep safety first in your circuit designs! notes regarding these materials
rev. 3.00 mar 17, 2006 page iii of xxiv general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product?s state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. do not access these registers; the system?s operation is not guaranteed if they are accessed.
rev. 3.00 mar 17, 2006 page iv of xxiv configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. main revisions for this edition the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents. for details, see the actual locations in this manual. 5. contents 6. overview 7. description of functional modules cpu and system-control modules on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 8. list of registers 9. electrical characteristics 10. appendix
rev. 3.00 mar 17, 2006 page v of xxiv preface the h8/3577 group and h8/3567 group comprise single-chip microcomputers built around the h8/300 cpu and equipped with on-chip supporting functions required for system configuration. versions are available with prom (ztat?) or mask rom as on-chip rom. on-chip supporting functions include a16-bit free-running timer (frt), 8-bit timer (tmr), watchdog timer (wdt), two pwm timers (pwm and pwmx), a serial communication interface (sci), i 2 c bus interface (iic), a/d converter (adc), and i/o ports. the h8/3577 group comprises 64-pin models with the above supporting functions on-chip. the h8/3567 group comprises the 42-pin h8/3567 and h8/3564 with fewer pwm, adc, and i/o port channels, and the 64-pin h8/3567u and h8/3564u with on-chip universal serial bus (usb) hubs and function. use of the h8/3577 group or h8/3567 group enables compact, high-performance systems to be implemented easily. the comprehensive timer functions and their interconnectability (timer connection facility) make these groups ideal for applications such as pc monitor systems. this manual describes the hardware of the h8/3577 group and h8/3567 group. refer to the h8/300 series programming manual for a detailed description of the instruction set. note: ztat (zero turn-around time) is a trademark of renesas technology corp.
rev. 3.00 mar 17, 2006 page vi of xxiv on-chip supporting modules group h8/3577 group h8/3567 group product names h8/3577, h8/3574 h8/3567, h8/3564, h8/3567u, h8/3564u universal serial bus (usb) ? ?/available (h8/3567u, h8/3564u) 8-bit pwm timer (pwm) 16 8 14-bit pwm timer (pwmx) 2 2 16-bit free-running timer (frt) 1 1 8-bit timer (tmr) 4 4 timer connection available available watchdog timer (wdt) 1 1 serial communication interface (sci) 1 1 i 2 c bus interface (iic) 2 2 a/d converter 8 4
rev. 3.00 mar 17, 2006 page vii of xxiv main revisions in this edition item page revision (see manual for details) all ? notification of change in company name amended (before) hitachi, ltd. (after) renesas technology corp. product naming convention amended (before) h8/3577 series (after) h8/3577 group (before) h8/3567 series (after) h8/3567 group 5.2.1 system control register (syscr) 84 bit table amended bit . . . 4 . . . . . . intm0 . . . initial value 0 read/write r 7.3.5 operation when out token is received (endpoints 0 and 2) figure 7.3 (2) operation when out token is received (ep2-out: initial fifo full) (cont) 155 figure amended clear ep2ts bit to 0 in tsfr 7.3.9 usb module startup sequence initial operation procedures: 164 description amended 8. after dpll operation stabilization time, hsrst bit is cleared to 0 by firmware figure 7.5 usb hub initial operation procedure 165 figure amended clear fonly bit to 0 in usbcr figure 7.6 usb function initial operation procedure 166 figure amended (wait for usb operating clock oscillation stabilization time (10 ms)) clear fpllrst bit to 0 in usbcr
rev. 3.00 mar 17, 2006 page viii of xxiv item page revision (see manual for details) 7.3.9 usb module startup sequence figure 7.6 usb function initial operation procedure (cont) 167 figure amended set epivld bit to 1 in usbcsr0 figure 7.9 usb function standalone mode upstream disconnection/ reconnection 172 figure amended set epivld bit to 1 in usbcsr0 12.2.8 timer connection register s (tconrs) 296 table amended bit 7 accessible registers tmrx/y h'fff0 h'fff1 h'fff2 h'fff3 h'fff4 h'fff5 h'fff6 h'fff7 0 (initial value) tcrx (tmrx ) tcsrx ) ticrr (tmrx ) ticrf (tmrx ) tcntx (tmrx ) tcorc (tmrx ) tcorax (tmrx ) tcorbx (tmrx ) 1 tcry (tmry ) tcsry (tmry ) tcoray (tmry ) tcorby (tmry ) tcnty (tmry ) tisr (tmry ) (tmrx 16.3.1 i 2 c bus data format table 16.4 description of i 2 c bus data format symbols 447 newly added b.1 addresses 579 table amended address register name . . . module name bus width h'ffe2 addrbh a/d 8 h'ffe3 addrbl h'ffe4 addrch h'ffe5 addrcl h'ffe6 addrdh h'ffe7 addrdl b.3 functions utestr0, utestr1 587 bit table added utestr2 606 bit table added
rev. 3.00 mar 17, 2006 page ix of xxiv item page revision (see manual for details) appendix g package dimensions figure g.1 dp-64s package dimensions 703 figure replaced figure g.2 fp-64a package dimensions 704 figure replaced figure g.3 dp-42s package dimensions 705 figure replaced figure g.4 fp-44a package dimensions 706 figure replaced
rev. 3.00 mar 17, 2006 page x of xxiv
rev. 3.00 mar 17, 2006 page xi of xxiv contents section 1 overview ............................................................................................................. 1 1.1 overview.................................................................................................................... ....... 1 1.2 internal block diagrams ................................................................................................... 6 1.3 pin arrangement and functions........................................................................................ 8 1.3.1 pin arrangement .................................................................................................. 8 1.3.2 list of pin functions............................................................................................ 14 1.3.3 pin functions ....................................................................................................... 22 section 2 cpu ...................................................................................................................... 29 2.1 overview.................................................................................................................... ....... 29 2.1.1 features................................................................................................................ 29 2.1.2 address space...................................................................................................... 30 2.1.3 register configuration......................................................................................... 30 2.2 register descriptions ....................................................................................................... .31 2.2.1 general registers ................................................................................................. 31 2.2.2 control registers ................................................................................................. 31 2.2.3 initial register values.......................................................................................... 33 2.3 data formats................................................................................................................ ..... 33 2.3.1 data formats in general registers ...................................................................... 34 2.3.2 memory data formats ......................................................................................... 35 2.4 addressing modes ............................................................................................................ 36 2.4.1 addressing modes ............................................................................................... 36 2.4.2 effective address calculation ............................................................................. 38 2.5 instruction set ............................................................................................................. ...... 42 2.5.1 data transfer instructions.................................................................................... 44 2.5.2 arithmetic operations.......................................................................................... 46 2.5.3 logic operations.................................................................................................. 47 2.5.4 shift operations ................................................................................................... 47 2.5.5 bit manipulations................................................................................................. 49 2.5.6 branching instructions ......................................................................................... 53 2.5.7 system control instructions................................................................................. 55 2.5.8 block data transfer instruction........................................................................... 57 2.6 basic operational timing ................................................................................................. 58 2.6.1 access to on-chip memory (ram, rom)......................................................... 58 2.6.2 access to on-chip peripheral modules............................................................... 59 2.7 cpu states .................................................................................................................. ...... 60 2.7.1 overview.............................................................................................................. 60 2.7.2 reset state............................................................................................................ 61
rev. 3.00 mar 17, 2006 page xii of xxiv 2.7.3 program execution state...................................................................................... 61 2.7.4 program halt state............................................................................................... 61 2.7.5 exception-handling state .................................................................................... 61 2.8 application notes ........................................................................................................... .. 62 2.8.1 notes on bit manipulation................................................................................... 62 2.8.2 notes on use of the eepmov instruction (cannot be used in the h8/3577 group and h8/3567 group)............................ 64 section 3 mcu operating modes .................................................................................. 65 3.1 overview.................................................................................................................... ....... 65 3.1.1 operating mode selection ................................................................................... 65 3.1.2 register configuration......................................................................................... 65 3.2 register descriptions ....................................................................................................... .66 3.2.1 mode control register (mdcr) ......................................................................... 66 3.2.2 system control register (syscr) ...................................................................... 67 3.2.3 serial timer control register (stcr) ................................................................ 68 3.3 address map ................................................................................................................. .... 69 section 4 exception handling ......................................................................................... 73 4.1 overview.................................................................................................................... ....... 73 4.1.1 exception handling types and priority............................................................... 73 4.1.2 exception handling operation............................................................................. 73 4.1.3 exception sources and vector table ................................................................... 74 4.2 reset....................................................................................................................... ........... 75 4.2.1 overview.............................................................................................................. 75 4.2.2 reset sequence .................................................................................................... 75 4.2.3 interrupts after reset............................................................................................ 76 4.3 interrupts .................................................................................................................. ......... 77 4.4 stack status after exception handling.............................................................................. 78 4.5 note on stack handling .................................................................................................... 79 section 5 interrupt controller .......................................................................................... 81 5.1 overview.................................................................................................................... ....... 81 5.1.1 features................................................................................................................ 81 5.1.2 block diagram..................................................................................................... 82 5.1.3 pin configuration................................................................................................. 83 5.1.4 register configuration......................................................................................... 83 5.2 register descriptions ....................................................................................................... .84 5.2.1 system control register (syscr) ...................................................................... 84 5.2.2 irq enable register (ier) .................................................................................. 85 5.2.3 irq sense control registers h and l (iscrh, iscrl)..................................... 86
rev. 3.00 mar 17, 2006 page xiii of xxiv 5.2.4 irq status register (isr).................................................................................... 87 5.3 interrupt sources........................................................................................................... .... 88 5.3.1 external interrupts ............................................................................................... 88 5.3.2 internal interrupts................................................................................................. 89 5.3.3 interrupt exception vector table ........................................................................ 89 5.4 interrupt operation......................................................................................................... ... 92 5.4.1 interrupt operation .............................................................................................. 92 5.4.2 interrupt control mode 0 ..................................................................................... 94 5.4.3 interrupt exception handling sequence .............................................................. 96 5.4.4 interrupt response times .................................................................................... 97 5.5 usage notes ................................................................................................................. ..... 98 5.5.1 contention between interrupt generation and disabling..................................... 98 5.5.2 instructions that disable interrupts ...................................................................... 99 5.5.3 interrupts during execution of eepmov instruction.......................................... 99 section 6 bus controller ................................................................................................... 101 6.1 overview.................................................................................................................... ....... 101 6.2 register descriptions ....................................................................................................... . 101 6.2.1 bus control register (bcr) ................................................................................ 101 6.2.2 wait state control register (wscr) .................................................................. 102 section 7 universal serial bus interface (usb) ......................................................... 103 7.1 overview.................................................................................................................... ....... 103 7.1.1 features................................................................................................................ 10 3 7.1.2 block diagram..................................................................................................... 104 7.1.3 pin configuration................................................................................................. 105 7.1.4 register configuration......................................................................................... 105 7.2 register descriptions ....................................................................................................... . 107 7.2.1 usb data fifo.................................................................................................... 107 7.2.2 endpoint size register 1 (epszr1) .................................................................... 108 7.2.3 endpoint data registers 0i, 0o, 1, 2 (epdr0i, epdr0o, epdr1, epdr2) ..... 109 7.2.4 fifo valid size registers 0i, 0o, 1, 2 (fvsr0i, fvsr0o, fvsr1, fvsr2)... 110 7.2.5 endpoint direction register (epdir) ................................................................. 111 7.2.6 packet transmit enable register (ptter) ......................................................... 112 7.2.7 usb interrupt enable register (usbier)........................................................... 113 7.2.8 usb interrupt flag register (usbifr) ............................................................... 115 7.2.9 transfer success flag register (tsfr) ............................................................... 118 7.2.10 transfer fail flag register (tffr) ..................................................................... 121 7.2.11 usb control/status register 0 (usbcsr0)........................................................ 124 7.2.12 endpoint stall register (epstlr) ...................................................................... 128 7.2.13 endpoint reset register (eprstr)..................................................................... 129
rev. 3.00 mar 17, 2006 page xiv of xxiv 7.2.14 device resume register (devrsmr) ............................................................... 131 7.2.15 interrupt source select register 0 (intselr0).................................................. 131 7.2.16 interrupt source select register 1 (intselr1).................................................. 133 7.2.17 hub overcurrent control register (hoccr)...................................................... 133 7.2.18 usb control register (usbcr).......................................................................... 135 7.2.19 usb pll control register (upllcr) ............................................................... 139 7.2.20 usb port control register (uprtcr)................................................................ 141 7.2.21 usb test registers 2, 1, 0 (utestr2, utestr1, utestr0)......................... 142 7.2.22 module stop control register (mstpcr) .......................................................... 143 7.2.23 serial timer control register (stcr) ................................................................ 143 7.3 operation ................................................................................................................... ....... 145 7.3.1 usb compound device configuration ............................................................... 145 7.3.2 functions of usb hub block .............................................................................. 145 7.3.3 functions of usb function ................................................................................. 146 7.3.4 operation when setup token is received (endpoint 0)................................... 148 7.3.5 operation when out token is received (endpoints 0 and 2) ........................... 153 7.3.6 operation when in token is received (endpoints 0, 1, and 2) .......................... 155 7.3.7 suspend/resume operations................................................................................ 159 7.3.8 usb module reset and operation-halted states ................................................ 159 7.3.9 usb module startup sequence............................................................................ 162 7.3.10 usb module slave cpu interrupts ..................................................................... 175 section 8 i/o ports .............................................................................................................. 177 8.1 overview.................................................................................................................... ....... 177 8.2 port 1...................................................................................................................... ........... 180 8.2.1 overview.............................................................................................................. 180 8.2.2 register configuration......................................................................................... 181 8.2.3 pin functions ....................................................................................................... 182 8.2.4 mos input pull-up function............................................................................... 185 8.3 port 2 [h8/3577 group only] ........................................................................................... 186 8.3.1 overview.............................................................................................................. 186 8.3.2 register configuration......................................................................................... 187 8.3.3 pin functions ....................................................................................................... 189 8.3.4 mos input pull-up function............................................................................... 191 8.4 port 3 [h8/3577 group only] ........................................................................................... 192 8.4.1 overview.............................................................................................................. 192 8.4.2 register configuration......................................................................................... 192 8.4.3 pin functions ....................................................................................................... 194 8.4.4 mos input pull-up function............................................................................... 194 8.5 port 4...................................................................................................................... ........... 195 8.5.1 overview.............................................................................................................. 195
rev. 3.00 mar 17, 2006 page xv of xxiv 8.5.2 register configuration......................................................................................... 195 8.5.3 pin functions ....................................................................................................... 197 8.6 port 5...................................................................................................................... ........... 199 8.6.1 overview.............................................................................................................. 199 8.6.2 register configuration......................................................................................... 199 8.6.3 pin functions ....................................................................................................... 201 8.7 port 6...................................................................................................................... ........... 202 8.7.1 overview.............................................................................................................. 202 8.7.2 register configuration......................................................................................... 202 8.7.3 pin functions ....................................................................................................... 203 8.8 port 7...................................................................................................................... ........... 206 8.8.1 overview.............................................................................................................. 206 8.8.2 register configuration......................................................................................... 206 8.8.3 pin functions ....................................................................................................... 207 8.9 port c [h8/3567 group version with on-chip usb only] ............................................. 208 8.9.1 overview.............................................................................................................. 208 8.9.2 register configuration......................................................................................... 208 8.9.3 pin functions ....................................................................................................... 210 8.10 port d [h8/3567 group version with on-chip usb only] ............................................. 211 8.10.1 overview.............................................................................................................. 211 8.10.2 register configuration......................................................................................... 211 8.10.3 pin functions ....................................................................................................... 213 section 9 8-bit pwm timers ........................................................................................... 215 9.1 overview.................................................................................................................... ....... 215 9.1.1 features................................................................................................................ 21 5 9.1.2 block diagram..................................................................................................... 216 9.1.3 pin configuration................................................................................................. 217 9.1.4 register configuration......................................................................................... 217 9.2 register descriptions ....................................................................................................... . 218 9.2.1 pwm register select (pwsl)............................................................................. 218 9.2.2 pwm data registers (pwdr0 to pwdr15) ...................................................... 220 9.2.3 pwm data polarity registers a and b (pwdpra and pwdprb).................... 220 9.2.4 pwm output enable registers a and b (pwoera and pwoerb) ................. 221 9.2.5 peripheral clock select register (pcsr) ............................................................ 222 9.2.6 port 1 data direction register (p1ddr)............................................................. 222 9.2.7 port 2 data direction register (p2ddr)............................................................. 223 9.2.8 port 1 data register (p1dr)................................................................................ 223 9.2.9 port 2 data register (p2dr)................................................................................ 223 9.2.10 module stop control register (mstpcr) .......................................................... 224 9.3 operation ................................................................................................................... ....... 225
rev. 3.00 mar 17, 2006 page xvi of xxiv 9.3.1 correspondence between pwm data register contents and output waveform.......................................................................................... 225 section 10 14-bit pwm timer ........................................................................................ 227 10.1 overview................................................................................................................... ........ 227 10.1.1 features................................................................................................................ 2 27 10.1.2 block diagram..................................................................................................... 228 10.1.3 pin configuration................................................................................................. 229 10.1.4 register configuration......................................................................................... 229 10.2 register descriptions ...................................................................................................... .. 230 10.2.1 pwm d/a counter (dacnt)............................................................................. 230 10.2.2 d/a data registers a and b (dadra and dadrb)......................................... 231 10.2.3 pwm d/a control register (dacr) .................................................................. 232 10.2.4 module stop control register (mstpcr) .......................................................... 234 10.3 bus master interface ....................................................................................................... .. 235 10.4 operation .................................................................................................................. ........ 238 section 11 16-bit free-running timer ......................................................................... 243 11.1 overview................................................................................................................... ........ 243 11.1.1 features................................................................................................................ 2 43 11.1.2 block diagram..................................................................................................... 244 11.1.3 input and output pins .......................................................................................... 245 11.1.4 register configuration......................................................................................... 246 11.2 register descriptions ...................................................................................................... .. 247 11.2.1 free-running counter (frc) .............................................................................. 247 11.2.2 output compare registers a and b (ocra, ocrb) ......................................... 247 11.2.3 input capture registers a to d (icra to icrd) ................................................ 248 11.2.4 output compare registers ar and af (ocrar, ocraf) ............................... 249 11.2.5 output compare register dm (ocrdm) ........................................................... 250 11.2.6 timer interrupt enable register (tier) .............................................................. 250 11.2.7 timer control/status register (tcsr)................................................................ 252 11.2.8 timer control register (tcr)............................................................................. 255 11.2.9 timer output compare control register (tocr) .............................................. 257 11.2.10 module stop control register (mstpcr) .......................................................... 260 11.3 operation .................................................................................................................. ........ 260 11.3.1 frc increment timing ........................................................................................ 260 11.3.2 output compare output timing .......................................................................... 262 11.3.3 frc clear timing................................................................................................ 263 11.3.4 input capture input timing ................................................................................. 263 11.3.5 timing of input capture flag (icfa to icfd) setting ....................................... 266 11.3.6 setting of output compare flags a and b (ocfa, ocfb)................................ 267
rev. 3.00 mar 17, 2006 page xvii of xxiv 11.3.7 setting of frc overflow flag (ovf) ................................................................. 268 11.3.8 automatic addition of ocra and ocrar/ocraf ......................................... 268 11.3.9 icrd and ocrdm mask signal generation ...................................................... 269 11.4 interrupts ................................................................................................................. .......... 270 11.5 sample application......................................................................................................... .. 271 11.6 usage notes ................................................................................................................ ...... 272 section 12 8-bit timers ..................................................................................................... 279 12.1 overview................................................................................................................... ........ 279 12.1.1 features................................................................................................................ 2 79 12.1.2 block diagram..................................................................................................... 280 12.1.3 pin configuration................................................................................................. 281 12.1.4 register configuration......................................................................................... 282 12.2 register descriptions ...................................................................................................... .. 283 12.2.1 timer counter (tcnt)........................................................................................ 283 12.2.2 time constant register a (tcora)................................................................... 284 12.2.3 time constant register b (tcorb) ................................................................... 285 12.2.4 timer control register (tcr)............................................................................. 286 12.2.5 timer control/status register (tcsr)................................................................ 290 12.2.6 serial timer control register (stcr) ................................................................ 294 12.2.7 system control register (syscr) ...................................................................... 295 12.2.8 timer connection register s (tconrs)............................................................ 295 12.2.9 input capture register (ticr) [tmrx additional function] ............................ 296 12.2.10 time constant register c (tcorc) [tmrx additional function]................... 296 12.2.11 input capture registers r and f (ticrr, ticrf) [tmrx additional functions]............................................................................. 297 12.2.12 timer input select register (tisr) [tmry additional function]..................... 297 12.2.13 module stop control register (mstpcr) .......................................................... 298 12.3 operation .................................................................................................................. ........ 299 12.3.1 tcnt incrementation timing ............................................................................. 299 12.3.2 compare-match timing....................................................................................... 300 12.3.3 tcnt external reset timing .............................................................................. 302 12.3.4 timing of overflow flag (ovf) setting ............................................................. 302 12.3.5 operation with cascaded connection.................................................................. 303 12.4 interrupt sources.......................................................................................................... ..... 304 12.5 8-bit timer application example..................................................................................... 305 12.6 usage notes ................................................................................................................ ...... 306 12.6.1 contention between tcnt write and clear........................................................ 306 12.6.2 contention between tcnt write and increment ................................................ 307 12.6.3 contention between tcor write and compare-match ...................................... 308 12.6.4 contention between compare-matches a and b................................................. 309
rev. 3.00 mar 17, 2006 page xviii of xxiv 12.6.5 switching of internal clocks and tcnt operation............................................. 309 section 13 timer connection ........................................................................................... 313 13.1 overview................................................................................................................... ........ 313 13.1.1 features................................................................................................................ 3 13 13.1.2 block diagram..................................................................................................... 314 13.1.3 input and output pins .......................................................................................... 315 13.1.4 register configuration......................................................................................... 316 13.2 register descriptions ...................................................................................................... .. 316 13.2.1 timer connection register i (tconri) ............................................................. 316 13.2.2 timer connection register o (tconro) .......................................................... 318 13.2.3 timer connection register s (tconrs)............................................................ 320 13.2.4 edge sense register (sedgr) ............................................................................ 323 13.2.5 module stop control register (mstpcr) .......................................................... 325 13.3 operation .................................................................................................................. ........ 327 13.3.1 pwm decoding (pdc signal generation) .......................................................... 327 13.3.2 clamp waveform generation (cl 1 /cl 2 /cl 3 signal generation) ........................ 328 13.3.3 measurement of 8-bit timer divided waveform period .................................... 330 13.3.4 ihi signal and 2fh modification ......................................................................... 332 13.3.5 ivi signal fall modification and ihi synchronization ....................................... 334 13.3.6 internal synchronization signal generation (ihg/ivg/cl 4 signal generation) 336 13.3.7 hsynco output ................................................................................................. 339 13.3.8 vsynco output ................................................................................................. 340 13.3.9 cblank output ................................................................................................. 341 section 14 watchdog timer (wdt) .............................................................................. 343 14.1 overview................................................................................................................... ........ 343 14.1.1 features................................................................................................................ 3 43 14.1.2 block diagram..................................................................................................... 344 14.1.3 register configuration......................................................................................... 345 14.2 register descriptions ...................................................................................................... .. 345 14.2.1 timer counter (tcnt)........................................................................................ 345 14.2.2 timer control/status register (tcsr0).............................................................. 346 14.2.3 system control register (syscr) ...................................................................... 348 14.2.4 notes on register access..................................................................................... 349 14.3 operation .................................................................................................................. ........ 349 14.3.1 watchdog timer operation ................................................................................. 349 14.3.2 interval timer operation ..................................................................................... 350 14.3.3 timing of setting of overflow flag (ovf)......................................................... 351 14.4 interrupts ................................................................................................................. .......... 352 14.5 usage notes ................................................................................................................ ...... 352
rev. 3.00 mar 17, 2006 page xix of xxiv 14.5.1 contention between timer counter (tcnt) write and increment ..................... 352 14.5.2 changing value of cks2 to cks0...................................................................... 353 14.5.3 switching between watchdog timer mode and interval timer mode................ 353 section 15 serial communication interface (sci) .................................................... 355 15.1 overview................................................................................................................... ........ 355 15.1.1 features................................................................................................................ 3 55 15.1.2 block diagram..................................................................................................... 357 15.1.3 pin configuration................................................................................................. 358 15.1.4 register configuration......................................................................................... 358 15.2 register descriptions ...................................................................................................... .. 359 15.2.1 receive shift register (rsr) .............................................................................. 359 15.2.2 receive data register (rdr) .............................................................................. 359 15.2.3 transmit shift register (tsr) ............................................................................. 360 15.2.4 transmit data register (tdr)............................................................................. 360 15.2.5 serial mode register (smr)................................................................................ 360 15.2.6 serial control register (scr).............................................................................. 363 15.2.7 serial status register (ssr) ................................................................................ 367 15.2.8 bit rate register (brr) ...................................................................................... 371 15.2.9 serial interface mode register (scmr).............................................................. 380 15.2.10 module stop control register (mstpcr) .......................................................... 381 15.3 operation .................................................................................................................. ........ 382 15.3.1 overview.............................................................................................................. 382 15.3.2 operation in asynchronous mode ....................................................................... 384 15.3.3 multiprocessor communication function............................................................ 395 15.3.4 operation in synchronous mode ......................................................................... 403 15.4 sci interrupts............................................................................................................. ....... 412 15.5 usage notes ................................................................................................................ ...... 413 section 16 i 2 c bus interface (iic) .................................................................................. 417 16.1 overview................................................................................................................... ........ 417 16.1.1 features................................................................................................................ 4 17 16.1.2 block diagram..................................................................................................... 418 16.1.3 input/output pins ................................................................................................. 420 16.1.4 register configuration......................................................................................... 421 16.2 register descriptions ...................................................................................................... .. 422 16.2.1 i 2 c bus data register (icdr) ............................................................................. 422 16.2.2 slave address register (sar) ............................................................................. 425 16.2.3 second slave address register (sarx) ............................................................. 427 16.2.4 i 2 c bus mode register (icmr) ........................................................................... 428 16.2.5 i 2 c bus control register (iccr) ......................................................................... 430
rev. 3.00 mar 17, 2006 page xx of xxiv 16.2.6 i 2 c bus status register (icsr)............................................................................ 436 16.2.7 serial timer control register (stcr) ................................................................ 441 16.2.8 ddc switch register (ddcswr) ...................................................................... 442 16.2.9 module stop control register (mstpcr) .......................................................... 445 16.3 operation .................................................................................................................. ........ 446 16.3.1 i 2 c bus data format ............................................................................................ 446 16.3.2 master transmit operation .................................................................................. 448 16.3.3 master receive operation.................................................................................... 450 16.3.4 slave receive operation...................................................................................... 452 16.3.5 slave transmit operation .................................................................................... 455 16.3.6 iric setting timing and scl control ................................................................ 457 16.3.7 automatic switching from formatless mode to i 2 c bus format ........................ 458 16.3.8 noise canceler ..................................................................................................... 459 16.3.9 sample flowcharts............................................................................................... 459 16.3.10 initialization of internal state .............................................................................. 463 16.4 usage notes ................................................................................................................ ...... 465 section 17 a/d converter ................................................................................................. 471 17.1 overview................................................................................................................... ........ 471 17.1.1 features................................................................................................................ 4 71 17.1.2 block diagram..................................................................................................... 472 17.1.3 pin configuration................................................................................................. 473 17.1.4 register configuration......................................................................................... 474 17.2 register descriptions ...................................................................................................... .. 474 17.2.1 a/d data registers a to d (addra to addrd).............................................. 474 17.2.2 a/d control/status register (adcsr) ............................................................... 475 17.2.3 a/d control register (adcr) ............................................................................ 478 17.2.4 module stop control register (mstpcr) .......................................................... 479 17.3 interface to bus master .................................................................................................... . 480 17.4 operation .................................................................................................................. ........ 481 17.4.1 single mode (scan = 0) .................................................................................... 481 17.4.2 scan mode (scan = 1)....................................................................................... 483 17.4.3 input sampling and a/d conversion time ......................................................... 485 17.4.4 external trigger input timing............................................................................. 486 17.5 interrupts ................................................................................................................. .......... 486 17.6 usage notes ................................................................................................................ ...... 487 section 18 ram .................................................................................................................. 493 18.1 overview................................................................................................................... ........ 493 18.1.1 block diagram..................................................................................................... 493 18.1.2 register configuration......................................................................................... 494
rev. 3.00 mar 17, 2006 page xxi of xxiv 18.2 system control register (syscr) ................................................................................... 494 18.3 operation .................................................................................................................. ........ 494 section 19 rom .................................................................................................................. 495 19.1 overview................................................................................................................... ........ 495 19.2 operation .................................................................................................................. ........ 495 19.3 writer mode (h8/3577, h8/3567, h8/3567u).................................................................. 496 19.3.1 writer mode setup............................................................................................... 496 19.3.2 socket adapter pin assignments and memory map ........................................... 497 19.4 prom programming ........................................................................................................ 502 19.4.1 programming and verification............................................................................. 502 19.4.2 notes on programming ........................................................................................ 507 19.4.3 reliability of programmed data .......................................................................... 508 section 20 clock pulse generator .................................................................................. 509 20.1 overview................................................................................................................... ........ 509 20.1.1 block diagram..................................................................................................... 509 20.1.2 register configuration......................................................................................... 509 20.2 register descriptions ...................................................................................................... .. 510 20.2.1 standby control register (sbycr) .................................................................... 510 20.3 oscillator................................................................................................................. .......... 511 20.3.1 connecting a crystal resonator........................................................................... 511 20.3.2 external clock input ............................................................................................ 513 20.4 duty adjustment circuit................................................................................................... 5 16 20.5 medium-speed clock divider .......................................................................................... 516 20.6 bus master clock selection circuit .................................................................................. 516 20.7 universal clock pulse generator [h8/3567 group version with on-chip usb] ........... 516 20.7.1 block diagram..................................................................................................... 516 20.7.2 registers............................................................................................................... 5 17 section 21 power-down state ......................................................................................... 521 21.1 overview................................................................................................................... ........ 521 21.1.1 register configuration......................................................................................... 524 21.2 register descriptions ...................................................................................................... .. 524 21.2.1 standby control register (sbycr) .................................................................... 524 21.2.2 module stop control register (mstpcr) .......................................................... 526 21.3 medium-speed mode........................................................................................................ 52 6 21.4 sleep mode ................................................................................................................. ...... 528 21.4.1 sleep mode .......................................................................................................... 528 21.4.2 clearing sleep mode............................................................................................ 528 21.5 module stop mode ........................................................................................................... 528
rev. 3.00 mar 17, 2006 page xxii of xxiv 21.5.1 module stop mode .............................................................................................. 528 21.5.2 usage note........................................................................................................... 529 21.6 software standby mode.................................................................................................... 53 0 21.6.1 software standby mode....................................................................................... 530 21.6.2 clearing software standby mode ........................................................................ 530 21.6.3 setting oscillation settling time after clearing software standby mode .......... 531 21.6.4 software standby mode application example.................................................... 531 21.6.5 usage note........................................................................................................... 532 21.7 hardware standby mode .................................................................................................. 533 21.7.1 hardware standby mode ..................................................................................... 533 21.7.2 hardware standby mode timing......................................................................... 534 section 22 electrical characteristics .............................................................................. 535 22.1 absolute maximum ratings ............................................................................................. 535 22.2 dc characteristics ......................................................................................................... ... 536 22.3 ac characteristics ......................................................................................................... ... 540 22.3.1 clock timing ....................................................................................................... 541 22.3.2 control signal timing ......................................................................................... 543 22.3.3 timing of on-chip supporting modules............................................................. 545 22.4 a/d conversion characteristics........................................................................................ 552 22.5 usb function pin characteristics..................................................................................... 553 22.6 usage notes ................................................................................................................ ...... 556 appendix a cpu instruction set .................................................................................... 559 a.1 instruction set list ........................................................................................................ .... 559 a.2 operation code map......................................................................................................... 5 67 a.3 number of states required for execution ........................................................................ 569 appendix b internal i/o registers ................................................................................. 575 b.1 addresses ................................................................................................................... ....... 575 b.2 register selection conditions ........................................................................................... 580 b.3 functions................................................................................................................... ........ 586 appendix c i/o port block diagrams ........................................................................... 673 c.1 port 1 block diagrams...................................................................................................... 6 73 c.2 port 2 block diagrams...................................................................................................... 6 78 c.3 port 3 block diagram ....................................................................................................... 6 82 c.4 port 4 block diagrams...................................................................................................... 6 83 c.5 port 5 block diagrams...................................................................................................... 6 88 c.6 port 6 block diagrams...................................................................................................... 6 91 c.7 port 7 block diagram ....................................................................................................... 6 96
rev. 3.00 mar 17, 2006 page xxiii of xxiv c.8 port 8 block diagrams...................................................................................................... 6 97 c.9 port d block diagram....................................................................................................... 6 99 appendix d pin states ....................................................................................................... 700 d.1 port states in each mode .................................................................................................. 70 0 appendix e timing of transition to and recovery from hardware standby mode ................................................................. 701 e.1 timing of transition to hardware standby mode ............................................................ 701 e.2 timing of recovery from hardware standby mode......................................................... 701 appendix f product code lineup .................................................................................. 702 appendix g package dimensions .................................................................................. 703
rev. 3.00 mar 17, 2006 page xxiv of xxiv
section 1 overview rev. 3.00 mar 17, 2006 page 1 of 706 rej09b0303-0300 section 1 overview 1.1 overview the h8/3577 group and h8/3567 group comprise single-chip microcomputers (mcus) built around the h8/300 cpu and equipped with on-chip supporting functions required for system configuration. on-chip supporting functions required for system configuration include rom and ram, a 16-bit free-running timer (frt), 8-bit timer (tmr), watchdog timer (wdt), two pwm timers (pwm and pwmx), serial communication interface (sci), i 2 c bus interface (iic), a/d converter (adc), and i/o ports. the h8/3577 group comprises 64-pin mcus, and the h8/3567 group 42-pin mcus, but the h8/3567 group also includes a 64-pin variation with on-chip universal serial bus (usb) hubs and function. the on-chip rom is either prom (ztat) or mask rom, with a capacity of 56 or 32 kbytes. there is only one operating mode: single-chip mode. the features of the h8/3577 group and h8/3567 group are shown in table 1.1.
section 1 overview rev. 3.00 mar 17, 2006 page 2 of 706 rej09b0303-0300 table 1.1 features item specifications cpu ? general-register architecture ? sixteen 8-bit general registers (also usable as eight 16-bit registers) ? high-speed operation suitable for realtime control ? maximum operating frequency: 20 mhz/5 v (hd6433564-10: 10 mhz/5 v) ? high-speed arithmetic operations 8/16-bit register-register add/subtract: 0.1 s (20-mhz operation) 8 8-bit register-register multiply: 0.7 s (20-mhz operation) 16 8-bit register-register divide: 0.7 s (20-mhz operation) ? instruction set suitable for high-speed operation ? 2-byte or 4-byte instruction length ? register-register basic operations ? memory-register data transfer by mov instruction ? instructions with special features ? multiply instructions (8 bits 8 bits) ? divide instructions (16 bits 8 bits) ? bit-accumulator instructions ? bit position specifiable by means of register indirect specification 16-bit free-running timer (frt), 1 channel ? one 16-bit free-running counter (usable for external event counting) ? two output compare outputs ? four input capture inputs (with buffer operation capability) 8-bit timer (tmr), 2 channels (tmr0, tmr1) each channel has: ? one 8-bit up-counter (usable for external event counting) ? two timer constant registers ? the two channels can be connected
section 1 overview rev. 3.00 mar 17, 2006 page 3 of 706 rej09b0303-0300 item specifications timer connection and 8-bit timer (tmr), 2 channels (tmrx, tmry) input/output and frt, tmr1, tmrx, tmry can be interconnected ? measurement of input signal or frequency-divided waveform pulse width and cycle (frt, tmr 1 ) ? output of waveform obtained by modification of input signal edge (frt, tmr 1 ) ? determination of input signal duty cycle (tmrx) ? output of waveform synchronized with input signal (frt, tmrx, tmry) ? automatic generation of cyclical waveform (frt, tmry) watchdog timer (wdt), 1 channel ? watchdog timer or interval timer function selectable 8-bit pwm timer (pwm) ? maximum of 16 (h8/3577 group) or 8 (h8/3567 group) outputs ? pulse duty cycle settable from 0 to 100% ? resolution: 1/256 ? 1.25 mhz maximum carrier frequency (20-mhz operation) 14-bit pwm timer (pwmx) ? maximum of 2 outputs ? resolution: 1/16384 ? 312.5 khz maximum carrier frequency (20-mhz operation) serial communi- cation interface (sci), 1 channel (sci0) ? asynchronous mode or synchronous mode selectable ? multiprocessor communication function a/d converter ? resolution: 10 bits ? input: 8 channels (h8/3577 group) 4 channels (h8/3567 group) ? high-speed conversion : 6.7 s minimum conversion time (20-mhz operation) ? single or scan mode selectable ? sample-and-hold function ? a/d conversion can be activated by external trigger or timer trigger i/o ports ? input/output pins: 43 (h8/3577 group, h8/3567 group models with on- chip usb) or 27 (h8/3567 group) ? input-only pins: 8 (h8/3577 group) or 4 (h8/3567 group)
section 1 overview rev. 3.00 mar 17, 2006 page 4 of 706 rej09b0303-0300 item specifications memory ? prom or mask rom ? high-speed static ram product code rom ram h8/3577, h8/3567, h8/3567u 56 kbytes 2 kbytes h8/3574, h8/3564, h8/3564u 32 kbytes 2 kbytes interrupt controller ? four external interrupt pins (nmi, irq 0 to irq 2 ) ? 26 internal interrupt sources (h8/3567u group: 30 sources) power-down state ? medium-speed mode ? sleep mode ? module stop mode ? software standby mode ? hardware standby mode clock pulse generator ? built-in duty correction circuit packages ? 64-pin plastic dip (dp-64s) ? 64-pin plastic qfp (fp-64a) ? 42-pin plastic dip (dp-42s) ? 44-pin plastic qfp (fp-44a) i 2 c bus interface (iic), 2 channels ? conforms to philips i 2 c bus interface standard ? single master mode/slave mode ? arbitration lost condition can be identified ? supports two slave addresses universal serial bus interface (usb) [h8/3567u, h8/3564u] ? comprises five downstream hubs and one function (four sets of downstream pins) ? three-endpoint monitor device class function ep0: for usb control ep1, ep2: for monitor control ? supports 12 mbps high-speed transfer mode ? built-in 12 mhz clock pulse generator and 4x multiplication circuit ? built-in bus driver/receiver (requires 3.3 v analog power supply)
section 1 overview rev. 3.00 mar 17, 2006 page 5 of 706 rej09b0303-0300 item specifications product lineup product code group mask rom version ztat version rom/ram (bytes) packages h8/3577 hd6433577 hd6473577 56 k/2 k dp-64s, fp-64a hd6433574 ? 32 k/2 k h8/3567 hd6433567 hd6473567 56 k/2 k dp-42s, fp-44a hd6433564-20 ? 32 k/2 k hd6433564-10 ? 32 k/2 k dp-42s hd6433567u hd6473567u 56 k/2 k dp-64s, fp-64a hd6433564u ? 32 k/2 k
section 1 overview rev. 3.00 mar 17, 2006 page 6 of 706 rej09b0303-0300 1.2 internal block diagrams figures 1.1 and 1.2 show internal block diagrams of the h8/3577 group and h8/3567 group. peripheral address bus p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 p2 7 /pw 15 / cblank p2 6 /pw 14 p2 5 /pw 13 p2 4 /pw 12 /scl 1 p2 3 /pw 11 /sda 1 p2 2 /pw 10 p2 1 /pw 9 p2 0 /pw 8 p1 7 /pw 7 p1 6 /pw 6 p1 5 /pw 5 p1 4 /pw 4 p1 3 /pw 3 p1 2 /pw 2 p1 1 /pw 1 / pwx 1 p1 0 /pw 0 / pwx 0 p5 2 /sck 0 /scl 0 p5 1 /rxd 0 p5 0 / txd 0 av cc av ss an 7 /p7 7 an 6 /p7 6 an 5 /p7 5 an 4 /p7 4 an 3 /p7 3 an 2 /p7 2 an 1 /p7 1 an 0 /p7 0 sda 0 /p4 7 irq 0 /p4 2 irq 1 /p4 1 adtrg / irq 2 /p4 0 hsynco/tmo 1 / tmox/p6 7 csynci/tmri 1 / ftob/p6 6 hsynci/tmci 1 / ftid/p6 5 clampo/tmo 0 / ftic/p6 4 vfbacki/tmri 0 / ftib/p6 3 vsynci/ tmiy/ftia/ p6 2 vsynco/ftoa/p6 1 hfbacki/tmci 0 /tmix/ ftci/p6 0 rom ram wdt0 8-bit timer stby res nmi h8/300 cpu interrupt controller internal address bus internal data bus peripheral data bus port 3 bus controller clock pulse generator port 2 port 1 port 5 port 7 port 6 port 4 figure 1.1 internal block diagram of h8/3577 group
section 1 overview rev. 3.00 mar 17, 2006 page 7 of 706 rej09b0303-0300 pd 7 /ds5d ? pd 6 /ds5d+ pd 5 /ds4d ? pd 4 /ds4d+ pd 3 /ds3d ? pd 2 /ds3d+ pd 1 /ds2d ? pd 0 /ds2d+ pc 7 / ocp 5 pc 6 / ocp 4 pc 5 / ocp 3 pc 4 / ocp 2 pc 3 / enp 5 pc 2 / enp 4 pc 1 / enp 3 pc 0 / enp 2 p1 7 /pw 7 /scl 1 p1 6 /pw 6 /sda 1 p1 5 /pw 5 / cblank p1 4 /pw 4 p1 3 /pw 3 p1 2 /pw 2 p1 1 /pw 1 /pwx 1 p1 0 /pw 0 /pwx 0 p5 2 /sck 0 /scl 0 p5 1 /rxd 0 p5 0 /txd 0 av cc av ss an 3 /p7 3 an 2 /p7 2 an 1 /p7 1 an 0 /p7 0 sda 0 /p4 7 irq 0 /p4 2 irq 1 /p4 1 adtrg / irq 2 /p4 0 hsynco/tmo 1 / tmox/p6 7 csynci/tmri 1 / ftob/p6 6 hsynci/tmci 1 / ftid/p6 5 clampo/tmo 0 / ftic/p6 4 vfbacki/tmri 0 / ftib/p6 3 vsynci/ tmiy/ftia/ p6 2 vsynco/ftoa/p6 1 hfbacki/tmci 0 /tmix/ ftci/p6 0 rom ram wdt0 8-bit timer test extal xtal stby res nmi h8/300 cpu interrupt controller internal address bus internal data bus peripheral data bus port d bus controller clock pulse generator usb drv cc drv ss extal12 xtal12 when on-chip usb is provided usd ? usd+ when on-chip usb is provided peripheral address bus port c port 1 port 5 port 7 port 6 port 4 figure 1.2 internal block diagram of h8/3567 group
section 1 overview rev. 3.00 mar 17, 2006 page 8 of 706 rej09b0303-0300 1.3 pin arrangement and functions 1.3.1 pin arrangement the pin arrangements of the h8/3577 group are shown in figures 1.3 and 1.4, and those of the h8/3567 group in figures 1.5 to 1.8. adtrg / irq 2 /p4 0 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 p1 0 /pw 0 /pwx 0 p1 1 /pw 1 /pwx 1 p1 2 /pw 2 p1 3 /pw 3 p1 4 /pw 4 p1 5 /pw 5 p1 6 /pw 6 p1 7 /pw 7 v ss p2 0 /pw 8 p2 1 /pw 9 p2 2 /pw 10 p2 3 /pw 11 /sda 1 p2 4 /pw 12 /scl 1 p2 5 /pw 13 p2 6 /pw 14 p2 7 /pw 15 /cblank v cc p6 6 /ftob/tmri 1 /csynci p6 5 /ftid/tmci 1 /hsynci p6 4 /ftic/tmo 0 /clampo p6 3 /ftib/tmri 0 /vfbacki p6 2 /ftia/tmiy/vsynci p6 7 /tmox/tmo 1 /hsynco irq 1 /p4 1 irq 0 /p4 2 p4 3 p4 4 p4 5 res nmi v cc /v cl stby v ss xtal extal md 1 md 0 av ss an 0 /p7 0 an 1 /p7 1 an 2 /p7 2 an 3 /p7 3 an 4 /p7 4 an 5 /p7 5 an 6 /p7 6 an 7 /p7 7 av cc hfbacki/tmix/tmci 0 /ftci/p6 0 vsynco/ftoa/p6 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 figure 1.3 h8/3577 group pin arrangement (dp-64s: top view)
section 1 overview rev. 3.00 mar 17, 2006 page 9 of 706 rej09b0303-0300 p7 3 /an 3 32 1 p2 7 /pw 15 /cblank p1 0 /pw 0 /pwx 0 p1 1 /pw 1 /pwx 1 p1 2 /pw 2 p1 3 /pw 3 p1 4 /pw 4 p1 5 /pw 5 p1 6 /pw 6 p1 7 /pw 7 v ss p2 0 /pw 8 p2 1 /pw 9 p2 2 /pw 10 p2 3 /pw 11 /sda 1 p2 4 /pw 12 /scl 1 p2 5 /pw 13 p2 6 /pw 14 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 txd 0 /p5 0 rxd 0 /p5 1 scl 0 /sck 0 /p5 2 res nmi v cc /v cl stby v ss xtal extal md 1 md 0 av ss an 0 /p7 0 an 1 /p7 1 an 2 /p7 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sda 0 /p4 7 irq 0 /p4 2 irq 1 /p4 1 adtrg / irq 2 /p4 0 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p6 0 /ftci/tmci 0 /tmix/hfbacki p6 1 /ftoa/vsynco p6 2 /ftia/tmiy/vsynci p6 3 /ftib/tmri 0 /vfbacki p6 4 /ftic/tmo 0 /clampo p6 5 /ftid/tmci 1 /hsynci p6 6 /ftob/tmri 1 /csynci p6 7 /tmox/tmo 1 /hsynco v cc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 p7 4 /an 4 p7 5 /an 5 p7 6 /an 6 p7 7 /an 7 av cc figure 1.4 h8/3577 group pin arrangement (fp-64a: top view)
section 1 overview rev. 3.00 mar 17, 2006 page 10 of 706 rej09b0303-0300 adtrg / irq 2 /p4 0 p4 5 p4 4 p4 3 p5 1 /rxd 0 p5 0 /txd 0 p1 0 /pw 0 /pwx 0 p1 1 /pw 1 /pwx 1 p1 2 /pw 2 p1 3 /pw 3 p1 4 /pw 4 v ss p1 5 /pw 5 /cblank p1 6 /pw 6 /sda 1 p1 7 /pw 7 /scl 1 p6 1 /ftoa/vsynco p6 2 /ftia/tmiy/vsynci p6 3 /ftib/tmri 0 /vfbacki p6 7 /tmox/tmo 1 /hsynco p6 6 /ftob/tmri 1 /csynci p6 5 /ftid/tmci 1 /hsynci p6 4 /ftic/tmo 0 /clampo irq 1 /p4 1 irq 0 /p4 2 res nmi v cc v cc /v cl stby xtal extal test v ss /av ss an 0 /p7 0 an 1 /p7 1 an 2 /p7 2 an 3 /p7 3 av cc hfbacki/tmix/tmci 0 /ftci/p6 0 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 figure 1.5 h8/3567 group pin arrangement (no usb; dp-42s: top view)
section 1 overview rev. 3.00 mar 17, 2006 page 11 of 706 rej09b0303-0300 p7 1 /an 1 1 p1 0 /pw 0 /pwx 0 p1 1 /pw 1 /pwx 1 p1 2 /pw 2 p1 3 /pw 3 p1 4 /pw 4 v ss p1 5 /pw 5 /cblank p1 6 /pw 6 /sda 1 p1 7 /pw 7 /scl 1 p6 1 /ftoa/vsynco p6 2 /ftia/tmiy/vsynci 33 32 31 30 29 28 27 26 25 24 23 scl 0 /sck 0 /p5 2 res nmi v cc v cc /v cl stby xtal extal test v ss /av ss an 0 /p7 0 2 3 4 5 6 7 8 9 10 11 sda 0 /p4 7 irq 0 /p4 2 irq 1 /p4 1 adtrg / irq 2 /p4 0 nc p4 5 p4 4 p4 3 rxd 0 /p5 1 txd 0 /p5 0 34 35 36 37 38 39 40 41 42 43 44 p6 4 /ftic/tmo 0 /clampo p6 5 /ftid/tmci 1 /hsynci p6 6 /ftob/tmri 1 /csynci p6 7 /tmox/tmo 1 /hsynco p6 3 /ftib/tmri 0 /vfbacki 22 21 20 19 18 17 16 15 14 13 12 p7 2 /an 2 p7 3 /an 3 av cc p6 0 /ftci/tmci 0 /tmix/hfbacki nc figure 1.6 h8/3567 group pin arrangement (no usb; fp-44a: top view)
section 1 overview rev. 3.00 mar 17, 2006 page 12 of 706 rej09b0303-0300 adtrg / irq 2 /p4 0 p4 5 p4 4 p4 3 p5 1 /rxd 0 p5 0 /txd 0 p1 0 /pw 0 /pwx 0 p1 1 /pw 1 /pwx 1 p1 2 /pw 2 p1 3 /pw 3 p1 4 /pw 4 v ss p1 5 /pw 5 /cblank p1 6 /pw 6 /sda 1 p1 7 /pw 7 /scl 1 p6 1 /ftoa/vsynco p6 2 /ftia/tmiy/vsynci p6 3 /ftib/tmri 0 /vfbacki p6 7 /tmox/tmo 1 /hsynco p6 6 /ftob/tmri 1 /csynci p6 5 /ftid/tmci 1 /hsynci p6 4 /ftic/tmo 0 /clampo p6 0 /ftci/tmci 0 /tmix/hfbacki extal12 xtal12 pc 7 / ocp 5 pc 6 / ocp 4 pc 4 / ocp 2 pc 3 / enp 5 pc 2 / enp 4 pc 1 / enp 3 pc 0 / enp 2 pc 5 / ocp 3 irq 1 /p4 1 irq 0 /p4 2 res nmi v cc v cl /v cc stby xtal extal test v ss /av ss an 0 /p7 0 an 1 /p7 1 an 2 /p7 2 an 3 /p7 3 av cc drv cc usd + ? + ? + ? + ? + ? figure 1.7 h8/3567 group pin arrangement (usb on-chip; dp-64s: top view)
section 1 overview rev. 3.00 mar 17, 2006 page 13 of 706 rej09b0303-0300 ds2d ? ocp 5 p1 3 /pw 3 p1 4 /pw 4 v ss p1 5 /pw 5 /cblank p1 6 /pw 6 /sda 1 p1 7 /pw 7 /scl 1 p6 1 /ftoa/vsynco p6 2 /ftia/tmiy/vsynci p6 3 /ftib/tmri 0 /vfbacki p6 7 /tmox/tmo 1 /hsynco p6 6 /ftob/tmri 1 /csynci p6 5 /ftid/tmci 1 /hsynci p6 4 /ftic/tmo 0 /clampo p6 0 /ftci/tmci 0 /tmix/hfbacki extal12 xtal12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v cc v cl /v cc stby xtal extal test v ss /av ss an 0 /p7 0 an 1 /p7 1 an 2 /p7 2 an 3 /p7 3 av cc drv cc usd + ? + res scl 0 /sck 0 /p5 2 sda 0 /p4 7 irq 0 /p4 2 irq 1 /p4 1 adtrg / irq 2 /p4 0 p4 5 p4 4 p4 3 rxd 0 /p5 1 txd 0 /p5 0 pwx 0 /pw 0 /p1 0 pwx 1 /pw 1 /p1 1 pw 2 /p1 2 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ds5d ? enp 2 pc 1 / enp 3 pc 2 / enp 4 pc 3 / enp 5 pc 4 / ocp 2 pc 5 / ocp 3 pc 6 / ocp 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ds3d + ? + ? + figure 1.8 h8/3567 group pin arrangement (usb on-chip; fp-64a: top view)
section 1 overview rev. 3.00 mar 17, 2006 page 14 of 706 rej09b0303-0300 1.3.2 list of pin functions h8/3577 group pin functions are listed in table 1.2, and h8/3567 group pin functions in tables 1.3 and 1.4. table 1.2 list of h8/3577 group pin functions pin no. pin name dp-64s fp-64a single-chip mode prom writer mode 157 p4 0 / irq 2 / adtrg ea 16 258 p4 1 / irq 1 ea 15 359 p4 2 / irq 0 pgm 460 p4 3 nc 561 p4 4 nc 662 p4 5 nc 763 p4 6 / res v pp 13 5 nmi ea 9 14 6 v cl , v cc (ztat) v cc 15 7 stby v ss 16 8 v ss v ss 17 9 xtal nc 18 10 extal nc 19 11 md 1 v ss 20 12 md 0 v ss 21 13 av ss v ss 22 14 p7 0 /an 0 nc 23 15 p7 1 /an 1 nc 24 16 p7 2 /an 2 nc 25 17 p7 3 /an 3 nc
section 1 overview rev. 3.00 mar 17, 2006 page 15 of 706 rej09b0303-0300 pin no. pin name dp-64s fp-64a single-chip mode prom writer mode 26 18 p7 4 /an 4 nc 27 19 p7 5 /an 5 nc 28 20 p7 6 /an 6 nc 29 21 p7 7 /an 7 nc 30 22 av cc v cc 31 23 p6 0 /ftci/tmci 0 /hfbacki/tmix nc 32 24 p6 1 /ftoa/vsynco nc 33 25 p6 2 /ftia/vsynci/tmiy nc 34 26 p6 3 /ftib/tmri 0 /vfbacki v cc 35 27 p6 4 /ftic/tmo 0 /clampo v cc 36 28 p6 5 /ftid/tmci 1 /hsynci nc 37 29 p6 6 /ftob/tmri 1 /csynci nc 38 30 p6 7 /tmo 1 /tmox/hsynco nc 39 31 v cc v cc 40 32 p2 7 /pw 15 /cblank ce 41 33 p2 6 /pw 14 ea 14 42 34 p2 5 /pw 13 ea 13 43 35 p2 4 /pw 12 /scl 1 ea 12 44 36 p2 3 /pw 11 /sda 1 ea 11 45 37 p2 2 /pw 10 ea 10 46 38 p2 1 /pw 9 oe 47 39 p2 0 /pw 8 ea 8 48 40 v ss v ss 49 41 p1 7 /pw 7 ea 7 50 42 p1 6 /pw 6 ea 6 51 43 p1 5 /pw 5 ea 5 52 44 p1 4 /pw 4 ea 4 53 45 p1 3 /pw 3 ea 3 54 46 p1 2 /pw 2 ea 2 55 47 p1 1 /pw 1 /pwx 1 ea 1
section 1 overview rev. 3.00 mar 17, 2006 page 16 of 706 rej09b0303-0300 pin no. pin name dp-64s fp-64a single-chip mode prom writer mode 56 48 p1 0 /pw 0 /pwx 0 ea 0 57 49 p3 0 eo 0 58 50 p3 1 eo 1 59 51 p3 2 eo 2 60 52 p3 3 eo 3 61 53 p3 4 eo 4 62 54 p3 5 eo 5 63 55 p3 6 eo 6 64 56 p3 7 eo 7
section 1 overview rev. 3.00 mar 17, 2006 page 17 of 706 rej09b0303-0300 table 1.3 list of h8/3567 group pin functions (no usb) pin no. pin name dp-42s fp-44a single-chip mode prom writer mode 140 p4 0 / irq 2 / adtrg ea 16 241 p4 1 / irq 1 ce 342 p4 2 / irq 0 pgm 443 p4 6 / res v pp 83 nmi ea 9 94 v cc v cc 10 5 v cl , v cc (ztat) v cc 11 6 stby v ss 12 7 xtal nc 13 8 extal nc 14 9 test v ss 15 10 av ss /v ss v ss 16 11 p7 0 /an 0 ea 12 17 12 p7 1 /an 1 ea 13 18 13 p7 2 /an 2 ea 14 19 14 p7 3 /an 3 ea 15 20 15 av cc v cc 21 16 p6 0 /ftci/tmci 0 /hfbacki/tmix eo 0 ? 17 nc nc 22 18 p6 4 /ftic/tmo 0 /clampo eo 4 23 19 p6 5 /ftid/tmci 1 /hsynci eo 5 24 20 p6 6 /ftob/tmri 1 /csynci eo 6 25 21 p6 7 /tmo 1 /tmox/hsynco eo 7 26 22 p6 3 /ftib/tmri 0 /vfbacki eo 3 27 23 p6 2 /ftia/vsynci/tmiy eo 2 28 24 p6 1 /ftoa/vsynco eo 1
section 1 overview rev. 3.00 mar 17, 2006 page 18 of 706 rej09b0303-0300 pin no. pin name dp-42s fp-44a single-chip mode prom writer mode 29 25 p1 7 /pw 7 /scl 1 ea 7 30 26 p1 6 /pw 6 /sda 1 ea 6 31 27 p1 5 /pw 5 /cblank ea 5 32 28 v ss v ss 33 29 p1 4 /pw 4 ea 4 34 30 p1 3 /pw 3 ea 3 35 31 p1 2 /pw 2 ea 2 36 32 p1 1 /pw 1 /pwx 1 ea 1 37 33 p1 0 /pw 0 /pwx 0 ea 0 38 34 p5 0 /txd 0 nc 39 35 p5 1 /rxd 0 nc 40 36 p4 3 ea 8 41 37 p4 4 oe 42 38 p4 5 ea 10 ? 39 nc nc
section 1 overview rev. 3.00 mar 17, 2006 page 19 of 706 rej09b0303-0300 table 1.4 list of h8/3567 group pin functions (usb on-chip) pin no. pin name dp-64s fp-64a single-chip mode prom writer mode 157 p4 0 / irq 2 / adtrg ea 16 258 p4 1 / irq 1 ce 359 p4 2 / irq 0 pgm 460 p4 6 / res v pp 864 nmi ea 9 91 v cc v cc 10 2 v cl , v cc (ztat) v cc 11 3 stby v ss 12 4 xtal nc 13 5 extal nc 14 6 test v ss 15 7 av ss /v ss v ss 16 8 p7 0 /an 0 ea 12 17 9 p7 1 /an 1 ea 13 18 10 p7 2 /an 2 ea 14 19 11 p7 3 /an 3 ea 15 20 12 av cc v cc 21 13 drv cc v cc 22 14 usd+ nc 23 15 usd ? nc 24 16 pd 0 /ds2d+ nc 25 17 pd 1 /ds2d ? nc 26 18 pd 2 /ds3d+ nc 27 19 pd 3 /ds3d ? nc 28 20 pd 4 /ds4d+ nc 29 21 pd 5 /ds4d ? nc
section 1 overview rev. 3.00 mar 17, 2006 page 20 of 706 rej09b0303-0300 pin no. pin name dp-64s fp-64a single-chip mode prom writer mode 30 22 pd 6 /ds5d+ nc 31 23 pd 7 /ds5d ? nc 32 24 drv ss v ss 33 25 pc 0 / enp 2 nc 34 26 pc 1 / enp 3 nc 35 27 pc 2 / enp 4 nc 36 28 pc 3 / enp 5 nc 37 29 pc 4 / ocp 2 nc 38 30 pc 5 / ocp 3 nc 39 31 pc 6 / ocp 4 nc 40 32 pc 7 / ocp 5 nc 41 33 xtal12 nc 42 34 extal12 nc 43 35 p6 0 /ftci/tmci 0 /hfbacki/tmix eo 0 44 36 p6 4 /ftic/tmo 0 /clampo eo 4 45 37 p6 5 /ftid/tmci 1 /hsynci eo 5 46 38 p6 6 /ftob/tmri 1 /csynci eo 6 47 39 p6 7 /tmo 1 /tmox/hsynco eo 7 48 40 p6 3 /ftib/tmri0/vfbacki eo 3 49 41 p6 2 /ftia/vsynci/tmiy eo 2 50 42 p6 1 /ftoa/vsynco eo 1 51 43 p1 7 /pw 7 /scl 1 ea 7 52 44 p1 6 /pw 6 /sda 1 ea 6 53 45 p1 5 /pw 5 /cblank ea 5 54 46 v ss v ss 55 47 p1 4 /pw 4 ea 4 56 48 p1 3 /pw 3 ea 3 57 49 p1 2 /pw 2 ea 2 58 50 p1 1 /pw 1 /pwx 1 ea 1 59 51 p1 0 /pw 0 /pwx 0 ea 0
section 1 overview rev. 3.00 mar 17, 2006 page 21 of 706 rej09b0303-0300 pin no. pin name dp-64s fp-64a single-chip mode prom writer mode 60 52 p5 0 /txd 0 nc 61 53 p5 1 /rxd 0 nc 62 54 p4 3 ea 8 63 55 p4 4 oe 64 56 p4 5 ea 10
section 1 overview rev. 3.00 mar 17, 2006 page 22 of 706 rej09b0303-0300 1.3.3 pin functions table 1.5 summarizes the functions of the h8/3577 group and h8/3567 group pins. table 1.5 pin functions pin no. h8/3577 group h8/3567 group (no usb) h8/3567 group (usb on-chip) type symbol dp- 64s fp- 64a dp- 42s fp- 44a dp- 64s fp- 64a i/o name and function power v cc 39 31 9 4 9 1 input power: for connection to the power supply (5 v). v cl /v cc 14 6 10 5 10 2 input internal step-up power: for connection to an external capacitor. in the ztat version, connect this pin to the power supply (5 v). v ss 16, 48 8, 40 32 28 15, 54 7, 46 input ground: for connection to the power supply (0 v). connect all v ss pins to the system power supply (0 v). clock xtal 17 9 12 7 12 4 input extal 18 10 13 8 13 5 input for connection of a crystal resonator or external clock input. for connection examples, see section 20, clock pulse generator. system clock: supplies the system clock to external devices. operating mode control md 1 md 0 19 20 11 12 ?? ?? input test ?? 14 9 14 6 mode pins: these pins set the operating mode. connect all three pins ? md 1 , md 0 , and t est ? to the power supply (5 v). system control res 12 4 7 2 7 63 input reset input: when this pin is driven low, the chip goes to the reset state. stby 15 7 11 6 11 3 input standby: when this pin is driven low, a transition is made to hardware standby mode.
section 1 overview rev. 3.00 mar 17, 2006 page 23 of 706 rej09b0303-0300 pin no. h8/3577 group h8/3567 group (no usb) h8/3567 group (usb on-chip) type symbol dp- 64s fp- 64a dp- 42s fp- 44a dp- 64s fp- 64a i/o name and function interrupts nmi 13 5 8 3 8 64 input nonmaskable interrupt: requests a nonmaskable interrupt. irq 0 to irq 2 3 to 1 59 to 57 3 to 1 42 to 40 3 to 1 59 to 57 input interrupt request 0 to 2: these pins request a maskable interrupt. 16-bit free- running timer (frt) ftci 31 23 21 16 43 35 input frt counter clock input: pin that inputs an external clock signal to the free- running counter (frc). ftoa 3224 2824 5042output frt output compare a output: the output compare a output pin. ftob 3729 2420 4638output frt output compare b output: the output compare b output pin. ftia 33 25 27 23 49 41 input frt input capture a input: the input capture a input pin. ftib 34 26 26 22 48 40 input frt input capture b input: the input capture b input pin. ftic 35 27 22 18 44 36 input frt input capture c input: the input capture c input pin. ftid 36 28 23 19 45 37 input frt input capture d input: the input capture d input pin. tmo 0 tmo 1 tmox 35 38 38 27 30 30 22 25 25 18 21 21 44 47 47 36 39 39 output compare-match output: compare-match output pins for tmr0, tmr1, and tmrx. 8-bit timer (tmr 0 , tmr 1 , tmrx, tmry) tmci 0 tmci 1 31 36 23 28 21 23 16 19 43 45 35 37 input counter external clock input: pins that input an external clock to the tmr0 and tmr1 counters. tmri 0 tmri 1 34 37 26 29 26 24 22 20 48 46 40 38 input counter external reset input: tmr0 and tmr1 counter reset input pins.
section 1 overview rev. 3.00 mar 17, 2006 page 24 of 706 rej09b0303-0300 pin no. h8/3577 group h8/3567 group (no usb) h8/3567 group (usb on-chip) type symbol dp- 64s fp- 64a dp- 42s fp- 44a dp- 64s fp- 64a i/o name and function 8-bit timer (tmr0, tmr1, tmrx, tmry) tmix tmiy 31 33 23 25 21 27 16 23 43 49 35 41 input counter external clock input/reset input: pins with a dual function of tmrx and tmry counter clock input and reset input. txd 0 9 1 38 34 60 52 output transmit data: data output pins. serial com- munication interface (sci0) rxd 0 10 2 39 35 61 53 input receive data: data input pins. sck 0 11 3 6 1 6 62 input/ output serial clock: clock input/output pins. the sck 0 output type is nmos push-pull. a/d converter an 7 to an 4 29 to 26 21 to 18 ?? ?? input analog 7 to 0: analog input pins. an 3 to an 0 25 to 22 17 to 14 19 to 16 14 to 11 19 to 16 11 to 8 input adtrg 1 57 1 40 1 57 input a/d conversion external trigger input: pin for input of an external trigger to start a/d conversion. av cc 30 22 20 15 20 12 input analog power: the a/d converter reference power supply pin. when the a/d converter is not used, connect this pin to the system power supply (+5 v). av ss 21 13 15 10 15 7 input analog ground: the a/d converter ground pin. connect this pin to the system power supply (0 v).
section 1 overview rev. 3.00 mar 17, 2006 page 25 of 706 rej09b0303-0300 pin no. h8/3577 group h8/3567 group (no usb) h8/3567 group (usb on-chip) type symbol dp- 64s fp- 64a dp- 42s fp- 44a dp- 64s fp- 64a i/o name and function pwm timer (pwm) pw 15 to pw 8 40 to 47 32 to 39 ?? ?? output pwm timer output: pwm timer pulse output pins. pw 7 to pw 0 49 to 56 41 to 48 29 to 31 33 to 37 25 to 27 29 to 33 51 to 53 55 to 59 43 to 45 47 to 51 14-bit pwm timer (pwmx) pwx 0 pwx 1 56 55 48 47 37 36 33 32 59 58 51 50 output pwmx timer output: pwm d/a pulse output pins. timer connection vsynci hsynci csynci vfbacki hfbacki 33 36 37 34 31 25 28 29 26 23 27 23 24 26 21 23 19 20 22 16 49 45 46 48 43 41 37 38 40 35 input timer connection input: timer connection synchronization signal input pins. vsynco hsynco clampo cblank 32 38 35 40 24 30 27 32 28 25 22 31 24 21 18 27 50 47 44 53 42 39 36 45 output timer connection output: timer connection synchronization signal output pins. i 2 c bus interface (iic) scl 0 scl 1 11 43 3 35 6 29 1 25 6 51 62 43 input/ output i 2 c clock input/output (channels 0 and 1): i 2 c clock input/output pins. these pins have a bus drive function. the scl 0 output type is nmos open-drain. sda 0 sda 1 8 44 64 36 5 30 44 26 5 52 61 44 input/ output i 2 c data input/output (channels 0 and 1): i 2 c data input/output pins. these pins have a bus drive function. the sda 0 output type is nmos open-drain.
section 1 overview rev. 3.00 mar 17, 2006 page 26 of 706 rej09b0303-0300 pin no. h8/3577 group h8/3567 group (no usb) h8/3567 group (usb on-chip) type symbol dp- 64s fp- 64a dp- 42s fp- 44a dp- 64s fp- 64a i/o name and function universal serial bus (usb) usd + usd ? ?? ?? 22 23 14 15 input/ output upstream data input/output: usb upstream data input/ output pins. ds2d + ds2d ? ds3d + ds3d ? ds4d + ds4d ? ds5d + ds5d ? ?? ?? 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 input/ output upstream data input/output 2 to 5: usb hub downstream data input/output pins. enp 2 to enp 5 ?? ?? 33 to 36 25 to 28 output power supply control ic power output enable signal output: output pins to usb port power supply control ic enable input ocp 2 to ocp 5 ?? ?? 37 to 40 29 to 32 input overcurrent detection signal input: input pins for overcurrent detection signal from usb port power supply control ic xtal12 ?? ?? 41 33 input extal12 ?? ?? 42 34 input usb clock input: for connection of a 12 mhz crystal resonator or external clock input. quadrupled to 48 mhz inside the chip. drv cc ?? ?? 21 13 input bus driver power: for connection of the bus driver/receiver power supply (3.3 v). drv ss ?? ?? 32 24 input bus driver ground: for connection of the bus driver/receiver power supply (0 v).
section 1 overview rev. 3.00 mar 17, 2006 page 27 of 706 rej09b0303-0300 pin no. h8/3577 group h8/3567 group (no usb) h8/3567 group (usb on-chip) type symbol dp- 64s fp- 64a dp- 42s fp- 44a dp- 64s fp- 64a i/o name and function i/o ports p1 7 to p1 0 49 to 56 41 to 48 29 to 31 33 to 37 25 to 27 29 to 33 51 to 53 55 to 59 43 to 45 47 to 51 input/ output port 1: eight input/output pins. the direction of each pin can be selected in the port 1 data direction register (p1ddr). p2 7 to p2 0 40 to 47 32 to 39 ?? ?? input/ output port 2: eight input/output pins. the direction of each pin can be selected in the port 2 data direction register (p2ddr). p3 7 to p3 0 64 to 57 56 to 49 ?? ?? input/ output port 3: eight input/output pins. the direction of each pin can be selected in the port 3 data direction register (p3ddr). p4 7 to p4 0 8 to 1 64 to 57 5, 4 42 to 40 3 to 1 44, 43 38 to 36 42 to 40 5, 4 64 to 62 3 to 1 61, 60 56 to 54 59 to 57 input/ output port 4: eight input/output pins. the direction of each pin (except p4 6 ) can be selected in the port 4 data direction register (p4ddr). p4 7 is an nmos push-pull output. p5 2 to p5 0 11 to 9 3 to 1 6 39 38 1 35 34 6 61 60 62 53 52 input/ output port 5: three input/output pins. the direction of each pin can be selected in the port 5 data direction register (p5ddr). p5 2 is an nmos push-pull output. p6 7 to p6 0 38 to 31 30 to 23 25 to 22 26 to 28 21 21 to 18 22 to 24 16 47 to 44 48 to 50 43 39 to 36 40 to 42 35 input/ output port 6: eight input/output pins. the direction of each pin can be selected in the port 6 data direction register (p6ddr). p7 7 to p7 4 29 to 26 21 to 18 ?? ?? input p7 3 to p7 0 25 to 22 17 to 14 19 to 16 14 to 11 19 to 16 11 to 8 port 7: eight (h8/3577 group) or four (h8/3567 group) input pins.
section 1 overview rev. 3.00 mar 17, 2006 page 28 of 706 rej09b0303-0300 pin no. h8/3577 group h8/3567 group (no usb) h8/3567 group (usb on-chip) type symbol dp- 64s fp- 64a dp- 42s fp- 44a dp- 64s fp- 64a i/o name and function i/o ports pc 7 to pc 0 ?? ?? 40 to 33 32 to 25 input/ output port c: eight input/output pins. the direction of each pin can be selected in the port c data direction register (pcddr). pd 7 to pd 0 ?? ?? 31 to 24 23 to 16 input/ output port d: eight input/output pins. the direction of each pin can be selected in the port d data direction register (pdddr). these pins are driven by drv cc (3.3 v).
section 2 cpu rev. 3.00 mar 17, 2006 page 29 of 706 rej09b0303-0300 section 2 cpu 2.1 overview the h8/300 cpu has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. its concise instruction set is designed for high-speed operation. 2.1.1 features features of the h8/300 cpu are listed below. ? general-register architecture sixteen 8-bit general registers, also usable as eight 16-bit general registers ? instruction set with 55 basic instructions, including: ? multiply and divide instructions ? powerful bit-manipulation instructions ? eight addressing modes ? register direct (rn) ? register indirect (@rn) ? register indirect with displacement (@(d:16, rn)) ? register indirect with post-increment or pre-decrement (@rn+/@?rn) ? absolute address (@aa:8/@aa:16) ? immediate (#xx:8/#xx:16) ? program-counter relative (@(d:8, pc)) ? memory indirect (@@aa:8) ? 64-kbyte address space ? high-speed operation ? all frequently used instructions are executed in two to four states ? high-speed arithmetic and logic operations 8- or 16-bit register-register add or subtract: 0.1 s (operating at = 20 mhz) 8 8-bit multiply: 0.7 s (operating at = 20 mhz) 16 8-bit divide: 0.7 s (operating at = 20 mhz) ? low-power operation modes sleep instruction for transfer to low-power operation
section 2 cpu rev. 3.00 mar 17, 2006 page 30 of 706 rej09b0303-0300 2.1.2 address space the h8/300 cpu supports an address space of up to 64 kbytes for storing program code and data. see section 3.3, address map, for details of the memory map. 2.1.3 register configuration figure 2.1 shows the register structure of the h8/300 cpu. there are two groups of registers: the general registers and control registers. 7070 15 0 pc r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l (sp) legend: sp: stack pointer pc: program counter ccr: condition code register carry flag overflow flag zero flag negative flag half-carry flag interrupt mask bit user bit user bit ccr i u h u n z v c general registers (rn) control registers (cr) 753210 64 figure 2.1 cpu registers
section 2 cpu rev. 3.00 mar 17, 2006 page 31 of 706 rej09b0303-0300 2.2 register descriptions 2.2.1 general registers all the general registers can be used as both data registers and address registers. when used as data registers, they can be accessed as 16-bit registers (r0 to r7), or the high bytes (r0h to r7h) and low bytes (r0l to r7l) can be accessed separately as 8-bit registers. when used as address registers, the general registers are accessed as 16-bit registers (r0 to r7). r7 also functions as the stack pointer (sp), used implicitly by hardware in exception processing and subroutine calls. when it functions as the stack pointer, as indicated in figure 2.2, sp (r7) points to the top of the stack. lower address side [h'0000] upper address side [h'ffff] unused area stack area sp (r7) figure 2.2 stack pointer 2.2.2 control registers the cpu control registers include a 16-bit program counter (pc) and an 8-bit condition code register (ccr). program counter (pc) this 16-bit register indicates the address of the next instruction the cpu will execute. all instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the pc is ignored (always regarded as 0).
section 2 cpu rev. 3.00 mar 17, 2006 page 32 of 706 rej09b0303-0300 condition code register (ccr) this 8-bit register contains internal status information, including the interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. these bits can be read and written by software (using the ldc, stc, andc, orc, and xorc instructions). the n, z, v, and c flags are used as branching conditions for conditional branching (bcc) instructions. bit 7?interrupt mask bit (i): when this bit is set to 1, interrupts are masked. this bit is set to 1 automatically at the start of exception handling. the interrupt mask bit may be read and written by software. for further details, see section 5, interrupt controller. bit 6?user bit (u): can be used freely by the user. bit 5?half-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. the h flag is used implicitly by the daa and das instructions. when the add.w, sub.w, or cmp.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. bit 4?user bit (u): can be used freely by the user. bit 3?negative flag (n): indicates the most significant bit (sign bit) of the result of an instruction. bit 2?zero flag (z): set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. bit 1?overflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0?carry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift/rotate carry the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave some or all of the flag bits unchanged.
section 2 cpu rev. 3.00 mar 17, 2006 page 33 of 706 rej09b0303-0300 refer to the h8/300 series programming manual for the action of each instruction on the flag bits. 2.2.3 initial register values in reset exception handling, the program counter (pc) is initialized by a vector address (h'0000) load, and the i bit in the ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (r7) is not initialized. the stack pointer should be initialized by software, by the first instruction executed after a reset. 2.3 data formats the h8/300 cpu can process 1-bit data, 4-bit (bcd) data, 8-bit (byte) data, and 16-bit (word) data. 1-bit data is handled by bit manipulation instructions, and is accessed by being specified as bit n (n = 0, 1, 2, ... 7) in the operand data (byte). byte data is handled by all arithmetic and logic instructions except adds and subs. word data is handled by the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions. with the daa and das decimal adjustment instructions, byte data is handled as two 4-bit bcd data units.
section 2 cpu rev. 3.00 mar 17, 2006 page 34 of 706 rej09b0303-0300 2.3.1 data formats in general registers data of all the sizes above can be stored in general registers as shown in figure 2.3. 7 6 5 4 3 2 1 0 don?t care data type register no. data format 70 1-bit data rnh 76543210 don?t care 70 1-bit data rnl msb lsb don?t care 70 byte data rnh byte data rnl word data rn 4-bit bcd data rnh 4-bit bcd data rnl legend: rnh: rnl: msb: lsb: upper byte of general register lower byte of general register most significant bit least significant bit msb lsb don?t care 70 msb lsb 15 0 upper digit lower digit don?t care 70 3 4 don?t care upper digit lower digit 70 3 4 figure 2.3 general register data formats
section 2 cpu rev. 3.00 mar 17, 2006 page 35 of 706 rej09b0303-0300 2.3.2 memory data formats figure 2.4 indicates the data formats in memory. for access by the h8/300l cpu, word data stored in memory must always begin at an even address. when word data beginning at an odd address is accessed, the least significant bit is regarded as 0, and the word data beginning at the preceding address is accessed. the same applies to instruction codes. data format 76543210 address data type 70 address n msb lsb msb lsb upper 8 bits lower 8 bits msb lsb ccr ccr * msb lsb msb lsb address n even address odd address even address odd address even address odd address 1-bit data byte data word data byte data (ccr) on stack word data on stack legend: ccr: condition code register note: * ignored on return figure 2.4 memory data formats when the stack is accessed using r7 as an address register, word access should always be performed. the ccr is stored as word data with the same value in the upper 8 bits and the lower 8 bits. on return, the lower 8 bits are ignored.
section 2 cpu rev. 3.00 mar 17, 2006 page 36 of 706 rej09b0303-0300 2.4 addressing modes 2.4.1 addressing modes the h8/300 cpu supports the eight addressing modes listed in table 2.1. each instruction uses a subset of these addressing modes. table 2.1 addressing modes no. address modes symbol 1 register direct rn 2 register indirect @rn 3 register indirect with displacement @(d:16, rn) 4 register indirect with post-increment register indirect with pre-decrement @rn+ @ ? rn 5 absolute address @aa:8 or @aa:16 6 immediate #xx:8 or #xx:16 7 program-counter relative @(d:8, pc) 8 memory indirect @@aa:8 1. register direct?rn: the register field of the instruction specifies an 8- or 16-bit general register containing the operand. only the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions have 16-bit operands. 2. register indirect?@rn: the register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. 3. register indirect with displacement?@(d:16, rn): the instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. this mode is used only in mov instructions. for the mov.w instruction, the resulting address must be even.
section 2 cpu rev. 3.00 mar 17, 2006 page 37 of 706 rej09b0303-0300 4. register indirect with post-increment or pre-decrement?@rn+ or @?rn: register indirect with post-increment ? @rn+ the @rn+ mode is used with mov instructions that load registers from memory. the register field of the instruction specifies a 16-bit general register containing the address of the operand. after the operand is accessed, the register is incremented by 1 for mov.b or 2 for mov.w, and the result of the addition is stored in the register. for mov.w, the original contents of the 16-bit general register must be even. register indirect with pre-decrement ? @ ? rn the @ ? rn mode is used with mov instructions that store register contents to memory. the register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. the register retains the decremented value. the size of the decrement is 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the register must be even. 5. absolute address?@aa:8 or @aa:16: the instruction specifies the absolute address of the operand in memory. the absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). the mov.b and bit manipulation instructions can use 8-bit absolute addresses. the mov.b, mov.w, jmp, and jsr instructions can use 16-bit absolute addresses. for an 8-bit absolute address, the upper 8 bits are assumed to be 1 (h'ff). the address range is h'ff00 to h'ffff (65280 to 65535). 6. immediate?#xx:8 or #xx:16: the second byte (#xx:8) or the third and fourth bytes (#xx:16) of the instruction code are used directly as the operand. only mov.w instructions can be used with #xx:16. the adds and subs instructions implicitly contain the value 1 or 2 as immediate data. some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. program-counter relative?@(d:8, pc): this mode is used in the bcc and bsr instructions. an 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address, and the pc contents to be added are the start address of the next instruction, so that the possible branching range is ? 126 to +128 bytes ( ? 63 to +64 words) from the branch instruction. the displacement should be an even number.
section 2 cpu rev. 3.00 mar 17, 2006 page 38 of 706 rej09b0303-0300 8. memory indirect?@@aa:8: this mode can be used by the jmp and jsr instructions. the second byte of the instruction code specifies an 8-bit absolute address. this specifies an operand in memory, and a branch is performed with the contents of this operand as the branch address. the upper 8 bits of the absolute address are assumed to be 0 (h'00), so the address range is from h'0000 to h'00ff (0 to 255). note that with the h8/300 series, the lower end of the address area is also used as a vector area. see section 4, exception handling, for details on the vector area. if an odd address is specified as a branch destination or as the operand address of a mov.w instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. see 2.3.2, memory data formats, for further information. 2.4.2 effective address calculation table 2.2 shows how effective addresses are calculated in each of the addressing modes. arithmetic and logic instructions use register direct addressing (1). the add.b, addx, subx, cmp.b, and, or, and xor instructions can also use immediate addressing (6). data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute addressing (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. the bset, bclr, bnot, and btst instructions can also use register direct addressing (1) to specify the bit position.
section 2 cpu rev. 3.00 mar 17, 2006 page 39 of 706 rej09b0303-0300 table 2.2 effective address calculation no. addressing mode and instruction format effective address calculation method effective address (ea) 1 register direct, rn operand is contents of registers indicated by rm/rn op rm rn 87 3 40 15 rm 30 rn 30 2 op rm 76 3 40 15 register indirect, @rn contents (16 bits) of register indicated by rm 0 15 0 15 3 register indirect with displacement, @(d:16, rn) op rm 76 3 40 15 disp 0 15 disp 0 15 contents (16 bits) of register indicated by rm 4 op rm 76 3 40 15 register indirect with post-increment, @rn+ op rm 76 3 40 15 register indirect with pre-decrement, @ ? rn incremented or decremented by 1 if operand is byte size, and by 2 if word size 0 15 1 or 2 0 15 0 15 1 or 2 0 15 contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm
section 2 cpu rev. 3.00 mar 17, 2006 page 40 of 706 rej09b0303-0300 no. addressing mode and instruction format effective address calculation method effective address (ea) 5 absolute address @aa:8 @aa:16 op 87 0 15 0 15 abs h'ff 87 0 15 0 15 abs op 6 op 0 15 imm #xx:16 op 87 0 15 imm immediate #xx:8 operand is 1- or 2-byte immediate data 7 op disp 70 15 program-counter relative @(d:8, pc) pc contents 0 15 0 15 8 sign extension disp
section 2 cpu rev. 3.00 mar 17, 2006 page 41 of 706 rej09b0303-0300 no. addressing mode and instruction format effective address calculation method effective address (ea) 8 memory indirect, @@aa:8 op 87 0 15 memory contents (16 bits) 0 15 abs h'00 87 0 15 abs legend: rm, rn: register field op: operation field disp: displacement imm: immediate data abs: absolute address
section 2 cpu rev. 3.00 mar 17, 2006 page 42 of 706 rej09b0303-0300 2.5 instruction set the h8/300 series can use a total of 55 instructions, which are grouped by function in table 2.3. table 2.3 instruction set function instructions number data transfer mov, push * 1 , pop * 1 1 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, daa, das, mulxu, divxu, cmp, neg 14 logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr 8 bit manipulation bset, bclr, bnot, btst, band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist 14 branch bcc * 2 , jmp, bsr, jsr, rts 5 system control rte, sleep, ldc, stc, andc, orc, xorc, nop 8 block data transfer (cannot be used in the h8/3577 group and h8/3567 group) eepmov 1 total: 55 notes: 1. push rn is equivalent to mov.w rn, @ ? sp. pop rn is equivalent to mov.w @sp+, rn. the same applies to machine language. 2. bcc is a conditional branch instruction.
section 2 cpu rev. 3.00 mar 17, 2006 page 43 of 706 rej09b0303-0300 tables 2.4 to 2.11 show the function of each instruction. the notation used is defined next. notation rd general register (destination) rs general register (source) rn general register (ead), destination operand (eas), source operand ccr condition code register n n (negative) flag of ccr z z (zero) flag of ccr v v (overflow) flag of ccr c c (carry) flag of ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction
section 2 cpu rev. 3.00 mar 17, 2006 page 44 of 706 rej09b0303-0300 2.5.1 data transfer instructions table 2.4 describes the data transfer instructions. figure 2.5 shows their object code formats. table 2.4 data transfer instructions instruction size * function mov b/w (eas) ? rn, and @rn+ addressing modes are available for word data. the @aa:8 addressing mode is available for byte data only. the @ ? r7 and @r7+ modes require a word-size specification. pop w @sp+ ? sp pushes general register onto the stack. equivalent to mov.w rn, @ ? sp. notes: * size: operand size b: byte w: word
section 2 cpu rev. 3.00 mar 17, 2006 page 45 of 706 rej09b0303-0300 15 0 87 op rm rn mov rm ? rm 15 0 87 op rn abs @aa:8 ? sp figure 2.5 data transfer instruction codes
section 2 cpu rev. 3.00 mar 17, 2006 page 46 of 706 rej09b0303-0300 2.5.2 arithmetic operations table 2.5 describes the arithmetic instructions. table 2.5 arithmetic instructions instruction size * function add sub b/w rd rs rs 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder cmp b/w rd ? rs, rd ? #imm compares data in a general register with data in another general register or with immediate data, and indicates the result in the ccr. word data can be compared only between two general registers. neg b 0 ? rd ? s complement (arithmetic complement) of data in a general register notes: * size: operand size b: byte w: word
section 2 cpu rev. 3.00 mar 17, 2006 page 47 of 706 rej09b0303-0300 2.5.3 logic operations table 2.6 describes the four instructions that perform logic operations. table 2.6 logic operation instructions instruction size * function and b rd ? s complement (logical complement) of general register contents notes: * size: operand size b: byte 2.5.4 shift operations table 2.7 describes the eight shift instructions. table 2.7 shift instructions instruction size * function shal shar b rd shift * size: operand size b: byte
section 2 cpu rev. 3.00 mar 17, 2006 page 48 of 706 rej09b0303-0300 figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. 15 0 87 op rm rn add, sub, cmp, addx, subx (rm) legend: op: rm, rn: imm: operation field register field immediate data 15 0 87 op rn adds, subs, inc, dec, daa, das, neg, not 15 0 87 op rn mulxu, divxu rm 15 0 87 rn imm add, addx, subx, cmp (#xx:8) op 15 0 87 op rn and, or, xor (rm) rm 15 0 87 rn imm and, or, xor (#xx:8) op 15 0 87 rn shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr op figure 2.6 arithmetic, logic, and shift instruction codes
section 2 cpu rev. 3.00 mar 17, 2006 page 49 of 706 rej09b0303-0300 2.5.5 bit manipulations table 2.8 describes the bit-manipulation instructions. figure 2.7 shows their object code formats. table 2.8 bit-manipulation instructions instruction size * function bset b 1 * size: operand size b: byte
section 2 cpu rev. 3.00 mar 17, 2006 page 50 of 706 rej09b0303-0300 instruction size * function bxor b c * size: operand size b: byte certain precautions are required in bit manipulation. see 2.8.1, notes on bit manipulation, for details.
section 2 cpu rev. 3.00 mar 17, 2006 page 51 of 706 rej09b0303-0300 15 0 87 op imm rn operand: bit no.: legend: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op rn bset, bclr, bnot, btst register direct (rn) immediate (#xx:3) operand: bit no.: register direct (rn) register direct (rm) rm 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm 15 0 87 op 0 operand: bit no.: register indirect (@rn) register direct (rm) rn 0 0 0 0 0 0 0 rm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op op 15 0 87 op operand: bit no.: absolute (@aa:8) register direct (rm) abs 0000 rm op 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) band, bor, bxor, bld, bst 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes
section 2 cpu rev. 3.00 mar 17, 2006 page 52 of 706 rej09b0303-0300 legend: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 87 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) biand, bior, bixor, bild, bist 15 0 87 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 87 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0000 imm op figure 2.7 bit manipulation instruction codes (cont)
section 2 cpu rev. 3.00 mar 17, 2006 page 53 of 706 rej09b0303-0300 2.5.6 branching instructions table 2.9 describes the branching instructions. figure 2.8 shows their object code formats. table 2.9 branching instructions instruction size function bcc ? branches to the designated address if condition cc is true. the branching conditions are given below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c ? branches unconditionally to a specified address bsr ? branches to a subroutine at a specified address jsr ? branches to a subroutine at a specified address rts ? returns from a subroutine
section 2 cpu rev. 3.00 mar 17, 2006 page 54 of 706 rej09b0303-0300 legend: op: cc: rm: disp: abs: operation field condition field register field displacement absolute address 15 0 87 op cc disp bcc 15 0 87 op rm 0 jmp (@rm) 000 15 0 87 op jmp (@aa:16) abs 15 0 87 op abs jmp (@@aa:8) 15 0 87 op disp bsr 15 0 87 op rm 0 jsr (@rm) 000 15 0 87 op jsr (@aa:16) abs 15 0 87 op abs jsr (@@aa:8) 15 0 87 op rts figure 2.8 branching instruction codes
section 2 cpu rev. 3.00 mar 17, 2006 page 55 of 706 rej09b0303-0300 2.5.7 system control instructions table 2.10 describes the system control instructions. figure 2.9 shows their object code formats. table 2.10 system control instructions instruction size * function rte ? returns from an exception-handling routine sleep ? causes a transition from active mode to a power-down mode. see section 21, power-down state, for details. ldc b rs ? pc + 2 * size: operand size b: byte
section 2 cpu rev. 3.00 mar 17, 2006 page 56 of 706 rej09b0303-0300 legend: op: rn: imm: operation field register field immediate data 15 0 87 op rte, sleep, nop 15 0 87 op rn ldc, stc (rn) 15 0 87 op imm andc, orc, xorc, ldc (#xx:8) figure 2.9 system control instruction codes
section 2 cpu rev. 3.00 mar 17, 2006 page 57 of 706 rej09b0303-0300 2.5.8 block data transfer instruction table 2.11 describes the block data transfer instruction. figure 2.10 shows its object code format. table 2.11 block data transfer instruction instruction size function eepmov (cannot be used in the h8/3577 group and h8/3567 group) ? if r4l ? 1 certain precautions are required in using the eepmov instruction. see 2.8.2, notes on use of the eepmov instruction, for details. legend: op: operation field 15 0 87 op op figure 2.10 block data transfer instruction code
section 2 cpu rev. 3.00 mar 17, 2006 page 58 of 706 rej09b0303-0300 2.6 basic operational timing cpu operation is synchronized by a system clock ( ). the period from a rising edge of to the next rising edge is called one state. a bus cycle consists of two states or three states. the cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 access to on-chip memory (ram, rom) access to on-chip memory takes place in two states. the data bus width is 16 bits, allowing access in byte or word size. figure 2.11 shows the on-chip memory access cycle. t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) figure 2.11 on-chip memory access cycle
section 2 cpu rev. 3.00 mar 17, 2006 page 59 of 706 rej09b0303-0300 2.6.2 access to on-chip peripheral modules on-chip peripheral modules are accessed in three states. the data bus width is either 8 or 16 bits, so access in both byte and word size is supported. there are two categories of on-chip peripheral modules: 8-bit and 16-bit. to access word data from an 8-bit module, two instructions must be used. the upper byte is accessed first, followed by the lower byte. accessing word data from a 16-bit module requires only one instruction. there are two types of registers: byte and word. the word register refers to registers were, as with a 16-bit counter, attempting to access the two bytes separately will cause problems. for word registers containing 8-bit modules, a circuit with a temporary register is available to allow normal access to the upper byte first, followed by the lower byte. note that word registers containing only 16-bit modules do not have such a circuit. therefore, only word access may be used with such registers. figure 2.12 shows the access timing for on-chip peripheral modules. bus cycle t 1 state t 2 state t 3 state figure 2.12 on-chip peripheral module access cycle
section 2 cpu rev. 3.00 mar 17, 2006 page 60 of 706 rej09b0303-0300 2.7 cpu states 2.7.1 overview there are four cpu states: the reset state, program execution state, program halt state, and exception-handling state. the program execution state includes active (high-speed or medium- speed) mode. in the program halt state there are a sleep (high-speed or medium-speed) mode and standby mode. these states are shown in figure 2.13. figure 2.14 shows the state transitions. cpu state reset state program execution state program halt state exception- handling state active (high speed) mode sleep (high-speed) mode standby mode low-power modes the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the system clock a state in which some or all of the chip functions are stopped to conserve power a transient state in which the cpu changes the processing flow due to a reset or an interrupt the cpu is initialized note: see section 21, power-down modes, for details on the modes and their transitions. sleep (medium-speed) mode active (medium speed) mode figure 2.13 cpu operation states
section 2 cpu rev. 3.00 mar 17, 2006 page 61 of 706 rej09b0303-0300 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source reset occurs exception- handling request exception- handling complete reset occurs figure 2.14 state transitions 2.7.2 reset state the cpu is initialized in the reset state. 2.7.3 program execution state in the program execution state the cpu executes program instructions in sequence. there are two active modes (high-speed and medium-speed) when the cpu is in the program execution state. 2.7.4 program halt state in the program halt state there are three modes: two sleep modes (high speed and medium speed) and standby mode. see section 21, power-down modes for details on these modes. 2.7.5 exception-handling state the exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the cpu changes its normal processing flow. in exception handling caused by an interrupt, sp (r7) is referenced and the pc and ccr values are saved on the stack. for details on interrupt handling, see section 4, exception handling.
section 2 cpu rev. 3.00 mar 17, 2006 page 62 of 706 rej09b0303-0300 2.8 application notes 2.8.1 notes on bit manipulation the bset, bclr, bnot, bst, and bist instructions read one byte of data, modify the data, then write the data byte again. special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an i/o port. order of operation operation 1 read read byte data at the designated address 2 modify modify a designated bit in the read data 3 write write the altered byte data to the designated address as in the examples above, p1 7 and p1 6 are input pins, with a low-level signal input at p1 7 and a high-level signal at p1 6 . the remaining pins, p1 5 to p1 0 , are output pins that output low-level signals. in this example, the bclr instruction is used to change pin p1 0 to an input port. [a: prior to executing bclr] p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level ddr 00111111 dr 10000000 [b: bclr instruction executed] bclr #0 , p1ddr the bclr instruction is executed designating ddr.
section 2 cpu rev. 3.00 mar 17, 2006 page 63 of 706 rej09b0303-0300 [c: after executing bclr] p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 input/output output output output output output output output input pin state low level high level low level low level low level low level low level low level ddr 1 111111 0 dr 10000000 [d: explanation of how bclr operates] when the bclr instruction is executed, first the cpu reads p1ddr. since p1ddr is a write- only register, the cpu reads an undefined value. in this example, the ddr value is h'ff, but the data read by the cpu is undefined; it is taken to be h'ff. next, the cpu clears bit 0 in the read data to 0, changing the data to h'fe. finally, this value (h'fe) is written to ddr and bclr instruction execution ends. as a result of this operation, bit 0 in ddr becomes 0, making p1 0 an input port. however, bits 7 and 6 in ddr change to 1, so that p1 7 and p1 6 change from input pins to output pins.
section 2 cpu rev. 3.00 mar 17, 2006 page 64 of 706 rej09b0303-0300 2.8.2 notes on use of the eepmov instruction (cannot be used in the h8/3577 group and h8/3567 group) ? the eepmov instruction is a block data transfer instruction. it moves the number of bytes specified by r4l from the address specified by r5 to the address specified by r6. ? when setting r4l and r6, make sure that the final destination address (r6 + r4l) does not exceed h'ffff. the value in r6 must not change from h'ffff to h'0000 during execution of the instruction. h'ffff not allowed
section 3 mcu operating modes rev. 3.00 mar 17, 2006 page 65 of 706 rej09b0303-0300 section 3 mcu operating modes 3.1 overview 3.1.1 operating mode selection the h8/3577 group and h8/3567 group operate in the single-chip mode. the operating mode is specified by the setting of the mode pins (md 1 to md 0 or test ). table 3.1 lists the mcu operating modes. table 3.1 mcu operating mode selection ? h8/3577 group mcu operating mode md 1 md 0 description mode 0 0 0 ? mode 1 0 1 ? mode 2 1 0 ? mode 3 1 1 single-chip mode h8/3567 group mcu operating mode test test test test description mode 0 0 ? mode 3 1 single-chip mode the h8/3577 group and h8/3567 group support the use of mode 3 only. therefore, the mode pins must be set for mode 3 as indicated above. 3.1.2 register configuration the h8/3577 group and h8/3567 group have a mode control register (mdcr) that indicates the inputs at the mode pins (md 1 and md 0 or test ), a system control register (syscr) that controls the operation of the mcu, and a serial timer control register (stcr) that controls the operation of the supporting modules. table 3.2 summarizes these registers.
section 3 mcu operating modes rev. 3.00 mar 17, 2006 page 66 of 706 rej09b0303-0300 table 3.2 mcu registers name abbreviation r/w initial value address * mode control register mdcr r h'03 h'ffc5 system control register syscr r/w h'09 h'ffc4 serial timer control register stcr r/w h'00 h'ffc3 note: * lower 16 bits of the address. 3.2 register descriptions 3.2.1 mode control register (mdcr) bit 76543210 expe ?????mds1mds0 initial value 0 * 000001 * 1 * read/write r ????? r r note: * determined by pins md 1 and md 0 or test pin. mdcr is an 8-bit read-only register that indicates the operating mode setting and the current operating mode of the mcu. bit 7?expanded mode enable (expe): this bit should not be set to 1. bits 6 to 2?reserved: these bits cannot be modified and are always read as 0. bits 1 and 0?mode select 1 and 0 (mds1, mds0): these bits indicate the input levels at pins md 1 , md 0 , and test (the current operating mode). bits mds1 and mds0 correspond to md 1 and md 0 (h8/3577 group). alternately, bits mds1 and mds0 both correspond to the test pin (h8/3567 group). mds1 and mds0 are read-only bits?they cannot be written to. the mode pin (md 1 , md 0 , and test ) input levels are latched into these bits when mdcr is read.
section 3 mcu operating modes rev. 3.00 mar 17, 2006 page 67 of 706 rej09b0303-0300 3.2.2 system control register (syscr) bit 76543210 cs2e iose intm1 intm0 xrst nmieg hie rame initial value00001001 read/write r/w r/w r r r r/w r/w r/w syscr is a readable/writable register that performs selection of system pin functions, reset source monitoring, interrupt control mode selection, nmi detected edge selection, supporting module register access control, and ram address space control. only bits 7, 6, 3, 1, and 0 are described here. for a detailed description of these bits, refer also to the description of the relevant modules (watchdog timer, ram, etc.). for information on bits 5, 4, and 2, see section 5.2.1, system control register (syscr). syscr is initialized to h'09 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?chip select 2 enable (cs2e): this bit should not be set to 1. bit 6?ios enable (iose): this bit should not be set to 1. bit 3?external reset (xrst): indicates the reset source. when the watchdog timer is used, a reset can be generated by watchdog timer overflow as well as by external reset input. xrst is a read-only bit. it is set to 1 by an external reset and cleared to 0 by watchdog timer overflow. bit 3 xrst description 0 a reset is generated by watchdog timer overflow 1 a reset is generated by an external reset (initial value) bit 1?host interface enable (hie): enables or disables cpu access to on-chip supporting function registers. this bit controls cpu access to the 8-bit timer (channel x and y) data registers and control registers (tcrx/tcry, tcsrx/tcsry, ticrr/tcoray, ticrf/tcorby, tcntx/tcnty, tcorc/tisr, tcorax, and tcorbx), and the timer connection control registers (tconri, tconro, tconrs, and sedgr).
section 3 mcu operating modes rev. 3.00 mar 17, 2006 page 68 of 706 rej09b0303-0300 bit 1 hie description 0 in areas h'fff0 to h'fff7 and h'fffc to h'ffff, cpu access to 8-bit timer (channels x and y) data registers and control registers, and timer connection control registers, is permitted (initial value) 1 in areas h'fff0 to h'fff7 and h'fffc to h'ffff, cpu access to 8-bit timer (channels x and y) data registers and control registers, and timer connection control registers, is not permitted bit 0?ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset state is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) 3.2.3 serial timer control register (stcr) bit 76543210 ? iicx1 iicx0 iice ? usbe icks1 icks0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w stcr is an 8-bit readable/writable register that controls register access, the iic operating mode, selects the tcnt input clock and controls usb. for details of functions other than register access control, see the descriptions of the relevant modules. if a module controlled by stcr is not used, do not write 1 to the corresponding bit. stcr is initialized to h'00 by a reset and in hardware standby mode. bit 7?reserved: do not write 1 to this bit. bits 6 and 5?i 2 c control (iicx1, iicx0): these bits control the operation of the i 2 c bus interface. for details, see section 16, i 2 c bus interface. bit 4?i 2 c master enable (iice): controls cpu access to the i 2 c bus interface data registers and control registers (iccr, icsr, icdr/sarx, and icmr/sar), the pwmx data registers and
section 3 mcu operating modes rev. 3.00 mar 17, 2006 page 69 of 706 rej09b0303-0300 control registers (dadrah/dacr, dadral, dadrbh/dacnth, and dadrbl/dacntl), and the sci control registers (smr, brr, and scmr). bit 4 iice description 0 addresses h'ffd8 and h'ffd9, and h'ffde and h'ffdf, are used for sci0 control register access (initial value) 1 addresses h'ff88 and h'ff89, and h'ff8e and h'ff8f, are used for iic1 data register and control register access addresses h'ffa0 and h'ffa1, and h'ffa6 and h'ffa7, are used for pwmx data register and control register access addresses h'ffd8 and h'ffd9, and h'ffde and h'ffdf, are used for iic0 data register and control register access bit 3?reserved: do not write 1 to this bit. bit 2?usb enable (usbe): this bit controls cpu access to the usb data register and control register. bit 2 usbe description 0 prohibition of the above register access (initial value) 1 permission of the above register access bits 1 and 0?internal clock source select 1 and 0 (icks1, icks0): these bits, together with bits cks2 to cks0 in tcr, select the clock to be input to tcnt. for details, see section 12, 8-bit timers. 3.3 address map address maps are shown in figure 3.1 and figure 3.2. the on-chip rom capacity is 56 kbytes (h8/3577, h8/3567, h8/3567u) or 32 kbytes (h8/3574, h8/3564, h8/3564u). do not try access to reserved areas and the addresses where no memory and no i/o register exists.
section 3 mcu operating modes rev. 3.00 mar 17, 2006 page 70 of 706 rej09b0303-0300 h'dfff h'0000 h'efff h'f000 h'f7ff h'f800 h'e080 on-chip ram reserved area h'e880 on-chip rom internal i/o register 2 internal i/o register 1 reserved area on-chip ram (128 bytes) h'feff h'ffff h'fe50 h'fe4f h'ff7f h'ff80 h'ff00 internal i/o register 3 (h8/3567u only) figure 3.1 h8/3577, h8/3567, and h8/3567u address map
section 3 mcu operating modes rev. 3.00 mar 17, 2006 page 71 of 706 rej09b0303-0300 h'dfff h'7fff h'0000 h'efff h'f000 h'f7ff h'f800 h'e080 on-chip ram reserved area reserved area reserved area h'e880 on-chip rom internal i/o register 2 internal i/o register 1 on-chip ram (128 bytes) h'feff h'ffff h'fe50 h'fe4f h'ff7f h'ff80 h'ff00 internal i/o register 3 (h8/3564u only) figure 3.2 h8/3574, h8/3564, and h8/3564u address map
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section 4 exception handling rev. 3.00 mar 17, 2006 page 73 of 706 rej09b0303-0300 section 4 exception handling 4.1 overview 4.1.1 exception handling types and priority as table 4.1 indicates, exception handling may be caused by a reset, or interrupt. exception handling is prioritized as shown in table 4.1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. table 4.1 exception types and priority priority exception type start of exception handling high reset starts immediately after a low-to-high transition at the res pin, or when the watchdog timer overflows. low interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. * note: * interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on completion of reset exception handling. 4.1.2 exception handling operation exceptions originate from various sources. trap instructions and interrupts are handled as follows: 1. the program counter (pc) and condition-code register ( ccr) are pushed onto the stack. 2. the interrupt mask bits are updated. 3. a vector address corresponding to the exception source is generated, and program execution starts from that address. for a reset exception, steps 2 and 3 above are carried out.
section 4 exception handling rev. 3.00 mar 17, 2006 page 74 of 706 rej09b0303-0300 4.1.3 exception sources and vector table the exception sources are classified as shown in figure 4.1. different vector addresses are assigned to different exception sources. table 4.2 lists the exception sources and their vector addresses. exception sources reset interrupts external interrupts: nmi, irq2 to irq0 internal interrupts: interrupt sources in on-chip supporting modules figure 4.1 exception sources table 4.2 exception vector table exception source vector number vector address * reset 0 h'0000 to h'0001 reserved for system use 1 h'0002 to h'0003 2 h'0004 to h'0005 3 h'0006 to h'0007 external interrupt nmi 4 h'0008 to h'0009 irq0 5 h'000a to h'000b irq1 6 h'000c to h'000d irq2 7 h'000e to h'000f reserved 8 h'0010 to h'0011 9 h'0012 to h'0013 10 h'0014 to h'0015 11 h'0016 to h'0017 12 h'0018 to h'0019 internal interrupt * 13 ? 53 h'001a to h'001b ? h'006a to h'006b note: * for details on internal interrupt vectors, see section 5.3.3, interrupt exception vector table.
section 4 exception handling rev. 3.00 mar 17, 2006 page 75 of 706 rej09b0303-0300 4.2 reset 4.2.1 overview a reset has the highest exception priority. when the res pin goes low, all processing halts and the mcu enters the reset state. a reset initializes the internal state of the cpu and the registers of on-chip supporting modules. reset exception handling begins when the res pin changes from low to high. mcus can also be reset by overflow of the watchdog timer. for details, see section 14, watchdog timer. 4.2.2 reset sequence the mcu enters the reset state when the res pin goes low. to ensure that the chip is reset, hold the res pin low for at least 20 ms when powering on. to reset the chip during operation, hold the res pin low for at least 20 states. for pin states in a reset, see appendix d.1, port states in each processing state. when the res pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: 1. the internal state of the cpu and the registers of the on-chip supporting modules are initialized, and the i bit is set to 1 in ccr. 2. the reset exception vector address is read and transferred to the pc, and program execution starts from the address indicated by the pc. figure 4.2 shows an example of the reset sequence.
section 4 exception handling rev. 3.00 mar 17, 2006 page 76 of 706 rej09b0303-0300 internal address bus internal read signal internal write signal internal data bus (1) (3) vector fetch internal processing fetch of first program instruction high (1) reset exception vector address ((1) = h'0000) (2) start address (contents of reset exception vector address) (3) start address ((3) = (2)) (4) first program instruction (2) (4) res figure 4.2 reset sequence 4.2.3 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.w #xx:16, sp).
section 4 exception handling rev. 3.00 mar 17, 2006 page 77 of 706 rej09b0303-0300 4.3 interrupts interrupt exception handling can be requested by four external sources (nmi and irq2 to irq0), and internal sources in the on-chip supporting modules. figure 4.3 shows the interrupt sources and the number of interrupts of each type. the on-chip supporting modules that can request interrupts include the watchdog timer (wdt), 16-bit free-running timer (frt), 8-bit timer (tmr), serial communication interface (sci), a/d converter (adc), i 2 c bus interface (iic). each interrupt source has a separate vector address. nmi is the highest-priority interrupt. interrupts are controlled by the interrupt controller. for details on interrupts, see section 5, interrupt controller. interrupts external interrupts internal interrupts nmi (1) irq2 to irq0 (3) wdt * (1) frt (7) tmr (10) sci (4) adc (1) iic (3) usb (4) numbers in parentheses are the numbers of interrupt sources. * when the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. notes: figure 4.3 interrupt sources and number of interrupts
section 4 exception handling rev. 3.00 mar 17, 2006 page 78 of 706 rej09b0303-0300 4.4 stack status after exception handling figure 4.4 shows the stack after completion of interrupt exception handling. sp ccr ccr * pc (16 bits) interrupt control mode 0 note: * ignored on return. figure 4.4 stack status after exception handling
section 4 exception handling rev. 3.00 mar 17, 2006 page 79 of 706 rej09b0303-0300 4.5 note on stack handling in word access, the least significant bit of the address is always assumed to be 0. the stack is always accessed by word access. care should be taken to keep an even value in the stack pointer (general register r7). use the push and pop (or mov.w rn, @?sp and mov.w @sp+, rn) instructions to push and pop registers on the stack. setting the stack pointer to an odd value can cause programs to crash. figure 4.5 shows an example of damage caused when the stack pointer contains an odd address. pc h sp pc l h'fecd h'fecf h'fecc bsr instruction mov.b r1l, @?r7 pc is improperly stored beyond top of stack h'fecf set in sp pc h is lost pc h : pc l : r1 l : sp: upper byte of program counter lower byte of program counter general register stack pointer sp r1 l sp pc l figure 4.5 example of damage caused by setting an odd address in r7
section 4 exception handling rev. 3.00 mar 17, 2006 page 80 of 706 rej09b0303-0300
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 81 of 706 rej09b0303-0300 section 5 interrupt controller 5.1 overview 5.1.1 features the mcus control interrupts by means of an interrupt controller. the interrupt controller has the following features: ? independent vector addresses ? all interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. ? four external interrupt pins ? nmi is the highest-priority interrupt, and is accepted at all times. a rising or falling edge at the nmi pin can be selected for the nmi interrupt. ? falling edge, rising edge, or both edge detection, or level sensing, at pins irq 2 to irq 0 can be selected for interrupts irq2 to irq0.
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 82 of 706 rej09b0303-0300 5.1.2 block diagram a block diagram of the interrupt controller is shown in figure 5.1. syscr nmi input irq input internal interrupt requests wovi to iici1 usb-related interrupts nmieg nmi input unit irq input unit isr iscr ier interrupt controller priority determination interrupt request vector number i ccr cpu irq sense control register irq enable register irq status register system control register legend: iscr: ier: isr: syscr: figure 5.1 block diagram of interrupt controller
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 83 of 706 rej09b0303-0300 5.1.3 pin configuration table 5.1 summarizes the pins of the interrupt controller. table 5.1 interrupt controller pins name symbol i/o function nonmaskable interrupt nmi input nonmaskable external interrupt; rising or falling edge can be selected external interrupt requests 2 to 0 irq 2 to irq 0 input maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected 5.1.4 register configuration table 5.2 summarizes the registers of the interrupt controller. table 5.2 interrupt controller registers name abbreviation r/w initial value address system control register syscr r/w h'09 h'ffc4 irq sense control register h iscrh r/w h'00 h'feec irq sense control register l iscrl r/w h'00 h'feed irq enable register ier r/w h'f8 h'ffc2 irq status register isr r/(w) * h'00 h'feeb note: * only 0 can be written, for flag clearing.
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 84 of 706 rej09b0303-0300 5.2 register descriptions 5.2.1 system control register (syscr) bit 76543210 cs2e iose intm1 intm0 xrst nmieg hie rame initial value00001001 read/write r/w r/w r r r r/w r/w r/w syscr is an 8-bit readable/writable register, bit 2 of which selects the detected edge for nmi. only bits 5, 4, and 2 are described here; for details on the other bits, see section 3.2.2, system control register (syscr). syscr is initialized to h'09 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 5 and 4?interrupt control mode 1 and 0 (intm1, intm0): the intm1 and 0 bits must not be set to 1. bit 5 bit 4 interrupt intm1 intm0 control mode description 0 0 0 interrupts are controlled by i bit (initial value) 1 1 cannot be used in h8/3577 group and h8/3567 group 1 0 2 cannot be used in h8/3577 group and h8/3567 group 1 3 cannot be used in h8/3577 group and h8/3567 group bit 2?nmi edge select (nmieg): selects the input edge for the nmi pin. bit 2 nmieg description 0 interrupt request generated at falling edge of nmi input (initial value) 1 interrupt request generated at rising edge of nmi input
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 85 of 706 rej09b0303-0300 5.2.2 irq enable register (ier) bit 76543210 ?????irq2eirq1eirq0e initial value11111000 read/write r rrrrr/wr/wr/w ier is a register that controls enabling and disabling of interrupt requests irq2 to irq0. ier is initialized to h'f8 by a reset and in hardware standby mode. bits 7 to 3?reserved: these bits cannot be modified and are always read as 1. bits 2 to 0?irq2 to irq0 enable (irq2e to irq0e): these bits select whether irq2 to irq0 are enabled or disabled. bit n irqne description 0 irqn interrupt disabled (initial value) 1 irqn interrupt enabled note: n = 2 to 0
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 86 of 706 rej09b0303-0300 5.2.3 irq sense control registers h and l (iscrh, iscrl) ? iscrh bit 151413121110 9 8 ???????? initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w ? iscrl bit 76543210 ? ? irq2scb irq2sca irq1scb irq1sca irq0scb irq0sca initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w iscrh and iscrl are 8-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins irq 2 to irq 0 . each of the iscr registers is initialized to h'00 by a reset and in hardware standby mode. iscrh bits 7 to 0, iscrl bits 7 and 6?reserved: do not write 1 to this bit. iscrl bits 5 to 0?irq2 sense control a and b (irq2sca, irq2scb) to irq0 sense control a and b (irq0sca, irq0scb) iscrl bits 5 to 0 irq2scb to irq0scb irq2sca to irq0sca description 0 0 interrupt request generated at irq 2 to irq 0 input low level (initial value) 1 interrupt request generated at falling edge of irq 2 to irq 0 input 1 0 interrupt request generated at rising edge of irq 2 to irq 0 input 1 interrupt request generated at both falling and rising edges of irq 2 to irq 0 input
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 87 of 706 rej09b0303-0300 5.2.4 irq status register (isr) bit 76543210 ?????irq2firq1firq0f initial value00000000 read/write r rrrrr/(w) * r/(w) * r/(w) * note: * only 0 can be written, to clear the flag. isr is an 8-bit readable/writable register that indicates the status of irq2 to irq0 interrupt requests. isr is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 3?reserved bits 2 to 0?irq2 to irq0 flags (irq2f to irq0f): these bits indicate the status of irq2 to irq0 interrupt requests. bit n irqnf description 0 [clearing conditions] (initial value) ? cleared by reading irqnf when set to 1, then writing 0 in irqnf ? when interrupt exception handling is executed when low-level detection is set (irqnscb = irqnsca = 0) and irqn input is high ? when irqn interrupt exception handling is executed when falling, rising, or both- edge detection is set (irqnscb = 1 or irqnsca = 1) 1 [setting conditions] ? when irqn input goes low when low-level detection is set (irqnscb = irqnsca = 0) ? when a falling edge occurs in irqn input when falling edge detection is set (irqnscb = 0, irqnsca = 1) ? when a rising edge occurs in irqn input when rising edge detection is set (irqnscb = 1, irqnsca = 0) ? when a falling or rising edge occurs in irqn input when both-edge detection is set (irqnscb = irqnsca = 1) note: n = 2 to 0
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 88 of 706 rej09b0303-0300 5.3 interrupt sources interrupt sources comprise external interrupts (nmi and irq2 to irq0) and internal interrupts. 5.3.1 external interrupts there are four external interrupt sources: nmi, and irq 2 to irq 0 . nmi, and irq2 to irq0 can be used to restore the h8/3577 group and h8/3567 group chip from software standby mode. nmi interrupt: nmi is the highest-priority interrupt, and is always accepted by the cpu regardless of the interrupt control mode and the status of the cpu interrupt mask bits. the nmieg bit in syscr can be used to select whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. the vector number for nmi interrupt exception handling is 4. irq2 to irq0 interrupts: interrupts irq2 to irq0 are requested by an input signal at pins irq 2 to irq 0 . interrupts irq2 to irq0 have the following features: ? using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins irq 2 to irq 0 . ? enabling or disabling of interrupt requests irq2 to irq0 can be selected with ier. ? the status of interrupt requests irq2 to irq0 is indicated in isr. isr flags can be cleared to 0 by software. a block diagram of interrupts irq2 to irq0 is shown in figure 5.2. irqn interrupt request irqne irqnf s r q clear signal edge/level detection circuit irqnsca, irqnscb irqn input note: n: 2 to 0 figure 5.2 block diagram of interrupts irq2 to irq0
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 89 of 706 rej09b0303-0300 figure 5.3 shows the timing of irqnf setting. irqn input pin irqnf figure 5.3 timing of irqnf setting the vector numbers for irq2 to irq0 interrupt exception handling are 7 to 5. detection of irq2 to irq0 interrupts does not depend on whether the relevant pin has been set for input or output. therefore, when a pin is used as an external interrupt input pin, do not clear the corresponding ddr bit to 0 and use the pin as an i/o pin for another function. as interrupt request flags irq2f to irq0f are set when the setting condition is met, regardless of the ier setting, only the necessary flags should be referenced. 5.3.2 internal interrupts there are 26 sources (30 sources in the version with an on-chip usb) for internal interrupts from on-chip supporting modules. for each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. if any one of these is set to 1, an interrupt request is issued to the interrupt controller. 5.3.3 interrupt exception vector table table 5.3 shows interrupt exception handling sources, vector addresses, and interrupt priorities. for default priorities, the lower the vector number, the higher the priority. priorities within a module are fixed as shown in table 5.3.
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 90 of 706 rej09b0303-0300 table 5.3 interrupt exception handling sources, vector addresses, and interrupt priorities interrupt source origin of interrupt source vector number vector address priority nmi external pin 4 h'0008 high irq0 5 h'000a irq1 6 h'000c irq2 7 h'000e reserved ? 8 to 12 h'0010 to h'0018 wovi0 (interval timer) watchdog timer 0 13 h'001a adi (a/d conversion end) a/d 14 h'001c icia (input capture a) icib (input capture b) icic (input capture c) icid (input capture d) ocia (output compare a) ocib (output compare b) fovi (overflow) free-running timer 15 16 17 18 19 20 21 h'001e h'0020 h'0022 h'0024 h'0026 h'0028 h'002a cmia0 (compare-match a) cmib0 (compare-match b) ovi0 (overflow) 8-bit timer channel 0 22 23 24 h'002c h'002e h'0030 cmia1 (compare-match a) cmib1 (compare-match b) ovi1 (overflow) 8-bit timer channel 1 25 26 27 h'0032 h'0034 h'0036 low
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 91 of 706 rej09b0303-0300 interrupt source origin of interrupt source vector number vector address priority cmiay (compare-match a) cmiby (compare-match b) oviy (overflow) icix (input capture x) 8-bit timer channels y, x 28 29 30 31 h'0038 h'003a h'003c h'003e high reserved ? 32 to 35 h'0040 to h'0046 eri0 (receive error 0) rxi0 (reception completed 0) txi0 (transmit data empty 0) tei0 (transmission end 0) sci channel 0 36 37 38 39 h'0048 h'004a h'004c h'004e reserved ? 40 to 43 h'0050 to h'0056 iici0 (1-byte transmission/ reception completed) ddcswi (format switch) iic channel 0 44 45 h'0058 h'005a iici1 (1-byte transmission/ reception completed) iic channel 1 46 h'005c reserved ? 47 to 49 h'005e to h'0062 usbia usbib usbic usbid usb 50 51 52 53 h'0064 h'0066 h'0068 h'006a low
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 92 of 706 rej09b0303-0300 5.4 interrupt operation 5.4.1 interrupt operation nmi interrupts are accepted at all times except in the reset state and the hardware standby state. in the case of irq interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. clearing an enable bit to 0 disables the corresponding interrupt request. interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. table 5.4 shows the interrupt control modes. table 5.4 interrupt control modes syscr interrupt control mode intm1 intm0 interrupt mask bits description 0 0 0 i interrupt mask control is performed by the i bit figure 5.4 shows a block diagram of the priority decision circuit. i default priority determination vector number interrupt acceptance control interrupt source figure 5.4 block diagram of interrupt control operation
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 93 of 706 rej09b0303-0300 interrupt acceptance control: in interrupt control mode 0, interrupt acceptance control is performed by means of the i bit in ccr. table 5.5 shows the interrupts selected in each interrupt control mode. table 5.5 interrupts selected in each interrupt control mode interrupt mask bits interrupt control mode i selected interrupts 0 0 all interrupts 1 nmi interrupts default priority determination: the priority is determined for the selected interrupt, and a vector number is generated. interrupt sources with a lower priority than the accepted interrupt source are held pending. table 5.6 shows operations and control signal functions in each interrupt control mode. table 5.6 operations and control signal functions in each interrupt control mode setting interrupt acceptance control interrupt control mode intm1 intm0 i determination 00 0o im o legend: o: interrupt operation control performed im: used as interrupt mask bit
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 94 of 706 rej09b0303-0300 5.4.2 interrupt control mode 0 enabling and disabling of irq interrupts and on-chip supporting module interrupts can be set by means of the i bit in the cpu?s ccr. interrupts are enabled when the i bit is cleared to 0, and disabled when set to 1. figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. if a number of interrupt requests are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.3 is selected. 3. the i bit is then referenced. if the i bit is cleared to 0, the interrupt request is accepted. if the i bit is set to 1, only an nmi interrupt is accepted, and other interrupt requests are held pending. 4. when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. 5. the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. next, the i bit in ccr is set to 1. this disables all interrupts except nmi. 7. a vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 95 of 706 rej09b0303-0300 program execution state interrupt generated? nmi? irq0? irq1? iici1 * ? i = 0? save pc and ccr i figure 5.5 flowchart of procedure up to interrupt acceptance
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 96 of 706 rej09b0303-0300 5.4.3 interrupt exception handling sequence figure 5.6 shows the interrupt exception handling sequence. (10) (9) (1) (4) (2) (1) (5) (6) (8) (9) interrupt handling routine instruction prefetch vector fetch stack instruction prefetch interrupt acceptance interrupt level determination wait for end of instruction interrupt request signal internal address bus internal read signal internal write signal internal data bus figure 5.6 interrupt exception handling
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 97 of 706 rej09b0303-0300 5.4.4 interrupt response times table 5.7 shows interrupt response times ? the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. table 5.7 interrupt response times number of states no. item normal mode 1 interrupt priority determination * 1 3 2 number of wait states until executing instruction ends * 2 1 to 13 3 pc, ccr stack save 4 4 vector fetch 2 5 instruction fetch * 3 4 6 internal processing * 4 4 total 18 to 30 notes: 1. two states in case of internal interrupt. 2. refers to mulxs and divxs instructions. except eepmov instruction. 3. prefetch after interrupt acceptance and interrupt handling routine prefetch. 4. internal processing after interrupt acceptance and internal processing after vector fetch.
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 98 of 706 rej09b0303-0300 5.5 usage notes 5.5.1 contention between interrupt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. in other words, when an interrupt enable bit is cleared to 0 by an instruction such as bclr or mov, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. the same also applies when an interrupt source flag is cleared to 0. figure 5.7 shows an example in which the cmiea bit in 8-bit timer register tcr is cleared to 0. internal address bus internal write signal figure 5.7 contention between interrupt generation and disabling the above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 99 of 706 rej09b0303-0300 5.5.2 instructions that disable interrupts instructions that disable interrupts are ldc, andc, orc, and xorc. after any of these instructions is executed, all interrupts, including nmi, are disabled and the next instruction is always executed. when the i bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 interrupts during execution of eepmov instruction with the eepmov instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the move is completed. the eepmov instruction cannot be used in the h8/3577 group and h8/3567 group.
section 5 interrupt controller rev. 3.00 mar 17, 2006 page 100 of 706 rej09b0303-0300
section 6 bus controller rev. 3.00 mar 17, 2006 page 101 of 706 rej09b0303-0300 section 6 bus controller 6.1 overview as the h8/3577 group and h8/3567 group do not have external expansion functions, they do not incorporate a bus controller function. however, from the viewpoint of maintaining software compatibility with similar products, care must be taken not to set inappropriate values in the bus controller related control registers. 6.2 register descriptions 6.2.1 bus control register (bcr) bit 76543210 icis1 icis0 brstrm brsts1 brsts0 ? ios1 ios0 initial value11010111 read/write r/w r/w r r/w r r/w r/w r/w bits 7 and 6?idle cycle insert 1 and 0 (icis1, icis0): do not write 0 to these bits. bit 5?burst rom enable (brstrm): do not write 1 to this bit. bit 4?burst cycle select 1 (brsts1): do not write 0 to this bit. bit 3?burst cycle select 0 (brsts0): do not write 1 to this bit. bit 2?reserved: do not write 0 to this bit. bits 1 and 0?ios select 1 and 0 (ios1, ios0): do not write 0 to these bits.
section 6 bus controller rev. 3.00 mar 17, 2006 page 102 of 706 rej09b0303-0300 6.2.2 wait state control register (wscr) bit 76543210 rams ram0 abw ast wms1 wms0 wc1 wc0 initial value00110011 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 7?ram select (rams)/bit 6?ram area setting (ram0): reserved bits. bit 5?bus width control (abw): do not write 0 to this bit. bit 4?access state control (ast): do not write 0 to this bit. bits 3 and 2?wait mode select 1 and 0 (wms1, wms0): do not write 1 to these bits. bits 1 and 0?wait count 1 and 0 (wc1, wc0): do not write 0 to these bits.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 103 of 706 rej09b0303-0300 section 7 universal serial bus interface (usb) it is built in the h8/3567u and h8/3564u group and not in the h8/3577, h8/3574, h8/3567 and h8/3564 group. 7.1 overview the h8/3567u and h8/3564u have an on-chip universal serial bus (usb) comprising hubs and a function. the universal serial bus is an interface for personal computer peripherals whose standardization is being promoted by a core group of companies, including intel corporation. the usb is provided with a number of device classes to handle the great variety of personal computer peripheral devices. the usb in the h8/3567u and h8/3564u are targeted at the hub device class and hid (human interface device) class (mainly a monitor device class). 7.1.1 features ? compound device conforming to usb standard * ? apart from initial settings and power-down mode settings, usb hubs decode and execute hub class commands automatically, independently of cpu operations ? usb function decodes and executes standard commands device class commands are decoded and executed by the cpu (firmware creation required) ? five downstream hubs and one function ? one down stream is connected internally to the usb function ? internal downstream disconnection function (only power-down mode usb hubs operable) ? four sets of downstream external pins ? automatic control of downstream port external power supply control ic (individual port control) ? three-endpoint monitor device class function ? ep0: usb control endpoint (dedicated to control transfer) ? ep1, ep2: monitor control endpoints (dedicated to interrupt transfer) ? ep0i, ep0o, and ep2 can use a maximum 16-byte fifo (maximum packet size of 8 bytes), and ep1 can use a maximum 32-byte fifo (maximum packet size of 16 bytes) ? supports 12 mbps high-speed transfer mode ? built-in 12 mhz clock pulse generator and frequency division/multiplication circuit ? built-in bus driver/receiver ? driven by drv ss /drv cc (3.3 v)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 104 of 706 rej09b0303-0300 note: * the usb function conforms to usb standard 1.1 and the usb hub to usb standard 1.0. 7.1.2 block diagram figure 7.1 shows a block diagram of the usb. internal data bus bus i/f interrupt i/f registers usb function core usb hub core bus driver/ receiver fifo fifo control module data bus fvsr2 fvsr1 fvsr0i fvsr0o epszr1 64 bytes clock selection address bus data bus pll internal interrupts ds2d + ds2d ? ds3d + ds3d ? ds4d + ds4d ? ds5d + ds5d ? enp 2 , enp 3 enp 4 , enp 5 ocp 2 , ocp 3 ocp 4 , ocp 5 usd + usd ? drv cc drv ss bus driver/ receiver ptter usbier usbifr tsfr tffr usbcsr0 epstlr epdir eprstr devrsmr intselr0 intselr1 hoccr usbcr upllcr uprtcr utestr0 utestr1 utestr2 (xtal12, extal12) connec- tion selection usb operating clock legend: epdr2: endpoint data register 2 epdr1: endpoint data register 1 epdr0i: endpoint data register 0i epdr0o: endpoint data register 0o fvsr2: fifo valid size register 2 fvsr1: fifo valid size register 1 fvsr0i: fifo valid size register 0i fvsr0o: fifo valid size register 0o epszr1: endpoint size register 1 ptter: packet transmit enable register usbier: usb interrupt enable register usbifr: usb interrupt flag register tsfr: transfer success flag register tffr: transfer fail flag register usbcsr0: usb control/status register 0 epstlr: endpoint stall register epdir: endpoint direction register eprstr: endpoint reset register devrsmr: device resume register intselr0: interrupt source select register 0 intselr1: interrupt source select register 1 hoccr: hub overcurrent control register usbcr: usb control register upllcr: usb pll control register uprtcr: usb port control register utestr0: usb test register 0 utestr1: usb test register 1 utestr2: usb test register 2 usd+: upstream data + pin usd?: upstream data ? pin ds2d+: downstream 2 data + pin ds2d?: downstream 2 data ? pin ds3d+: downstream 3 data + pin ds3d?: downstream 3 data ? pin ds4d+: downstream 4 data + pin ds4d?: downstream 4 data ? pin ds5d+: downstream 5 data + pin ds5d?: downstream 5 data ? pin xtal12: usb clock oscillator pin extal12: usb clock oscillator pin drv cc : bus driver power supply pin drv ss : bus driver ground pin ocp 2 : overcurrent detection pin 2 ocp 3 : overcurrent detection pin 3 ocp 4 : overcurrent detection pin 4 ocp 5 : overcurrent detection pin 5 enp 2 : power supply output enable pin 2 enp 3 : power supply output enable pin 3 enp 4 : power supply output enable pin 4 enp 5 : power supply output enable pin 5 connec- tion selection power supply control ic control epdr2 epdr1 epdr0i epdr0o figure 7.1 block diagram of usb
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 105 of 706 rej09b0303-0300 7.1.3 pin configuration table 7.1 shows the pins used by the usb. table 7.1 usb pins name abbre- viation i/o function upstream data + pin usd+ input/output usb hub/function data input/output upstream data ? pin usd? input/output downstream 2 data + pin ds2d+ input/output usb hub repeater input/output (port 2) downstream 2 data ? pin ds2d? input/output downstream 3 data + pin ds3d+ input/output usb hub repeater input/output (port 3) downstream 3 data ? pin ds3d? input/output downstream 4 data + pin ds4d+ input/output usb hub repeater input/output (port 4) downstream 4 data ? pin ds4d? input/output downstream 5 data + pin ds5d+ input/output usb hub repeater input/output (port 5) downstream 5 data ? pin ds5d? input/output overcurrent detection pins 2 to 5 ocp 2 to ocp 5 input power supply control ic overcurrent detection signal input power supply output enable control pins 2 to 5 enp 2 to enp 5 output power supply control ic power output enable signal output usb clock oscillator pin xtal12 input 12 mhz crystal oscillation usb clock oscillator pin extal12 input bus driver power supply pin drv cc input bus driver/receiver, port d power supply bus driver ground pin drv ss input bus driver/receiver, port d ground 7.1.4 register configuration the usb register configuration is shown in table 7.2. registers relating to usb hub initialization and status display are usbcr, usbcsr0, hoccr, and upllcr, as well as some bits in the test registers; the other registers relate to the usb function. when usbcr, usbcsr0, hoccr, and upllcr are all in the initial state, the usb module is completely disabled, and ports c and d function as i/o ports. when accessing a usb register, the usbe bit in stcr must be set to 1.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 106 of 706 rej09b0303-0300 table 7.2 usb registers name abbreviation r/w initial value address endpoint data register 2 epdr2 r or w * 1 h'00 h'fde1 fifo valid size register 2 fvsr2 r h'0010 h'fde2 endpoint size register 1 epszr1 r/w h'44 h'fde4 endpoint data register 1 epdr1 w h'00 h'fde5 fifo valid size register 1 fvsr1 r h'0010 h'fde6 endpoint data register 0o epdr0o r h'00 h'fde9 fifo valid size register 0o fvsr0o r h'0000 h'fdea endpoint data register 0i epdr0i w h'00 h'fded fifo valid size register 0i fvsr0i r h'0010 h'fdee packet transmit enable register ptter r/(w) * 2 h'00 h'fdf0 usb interrupt enable register usbier r/w h'00 h'fdf1 usb interrupt flag register usbifr r/(w) * 3 h'00 h'fdf2 transfer success flag register tsfr r/(w) * 3 h'00 h'fdf3 transfer fail flag register tffr r/(w) * 3 h'00 h'fdf4 usb control/status register 0 usbcsr0 r/w h'00 h'fdf5 endpoint stall register epstlr r/w h'00 h'fdf6 endpoint direction register epdir r/w h'fc h'fdf7 endpoint reset register eprstr r/(w) * 2 h'00 h'fdf8 device resume register devrsmr r/(w) * 2 h'00 h'fdf9 interrupt source select register 0 intselr0 r/w h'00 h'fdfa interrupt source select register 1 intselr1 r/w h'00 h'fdfb hub overcurrent control register hoccr r/w h'00 h'fdfc usb control register usbcr r/w h'7f h'fdfd usb pll control register upllcr r/w h'01 h'fdfe usb port control register uprtcr r/w h'00 h'fdc0 usb test register 0 utestr0 r/w h'00 h'fdc1 usb test register 1 utestr1 r/w h'00 h'fdc2 usb test register 2 utestr2 r/w h'ff h'fdff other test registers ? ? ? h'fdc3 to h'fde0
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 107 of 706 rej09b0303-0300 name abbreviation r/w initial value address serial timer control register stcr r/w h'00 h'ffc3 module stop control register mstpcrh mstpcrl r/w r/w h'3f h'ff h'ff86 h'ff87 notes: 1. write-only or read-only depending on the transfer direction set in the endpoint direction register. 2. only 1 can be written. 3. only 0 can be written after reading 1 to clear the flags. 7.2 register descriptions in the usb protocol, the host transmits a token to initiate a single data transfer (a transaction). a transaction consists of a token packet, data packet, and handshake packet. the token packet contains the address endpoint of the transfer target device and the transfer type, the data packet contains data, and the handshake packet contains information relating to transfer setup/non-setup. in data transfer from the host to a slave, the host transmits an out token or setup token, followed by data (an out or setup transaction). in data transfer from a slave to the host, the host transmits an in token and waits for data from the slave (an in transaction). in the following descriptions, these host-based in and out operations may be referred to as ?input? and ?output.? also, items relating to host input transfer may be designated ?in? (in transaction, in-fifo, ep0in, etc.), while items relating to host output transfer are designated ?out? (out transaction, out-fifo, ep0out, etc.). where an explicit expression such as ?transmitted by the host? or ?received by the host? is not used, the terms ?transmission? and ?reception? refer to transmission and reception from the standpoint of the usb module and slave cpu. 7.2.1 usb data fifo the fifo, together with epdr, functions as an intermediary role in data transfer between the h8 cpu (slave) and the usb function. the usb function uses the fifo to execute data transfer to and from the usb host (host). the h8/3567u and h8/3564u have an on-chip 64-byte fifo. this fifo is divided into four 16- byte fifos, used for endpoint 0 host input transfer and host output transfer (control transfer), endpoint 1 host input transfer (interrupt transfer), and endpoint 2 host input transfer or host output transfer. if endpoint 2 is not used, a 32-byte length can be selected for the endpoint 1 fifo. the maximum data packet size is set at half the number of fifo bytes.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 108 of 706 rej09b0303-0300 in host input transfer, all the data to be transmitted from the slave is written to the fifo before slave transmission is started. in host output transfer, the slave reads all the data from the fifo after host output transfer is completed. 7.2.2 endpoint size register 1 (epszr1) bit 76543210 ep1sz3 ep1sz2 ep1sz1 ep1sz0 ep2sz3 ep2sz2 ep2sz1 ep2sz0 initial value01000100 read/write r/w r/w r/w r/w r/w r/w r/w r/w epszr1 specifies the number of fifo bytes used for each usb function endpoint 1 and 2 host input transfer/host output transfer. the number of bytes in the endpoint 0 fifo is fixed at 16. both host input (ep0in) and host output (ep0out) can be selected for endpoint 0, host input for endpoint 1, and host input and host output for endpoint 2. with the h8/3567u and h8/3564u, when endpoints 1 and 2 are both used, set a 16-byte size for the respective fifos. when only endpoint 1 is used, set a 16- or 32-byte size. if the 32-byte size is selected, set 0 as the endpoint 2 fifo size. epszr1 is initialized to h'44 by a system reset or a function soft reset. epszr1 bits 7 to 4 ep1 fifo size epszr1 bits 3 to 0 ep2 fifo size bit 7 bit 3 bit 6 bit 2 bit 5 bit 1 bit 4 bit 0 sz3 sz2 sz1 sz0 operating mode 0000fifo size = 0 bytes (settable for ep2 only) 1 setting prohibited 1 0 setting prohibited 1 setting prohibited 100fifo size = 16 bytes (initial value) 1 fifo size = 32 bytes (settable for ep1 only) 1 0 setting prohibited 1 setting prohibited 1 ???setting prohibited
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 109 of 706 rej09b0303-0300 7.2.3 endpoint data registers 0i, 0o, 1, 2 (epdr0i, epdr0o, epdr1, epdr2) bit 76543210 d7 d6 d5 d4 d3 d2 d1 d0 initial value 00000000 epdr0iwwwwwwww read/ epdr0o r r r r r r r r write epdr1wwwwwwww epdr2 r or w * r or w * r or w * r or w * r or w * r or w * r or w * r or w * note: * write-only or read-only depending on the transfer direction set in the endpoint direction register. the epdr registers play an intermediary role in data transfer between the cpu and fifo for each host input transfer/host output transfer involving the respective usb function endpoints. epdr0i and epdr1 are used for host input transfer, and so are write-only registers; if read, the contents of the read data are not guaranteed. epdr0o is used for host output transfer, and so is a read-only register; it cannot be written to. for epdr2, the endpoint transfer direction is determined by the endpoint direction register. epdr2 is a write-only register when designated for host input transfer, and a read-only register when designated for host output transfer. if epdr2 is read when functioning as a write-only register, the contents of the read data are not guaranteed. when epdr2 is functioning as a read- only register, it cannot be written to. data written to epdr0i, epdr1, or epdr2 (when a write-only register) is stored in the fifo, and is made valid by setting the epte bit in the packet transmit enable register (ptter). valid data is transferred to the usb function, and transferred to the host, in accordance with a usb function request. data transferred from the host is stored in the fifo by the usb function, and becomes valid when all the data packet bytes have been received and an ack handshake is transmitted. when epdr0o or epdr2 (when a read-only register) is read, the contents are stored in the fifo, and when the data is valid it is read in the order in which it was transferred. the epdr registers are initialized to h'00 by a system reset or a function soft reset.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 110 of 706 rej09b0303-0300 7.2.4 fifo valid size registers 0i, 0o, 1, 2 (fvsr0i, fvsr0o, fvsr1, fvsr2) fvsr0ih, fvsr0oh, fvsr1h, fvsr2h fvsr0il, fvsr0ol, fvsr1l, fvsr2l bit 7654321076543210 ??????n9n8n7n6n5n4n3n2n1n0 initial value000000000000/1 * 0000 read/write rrrrrrrrrrrrrrrr note: * the initial value of bit n4 is 0 in fvsr0o, and 1 in the other fvsr registers. the fvsr registers indicate the number of valid data bytes in the fifo for each host input/host output involving the respective usb function endpoints. in host input transfer, the fvsr register indicates the number of bytes that the slave cpu can write to the fifo (the fifo size minus the number of bytes written to the fifo by the slave cpu but not read (transmitted) by the usb function). in host output transfer, the fvsr register indicates the number of bytes received and written to the fifo by the usb function but not read by the slave cpu. in host input transfer, the fvsr value is decremented by the number of bytes written when the slave cpu writes to epdr and sets the epte bit in ptter, and is incremented by the number of bytes read when the usb function reads the fifo and receives an ack handshake from the host. in host output transfer, the fvsr value is incremented by the number of bytes written when the usb function writes to the fifo and transmits an ack handshake, and is decremented by 1 each time the slave cpu reads epdr. if a transfer error occurs, data retransfer may be necessary. in this case, the fvsr value is not changed and the fifo for the relevant channel is rewound. in the usb protocol, for each endpoint data0 and data1 packets are transmitted and received alternately when data transfer is performed. this toggling between data0 and data1 also serves as an indicator of whether or not data transfer has been performed normally. if data0/data1 toggling is not performed normally in host output transfer, the usb function will abort processing of that transaction and the fvsr value will not change. since the fvsr registers are 2-byte registers and the h8?s fifos are 16 or 32 bytes in length, the fifo status can be indicated in the lower byte alone. only the lower byte of the fvsr registers should be read. the upper byte of the fvsr registers cannot be accessed directly. when the lower byte is read, the upper byte is transferred to a temporary register, and when the upper byte is read, the contents of this temporary register are read. when a word read is used on an fvsr register, the operation is
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 111 of 706 rej09b0303-0300 automatically divided into two byte accesses, with the upper byte read first, followed by the lower byte. caution is required in this case, since the upper byte value that is read is the value at the point when the lower byte was read previously. fvsr0i and fvsr1 are automatically initialized to h'0010 and h'0000, respectively, when a setup token is received. the fvsr registers are initialized by a system reset or a function soft reset. the initial value depends on the transfer direction and fifo size determined by epdir and epszr. 7.2.5 endpoint direction register (epdir) bit 76543210 ? ? ? ? ep2dir ep1dir ? ? initial value11111100 read/write r r r r r/w r/w r r epdir controls the data transfer direction for usb function endpoints other than endpoint 0. with the h8/3567u and h8/3564u, ep1 should be designated for host input transfer and ep2 for host input transfer or host output transfer. epdir is initialized to h'fc by a system reset or a function soft reset. bit 3?endpoint 2 data transfer direction control flag (ep2dir): switches the endpoint 2 data transfer direction. bit 3 ep2dir description 0 endpoint 2 is designated for host output transfer 1 endpoint 2 is designated for host input transfer (initial value)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 112 of 706 rej09b0303-0300 bit 2?endpoint 1 data transfer direction control flag (ep1dir): switches the endpoint 1 data transfer direction. this bit must not be cleared to 0. bit 2 ep1dir description 0 setting prohibited 1 endpoint 1 is designated for host input transfer (initial value) 7.2.6 packet transmit enable register (ptter) bit 76543210 ? ? ? ? ep2te ep1te ep0ite ? initial value00000000 read/write r r r r r/(w) * r/(w) * r/(w) * r note: * only 1 can be written. ptter contains control bits (epte) that control the fifo valid size registers for usb function host input transfer. in the usb protocol, communication is carried out using packets. the minimum unit of data transfer is a transaction, and a transaction is made up of a token packet, data packet, and handshake packet. in host input transfer, the usb function receives an in token (packet). if operation has not stalled, in response to this token the usb function must transmit a data packet or, if there is no data, a nak handshake. when epte is set to 1 after the data to be transmitted by the usb function has been written to the fifo by the slave cpu, the fvsr contents are updated. this enables transmission of the data written to the fifo. this epte-bit data transmission control prevents data transmission from being done while the slave cpu is writing data to the fifo. the epte can only be written with 1, and are always read as 0.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 113 of 706 rej09b0303-0300 bit 3?endpoint 2 packet transmit enable (ep2te): updates endpoint 2 fvsr2 when the ep2dir bit is set to 1. bit 3 ep2te description 0 normal read value (initial value) (1) [1 write] endpoint 2 in-fifo fvsr2 is updated bit 2?endpoint 1 packet transmit enable (ep1te): updates endpoint 1 fvsr1. bit 2 ep1te description 0 normal read value (initial value) (1) [1 write] endpoint 1 in-fifo fvsr1 is updated bit 1?endpoint 0i packet transmit enable (ep0ite): updates endpoint 0 fvsr0i. bit 1 ep0ite description 0 normal read value (initial value) (1) [1 write] endpoint 0 in-fifo fvsr0i is updated 7.2.7 usb interrupt enable register (usbier) bit 76543210 ? ? brste sofe spnde tfe tse setupe initial value00000000 read/write r r r/w r/w r/w r/w r/w r/w usbier contains enable bits that enable interrupts from the usb function to the slave cpu. usbier is initialized to h'00 by a system reset or a function soft reset.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 114 of 706 rej09b0303-0300 bit 5?bus reset interrupt enable (brste): enables or disables bus request interrupts to the internal cpu. bit 5 brste description 0 usb function bus request interrupts disabled (initial value) 1 usb function bus request interrupts enabled bit 4?sof interrupt enable (sofe): enables or disables sof (start of frame) interrupts to the internal cpu. bit 4 sofe description 0 usb function sof interrupts disabled (initial value) 1 usb function sof interrupts enabled bit 3?suspend interrupt enable (spnde): enables or disables suspend out interrupts and suspend in interrupts to the internal cpu. bit 3 spnde description 0 usb function suspend out interrupts and suspend in interrupts disable (initial value) 1 usb function suspend out interrupts and suspend in interrupts enabled bit 2?transfer failed interrupt enable (tfe): enables or disables transfer failed interrupts to the internal cpu. bit 2 tfe description 0 usb function transfer failed interrupts disabled (initial value) 1 usb function transfer failed interrupts enabled
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 115 of 706 rej09b0303-0300 bit 1?transfer successful interrupt enable (tse): enables or disables transfer successful interrupts to the internal cpu. bit 1 tse description 0 usb function transfer successful interrupts disabled (initial value) 1 usb function transfer successful interrupts enabled bit 0?setup interrupt enable (setupe): enables or disables setup interrupts to the internal cpu. bit 0 setupe description 0 usb function setup interrupts disabled (initial value) 1 usb function setup interrupts enabled 7.2.8 usb interrupt flag register (usbifr) bit 76543210 ts tf ? brstf soff spndof spndif setupf initial value00000000 read/write r r r r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * only 0 can be written, after reading 1, to clear the flag. usbifr contains interrupt flags that generate interrupts from the usb function to the slave cpu. the usb module has four interrupt sources (usbia, usbib, usbic, and usbid). usbia is a dedicated setup interrupt. a single transfer successful interrupt or transfer failed interrupt can be assigned to usbib and usbic. all other interrupts (all transfer successful interrupts and transfer failed interrupts, bus reset interrupts, sof interrupts, and suspend out and suspend in interrupts) are assigned to usbid. usbifr is initialized to h'00 by a system reset or a function soft reset.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 116 of 706 rej09b0303-0300 bit 7?transfer successful interrupt status (ts): status flag that indicates that transfer has ended normally at a usb function endpoint. when the tse bit is 1, usbid interrupt request is sent to the slave cpu, but if a setting has been made for the source that set ts to 1 to request usbib or usbic interrupt, has priority for processing in accordance with the priority order in the slave cpu?s interrupt controller (intc). ts is a read-only flag. bit 7 ts description 0 all bits in transfer success flag register (tsfr) are 0 (initial value) 1 at least one bit in transfer success flag register (tsfr) is 1 bit 6?transfer failed interrupt status (tf): status flag that indicates that transfer has ended abnormally at a usb function endpoint. when the tfe bit is 1, usbid interrupt request is sent to the slave cpu, but if a setting has been made for the source that set tf to 1 to request usbib or usbic interrupt, has priority for processing in accordance with the priority order in the slave cpu?s interrupt controller (intc). tf is a read-only flag. bit 6 tf description 0 all bits in transfer fail flag register (tffr) are 0 (initial value) 1 at least one bit in transfer fail flag register (tffr) is 1 bit 4?bus reset interrupt flag (brstf): status flag that indicates that the usb function has detected a bus reset from upstream. when the brste bit is 1, usbid interrupt request is sent to the slave cpu.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 117 of 706 rej09b0303-0300 bit 4 brstf description 0 [clearing condition] (initial value) when 0 is written to brstf after reading brstf = 1 1 [setting condition] when usb function detects a bus reset from upstream bit 3?sof interrupt flag (soff): status flag that indicates that the usb function has detected sof (start of frame). when the sofe bit is 1, usbid interrupt request is sent to the slave cpu. bit 3 soff description 0 [clearing condition] (initial value) when 0 is written to soff after reading soff = 1 1 [setting condition] when usb function detects sof (start of frame) bit 2?suspend out interrupt flag (spndof): status flag that indicates that the usb function has detected a change in the bus status, and has switched from the suspend state to the normal state. when the spnde bit is 1, usbid interrupt request is sent to the slave cpu. bit 2 spndof description 0 [clearing condition] (initial value) when 0 is written to spndof after reading spndof = 1 1 [setting condition] when usb function switches from suspend state to normal state bit 1?suspend in interrupt flag (spndif): status flag that indicates that the usb function has detected a bus idle state lasting longer that the specified time, and has switched from the normal state to the suspend state. when the spnde bit is 1, usbid interrupt request is sent to the slave cpu.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 118 of 706 rej09b0303-0300 bit 1 spndif description 0 [clearing condition] (initial value) when 0 is written to spndif after reading spndif = 1 1 [setting condition] when usb function switches from normal state to suspend state bit 0?setup interrupt flag (setupf): status flag that indicates that usb function endpoint 0 has received a setup token. when the setupe bit is 1, usbia interrupt request is sent to the slave cpu. bit 0 setupf description 0 [clearing condition] (initial value) when 0 is written to setupf after reading setupf = 1 1 [setting condition] when usb function endpoint 0 receives setup token 7.2.9 transfer success flag register (tsfr) bit 76543210 ? ? ? ? ep2ts ep1ts ep0its ep0ots initial value00000000 read/write r r r r r/(w) * r/(w) * r/(w) * r/(w) * note: * only 0 can be written, after reading 1, to clear the flag. tsfr contains status flags (epts flags) that indicate that a usb function endpoint host input/host output transaction has ended normally. the condition for a normal end of a transaction is reception of an ack handshake in host input transfer, or transmission of an ack handshake in host output transfer. when at least one epts flag is set to 1, the ts flag in usbifr is also set at the same time. the ts flag generates an interrupt to the slave cpu. the epts flags must be cleared to 0 in the interrupt handling routine. when all the epts flags are cleared, the ts flag is automatically cleared to 0. only 0 can be written to the epts flags, after first reading 1.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 119 of 706 rej09b0303-0300 when the usb function receives a setup token, the ep0its and ep0ots flags are automatically cleared to 0. tsfr is initialized to h'00 by a system reset or a function soft reset. bit 3?endpoint 2 transfer success flag (ep2ts): indicates that an endpoint 2 host input transfer or host output transfer has ended normally. bit 3 ep2ts description 0 endpoint 2 is in transfer standby state (initial value) [clearing condition] when 0 is written to ep2ts after reading ep2ts = 1 1 endpoint 2 host input transfer (in transaction) or host output transfer (out transaction) has ended normally [setting conditions] ? ack handshake established after in token reception and data transfer (ack reception) ? ack handshake established after out token reception and data transfer (ack transmission) bit 2?endpoint 1 transfer success flag (ep1ts): indicates that an endpoint 1 host input transfer has ended normally. bit 2 ep1ts description 0 endpoint 1 is in transfer standby state (initial value) [clearing condition] when 0 is written to ep1ts after reading ep1ts = 1 1 endpoint 1 host input transfer (in transaction) has ended normally [setting condition] ack handshake established after in token reception and data transfer (ack reception) bit 1?endpoint 0 host input transfer success flag (ep0its): indicates that an endpoint 0 host input transfer has ended normally.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 120 of 706 rej09b0303-0300 bit 1 ep0its description 0 endpoint 0 is in host input transfer standby state (initial value) [clearing conditions] ? when 0 is written to ep0its after reading ep0its = 1 ? when endpoint 0 receives a setup token 1 endpoint 0 host input transfer (in transaction) has ended normally [setting condition] ack handshake established after in token reception and data transfer (ack reception) bit 0?endpoint 0 host output transfer success flag (ep0ots): indicates that an endpoint 0 host output transfer has ended normally. host output transfers to endpoint 0 include out transactions and setup transactions. these operations are the same in terms of data transfer, but differ as regards flag handling. most commands transferred in setup transactions are processed within the usb function, in which case the ep0ots flag is not set and the ep0otf flag is. in the case of a command that cannot be processed within the usb function, the ep0ots flag is set. bit 0 ep0ots description 0 endpoint 0 is in host output transfer standby state (initial value) [clearing conditions] ? when 0 is written to ep0ots after reading ep0ots = 1 ? when endpoint 0 receives a setup token 1 endpoint 0 host output transfer (out transaction or setup transaction) has ended normally [setting conditions] ? ack handshake established after out token reception and data transfer (ack transmission) ? when command received after setup token reception requires processing by the slave cpu
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 121 of 706 rej09b0303-0300 7.2.10 transfer fail flag register (tffr) bit 76543210 ? ? ? ? ep2tf ep1tf ep0itf ep0otf initial value00000000 read/write rrrrr/(w) * r/(w) * r/(w) * r/(w) * note: * only 0 can be written, after reading 1, to clear the flag. tffr contains status flags (eptf flags) that indicate that a usb function endpoint host input/host output transaction has not ended normally. the condition for an abnormal end of a transaction is nak handshake reception, or nak handshake transmission when there is no transfer data (fvsr = fifo size (fifo empty)), in host input transfer, or, in host output transfer, nak handshake transmission due to a fifo full condition, etc., or any of various communication errors (data0/data1 toggle error, bit stuffing error, bit count error, crc error, transfer of a number of bytes exceeding maxpktsz, etc.) during data transfer. when at least one eptf flag is set to 1, the tf flag in usbifr is also set at the same time. the tf flag generates an interrupt to the slave cpu. the eptf flags must be cleared to 0 in the interrupt handling routine. when all the eptf flags are cleared, the tf flag is automatically cleared to 0. only 0 can be written to the eptf flags, after first reading 1. when the usb function receives a setup token, the ep0itf and ep0otf flags are automatically cleared to 0. tffr is initialized to h'00 by a system reset or a function soft reset.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 122 of 706 rej09b0303-0300 bit 3?endpoint 2 transfer fail flag (ep2tf): indicates that an endpoint 2 host input transfer or host output transfer has not ended normally. bit 3 ep2tf description 0 endpoint 2 is in transfer standby state (initial value) [clearing condition] when 0 is written to ep2tf after reading ep2tf = 1 1 endpoint 2 host input transfer (in transaction) or host output transfer (out transaction) has ended abnormally [setting conditions] ? ack handshake not established after in token reception and data transfer ? data transfer not possible due to fifo empty condition after in token reception ? data transfer not possible due to fifo full condition after out token reception (nak transmission) ? data transfer errors after out token reception bit 2?endpoint 1 transfer fail flag (ep1tf): indicates that an endpoint 1 host input transfer has not ended normally. bit 2 ep1tf description 0 endpoint 1 is in transfer standby state (initial value) [clearing condition] when 0 is written to ep1tf after reading ep1tf = 1 1 endpoint 1 host input transfer (in transaction) has ended abnormally [setting conditions] ? ack handshake not established after in token reception and data transfer ? data transfer not possible due to fifo empty condition after in token reception (nak transmission)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 123 of 706 rej09b0303-0300 bit 1?endpoint 0 host input transfer fail flag (ep0itf): indicates that an endpoint 0 host input transfer has not ended normally. bit 1 ep0itf description 0 endpoint 0 is in host input transfer standby state (initial value) [clearing conditions] ? when 0 is written to ep0itf after reading ep0itf = 1 ? when endpoint 0 receives a setup token 1 endpoint 0 host input transfer (in transaction) has ended abnormally [setting conditions] ? ack handshake not established after in token reception and data transfer ? data transfer not possible due to fifo empty condition after in token reception (nak transmission) bit 0?endpoint 0 host output transfer fail flag (ep0otf): indicates that an endpoint 0 host output transfer has not ended normally. host output transfers to endpoint 0 include out transactions and setup transactions. these operations are the same in terms of data transfer, but differ as regards flag handling. most commands transferred in setup transactions are processed within the usb function, in which case the ep0ots flag is not set and the ep0otf flag is. in the case of a command that cannot be processed within the usb function, the ep0ots flag is set.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 124 of 706 rej09b0303-0300 bit 0 ep0otf description 0 endpoint 0 is in host output transfer standby state (initial value) [clearing conditions] ? when 0 is written to ep0otf after reading ep0otf = 1 ? when endpoint 0 receives a setup token 1 endpoint 0 host output transfer (out transaction or setup transaction) has ended abnormally [setting conditions] ? transfer not possible due to fifo full condition after out token reception (nak transmission) ? data transfer not possible because ep0otc = 0 after out token reception (nak transmission) ? communication error after out token reception ? when command received after setup token reception can be processed within the usb function 7.2.11 usb control/status register 0 (usbcsr0) bit 76543210 dp5cnct dp4cnct dp3cnct dp2cnct ep0stop epivld ep0otc ckstop initial value00000000 read/write r r r r r/w r/w r/w r/w usbcsr0 contains flags that indicate the usb hubs? downstream port connection status, and bits that control the operation of the usb function. usbcsr0 is initialized to h'00 by a system reset, and bits 3 to 0 are also cleared to 0 by a function soft reset.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 125 of 706 rej09b0303-0300 bits 7 to 4?downstream port connect 5 to 2 (dp5cnct, dp4cnct, dp3cnct, dp2cnct): read-only status flags that indicate the connection status of the usb hubs? external downstream ports. bits 7 to 4 dp5cnct to dp2cnct description 0 cable is not connected to downstream port (initial value) [clearing conditions] ? system reset ? downstream port disconnect ? usb hub upstream port disconnect (total downstream disconnect by software in reconnect process) 1 cable is connected to downstream port, and power is being supplied [setting condition] downstream port connect bit 3?endpoint 0 stop (ep0stop): bit that protects the contents of the usb function endpoint 0 fifo. setting ep0stop to 1 enables the data transferred to the ep0 out-fifo by a setup transaction to be protected. bit 3 ep0stop description 0 ep0 out-fifo, in-fifo operational (initial value) [clearing conditions] ? system reset ? function soft reset 1 ep0 out-fifo reading stopped ? fvsr0o contents are not changed by an epdr0o read ep0 in-fifo writing and transfer stopped ? fifo contents are not changed by an epdr0i write ? fvsr0i contents are not changed by setting ep0ite
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 126 of 706 rej09b0303-0300 bit 2?endpoint information valid (epivld): this bit makes the usb function block operational. part of the process that makes the usb function block operational includes an endpoint information setting. after a system reset or function soft reset, the usb function block does not have any endpoint information. endpoint information for the usb function in the h8/3567u and h8/3564u (see section 7.3.9, usb module startup sequence) can be set by sequential writes to epdr0i. when all the data has been written, the written endpoint information is made valid by setting the epivld bit to 1. writing 0 to the epivld bit has no effect. bit 2 epivld description 0 endpoint information (epinfo) has not been set (initial value) [clearing conditions] ? system reset ? function soft reset 1 endpoint information (epinfo) has been set bit 1?endpoint 0o transfer control (ep0otc): controls usb function endpoint 0 control transfer. clearing ep0otc to 0 disables writes to the ep0 out-fifo. a change of data transfer direction within a control transfer can be reported by means of the transfer fail interrupt caused by this action. in control transfer, a command is received in the setup transaction (command stage), then data transfer is performed in an out or in transaction (data stage), and finally a transfer equivalent to a handshake is carried out in an in or out transaction (status stage). when a setup token is received, ep0otc is set to 1, fvsr is initialized, and command data can be received. on completion of command data reception, ep0otc is cleared to 0 and the contents of the ep0o-fifo are protected. if the command cannot be processed automatically by the usb function core, the ep0ots flag is set and the slave cpu must decode the command. if command decoding shows that an out transaction will follow as the data stage, the slave cpu must set ep0otc to 1 in preparation for an out transaction. if the command stage is followed by an in transaction data stage, the slave cpu leaves ep0otc cleared to 0. when the host cpu begins an out transaction as the status stage, the ep0otf flag is set and a transfer fail interrupt is generated, enabling the slave cpu to recognize the end of the data stage. in response to this interrupt, the slave cpu sets ep0otc to 1 and receives retransferred status stage data.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 127 of 706 rej09b0303-0300 bit 1 ep0otc description 0 ep0 out-fifo writing stopped (initial value) ? subsequent writes to ep0 out-fifo are invalid [clearing conditions] ? system reset ? function soft reset ? command data reception in setup transaction (ep0ots flag setting) 1 ep0 out-fifo operational [setting conditions] ? setup token reception ? when 1 is written to ep0otc after reading ep0otc = 0 bit 0?clock stop (ckstop): controls the usb function operating clock. when the usb function is placed in the suspend state due to a bus idle condition, this bit should be set to 1 after the necessary processing is completed. the clock supply to the usb function is then stopped, reducing power consumption. when the ckstop bit is set to 1, writes to usb module registers are invalid. if these registers are read, the contents of the read data are not guaranteed, but there are no read-related status changes (such as decrementing of fvsr). if a bus idle condition of the specified duration or longer is detected, the suspend in interrupt flag is set, and when a change in the bus status is subsequently detected the suspend out interrupt flag is set. when the suspend out interrupt flag is set, the ckstop bit is simultaneously cleared to 0.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 128 of 706 rej09b0303-0300 bit 0 ckstop description 0 clock is supplied to usb function (initial value) [clearing conditions] ? system reset ? function soft reset ? suspend out interrupt flag setting 1 clock supply to usb function is stopped [setting condition] when 1 is written to ckstop after reading ckstop = 0 in the function suspend state 7.2.12 endpoint stall register (epstlr) bit 76543210 ? ? ? ? ep2stl ep1stl ? ep0stl initial value00000000 read/write r r r r r/w r/w r r/w epstlr contains bits (epstl) that place the usb function endpoints in the stall state. when an epstl bit is set to 1, the corresponding endpoint sends a stall handshake in reply to the start of a transaction through reception of a token from the host. when the usb function receives a setup token, the ep0stl bit is automatically cleared to 0. epstlr is initialized to h'00 by a system reset or a function soft reset. bit 3?endpoint 2 stall (ep2stl): places endpoint 2 in the stall state. bit 3 ep2stl description 0 endpoint 2 is operational (initial value) 1 endpoint 2 is in stall state
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 129 of 706 rej09b0303-0300 bit 2?endpoint 1 stall (ep1stl): places endpoint 1 in the stall state. bit 2 ep1stl description 0 endpoint 1 is operational (initial value) 1 endpoint 1 is in stall state bit 0?endpoint 0 stall (ep0stl): places endpoint 0 in the stall state. writing 0 to the ep0stl bit has no effect. bit 0 ep0stl description 0 endpoint 0 is operational (initial value) [clearing condition] when endpoint 0 receives a setup token 1 endpoint 0 is in stall state [setting condition] when 1 is written to ep0stl after reading ep0stl = 0 7.2.13 endpoint reset register (eprstr) bit 76543210 ? ? ? ? ep2rst ep1rst ep0irst ? initial value00000000 read/write r r r r r/(w) * r/(w) * r/(w) * r note: * only 1 can be written. eprstr contains control bits (eprst) that reset the pointer of the fifo for a usb function endpoint host input transfer. when an eprst bit is set to 1, the corresponding fifo valid size register (fvsr) is initialized. the eprst bits can only be written with 1, and are always read as 0.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 130 of 706 rej09b0303-0300 bit 3?endpoint 2 reset (ep2rst): initializes the endpoint 2 fifo. bit 3 ep2rst description 0 normal read value (initial value) (1) [1 write] ep2dir = 0: fvsr2 is initialized to h'0000 ep2dir = 1: fvsr2 is initialized to h'0010 bit 2?endpoint 1 reset (ep1rst): initializes the endpoint 1 fifo. bit 2 ep1rst description 0 normal read value (initial value) (1) [1 write] ep1 fifo size = 16 bytes: fvsr1 is initialized to h'0010 ep1 fifo size = 32 bytes: fvsr1 is initialized to h'0020 bit 1?endpoint 0i reset (ep0irst): initializes the endpoint 0i fifo. bit 1 ep0irst description 0 normal read value (initial value) (1) [1 write] fvsr0i is initialized to h'0010
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 131 of 706 rej09b0303-0300 7.2.14 device resume register (devrsmr) bit 76543210 ???????dvr initial value00000000 read/write rrrrrrrr/(w) * note: * only 1 can be written. devrsmr contains a bit (dvr) that control remote wakeup of the usb function suspend state. when 1 is written to the dvr bit, the suspend state is cleared. the dvr bit can only be written with 1, and is always read as 0. 1 can be written to the dvr bit even if the ckstop bit is set to 1 in usbcsr0. bit 0?device resume (dvr): clears the suspend state. bit 0 dvr description 0 normal read value (initial value) (1) [1 write] suspend state is cleared (remote wakeup) 7.2.15 interrupt source select register 0 (intselr0) bit 76543210 tselb epibs2 epibs1 epibs0 tselc epics2 epics1 epics0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w intselr0 contains bits that select the usb function usbib and usbic interrupt sources. intselr0 is initialized to h'00 by a system reset or a function soft reset.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 132 of 706 rej09b0303-0300 bit 7?transfer select b (tselb): together with bits epibs2 to epibs0, selects usbib interrupt source. bit 7 tselb description 0 usbib interrupt is requested by a ts interrupt; the endpoint constituting the ts interrupt source is specified by bits epibs2 to epibs0 (initial value) 1 usbib interrupt is requested by a tf interrupt; the endpoint constituting the tf interrupt source is specified by bits epibs2 to epibs0 bits 6 to 4?interrupt b endpoint select 2 to 0 (epibs2 to epibs0): together with the tselb bit, these bits select usbib interrupt source. bit 6 bit 5 bit 4 epibs2 epibs1 epibs0 description 0 0 0 endpoint not selected (initial value) 1 endpoint 1 selected 1 0 endpoint 2 selected 1 setting prohibited 1 ? ? setting prohibited bit 3?transfer select c (tselc): together with bits epics2 to epics0, selects usbic interrupt source. bit 3 tselc description 0 usbic interrupt is requested by a ts interrupt; the endpoint constituting the ts interrupt source is specified by bits epics2 to epics0 (initial value) 1 usbic interrupt is requested by a tf interrupt; the endpoint constituting the tf interrupt source is specified by bits epics2 to epics0
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 133 of 706 rej09b0303-0300 bits 2 to 0?interrupt c endpoint select 2 to 0 (epics2 to epics0): together with the tselc bit, these bits select usbic interrupt source. bit 2 bit 1 bit 0 epics2 epics1 epics0 description 0 0 0 endpoint not selected (initial value) 1 endpoint 1 selected 1 0 endpoint 2 selected 1 setting prohibited 1 ? ? setting prohibited 7.2.16 interrupt source select register 1 (intselr1) bit 76543210 ??????dtcbedtcce initial value00000000 read/write r rrrrrr/wr/w register intselr1 is not used in this model. do not write 1 to the bits in intselr1. 7.2.17 hub overcurrent control register (hoccr) bit 76543210 ? ? pcsp ocdsp hoc5e hoc4e hoc3e hoc2e initial value00000000 read/write r r r/w r/w r/w r/w r/w r/w the usb hub downstream ports are connected to the usb connector as data (d+/d?). the power supply (vbus) connected to the usb connector is generated by connecting a power supply control ic externally. hoccr contains bits that control the power supply control ic control input/output. hoccr is initialized to h'00 by a system reset.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 134 of 706 rej09b0303-0300 bit 5?power supply enable control polarity (pcsp): this bit is set according to the polarity of the power supply control ic output enable inputs. the power supply control ic output enable inputs are connected to h8 pins enp 5 to enp 2 . bit 5 pcsp description 0 power supply control ic requires low-level input for enabling (initial value) 1 power supply control ic requires high-level input for enabling bit 4?overcurrent detection polarity (ocdsp): this bit is set according to the polarity of the power supply control ic overcurrent detection outputs. the power supply control ic overcurrent detection outputs are connected to h8 pins ocp 5 to ocp 2 . bit 4 ocdsp description 0 power supply control ic outputs low level in case of overcurrent detection (initial value) 1 power supply control ic outputs high level in case of overcurrent detection bits 3 to 0?overcurrent detection control enable 5 to 2 (hoc5e to hoc2e): these pins select whether or not power supply control ic control is performed for each usb hub downstream port. if any of the four downstream ports are not used, the corresponding d+/d- pins should be pulled down as specified. leave the corresponding hoce bit cleared to 0, disabling the corresponding output enable pin and overcurrent detection pin. disabled pins can be used as general port pins (port c). bit 3 hoc5e description 0pins enp 5 and ocp 5 are general ports (pc 7 , pc 3 ) (initial value) 1pins enp 5 and ocp 5 have output enable and overcurrent detection functions
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 135 of 706 rej09b0303-0300 bit 2 hoc4e description 0pins enp 4 and ocp 4 are general ports (pc 6 , pc 2 ) (initial value) 1pins enp 4 and ocp 4 have output enable and overcurrent detection functions bit 1 hoc3e description 0pins enp 3 and ocp 3 are general ports (pc 5 , pc 1 ) (initial value) 1pins enp 3 and ocp 3 have output enable and overcurrent detection functions bit 0 hoc2e description 0pins enp 2 and ocp 2 are general ports (pc 4 , pc 0 ) (initial value) 1pins enp 2 and ocp 2 have output enable and overcurrent detection functions 7.2.18 usb control register (usbcr) bit 76543210 fadsel fonly fncstp uifrst hpllrst hsrst fpllrst fsrst initial value01111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w usbcr contains bits (fadsel, fonly, fncstp) that control usb function and usb hub internal connection, and reset control bits for sequential enabling of the operation of each part according to the usb module start-up sequence. usbcr is initialized to h'7f by a system reset [in an h8/3567u and h8/3564u reset (by res input or the watchdog timer), and in hardware standby mode]. it is not initialized in software standby mode.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 136 of 706 rej09b0303-0300 bit 7?usb function i/o analog/digital select (fadsel): selects the usb function data input/output method when the fonly bit is set to 1 so that the usb hub block is disabled and only the usb function block operates. bit 7 fadsel description 0 usd+ and usd? pins are used for usb function block data input/output (initial value) 1 usb function block data input/output is implemented by multiplexing philips transceiver/receiver (pdiusb11a) compatible control input/output with port c pins port c philips pdiusb11a pc 7 input vp differential input (+) pc 6 input vm differential input (?) pc 5 input rcv data input pc 4 output vpo differential output (+) pc 3 output vmo differential output (?) pc 2 output oe output enable pc 1 output suspend suspend setting pc 0 output speed speed setting high level fixed output for 12 mbps specification bit 6?usb function select (fonly): selects enabling/disabling of the usb hub block. when the usb hub block is enabled, the usb function block is connected internally to usb hub downstream port 1. when the usb hub block is disabled, the usb function block is directly connected to the upstream port, and the usb operating clock selected/divided/multiplied in accordance with upllcr settings is not supplied to the usb hub block. bit 6 fonly description 0 usb function block is connected internally to usb hub downstream port 1 usb hub block is enabled 1 usb function block is directly connected to upstream port usb hub block is disabled (initial value)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 137 of 706 rej09b0303-0300 bit 5?usb function stop/suspend (fncstp): with the h8/3567u and h8/3564u, it is possible to disconnect the usb function block from the usb hub block?s downstream port 1, and set a power-down state in which the usb operating clock supply is halted. register accesses by the cpu are still possible in this state. the fncstp bit is used when disconnecting the usb function block and switching the microcomputer block to power-down mode when the system?s power supply is cut, or when reconnecting the usb function block when recovering from power-down mode or in the event of a power-on reset. when the fncstp bit is set to 1, the usb operating clock selected/divided/multiplied in accordance with upllcr settings is not supplied to the usb function block. bit 5 fncstp description 0 for usb function block, usb hub downstream port 1 internal connection is set to connected state 1 for usb function block, usb hub downstream port 1 internal connection is set to disconnected state, and power-down state is set (initial value) bit 4?usb interface soft reset (uifrst): resets the epszr1, usbier, epdir, intselr0, and intselr1 registers. when uifrst is set to 1, the epszr1, usbier, epdir, intselr0, and intselr1 registers are initialized. bit 4 uifrst description 0 epszr1, usbier, epdir, intselr0, and intselr1 are placed in operational state 1 epszr1, usbier, epdir, intselr0, and intselr1 are placed in reset state (initial value)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 138 of 706 rej09b0303-0300 bit 3?hub block pll soft reset (hpllrst): resets the usb bus clock circuit (dpll) in the hub. when hpllrst is set to 1, the dpll circuit in the hub is reset, and bus clock synchronous operation halts. hpllrst is cleared to 0 after pll operation stabilizes. bit 3 hpllrst description 0 hub dpll is placed in operational state 1 hub dpll is placed in reset state (initial value) bit 2?hub block internal state soft reset (hsrst): resets the internal state of the usb hub block. when hsrst is set to 1, the internal state of the usb hub block, excluding the internal usb bus clock circuit (dpll), is initialized. hsrst is cleared to 0 after dpll operation stabilizes. bit 2 hsrst description 0 internal state of usb hub block is set to operational state 1 internal state of usb hub block is set to reset state (excluding dpll) (initial value) bit 1?function block pll soft reset (fpllrst): resets the usb bus clock circuit (dpll) in the function. when fpllrst is set to 1, the dpll circuit in the function is reset, and bus clock synchronous operation halts. fpllrst is cleared to 0 after pll operation stabilizes. bit 1 fpllrst description 0 function dpll is placed in operational state 1 function dpll is placed in reset state (initial value)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 139 of 706 rej09b0303-0300 bit 0?function block internal state reset (fsrst): resets the internal state of the usb function block. when fsrst is set to 1, the internal state of the usb function block, excluding the internal bus clock circuit (dpll), is initialized. fsrst is cleared to 0 after dpll operation stabilizes. the state in which fsrst = 1 and uifrst = 1 is called a function soft reset. bit 0 fsrst description 0 internal state of usb function block is set to operational state 1 internal state of usb function block is set to reset state (excluding dpll) (initial value) 7.2.19 usb pll control register (upllcr) bit 76543210 ? ? ? cksel2 cksel1 cksel0 pfsel1 pfsel0 initial value00000001 read/write r r r r/w r/w r/w r/w r/w upllcr contains bits that control the method of generating the usb function and usb hub operating clock. upllcr is initialized to h'01 by a system reset [in an h8/3567u and h8/3564u reset (by res input or the watchdog timer), and in hardware standby mode]. it is not initialized in software standby mode. bits 4 to 2?clock source select 2 to 0 (cksel2 to cksel0): these bits select the source of the clock supplied to the usb operating clock generator (pll). cksel0 selects either the usb clock pulse generator (xtal12) or the system clock pulse generator (xtatl) as as the clock source. when selected as a clock source, the usb clock pulse generator starts operating. it operates with cksel2=1, cksel0=1. when cksel2 = 1 and cksel1 = 1, the pll operates. when cksel1 is cleared to 0, a clock is not input to the pll, and pll operation halts. the 48 mhz signal from the usb clock pulse generator can be input directly as the usb operating clock.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 140 of 706 rej09b0303-0300 when cksel2 is cleared to 0, a clock is not input to the pll, and pll operation halts. bit 4 bit 3 bit 2 cksel2 cksel1 cksel0 description 0 0 0 pll operation halted, clock input halted (initial value) ? ? pll operation halted, clock input halted 1 0 0 setting prohibited 1 pll operation halted usb clock pulse generator (xtal12: 48 mhz) used directly instead of pll output 1 0 pll operates with system clock pulse generator (xtal) as clock source 1 pll operates with usb clock pulse generator (xtal12) as clock source bits 1 and 0?pll frequency select 1 and 0 (pfsel1, pfsel0): these bits select the frequency of the clock supplied to the usb operating clock pulse generator (pll). the pll generates the 48 mhz usb operating clock using the frequency selected with these bits as the clock source frequency. bit 1 bit 0 pfsel1 pfsel0 description 0 0 pll input clock is 8 mhz 1 pll input clock is 12 mhz (initial value) 1 0 pll input clock is 16 mhz 1 pll input clock is 20 mhz
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 141 of 706 rej09b0303-0300 7.2.20 usb port control register (uprtcr) bit 76543210 ? ? dspsel2 dspsel1 dspsel0 pcnmd2 pcnmd1 pcnmd0 initial value00000000 read/write r r r/w r/w r/w r/w r/w r/w uprtcr is a test register. its initial settings should not be changed. uprtcr is initialized to h'00 by a system reset (reset of this lsi by a res input or by the watchdog timer, and in hardware standby mode). it is not initialized in software standby mode. bits 5 to 3?downstream port select 2 to 0 (dspsel2 to dspsel0): these bits select the downstream port to be tested. bit 5 bit 4 bit 3 dspsel2 dspsel1 dspsel0 description 0 0 0 downstream port 2 selected (initial value) 1 downstream port 3 selected 1 0 downstream port 4 selected 1 downstream port 5 selected 1 ? ? downstream port 1 selected bits 2 to 0?port connection mode select 2 to 0 (pcnmd2 to pcnmd0): these bits set ports c and d to the normal operating mode or a test operating mode. the pcnmd bits must be set to b'000. bit 2 bit 1 bit 0 pcnmd2 pcnmd1 pcnmd0 description 0 0 0 user mode (initial value) 1 digital upstream mode 1 0 digital downstream mode 1 digital upstream/downstream mode 1 0 0 upstream transceiver/receiver monitor mode 1 downstream transceiver/receiver monitor mode 1?reserved
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 142 of 706 rej09b0303-0300 7.2.21 usb test registers 2, 1, 0 (utestr2, utestr1, utestr0) utestr2, utestr1, and utestr0 are test registers. their initial settings should not be changed. utestr1 and utestr0 are initialized to h'00 by a system reset [in an h8/3567u or h8/3564u reset (by res input or the watchdog timer), and in standby mode]. they are not initialized in software standby mode. utestr2 is initialized to h'ff by a system reset [in an h8/3567u or h8/3564u reset (by res input or the watchdog timer), and in standby mode]. it is not initialized in software standby mode. utestr0 bit 76543210 test15 test14 test13 test12 test11 test10 test9 test8 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w utestr1 bit 76543210 test7 test6 test5 test4 test3 test2 test1 test0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w utestr2 bit 76543210 testa testb testc testd teste testf testg testh initial value11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 143 of 706 rej09b0303-0300 7.2.22 module stop control register (mstpcr) mstpcrh mstpcrl bit 7654321076543210 mstp 15 mstp 14 mstp 13 mstp 12 mstp 11 mstp 10 mstp 9 mstp 8 mstp 7 mstp 6 mstp 5 mstp 4 mstp 3 mstp 2 mstp 1 mstp 0 initial value 0011111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w mstpcr comprises two 8-bit readable/writable registers that perform module stop mode control. when the mstp1 bit is set to 1, the usb module stops operating and enters module stop mode at the end of the bus cycle. however, when usb clocks (xtal12, extal12) are selected as usb operating clocks, the usb module does not stop operating. for details, see section 21.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrl bit 1?module stop (mstp1): specifies module stop mode for the usb module. mstpcrl bit 1 mstp1 description 0 usb module stop mode cleared 1 usb module stop mode set (initial value) 7.2.23 serial timer control register (stcr) bit 76543210 ? iicx1 iicx0 iice ? usbe icks1 icks0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w stcr is an 8-bit readable/writable register that controls register access, the iic operating mode, selects the tcnt input clock and controls usb. for details of functions other than register access control, see the descriptions of the relevant modules. if a module controlled by stcr is not used, do not write 1 to the corresponding bit.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 144 of 706 rej09b0303-0300 stcr is initialized to h'00 by a reset and in hardware standby mode. bit 7?reserved: do not write 1 to this bit. bits 6 and 5?i 2 c control (iicx1, iicx0): these bits control the operation of the i 2 c bus interface. for details, see section 16, i 2 c bus interface. bit 4?i 2 c master enable (iice): controls cpu access to the i 2 c bus interface data registers and control registers (iccr, icsr, icdr/sarx, and icmr/sar), the pwmx data registers and control registers (dadrah/dacr, dadral, dadrbh/dacnth, and dadrbl/dacntl), and the sci control registers (smr, brr, and scmr). bit 4 iice description 0 addresses h'ffd8 and h'ffd9, and h'ffde and h'ffdf, are used for sci0 control register access (initial value) 1 addresses h'ff88 and h'ff89, and h'ff8e and h'ff8f, are used for iic1 data register and control register access addresses h'ffa0 and h'ffa1, and h'ffa6 and h'ffa7, are used for pwmx data register and control register access addresses h'ffd8 and h'ffd9, and h'ffde and h'ffdf, are used for iic0 data register and control register access bit 3?reserved: do not write 1 to this bit. bit 2?usb enable (usbe): this bit controls cpu access to the usb data register and control register. bit 2 usbe description 0 prohibition of the above register access (initial value) 1 permission of the above register access bits 1 and 0?internal clock source select 1 and 0 (icks1, icks0): these bits, together with bits cks2 to cks0 in tcr, select the clock to be input to tcnt. for details, see section 12, 8-bit timers.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 145 of 706 rej09b0303-0300 7.3 operation usb is an interface for peripherals of the personal computers standardized by intel and others and the standard is defined by the usb specification. operation of the usb hubs and usb function in this model is based on the definitions of the usb specification. this section gives only a brief overview of the usb bus specifications, and focuses on operations by the slave cpu. 7.3.1 usb compound device configuration a usb compound device is a usb device incorporating usb hubs and a usb function. the h8/3567u and h8/3564u incorporate a compound device with a configuration in which the usb function is internally connected to one downstream port of a usb hub with five downstream ports. with a usb compound device, it is usual for the usb function to be constantly connected to the usb hub. with the h8/3567u and h8/3564u, however, the internally connected usb function is not constantly connected to the usb hub. after release from an h8 reset, the usb function can be connected or disconnected under program control. therefore, the device is not identified as a compound device in the hub descriptor whub characteristics. there are two power feed modes for a usb device: bus feed and self-feed. the h8/3567 group use the self-feed method. with the h8/3567u and h8/3564u a setting can be made to disconnect the usb function block and operate the usb hub block alone. in this case, it is possible to place the slave cpu in software standby mode, and operate it in power-down mode. 7.3.2 functions of usb hub block the usb hub block implements the functions described in section 11 of the usb specification. there are five downstream ports; downstream port 1 can be connected to the usb function block internally, while downstream ports 2 to 5 are connected to external pins. downstream ports 2 to 5 have their respective overcurrent detection pins ( ocp 2 to ocp 5 ) and power supply output enable pins ( enp 2 to enp 5 ), making it is possible to control enabling/disabling of the power supply control ic connected to the vbus, and report overcurrent detection to the host, on an individual port basis. as exchanges with the usb host are all executed automatically within the usb hub, usb hub block exchanges with the slave cpu are limited to the following cases:
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 146 of 706 rej09b0303-0300 1. usb module reset or operation halt a. slave cpu system reset (internal reset by res or stby input, or wdt0) b. module stop condition initiated by slave cpu (usb module stopped by means of mstpcr) c. usb module reset by means of hpllrst or hsrst bit in usbcr 2. downstream port overcurrent detection and power supply output enable control a. overcurrent detection and power supply output enable for individual ports by bits hoc5e to hoc2e in hoccr. (when a downstream port itself is not used, dsd+/dsd- pins require pullup/pulldown as specified.) 7.3.3 functions of usb function the usb function block has three endpoints. by using a combination of endpoint 2 enabling/disabling and in/out mode with endpoint 1 maxpacketsize, the three alternates shown below can be selected for the usb function block. twice the maxpacketsize value is set for the number of fifo bytes. as the command that selects the alternate is a usb standard command, it is not possible to notify the slave cpu of the alternate selected. it is therefore necessary to ensure that the selected alternate is the same for the h8 firmware and the host cpu device driver. endpoint 0 endpoint 1 endpoint 2 configuration interface alternate in/out fifo in/out fifo in/out fifo 1 00in/out16 bytes each in 16 bytes in 16 bytes 1 in/out 16 bytes each in 16 bytes out 16 bytes 2 in/out 16 bytes each in 32 bytes none none the usb function supports control transfer by means of endpoint 0 and input transfer by means of endpoints 1 and 2. a control transfer consists of a number of transactions. the command transmitted from the host in the setup transaction is first decoded by the usb function core.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 147 of 706 rej09b0303-0300 when a setup token is received, fvsr is initialized and ep0otc is set to 1, and command reception is enabled. if the received command is a usb standard command (other than getdescriptor or setdescriptor), the ep0otf flag is set and the slave cpu is notified of the fact that a usb standard command has been received. in this case, the remaining transactions in the control transfer are processed within the usb function without intervention by the slave cpu. if the received command is a getdescriptor or setdescriptor command, or a command specific to a device class, the ep0ots flag is set. the slave cpu must read the command from the fifo, then decode and execute it. the remaining transactions in the control transfer must also be processed by the slave cpu using the fifo, etc. input transfers consist of individual in or out transactions. these must all be processed by the slave cpu using the fifo, etc. when processing by the slave cpu is necessary as described above, the communication processing load is shared between the usb function and the slave cpu. the roles of the usb function and the slave cpu, and the flag and bits used in the interface, are shown in table 7.3. table 7.3 role sharing between usb function and slave cpu item/description operating hardware related registers/ flags/bits 1 d+/d? signal analog ? digital conversion port block usb function core ? 2 serial ? parallel conversion/bit stuffing pid determination/addition, crc determination/addition usb function core soff 3 token packet determination/notifying slave cpu of setup usb function core setupf 4 handshake packet determination/generation usb function core dat0/1 pid toggling, fifo rewinding, ack/nak detection/return fvsr, epte ack handshake detection and slave cpu notification/ack handshake return ts, epts data error detection and slave cpu notification/nak handshake return tf, eptf stall handshake return epstl 5 data packet reception/regeneration/transfer to slave cpu usb function core fifo 6 usb command decoding and execution usb function core slave cpu fifo
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 148 of 706 rej09b0303-0300 processing of electrical signals on the usb bus line and processing of signal bit streams is performed by the bus driver/receiver in the port block and the usb function core block. the token/acknowledgment type and data bytes are extracted and, conversely, acknowledgment and data bytes are converted to bit stream electrical signals (items 1 and 2). when a setup token is received, if a getdescriptor or setdescriptor command, or a command specific to a device class, is received, the ep0ots flag is set and the slave cpu is notified (item 3). the command itself is transferred using the fifo, and must be decoded and executed by the slave cpu (item 6). the remaining transactions in the control transfer must also be processed by the slave cpu using the fifo, etc. (items 4 and 5). reception of an in or out token in control transfer or interrupt transfer is not reported to the cpu, and the operation continues with data transfer. in the case of an in transaction, the transmit data is prepared in the fifo beforehand, and if the epte bit is set transmission is started, or if not, a nak handshake is performed. when an in transaction ends, normal or abnormal termination of the transfer is confirmed by means of the host handshake, and is reported to the slave cpu by means of ts/tf/epts/eptf. in the case of an out transaction, an ack handshake is performed when all the data has been received in the fifo, or a nak handshake if it was not possible to receive all the data. with both in transactions and out transactions, a stall handshake is performed if the endpoint is placed in the stall state by means of epstl. 7.3.4 operation when setup token is received (endpoint 0) the group of transactions initiated when the host issues a setup token is called a control transfer. a control transfer consists of three stages: setup, data, and status. control transfers are of two kinds: control write transfers and control read transfers. the type of transfer (read or write) and the number of transfer bytes in the data stage are determined by the 8-byte command transferred out in the setup stage. the setup stage consists of a setup transaction, the data stage may have no transaction or one or more data transactions, and the status stage consists of a single data transaction. the packets contained in each transaction are shown in the table 7.4.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 149 of 706 rej09b0303-0300 table 7.4 packets in each transaction stage token phase data phase handshake phase * 1 setup stage setup token packet out data packet (8 bytes) (host slave) ack handshake packet (slave host) control write transfer data stage out token packet out data packet (host slave) ack/nak/stall handshake packet (slave host) status stage in token packet in data packet (0 bytes) * 2 (slave host) ack handshake packet (host slave) nak/stall handshake packet (slave host) ? control read transfer data stage in token packet in data packet (slave host) ack handshake packet (host slave) nak/stall handshake packet (slave host) ? status stage out token packet out data packet (host slave) ack/nak/stall handshake packet (slave host) no data stage status stage in token packet in data packet (0 bytes) * 2 (slave host) ack handshake packet (host slave) nak/stall handshake packet (slave host) ? notes: 1. this phase is present only if a data packet transfer was executed in the data phase. 2. when all the data in the fifo has been transferred and the fifo is empty, the epte bit is cleared to 0. if an in transaction is then started, a nak handshake is returned. a 0-byte data packet is transferred by setting the epte bit to 1 when the fifo is empty. figure 7.2 shows the operation of the usb function core and the h8 firmware when the usb function receives a setup token (setup transaction). for other cases, see section 7.3.5, operation when out token is received, and section 7.3.6, operation when in token is received.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 150 of 706 rej09b0303-0300 usb host usb function core slave cpu core interface setup token packet output setup token packet reception automatic setting of various flags * 1 usbia (setup) interrupt request data write to ep0o fifo out data packet (8 bytes) reception out data packet (8 bytes) output command data decoding determination of necessity of decoding by slave cpu ack transmission to host nak transmission to slave cpu ack handshake packet reception fvsr0o not updated usbid (ep0otf) interrupt request start of usbia interrupt handling read usbifr * 2 record in user memory etc. that this is state in which decoding is performed by ep0ots interrupt occurring next clear setupf bit to 0 in usbifr end of usbia interrupt handling start of usbid interrupt handling read usbifr confirm tf interrupt read tffr confirm ep0otf interrupt confirm that com- mand decoding by slave cpu is not necessary, and amend record in user memory, etc. clear ep0otf bit to 0 in tffr end of usbid interrupt handling notes: 1. bit ep0otc set to 1 in usbcsr0, fvsr0i and fvsr0o initialized, bits ep0its and ep0ots cleared to 0 in tsfr, bits ep0itf and ep0otf cleared to 0 in tffr, bit ep0stl cleared to 0 in epstlr. 2. as the usbia interrupt is assigned only to the setup interrupt, there is no need for processing to determine the interrupt source. figure 7.2 (1) operation when setup token is received (decoding by slave cpu not required)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 151 of 706 rej09b0303-0300 usb host usb function core core interface setup token packet output setup token packet reception automatic setting of various flags * 1 usbia (setup) interrupt request data write to ep0o fifo out data packet (8 bytes) reception out data packet (8 bytes) output command data decoding determination of necessity of decoding by slave cpu ack transmission to host ack transmission to slave cpu ack handshake packet reception update fvsr0o clear ep0otc bit to 0 in usbcsr0 start of usbia interrupt handling read usbifr * 2 record in user memory etc. that this is state in which decoding is performed by ep0ots interrupt occurring next clear setupf bit to 0 in usbifr end of usbia interrupt handling start of usbid interrupt handling read usbifr confirm ts interrupt read tsfr confirm ep0ots interrupt continued on next page slave cpu notes: 1. bit ep0otc set to 1 in usbcsr0, fvsr0i and fvsr0o initialized, bits ep0its and ep0ots cleared to 0 in tsfr, bits ep0itf and ep0otf cleared to 0 in tffr, bit ep0stl cleared to 0 in epstlr. 2. as the usbia interrupt is assigned only to the setup interrupt, there is no need for processing to determine the interrupt source. usbid (ep0ots) interrupt request decode execution determined from record status in user memory, etc. figure 7.2 (2) operation when setup token is received (decoding by slave cpu required)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 152 of 706 rej09b0303-0300 usb host usb function core core interface read 8 bytes of data in ep0o fifo from epdr0o determine instruction by data decoding if instruction is control-out, set ep0otc bit to 1 in usbcsr0 (write 1 after reading 0) clear ep0ots bit to 0 in tsfr end of usbid interrupt handling slave cpu read fvsr0o confirm presence of 8 bytes of data in ep0o fifo update fvsr0o continued from previous page figure 7.2 (2) operation when setup token is received (decoding by slave cpu required) (cont)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 153 of 706 rej09b0303-0300 7.3.5 operation when out token is received (endpoints 0 and 2) figure 7.3 shows the operation of the usb function core and the h8 firmware when the usb function receives an out token (out transaction). out transactions are used in the data stage and status stage of a control transfer, and in an input transfer. usb host usb function core core interface out token packet output out token packet reception data write to ep2 fifo out data packet (8 bytes) reception out data packet (8 bytes) output ack transmission to host ack transmission to slave cpu ack handshake packet reception update fvsr2 usbid (ep2ts) interrupt request * start of usbid interrupt handling read usbifr confirm ts interrupt read tsfr confirm ep2ts interrupt read fvsr2 confirm amount of readable data (8 bytes) read data (8 bytes) in ep2 fifo from epdr2 clear ep2ts bit to 0 in tsfr slave cpu note: * when the ep2ts interrupt is set for usbib or usbic by the intselr0 setting, that interrupt request is generated. when an usbib or usbic interrupt is generated, there is no need for processing to determine the interrupt source. (a register read is necessary in order to write 0 after reading 1.) update fvsr2 end of usbid interrupt handling figure 7.3 (1) operation when out token is received (ep2-out: initial fifo empty)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 154 of 706 rej09b0303-0300 usb host usb function core core interface out token packet output out token packet reception data write not possible because ep2 fifo is full usbid (ep2tf) interrupt request * 1 nak transmission to host out data packet (8 bytes) output nak transmission to slave cpu start of usbid interrupt handling read usbifr confirm tf interrupt slave cpu note: 1. when the ep2tf interrupt is set for usbib or usbic by the intselr0 setting, that interrupt request is generated. when an usbib or usbic interrupt is generated, there is no need for processing to determine the interrupt source. (a register read is necessary in order to write 0 after reading 1.) nak handshake packet reception out data packet (8 bytes) reception read tffr confirm ep2tf interrupt read fvsr2 confirm amount of readable data (16 bytes) read data (16 bytes) in ep2 fifo from epdr2 clear ep2tf bit to 0 in tffr end of usbid interrupt handling update fvsr2 out token packet output out token packet reception data write to ep2 fifo update fvsr2 ack transmission to host out data packet (8 bytes) output ack transmission to slave cpu ack handshake packet reception out data packet (8 bytes) reception retransmission continued on next page figure 7.3 (2) operation when out token is received (ep2-out: initial fifo full)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 155 of 706 rej09b0303-0300 usb host usb function core core interface slave cpu continued from previous page note: 2. when the ep2ts interrupt is set for usbib or usbic by the intselr0 setting, that interrupt request is generated. when an usbib or usbic interrupt is generated, there is no need for processing to determine the interrupt source. (a register read is necessary in order to write 0 after reading 1.) usbid (ep2ts) interrupt request * 2 start of usbid interrupt handling read usbifr confirm ts interrupt read tsfr confirm ep2ts interrupt read fvsr2 confirm amount of readable data (8 bytes) read data (8 bytes) in ep2 fifo from epdr2 clear ep2ts bit to 0 in tsfr end of usbid interrupt handling update fvsr2 figure 7.3 (2) operation when out token is received (ep2-out: initial fifo full) (cont) 7.3.6 operation when in token is received (endpoints 0, 1, and 2) figure 7.4 shows the operation of the usb function core and the h8 firmware when the usb function receives an in token (in transaction). in transactions are used in the data stage and status stage of a control transfer, and in an input transfer.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 156 of 706 rej09b0303-0300 usb host usb function core core interface in token packet output in token packet reception data read not possible because ep2 fifo is empty nak transmission to host nak handshake packet reception nak transmission to slave cpu start of usbid interrupt handling slave cpu note: 1. when the ep2tf interrupt is set for usbib or usbic by the intselr0 setting, that interrupt request is generated. when an usbib or usbic interrupt is generated, there is no need for processing to determine the interrupt source. (a register read is necessary in order to write 0 after reading 1.) usbid (ep2tf) interrupt request * 1 read usbifr confirm tf interrupt read tffr confirm ep2tf interrupt read fvsr2 confirm amount of data writable (16 bytes) write amount of data writable in ep2 fifo into epdr2 set ep2te bit to 1 in ptter clear ep2tf bit to 0 in tffr end of usbid interrupt handling data write to ep2 fifo update fvsr2 data transmission enabled in token packet output in token packet reception data read from ep2 fifo in data packet transmission in data packet reception ack reception retransmission ack handshake packet transmission ack transmission to slave cpu update fvsr2 continued on next page figure 7.4 (1) operation when in token is received (ep2-in: initial fifo empty)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 157 of 706 rej09b0303-0300 usb host usb function core core interface slave cpu continued from previous page note: 2. when the ep2ts interrupt is set for usbib or usbic by the intselr0 setting, that interrupt request is generated. when an usbib or usbic interrupt is generated, there is no need for processing to determine the interrupt source. (a register read is necessary in order to write 0 after reading 1.) usbid (ep2ts) interrupt request * 2 start of usbid interrupt handling read usbifr confirm ts interrupt read tsfr confirm ep2ts interrupt read fvsr2 confirm amount of data writable write amount of data writable in ep2 fifo into epdr2 set ep2te bit to 1 in ptter clear ep2tsf bit to 0 in tsfr end of usbid interrupt handling update fvsr2 data transmission enabled data write to ep2 fifo figure 7.4 (1) operation when in token is received (ep2-in: initial fifo empty) (cont)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 158 of 706 rej09b0303-0300 usb host usb function core core interface in token packet output in token packet reception data read from ep2 fifo in data packet (8 bytes) transmission in data packet (8 bytes) reception ack reception ack transmission to slave cpu ack handshake packet transmission update fvsr2 usbid (ep2ts) interrupt request * start of usbid interrupt handling read usbifr confirm ts interrupt read tsfr confirm ep2ts interrupt read fvsr2 confirm amount of data writable (8 bytes) write amount of data writable in ep2 fifo into epdr2 set ep2te bit to 1 in ptter slave cpu note: * when the ep2ts interrupt is set for usbib or usbic by the intselr0 setting, that interrupt request is generated. when an usbib or usbic interrupt is generated, there is no need for processing to determine the interrupt source. (a register read is necessary in order to write 0 after reading 1.) data write to ep2 fifo clear ep2ts bit to 0 in tsfr end of usbid interrupt handling update fvsr2 data transmission enabled figure 7.4 (2) operation when in token is received (ep2-in: initial fifo full)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 159 of 706 rej09b0303-0300 7.3.7 suspend/resume operations if the usb data line is idle for a period longer than that stipulated in the usb specification, the h8/3567 group ? s usb hubs and usb function automatically enter the suspend state. the suspend state is automatically cleared (i.e. operation is resumed) when the upstream side (host) restarts data transmission, but operation can also be forcibly resumed by the usb function (remote wakeup). changes in the suspend/resume state can be ascertained by means of the spndif and spndof flags. remote wakeup is executed by setting the dvr bit. 7.3.8 usb module reset and operation-halted states a reset or operation-halted state can be set for the usb module by means of a number of control bits. for information on sequential setting of these bits when starting up the usb module, see section 7.3.9, usb module startup sequence. there are several kinds of usb module reset and operation-halted state, as listed below. in the hardware standby and reset, the entire usb module is initialized. in the descriptions of individual bits in the register descriptions, this initialization condition is not indicated, and only ? (initial value) ? is shown. 1. hardware standby state 2. reset state 3. module stop state 4. software standby state 5. usb function stop state 6. usb function only state 7. usb bus reset state 8. usb suspend state hardware standby state: when the h8/3567 group ? s stby pin is driven low, the chip enters the hardware standby state. in the hardware standby state, all the h8/3567 group ? s initializable registers and internal states are initialized, and all h8/3567 group pins go to the high-impedance state. xtal-extal system clock oscillation and xtal12-extal12 usb clock oscillation both halt. reset state: when the h8/3567 group ? s res pin is driven low, the chip enters the reset state. in the reset state, all the h8/3567 group ? s initializable registers and internal states are initialized, and all h8/3567 group pins go to the input state. xtal-extal system clock oscillation is enabled.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 160 of 706 rej09b0303-0300 module stop state: when bit 1 of mstpcr is set to 1, the usb module enters the module stop state. in the module stop state, supply of system clock to the usb module is stopped. however, when usb clocks (xtal12, extal12) are selected as usb operating clocks, the usb module does not stop the operation. when setting the usb module stop state, return the value of upllcr to the initial state. also, it is recommended to return the value of usbcr to the initial state to prepare for cancellation of the module stop state. as bit 1 of mstpcr is initialized to 1 by a transition to hardware standby mode or a reset, the usb module is in the module stop state after reset release. software standby state: when a sleep instruction is executed after setting the ssby bit to 1 in sbycr, the chip enters the software standby state. in the software standby state the usb module does not enter the reset or operation-halted state. however, since the usb function cannot fulfill its role when the slave cpu halts due to a transition to the software standby state, operation of the usb function must be halted before the software standby state setting is made. set the fncstp bit to 1 in usbcr to disc onnect the usb function from the bus (see usb function stop state below). in the software standby state, xtal-extal system clock oscillation halts. if the system clock has been set as the usb operating clock by means of the cksel bits in upllcr, the usb hubs cannot operate, either, since the clock is halted. if the usb clock (xtal12-extal12) has been set as the usb operating clock, the hub block alone can operate. usb function stop state: when the fncstp bit is set to 1 in usbcr, the usb function stop state is entered. in the usb function stop state, the usb function is disconnected from the bus. if the fonly bit has been cleared to 0 in usbcr, internal connection between the usb function and usb hub is also cut. if the fonly bit has been set to 1, the usb function is connected to the upstream port usd+/usd ? pins. if the fncstp bit and fsrst bits are both set to 1, the usd+/usd ? pins go to the high-impedance state. the usb operating clock supply to the usb function block is halted. clearing the usb function stop state requires execution of the usb function block related sequence described in section 7.3.9, usb module startup sequence. when setting the usb function stop state, it is recommended that the uifrst, fpllrst, and fsrst bits be set to 1 in usbcr in preparation for reduced current dissipation and release. as a result, the following registers are initialized.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 161 of 706 rej09b0303-0300 registers uifrst/fsrs notes epdr2, epdr1, epdr0o, epdr0i fsrst fvsr2, fvsr1, fvsr0o, fvsr0i fsrst epszr1 uifrst usbier uifrst usbifr, tsfr, tffr fsrst usbcsr0 fsrst bits 3 to 0 only epstlr fsrst epdir uifrst intselr0, intselr1 uifrst usb function only state: when the fonly bit is set to 1 in usbcr, the usb function only state is entered. in the usb function stop state, the usb function is connected to the upstream port, and the usb operating clock supply to the usb hub block is halted. it is recommended that usb hub block operation be halted by setting the hsrst bit to 1. this will place the downstream ports in the high-impedance state and enable port d, which also has a downstream port function, to operate as a general i/o port. hoccr s hould be initialized to h'00. usb bus reset state: when a new device is connected to the usb bus, or when error recovery is executed, the usd+/usd ? pin signals go to the bus reset state for a given period. in the usb function, the bus reset interrupt flag is set to 1 when a usb bus reset is detected. a bus reset initializes the usb hub internal state to the default state. control registers that select the usb function internal state and usb function operating state are not initialized by a usb bus reset. these registers must be initialized by setting the fsrst bit to 1. registers initialized by the uifrst bit are not initialized by a usb bus reset. usb suspend state: if the usb bus remains idle for longer than a certain time, the usb hub block and usb function block enter the suspend state. in the suspend state, some operating clocks are halted internally and current dissipation is reduced. when the usb function enters the suspend state, or when the suspend state is cleared by a change in the usd+/usd ? pin signals, the suspend in interrupt flag or suspend out interrupt flag, respectively, is set to 1. the remote wakeup from the suspend state can be executed by write 1 to the dvr bit in devrsmr.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 162 of 706 rej09b0303-0300 7.3.9 usb module startup sequence component elements: the usb module has a number of component elements requiring startup in a fixed sequence by firmware (an h8 program) to ensure normal operation and correct recognition by the usb host. the usb components that need to be considered are as follows: a. usb clock pulse generator (12 mhz), usb operating clock generation pll (48 mhz) b. usb bus clock synchronization dpll (12 mhz) c. epinfo ? endpoint configuration information d. slave cpu, core interface e. usb hub core, usb function core a. usb clock pulse generator (12 mhz), usb operating clock generation pll (48 mhz) the usb clock pulse generator is connected to xtal12-extal12 and generates a 12 mhz usb clock. the usb operating clock pll, multiplies the clock input from the usb clock pulse generator or system clock pulse generator to give a 48 mhz clock. the input clock frequency must be 8, 12, 16, or 20 mhz. as usb clock pulse generator oscillation has not started when a system reset is released, an oscillation stabilization period 10 ms that includes the usb operating clock pll must be provided by firmware. oscillation is started when xtal12-extal12 is set as the usb clock source with the cksel bits in upllcr. the pll multiplication factor is selected with the pfsel bits in upllcr. while waiting for oscillation to stabilize 10 ms, the uifrst, hpllrst, hsrst, fpllrst, and fsrst bits are set to 1 in usbcr, placing the usb bus clock synchronization dpll, usb hub core, usb function core, etc., in the reset state. b. usb bus clock synchronization dpll (12 mhz) usb data transfer is performed at a maximum rate of 12 mbps. the bit data sampling timing can be controlled by adjusting the phase during reception of the synchronization pattern that precedes a packet, using the 48 mhz usb operating clock. this mechanism is called the usb bus clock synchronization dpll. a usb bus clock synchronization dpll operation stabilization period must be provided by firmware. while waiting for operation to stabilize, the hsrst and fsrst bits are set to 1 in usbcr, placing the usb hub core, usb function core, etc., in the reset state. an operation stabilization period of at least ten 48 mhz clock cycles is recommended.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 163 of 706 rej09b0303-0300 c. epinfo ? endpoint configuration information the usb function core block can handle both bulk transfer and isochronous transfer, but for reasons related to the cpu interface specifications and the data transfer capability of the cpu itself, the h8 handles only control transfer and interrupt transfer processing. information comprising settings for the number of endpoints, supported transfer types, maximum packet byte length, etc. (epinfo) is written to the usb function block by firmware each time the usb function is initialized. in the h8/3567u and h8/3564u, three alternates are provided, and epinfo is written for all three. however, since firmware has no way of knowing which alternate the host has selected, the module will not operate normally if the choice of alternate is changed during operation. the same alternate must be designated in the host driver software and the slave firmware. table 7.5 shows the endpoint configuration information to be written to the usb function block. write all 65 one-byte values to epdr01 in the order a1, a2, .... a5, b1, b2, .... m4, m5. table 7.5 endpoint configuration information 12345 a h'00 h'00 h'11 h'00 h'00 b h'14 h'38 h'10 h'00 h'01 c h'24 h'38 h'10 h'00 h'02 d h'14 h'78 h'10 h'00 h'01 e h'24 h'70 h'10 h'00 h'02 f h'14 h'b8 h'20 h'00 h'01 g h'35 h'20 h'10 h'00 h'03 h h'45 h'20 h'10 h'00 h'04 i h'55 h'20 h'10 h'00 h'05 j h'65 h'20 h'10 h'00 h'06 k h'36 h'20 h'10 h'00 h'03 l h'46 h'20 h'10 h'00 h'04 m h'56 h'20 h'10 h'00 h'05 d. slave cpu, core interface these are the basic parts that execute firmware. the slave cpu begins operating immediately after reset release, whereas core interface access is enabled when the module stop state is cleared.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 164 of 706 rej09b0303-0300 e. usb hub core, usb function core these are the central parts of the usb interface. implementation of the usb bus interface is made possible by normal operation of component elements a to d. initial operation procedures: the initial operation procedures for the usb hubs and usb function are shown in figures 7.5 and 7.6. when the usb module is used as a compound device, these two initial operation procedures must be executed, first for the usb hubs, then for the usb function. clear the uifrst bit to 0 before executing the usb function block procedure. the compound device initial operation procedure is summarized below. 1. h8 is in power-off or hardware standby state 2. power-on, stby pin high-level application, etc., is performed, and finally high level is applied to res pin and h8 starts operating 3. usbe bit in stcr is set to 1 by firmware 4. usb module is released from module stop state by firmware 5. fonly bit is cleared to 0 by firmware 6. hoccr and pllcr are set by firmware; wait for usb operating clock oscillation to stabilize 7. after elapse of 10 ms oscillation stabilization time, hpllrst bit is cleared to 0 by firmware 8. after dpll operation stabilization time, hsrst bit is cleared to 0 by firmware a. usb host (upstream port) performs usb hub block bus reset b. usb host performs usb hub block configuration c.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 165 of 706 rej09b0303-0300 external event slave cpu usb function core usb hub core core interface usb operating clock pll power-on reset stby = 0 reset = 0 start of operation clock oscillation standby release stby = 1 reset release reset = 1 system operation set usbe bit to 1 in stcr usb module stop release system clock oscillation hoccr usbcr upllcr access ok clear fonly bit to 0 in usbcr connect usb hub to upstream port downstream port control setting usb operating clock oscillation usbcr hpllrst = 0 hoccr setting upllcr setting wait for usb operating clock oscillation stabilization time (10 ms) clear hpllrst bit to 0 in usbcr wait for dpll block operation stabilization clear hsrst bit to 0 in usbcr usbcr hsrst = 0 start of usb operating clock supply start of dpll block operation bus reset by host internal state reset release configuration by host start of usb hub operation figure 7.5 usb hub initial operation procedure
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 166 of 706 rej09b0303-0300 external event slave cpu usb function core usb hub core core interface usb operating clock pll power-on reset stby = 0 reset = 0 start of operation clock oscillation standby release stby = 1 reset release reset = 1 system operation set usbe bit to 1 in stcr usb module stop release system clock oscillation hoccr usbcr upllcr access ok compound device upllcr setting usb operating clock oscillation clear uifrst bit to 0 in usbcr usb function related register settings clear fncstp bit to 0 in usbcr (wait for usb operating clock oscillation stabilization time (10 ms)) clear fpllrst bit to 0 in usbcr wait for dpll block operation stabilization clear fsrst bit to 0 in usbcr usb function related register access ok continued on next page usb function operation setting usb function connection usbcr fpllrst = 0 usbcr fsrst = 0 start of usb operating clock supply start of dpll block operation internal state reset release figure 7.6 usb function initial operation procedure
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 167 of 706 rej09b0303-0300 external event slave cpu usb function core usb hub core core interface usb operating clock pll epinfo write to epdr0i epinfo transfer to core continued from previous page set epivld bit to 1 in usbcsr0 bus reset interrupt handling (no action) end of epinfo transfer bus reset interrupt request epinfo recording end of epinfo recording bus reset by host configuration by host start of usb function operation figure 7.6 usb function initial operation procedure (cont) disconnection/reconnection procedures: the initial operation procedures for usb hub/usb function disconnection and reconnection are shown in figures 7.7 to 7.10. there are three kinds of usb function disconnection: compound device hub block upstream disconnection, upstream disconnection in usb function standalone mode, and compound device function block disconnection by firmware. in the case of upstream disconnection, the usb bus continues in the idle state, and so the suspend state is entered. in order to detect reconnection, some method independent of the usb protocol is needed, such as detecting vbus connection by means of an interrupt. trigger events (such as cutoff of the system power supply) whereby the usb function block is disconnected by firmware also require detection by means of a separate interrupt, etc. when usb hub upstream disconnection occurs in the compound device state, the usb function block enters the suspend state. when upstream reconnection is detected by means of an external interrupt, etc., initialization of both the usb hub block and usb function block is performed by firmware.
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 168 of 706 rej09b0303-0300 the compound device upstream port disconnection/reconnection procedure is as follows: 1. upstream port is disconnected 2. usb hub block and usb function block enter suspend state, and suspend in interrupt is generated in usb function block 3. upstream port is reconnected 4. upstream port reconnection is detected by means of external interrupt, etc. 5. hsrst and fsrst bits are set to 1 by firmware 6. step 8 in initial operation procedure is executed 7 onward: operations from step 12 onward in initial operation procedure are executed the compound device usb function block disconnection/reconnection procedure is as follows: 1. state requiring disconnection of usb function is detected 2. bits fncstp, fpllrst, and fsrst are set to 1 if necessary, software standby mode is set 3. detection of event enabling reconnection of usb function software standby mode is exited 4. if necessary, usb function control registers are re-set 5. fncstp bit is cleared to 0 6. fpllrst bit is cleared to 0 7. fsrst bit is cleared to 0 8 onward: operations from step 13 onward in initial operation procedure are executed
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 169 of 706 rej09b0303-0300 external event slave cpu usb function core usb hub core core interface usb operating clock pll upstream port disconnection reconnection recognized by means of external interrupt set hsrst bit to 1 in usbcr usb operating clock halted suspend state transition upstream port reconnection usb operating clock supply halted usbcr hsrst = 1 usb operating clock oscillation internal state reset usb operating clock supply started suspend state release wait for dpll block operation stabilization clear hsrst bit to 0 in usbcr usbcr hsrst = 0 internal state reset release bus reset by host configuration by host start of usb hub operation figure 7.7 usb hub block upstream disconnection/reconnection
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 170 of 706 rej09b0303-0300 external event slave cpu usb function core usb hub core core interface usb operating clock pll upstream port disconnection reconnection recognized by means of external interrupt set hsrst bit and fsrst bit to 1 in usbcr usb hub operating clock halted suspend state transition upstream port reconnection usb operating clock supply halted usbcr hsrst = 1 fsrst = 1 usb operating clock oscillation internal state reset usb operating clock supply started suspend state release wait for dpll block operation stabilization clear hsrst bit to 0 in usbcr usbcr hsrst = 0 internal state reset release suspend in interrupt handling set ckstop bit to 1 in usbcsr0 suspend state transition suspend in interrupt request usb function operating clock halted usb operating clock supply halted internal state reset usb operating clock supply started suspend state release clear fsrst bit to 0 in usbcr usbcr fsrst = 0 internal state reset release bus reset by host epinfo write to epdr0i epinfo transfer to core epinfo recording set epivld bit to 1 in usbcsr0 end of epinfo transfer end of epinfo recording continued on next page figure 7.8 usb compound device upstream disconnection/reconnection
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 171 of 706 rej09b0303-0300 external event slave cpu usb function core usb hub core core interface usb operating clock pll configuration by host start of usb hub operation usb function connection recognized bus reset by host bus reset interrupt request bus reset interrupt handling (no action) configuration by host start of usb function operation continued from previous page figure 7.8 usb compound device upstream disconnection/reconnection (cont)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 172 of 706 rej09b0303-0300 external event slave cpu usb function core usb hub core core interface usb operating clock pll upstream port disconnection suspend in interrupt handling set ckstop bit to 1 in usbcsr0 suspend in interrupt request suspend state transition usb function operating clock halted usb operating clock supply halted upstream port reconnection reconnection recognized by means of external interrupt set fsrst bit to 1 in usbcr usbcr fsrst = 1 usb operating clock oscillation internal state reset usb operating clock supply started suspend state release internal state reset release usbcr fsrst = 0 wait for dpll block operation stabilization clear fsrst bit to 0 in usbcr epinfo write to epdr0i epinfo transfer to core epinfo recording set epivld bit to 1 in usbcsr0 end of epinfo transfer end of epinfo recording bus reset interrupt handling (no action) bus reset interrupt request bus reset by host configuration by host start of usb hub operation figure 7.9 usb function standalone mode upstream disconnection/reconnection
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 173 of 706 rej09b0303-0300 external event slave cpu usb function core usb hub core core interface usb operating clock pll trigger event detection of state requiring disconnection usbcr fncstp = 1 fpllrst = 1 fsrst = 1 usb function disconnection dpll block operation halted internal state reset usb function disconnection recognized set bits fncstp, fpllrst, fsrst to 1 in usbcr trigger event detection of state enabling reconnection if necessary, re-set usb function related registers usb function operation re-setting clear fncstp bit to 0 in usbcr usb function connection usb operating clock oscillation usb operating clock supply halted usb function connection recognized clear fpllrst bit to 0 in usbcr usbcr fpllrst = 0 dpll block operation started wait for dpll block operation stabilization clear fsrst bit to 0 in usbcr usbcr fsrst = 0 internal state reset release continued on next page figure 7.10 usb function block disconnection/reconnection
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 174 of 706 rej09b0303-0300 external event slave cpu usb function core usb hub core core interface usb operating clock pll epinfo write to epdr0i epinfo transfer to core epinfo recording continued from previous page set epivld bit to 1 in usbcsr0 bus reset interrupt handling (no action) end of epinfo transfer end of epinfo recording bus reset interrupt request bus reset by host configuration by host start of usb function operation figure 7.10 usb function block disconnection/reconnection (cont)
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 175 of 706 rej09b0303-0300 7.3.10 usb module slave cpu interrupts the usb module has four slave cpu interrupt sources: usbia, usbib, usbic and usbid. table 7.6 shows the interrupt sources and their priority order. the interrupt sources are the usbifr and tsfr/tffr interrupt flags. for each interrupt, the interrupt flag can be enabled or disabled by means of the corresponding interrupt enable bit in usbier. in the usbid interrupt handling routine, usbifr and tsfr/tffr must be read to determine the interrupt source before processing is carried out. table 7.6 usb interrupt sources interrupt source description priority usbia interrupt initiated by setup high usbib interrupt initiated by epts or eptf of endpoint specified by intselr0 usbic interrupt initiated by epts or eptf of endpoint specified by intselr0 usbid interrupt initiated by sof, spnd, brst, ts, or tf low
section 7 universal serial bus interface (usb) rev. 3.00 mar 17, 2006 page 176 of 706 rej09b0303-0300
section 8 i/o ports rev. 3.00 mar 17, 2006 page 177 of 706 rej09b0303-0300 section 8 i/o ports 8.1 overview the h8/3577 group has six input/output ports (ports 1 to 6), and one input-only port (port 7). the h8/3567 group has four input/output ports (ports 1, 4, 5, and 6), and one input-only port. h8/3567 group models with an on-chip usb have additional usb pins plus two input/output ports (ports c and d) for controlling the usb power supply circuit. table 8.1 summarizes the port functions. the pins of each port also have other functions. each port includes a data direction register (ddr) that controls input/output (not provided for the input-only ports), and a data register (dr) that stores output data. h8/3577 group ports 1 to 3 have a built-in mos input pull-up function, and use ddr and a mos input pull-up control register (pcr) to control the on/off status of the mos input pull-ups. ports 1 to 6 can drive one ttl load and a 30 pf capacitive load. all the input/output ports can drive a darlington transistor pair when in output mode. the output type of pin p5 2 in port 5 and pin p4 7 in port 4 is nmos push-pull. port c has the same load drive capacity as ports 1 to 6. port d also has a usb hub downstream input/output function, and operates on the usb power supply (3.3 v).
section 8 i/o ports rev. 3.00 mar 17, 2006 page 178 of 706 rej09b0303-0300 table 8.1 h8/3577 group and h8/3567 group port functions port summary pins description port 1 ? 8-bit i/o port built-in mos input pull-up (h8/3577 group only) p1 7 /pw 7 (/scl 1 ) p1 6 /pw 6 (/sda 1 ) p1 5 /pw 5 (/cblank) p1 4 /pw 4 p1 3 /pw 3 p1 2 /pw 2 p1 1 /pw 1 /pwx 1 p1 0 /pw 0 /pwx 0 i/o port also functioning as pwm timer output pins (pw 7 to pw 0 , pwx 1 , pwx 0 ) (both h8/3577 and h8/3567 group) additional functions: timer connection output pin (cblank) and i 2 c bus interface 1 i/o pins (scl 1 , sda 1 ) (h8/3567 group only) port 2 8-bit i/o port h8/3577 group: present h8/3567 group: absent built-in mos input pull-up (h8/3577 group only) p2 7 /pw 15 /cblank p2 6 /pw 14 p2 5 /pw 13 p2 4 /pw 12 /scl 1 p2 3 /pw 11 /sda 1 p2 2 /pw 10 p2 1 /pw 9 p2 0 /pw 8 i/o port also functioning as pwm timer output pins (pw 15 to pw 8 ), or timer connection output pin (cblank) and i 2 c bus interface 1 i/o pins (scl 1 , sda 1 ) port 3 8-bit i/o port h8/3577 group: present h8/3567 group: absent built-in mos input pull-up (h8/3577 group only) p3 7 to p3 0 i/o port port 4 8-bit i/o port p4 7 /sda 0 i/o port also functioning as i 2 c bus interface 0 i/o pin (sda0) p4 6 / when ddr = 0 (after reset): input port when ddr = 1: output pin p4 5 to p4 3 i/o ports p4 2 / irq 0 p4 1 / irq 1 i/o ports also functioning as external interrupt input pins ( irq 0 , irq 1 ) p4 0 / irq 2 / adtrg i/o port also functioning as external interrupt input pin ( irq 2 ) and a/d converter external trigger input pin ( adtrg )
section 8 i/o ports rev. 3.00 mar 17, 2006 page 179 of 706 rej09b0303-0300 port summary pins description port 5 3-bit i/o port p5 2 /sck 0 /scl 0 p5 1 /rxd 0 p5 0 /txd 0 i/o port also functioning as sci0 i/o pins (txd 0 , rxd 0 , sck 0 ) and i 2 c bus interface 0 i/o pin (scl 0 ) port 6 8-bit i/o port p6 7 /tmox/tmo 1 /hsynco p6 6 /ftob/tmri 1 /csynci p6 5 /ftid/tmci 1 /hsynci p6 4 /ftic/tmo 0 /clampo p6 3 /ftib/tmri 0 /vfbacki p6 2 /ftia/tmiy/vsynci p6 1 /ftoa/vsynco p6 0 /ftci/tmix/tmci 0 / hfbacki i/o port also functioning as frt i/o pins (ftci, ftoa, ftia, ftib, ftic, ftid, ftob), 8-bit timer 0 and 1 i/o pins (tmci 0 , tmri 0 , tmo 0 , tmci 1 , tmri 1 , tmo 1 ), 8-bit timer x and y i/o pins (tmox, tmix, tmiy), and timer connection i/o pins (hsynco, csynci, hsynci, clampo, vfbacki, vsynci, vsynco, hfbacki) port 7 8-bit input port (h8/3577 group) 4-bit input port (h8/3567 group) p7 7 to p7 4 /an 7 to an 4 p7 3 to p7 0 /an 3 to an 0 i/o port also functioning as a/d converter analog inputs (an 7 to an 0 ) port c 8-bit i/o port (h8/3567 group version with on-chip usb only) pc 7 to pc 4 / ocp 5 to ocp 2 pc 3 to pc 0 / enp 5 to enp 2 i/o port also functioning as external power supply circuit overcurrent detection signal input pins ( ocp 5 to ocp 2 ) and power output enable signal output pins ( enp 5 to enp 2 ) port d 8-bit i/o port (h8/3567 group version with on-chip usb only) power supply: drvcc (3.3 v) pd 7 /ds5d?, pd6/ds5d+, pd 5 /ds4d?, pd4/ds4d+, pd 3 /ds3d?, pd2/ds3d+, pd 1 /ds2d?, pd0/ds2d+ i/o port also functioning as usb downstream i/o pins
section 8 i/o ports rev. 3.00 mar 17, 2006 page 180 of 706 rej09b0303-0300 8.2 port 1 8.2.1 overview port 1 is an 8-bit i/o port. port 1 is also used for 8-bit pwm output (pw 7 to pw 0 ), 14-bit pwm output (pwx 1 , pwx 0 ), timer connection output (cblank) [h8/3567 group only], and iic1 input/output (scl 1 , sda 1 ) [h8/3567 group only]. in the h8/3577 group, port 1 has a built-in mos input pull-up function that can be controlled by software. figure 8.1 shows the port 1 pin configuration. p1 7 (input/output) / scl 1 (h8/3567 group: input/output) p1 6 (input/output) / sda 1 (h8/3567 group: input/output) p1 5 (input/output) / cblank (h8/3567 group: output) p1 4 (input/output) p1 3 (input/output) p1 2 (input/output) p1 1 (input/output) / pwx 1 (output) p1 0 (input/output) / pwx 0 (output) when p1ddr = 1 and pwoera = 1 pw 7 (output) / scl 1 (h8/3567 group: input/output) pw 6 (output) / sda 1 (h8/3567 group: input/output) pw 5 (output) / cblank (h8/3567 group: output) pw 4 (output) pw 3 (output) pw 2 (output) pw 1 (output) / pwx 1 (output) pw 0 (output) / pwx 0 (output) port 1 p1n: input pin when p1ddr = 0, output pin when p1ddr = 1 and pwoera = 0 figure 8.1 port 1 pin functions
section 8 i/o ports rev. 3.00 mar 17, 2006 page 181 of 706 rej09b0303-0300 8.2.2 register configuration table 8.2 shows the port 1 register configuration. table 8.2 port 1 registers name abbreviation r/w initial value address port 1 data direction register p1ddr w h'00 h'ffb0 port 1 data register p1dr r/w h'00 h'ffb2 port 1 mos pull-up control register * [h8/3577 group only] p1pcr r/w h'00 h'ffac note: * p1pcr cannot be read or written to in the h8/3567 group. a read will return an undefined value. port 1 data direction register (p1ddr) bit 76543210 p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr initial value00000000 read/write w wwwwwww p1ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. p1ddr cannot be read; if it is, an undefined value will be returned. p1ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. setting a p1ddr bit to 1 makes the corresponding port 1 pin an output port or pwm output, while clearing the bit to 0 makes the pin an input port. p1 0 and p1 1 can be used for pwmx output regardless of the p1ddr settings. in the h8/3567 group, p1 7 , p1 6 , and p1 5 can be used for supporting function output or input/output regardless of the p1ddr settings.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 182 of 706 rej09b0303-0300 port 1 data register (p1dr) bit 76543210 p1 7 dr p1 6 dr p1 5 dr p1 4 dr p1 3 dr p1 2 dr p1 1 dr p1 0 dr initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w p1dr is an 8-bit readable/writable register that stores output data for the port 1 pins (p1 7 to p1 0 ). if a port 1 read is performed while p1ddr bits are set to 1, the p1dr values are read directly regardless of the actual pin states. if a port 1 read is performed while p1ddr bits are cleared to 0, the pin states are read. p1dr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. port 1 mos pull-up control register (p1pcr) bit 76543210 p1 7 pcr p1 6 pcr p1 5 pcr p1 4 pcr p1 3 pcr p1 2 pcr p1 1 pcr p1 0 pcr initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w p1pcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port 1 on a bit-by-bit basis. when a p1ddr bit is cleared to 0 (input port setting), setting the corresponding p1pcr bit to 1 turns on the mos input pull-up for that pin. p1pcr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. 8.2.3 pin functions port 1 is used for pwm output or as an i/o port, with input or output specifiable individually for each pin. setting a p1ddr bit to 1 makes the corresponding port 1 pin a pwm output or output port, while clearing the bit to 0 makes the pin an input port. p1 0 and p1 1 can be used for pwmx output regardless of the p1ddr settings.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 183 of 706 rej09b0303-0300 in the h8/3567 group, p1 7 , p1 6 , and p1 5 also function as iic1 i/o pins (scl 1 , sda 1 ) and the timer connection output pin (cblank). p1 7 , p1 6 , and p1 5 can be used for supporting function input/output regardless of the p1ddr settings. port 1 pin functions are shown in table 8.3. table 8.3 port 1 pin functions pin pin functions and selection method p1 7 /pw 7 (/scl 1 ) the pin function is selected as shown below by a combination of bit ice in iccr of iic1 (h8/3567 group), bit oe7 in pwoera, and bit p1 7 ddr. ice 0 1 p1 7 ddr 0 1 ? pwoera: oe7 ? 01 ? pin function p1 7 input p1 7 output pw 7 output scl 1 i/o p1 6 /pw 6 (/sda 1 ) the pin function is selected as shown below by a combination of bit ice in iccr of iic1 (h8/3567 group), bit oe6 in pwoera, and bit p1 6 ddr. ice 0 1 p1 6 ddr 0 1 ? pwoera: oe6 ? 01 ? pin function p1 6 input p1 6 output pw 6 output sda 1 i/o p1 5 /pw 5 (/cblank) the pin function is selected as shown below by a combination of bit cbe in timer connection tconr0 (h8/3567 group), bit oe5 in pwoera, and bit p1 5 ddr. cbe 0 1 p1 5 ddr 0 1 ? pwoera: oe5 ? 01 ? pin function p1 5 input p1 5 output pw 5 output cblank output
section 8 i/o ports rev. 3.00 mar 17, 2006 page 184 of 706 rej09b0303-0300 pin pin functions and selection method p1 4 /pw 4 p1 4 ddr 0 1 pwoera: oe4 0 0 1 pin function p1 4 input p1 4 output pw 4 output p1 3 /pw 3 p1 3 ddr 0 1 pwoera: oe3 0 0 1 pin function p1 3 input p1 3 output pw 3 output p1 2 /pw 2 p1 2 ddr 0 1 pwoera: oe2 0 0 1 pin function p1 2 input p1 2 output pw 2 output p1 1 /pw 1 / pwx 1 the pin function is selected as shown below by a combination of bit oeb in dacr of pwmx, bit oe1 in pwoera, and bit p1 1 ddr. dacr: oeb 0 1 p1 1 ddr 0 1 ? pwoera: oe1 ? 01 ? pin function p1 1 input p1 1 output pw 1 output pwx 1 output p1 0 /pw 0 / pwx 0 the pin function is selected as shown below by a combination of bit oea in dacr of pwmx, bit oe0 in pwoera, and bit p1 0 ddr. dacr: oea 0 1 p1 0 ddr 0 1 ? pwoera: oe0 ? 01 ? pin function p1 0 input p1 0 output pw 0 output pwx 0 output
section 8 i/o ports rev. 3.00 mar 17, 2006 page 185 of 706 rej09b0303-0300 8.2.4 mos input pull-up function in the h8/3577 group, port 1 has a built-in mos input pull-up function that can be controlled by software. when a p1ddr bit is cleared to 0, setting the corresponding p1pcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset and in hardware standby mode. the previous state is retained in software standby mode. table 8.4 summarizes the mos input pull-up states. table 8.4 mos input pull-up states (port 1) reset hardware standby mode software standby mode in other operations off off on/off on/off legend: off: mos input pull-up is always off. on/off: on when p1ddr = 0 and p1pcr = 1; otherwise off.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 186 of 706 rej09b0303-0300 8.3 port 2 [h8/3577 group only] 8.3.1 overview port 2 is an 8-bit i/o port. port 2 is also used for 8-bit pwm output (pw 15 to pw 8 ), timer connection output (cblank), and iic1 input/output (scl 1 , sda 1 ). port 2 is provided in the h8/3577 group, but not in the h8/3567 group. therefore the h8/3567 group does not have the port 2 i/o pin functions or eight 8-bit pwm output pin (pw 15 to pw 8 ) functions, and provides the timer connection output pin (cblank) function and iic1 i/o pin (scl 1 , sda 1 ) functions in port 1. port 2 has a built-in mos input pull-up function that can be controlled by software. figure 8.2 shows the port 2 pin configuration. p2 7 (input/output) / cblank (output) p2 6 (input/output) p2 5 (input/output) p2 4 (input/output) / scl 1 (input/output) p2 3 (input/output) / sda 1 (input/output) p2 2 (input/output) p2 1 (input/output) p2 0 (input/output) when p2ddr = 1 and pwoerb = 1 pw 15 (output) / cblank (output) pw 14 (output) pw 13 (output) pw 12 (output) / scl 1 (input/output) pw 11 (output) / sda 1 (input/output) pw 10 (output) pw 9 (output) pw 8 (output) port 2 p2n: input pin when p2ddr = 0, output pin when p2ddr = 1 and pwoerb = 0 figure 8.2 port 2 pin functions
section 8 i/o ports rev. 3.00 mar 17, 2006 page 187 of 706 rej09b0303-0300 8.3.2 register configuration table 8.5 shows the port 2 register configuration. table 8.5 port 2 registers name abbreviation r/w initial value address port 2 data direction register p2ddr w h'00 h'ffb1 port 2 data register p2dr r/w h'00 h'ffb3 port 2 mos pull-up control register p2pcr r/w h'00 h'ffad port 2 data direction register (p2ddr) bit 76543210 p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr initial value00000000 read/write w wwwwwww p2ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. p2ddr cannot be read; if it is, an undefined value will be returned. p2ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. setting a p2ddr bit to 1 makes the corresponding port 2 pin an output port or pwm output, while clearing the bit to 0 makes the pin an input port. p2 3 , p2 4 , and p2 7 can be used for supporting function output regardless of the p2ddr settings.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 188 of 706 rej09b0303-0300 port 2 data register (p2dr) bit 76543210 p2 7 dr p2 6 dr p2 5 dr p2 4 dr p2 3 dr p2 2 dr p2 1 dr p2 0 dr initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w p2dr is an 8-bit readable/writable register that stores output data for the port 2 pins (p2 7 to p2 0 ). if a port 2 read is performed while p2ddr bits are set to 1, the p2dr values are read directly regardless of the actual pin states. if a port 2 read is performed while p2ddr bits are cleared to 0, the pin states are read. p2dr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. port 2 mos pull-up control register (p2pcr) bit 76543210 p2 7 pcr p2 6 pcr p2 5 pcr p2 4 pcr p2 3 pcr p2 2 pcr p2 1 pcr p2 0 pcr initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w p2pcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port 2 on a bit-by-bit basis. when a p2ddr bit is cleared to 0 (input port setting), setting the corresponding p2pcr bit to 1 turns on the mos input pull-up for that pin. p2pcr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 189 of 706 rej09b0303-0300 8.3.3 pin functions port 2 is used for pwm output, timer connection output (cblank), and iic1 input/output (scl1, sda1), or as an i/o port, with input or output specifiable individually for each pin. setting a p2ddr bit to 1 makes the corresponding port 2 pin a pwm output or output port, while clearing the bit to 0 makes the pin an input port. p2 3 , p2 4 , and p2 7 can be used for supporting function output regardless of the p2ddr settings. port 2 pin functions are shown in table 8.6. table 8.6 port 2 pin functions pin pin functions and selection method p2 7 /pw 15 / cblank the pin function is selected as shown below by a combination of bit cbe in timer connection tconr0, bit oe15 in pwoerb, and bit p2 7 ddr. cbe 0 1 p2 7 ddr 0 1 ? pwoerb: oe15 ? 01 ? pin function p2 7 input p2 7 output pw 15 output cblank output p2 6 /pw 14 p2 6 ddr 0 1 pwoerb: oe14 0 0 1 pin function p2 6 input p2 6 output pw 14 output p2 5 /pw 13 p2 5 ddr 0 1 pwoerb: oe13 0 0 1 pin function p2 5 input p2 5 output pw 13 output p2 4 /pw 12 / scl 1 the pin function is selected as shown below by a combination of bit ice in iccr of iic1, bit oe12 in pwoerb, and bit p2 4 ddr. ice 0 1 p2 4 ddr 0 1 ? pwoerb: oe12 ? 01 ? pin function p2 4 input p2 4 output pw 12 output scl 1 i/o
section 8 i/o ports rev. 3.00 mar 17, 2006 page 190 of 706 rej09b0303-0300 pin pin functions and selection method p2 3 /pw 11 / sda 1 the pin function is selected as shown below by a combination of bit ice in iccr of iic1, bit oe11 in pwoerb, and bit p2 3 ddr. ice 0 1 p2 3 ddr 0 1 ? pwoerb: oe11 ? 01 ? pin function p2 3 input p2 3 output pw 11 output sda 1 i/o p2 2 /pw 10 p2 2 ddr 0 1 pwoerb: oe10 0 0 1 pin function p2 2 input p2 2 output pw 10 output p2 1 /pw 9 p2 1 ddr 0 1 pwoerb: oe9 0 0 1 pin function p2 1 input p2 1 output pw 9 output p2 0 /pw 8 p2 0 ddr 0 1 pwoerb: oe8 0 0 1 pin function p2 0 input p2 0 output pw 8 output
section 8 i/o ports rev. 3.00 mar 17, 2006 page 191 of 706 rej09b0303-0300 8.3.4 mos input pull-up function port 2 has a built-in mos input pull-up function that can be controlled by software. mos input pull-up can be specified as on or off for individual bits. when a p2ddr bit is cleared to 0, setting the corresponding p2pcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset and in hardware standby mode. the previous state is retained in software standby mode. table 8.7 summarizes the mos input pull-up states. table 8.7 mos input pull-up states (port 2) reset hardware standby mode software standby mode in other operations off off on/off on/off legend: off: mos input pull-up is always off. on/off: on when p2ddr = 0 and p2pcr = 1; otherwise off.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 192 of 706 rej09b0303-0300 8.4 port 3 [h8/3577 group only] 8.4.1 overview port 3 is an 8-bit i/o port. port 3 is provided in the h8/3577 group, but not in the h8/3567 group. port 3 has a built-in mos input pull-up function that can be controlled by software. figure 8.3 shows the port 3 pin configuration. p3 7 (input/output) p3 6 (input/output) p3 5 (input/output) p3 4 (input/output) p3 3 (input/output) p3 2 (input/output) p3 1 (input/output) p3 0 (input/output) port 3 figure 8.3 port 3 pin functions 8.4.2 register configuration table 8.8 shows the port 3 register configuration. table 8.8 port 3 registers name abbreviation r/w initial value address port 3 data direction register p3ddr w h'00 h'ffb4 port 3 data register p3dr r/w h'00 h'ffb6 port 3 mos pull-up control register p3pcr r/w h'00 h'ffae
section 8 i/o ports rev. 3.00 mar 17, 2006 page 193 of 706 rej09b0303-0300 port 3 data direction register (p3ddr) bit 76543210 p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr initial value00000000 read/write w wwwwwww p3ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. p3ddr cannot be read; if it is, an undefined value will be returned. p3ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. setting a p3ddr bit to 1 makes the corresponding port 3 pin an output port, while clearing the bit to 0 makes the pin an input port. port 3 data register (p3dr) bit 76543210 p3 7 dr p3 6 dr p3 5 dr p3 4 dr p3 3 dr p3 2 dr p3 1 dr p3 0 dr initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w p3dr is an 8-bit readable/writable register that stores output data for the port 3 pins (p3 7 to p3 0 ). if a port 3 read is performed while p3ddr bits are set to 1, the p3dr values are read directly regardless of the actual pin states. if a port 3 read is performed while p3ddr bits are cleared to 0, the pin states are read. p3dr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. port 3 mos pull-up control register (p3pcr) bit 76543210 p3 7 pcr p3 6 pcr p3 5 pcr p3 4 pcr p3 3 pcr p3 2 pcr p3 1 pcr p3 0 pcr initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w p3pcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port 3 on a bit-by-bit basis.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 194 of 706 rej09b0303-0300 when a p3ddr bit is cleared to 0 (input port setting), setting the corresponding p3pcr bit to 1 turns on the mos input pull-up for that pin. p3pcr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. 8.4.3 pin functions port 3 is used as an i/o port, with input or output specifiable individually for each pin. setting a p3ddr bit to 1 makes the corresponding port 3 pin an output port, while clearing the bit to 0 makes the pin an input port. 8.4.4 mos input pull-up function port 3 has a built-in mos input pull-up function that can be controlled by software. mos input pull-up can be specified as on or off for individual bits. when a p3ddr bit is cleared to 0, setting the corresponding p3pcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset and in hardware standby mode. the previous state is retained in software standby mode. table 8.9 summarizes the mos input pull-up states. table 8.9 mos input pull-up states (port 3) reset hardware standby mode software standby mode in other operations off off on/off on/off legend: off: mos input pull-up is always off. on/off: on when p3ddr = 0 and p3pcr = 1; otherwise off.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 195 of 706 rej09b0303-0300 8.5 port 4 8.5.1 overview port 4 is an 8-bit i/o port. port 4 is also used for external interrupt input ( irq 0 to irq 2 ), a/d converter input ( adtrg ), iic0 input/output (sda0), and system clock ( ) output. the output type of p4 7 is nmos push-pull. the output type of sda0 is nmos open-drain with direct bus drive capability. figure 8.4 shows the port 4 pin configuration. p4 7 (input/output) / sda 0 (input/output) p4 6 (input/output) / irq 0 (input) p4 1 (input/output) / irq 1 (input) p4 0 (input/output) / irq 2 (input) / adtrg (input) port 4 figure 8.4 port 4 pin functions 8.5.2 register configuration table 8.10 shows the port 4 register configuration. table 8.10 port 4 registers name abbreviation r/w initial value address port 4 data direction register p4ddr w h'00 h'ffb5 port 4 data register p4dr r/w h'00 h'ffb7
section 8 i/o ports rev. 3.00 mar 17, 2006 page 196 of 706 rej09b0303-0300 port 4 data direction register (p4ddr) bit 76543210 p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr initial value00000000 read/write w wwwwwww p4ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 4. p4ddr cannot be read; if it is, an undefined value will be returned. p4ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. when p4ddr bits are set to 1, pin p4 6 functions as the output pin, and pins p4 7 and p4 5 to p4 0 function as output ports. clearing a p4ddr bit to 0 makes the corresponding pin an input port. port 4 data register (p4dr) bit 76543210 p4 7 dr p4 6 dr p4 5 dr p4 4 dr p4 3 dr p4 2 dr p4 1 dr p4 0 dr initial value 0 ? * 000000 read/write r/w r r/w r/w r/w r/w r/w r/w note: * determined by the state of pin p4 6 . p4dr is an 8-bit readable/writable register that stores output data for the port 4 pins (p4 7 to p4 0 ). except for p4 6 , if a port 4 read is performed while p4ddr bits are set to 1, the p4dr values are read directly regardless of the actual pin states. if a port 4 read is performed while p4ddr bits are cleared to 0, the pin states are read. p4dr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 197 of 706 rej09b0303-0300 8.5.3 pin functions port 4 pins are also used for external interrupt input ( irq 0 to irq 2 ), a/d converter input ( adtrg ), iic0 input/output (sda 0 ), and system clock ( ) output. port 4 pin functions are shown in table 8.11. table 8.11 port 4 pin functions pin pin functions and selection method p4 7 /sda 0 the pin function is selected as shown below by a combination of bit ice in iccr of iic0 and bit p4 7 ddr. ice 0 1 p4 7 ddr 0 1 ? pin function p4 7 input p4 7 output sda 0 i/o when this pin is designated as the p4 7 output pin, it is an nmos push-pull output. the output type of sda0 is nmos open-drain with direct bus drive capability. p4 6 / irq 0 p4 2 ddr 0 1 pin function p4 2 input p4 2 output irq 0 input when bit irq0e is set to 1 in ier, this pin is used as the irq 0 input pin.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 198 of 706 rej09b0303-0300 pin pin functions and selection method p4 1 / irq 1 p4 1 ddr 0 1 pin function p4 1 input p4 1 output irq 1 input when bit irq1e is set to 1 in ier, this pin is used as the irq 1 input pin. p4 0 / irq 2 /p4 0 ddr 0 1 adtrg pin function p4 0 input p4 0 output irq 2 input, adtrg input when bit irq2e is set to 1 in ier, this pin is used as the irq 2 input pin. when bits trgs1 and trgs0 are both set to 1 in the a/d converter ? s adcr register, this pin is used as the adtrg input pin.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 199 of 706 rej09b0303-0300 8.6 port 5 8.6.1 overview port 5 is a 3-bit i/o port. port 5 is also used for sci0 input/output (txd 0 , rxd 0 , sck 0 ) and iic0 input/output (scl 0 ). the output type of p5 2 and sck 0 is nmos push-pull. the output type of scl 0 is nmos open-drain. figure 8.5 shows the port 5 pin configuration. port 5 pins p5 2 (input/output) / sck 0 (input/output) / scl 0 (input/output) p5 1 (input/output) / rxd 0 (input) p5 0 (input/output) / txd 0 (output) port 5 figure 8.5 port 5 pin functions 8.6.2 register configuration table 8.12 shows the port 5 register configuration. table 8.12 port 5 registers name abbreviation r/w initial value address port 5 data direction register p5ddr w h'f8 h'ffb8 port 5 data register p5dr r/w h'f8 h'ffba
section 8 i/o ports rev. 3.00 mar 17, 2006 page 200 of 706 rej09b0303-0300 port 5 data direction register (p5ddr) bit 76543210 ????? p5 2 ddr p5 1 ddr p5 0 ddr initial value11111000 read/write ????? www p5ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. p5ddr cannot be read; if it is, an undefined value will be returned. bits 7 to 3 are reserved. setting a p5ddr bit to 1 makes the corresponding port 5 pin an output port, while clearing the bit to 0 makes the pin an input port. p5ddr is initialized to h'f8 by a reset and in hardware standby mode. it retains its previous state in software standby mode. as sci0 is initialized, the pin states are determined by iic0?s iccr, p5ddr, and p5dr specifications. port 5 data register (p5dr) bit 76543210 ????? p5 2 dr p5 1 dr p5 0 dr initial value11111000 read/write ????? r/w r/w r/w p5dr is an 8-bit readable/writable register that stores output data for the port 5 pins (p5 2 to p5 0 ). if a port 5 read is performed while p5ddr bits are set to 1, the p5dr values are read directly regardless of the actual pin states. if a port 5 read is performed while p5ddr bits are cleared to 0, the pin states are read. bits 7 to 3 are reserved; they cannot be modified and are always read as 1. p5dr is initialized to h'f8 by a reset and in hardware standby mode. it retains its previous state in software standby mode.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 201 of 706 rej09b0303-0300 8.6.3 pin functions port 5 pins are also used for sci0 input/output (txd 0 , rxd 0 , sck 0 ) and iic0 input/output (scl 0 ). port 5 pin functions are shown in table 8.13. table 8.13 port 5 pin functions pin pin functions and selection method p5 2 /sck 0 / scl 0 the pin function is selected as shown below by a combination of bit c/ a in smr of sci0, bits cke0 and cke1 in scr, bit ice in iccr of iic0, and bit p5 2 ddr. ice 0 1 cke1 0 1 0 c/ a 01 ? 0 cke0 0 1 ?? 0 p5 2 ddr 0 1 ???? pin function p5 2 input p5 2 output sck 0 output sck 0 output sck 0 input scl 0 i/o when this pin is used as the scl 0 i/o pin, bits cke1 and cke0 in scr of sci0 and bit c/ a in smr must all be cleared to 0. the output type of scl 0 is nmos open-drain with direct bus drive capability. when this pin is designated as the p5 2 output pin or sck 0 output pin, it is an nmos push-pull output. p5 1 /rxd 0 the pin function is selected as shown below by a combination of bit re in scr of sci0 and bit p5 1 ddr. re 0 1 p5 1 ddr 0 1 ? pin function p5 1 input p5 1 output rxd 0 input p5 0 /txd 0 the pin function is selected as shown below by a combination of bit te in scr of sci0 and bit p5 0 ddr. te 0 1 p5 0 ddr 0 1 ? pin function p5 0 input p5 0 output txd 0 output
section 8 i/o ports rev. 3.00 mar 17, 2006 page 202 of 706 rej09b0303-0300 8.7 port 6 8.7.1 overview port 6 is an 8-bit i/o port. it is also used for 16-bit free-running timer (frt) input/output (ftoa, ftob, ftia to ftid, ftci), timer 0 and 1 (tmr 0 , tmr 1 ) input/output (tmci 0 , tmri 0 , tmo 0 , tmci 1 , tmri 1 , tmo 1 ), timer x (tmrx) input/output (tmox, tmix), timer y (tmry) input (tmiy), and timer connection input/output (csynci, hsynci, hsynco, hfbacki, vsynci, vsynco, vfbacki, clampo). figure 8.6 shows the port 6 pin configuration. port 6 pins p6 7 (input/output) / tmox (output) / tmo 1 (output) / hsynco (output) p6 6 (input/output) / ftob (output) / tmri 1 (input) / csynci (input) p6 5 (input/output) / ftid (input) / tmci 1 (input) / hsynci (input) p6 4 (input/output) / ftic (input) / tmo 0 (output) / clampo (output) p6 3 (input/output) / ftib (input) / tmri 0 (input) / vfbacki (input) p6 2 (input/output) / ftia (input) / vsynci(input) / tmiy (input) p6 1 (input/output) / ftoa (output) / vsynco(output) p6 0 (input/output) / ftci (input) / tmci 0 (input) / hfbacki (input) / tmix (input) port 6 figure 8.6 port 6 pin functions 8.7.2 register configuration table 8.14 shows the port 6 register configuration. table 8.14 port 6 registers name abbreviation r/w initial value address port 6 data direction register p6ddr w h'00 h'ffb9 port 6 data register p6dr r/w h'00 h'ffbb
section 8 i/o ports rev. 3.00 mar 17, 2006 page 203 of 706 rej09b0303-0300 port 6 data direction register (p6ddr) bit 76543210 p6 7 ddr p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr initial value00000000 read/write w wwwwwww p6ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 6. p6ddr cannot be read; if it is, an undefined value will be returned. setting a p6ddr bit to 1 makes the corresponding port 6 pin an output port, while clearing the bit to 0 makes the pin an input port. p6ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. port 6 data register (p6dr) bit 76543210 p6 7 dr p6 6 dr p6 5 dr p6 4 dr p6 3 dr p6 2 dr p6 1 dr p6 0 dr initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w p6dr is an 8-bit readable/writable register that stores output data for the port 6 pins (p6 7 to p6 0 ). if a port 6 read is performed while p6ddr bits are set to 1, the p6dr values are read directly regardless of the actual pin states. if a port 6 read is performed while p6ddr bits are cleared to 0, the pin states are read. p6dr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. 8.7.3 pin functions port 6 pins are also used for 16-bit free-running timer (frt) input/output (ftoa, ftob, ftia to ftid, ftci), timer 0 and 1 (tmr 0 , tmr 1 ) input/output (tmci 0 , tmri 0 , tmo 0 , tmci 1 , tmri 1 , tmo 1 ), timer x (tmrx) input/output (tmox, tmix), timer y (tmry) input (tmiy), and timer connection input/output (csynci, hsynci, hsynco, hfbacki, vsynci, vsynco, vfbacki, clampo. port 6 pin functions are shown in table 8.15.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 204 of 706 rej09b0303-0300 table 8.15 port 6 pin functions pin pin functions and selection method p6 7 /tmo 1 / tmox/ hsynco the pin function is selected as shown below by a combination of bits os3 to os0 in tcsr of tmr1 and tmrx, bit hoe of timer connection tconro, and bit p6 7 ddr. hoe 0 1 tmrx: os3 ? 0 all 0 not all 0 ? tmr1: os3 ? 0 all 0 not all 0 ?? p6 7 ddr 0 1 ??? pin function p6 7 input p6 7 output tmo 1 output tmox output hsynco output p6 6 /ftob/ tmri 1 /csynci the pin function is selected as shown below by a combination of bit oeb in tocr of frt and bit p6 6 ddr. oeb 0 1 p6 6 ddr 0 1 ? pin function p6 6 input p6 6 output ftob output tmri 1 input, csynci input when bits cclr1 and cclr0 are both set to 1 in tcr of tmr1, this pin is used as the tmri 1 input pin. p6 5 /ftid/ p6 5 ddr 0 1 tmci 1 /hsynci pin function p6 5 input p6 5 output ftid input, tmci 1 input, hsynci input when an external clock is selected with bits cks2 to cks0 in tcr of tmr 1 , this pin is used as the tmci 1 input pin. p6 4 /ftic/ tmo 0 / the pin function is selected as shown below by a combination of bits os3 to os0 in tcsr of tmr0, bit cloe of timer connection tconro, and bit p6 4 ddr. clampo cloe 0 1 os3 ? 0 all 0 not all 0 all 0 p6 4 ddr 0 1 ?? pin function p6 4 input p6 4 output tmo 0 output clampo output ftic input when this pin is used as the clampo pin, bits os3 to os0 in tcsr of tmr 0 must be cleared to 0.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 205 of 706 rej09b0303-0300 pin pin functions and selection method p6 3 ddr 0 1 p6 3 /ftib/ tmri0/vfbacki pin function p6 3 input p6 3 output ftib input, tmri0 input, vfbacki input when bits cclr1 and cclr0 are both set to 1 in tcr of tmr0, this pin is used as the tmri 0 input pin. p6 2 ddr 0 1 p6 2 /ftia/ vsynci/tmiy pin function p6 2 input p6 2 output ftia input, vsynci input, tmiy input p6 1 /ftoa/ vsynco the pin function is selected as shown below by a combination of bit oea in tocr of frt, bit voe of timer connection tconro, and bit p6 1 ddr. voe 0 1 oea 0 1 0 p6 1 ddr 0 1 ?? pin function p6 1 input p6 1 output ftoa 0 output vsynco output when this pin is used as the vsynco pin, bit oea in tocr of frt must be cleared to 0. p6 0 ddr 0 1 p6 0 /ftci/tmci 0 / hfbacki/tmix pin function p6 0 input p6 0 output ftci input, tmci 0 input, hfbacki input, tmix input when an external clock is selected with bits cks1 and cks0 in tcr of frt, this pin is used as the ftci input pin. when an external clock is selected with bits cks2 to cks0 in tcr of tmr0, this pin is used as the tmci 0 input pin.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 206 of 706 rej09b0303-0300 8.8 port 7 8.8.1 overview port 7 is an 8-bit input port. port 7 is also used for a/d converter analog input (an 7 to an 0 ). bits 7 to 4 of port 7 are provided in the h8/3577 group, but not in the h8/3567 group. therefore the h8/3567 group does not have the input pin functions or four a/d converter analog input pin (an 7 to an 4 ) functions corresponding to bits 7 to 4 of port 7. figure 8.7 shows the port 7 pin configuration. port 7 pins p7 7 (input) / an 7 (input) p7 6 (input) / an 6 (input) p7 5 (input) / an 5 (input) p7 4 (input) / an 4 (input) p7 3 (input) / an 3 (input) p7 2 (input) / an 2 (input) p7 1 (input) / an 1 (input) p7 0 (input) / an 0 (input) port 7 figure 8.7 port 7 pin functions 8.8.2 register configuration table 8.16 shows the port 7 register configuration. as port 7 is an input port, it has no data direction register or data register. table 8.16 port 7 registers name abbreviation r/w initial value address port 7 input data register p7pin r undefined h'ffbe
section 8 i/o ports rev. 3.00 mar 17, 2006 page 207 of 706 rej09b0303-0300 port 7 input data register (p7pin) bit 76543210 p7 7 pin p7 6 pin p7 5 pin p7 4 pin p7 3 pin p7 2 pin p7 1 pin p7 0 pin initial value ? * ? * ? * ? * ? * ? * ? * ? * read/write r rrrrrrr note: * determined by the state of pins p7 7 to p7 0 . when a p7pin read is performed, the pin states are always read. in the h8/3567 group, reading bits 7 to 4 will return an undefined value. 8.8.3 pin functions port 7 pins are also used for a/d converter analog input (an 7 to an 0 ). in the h8/3567 group, the port 7 pins (p7 0 to p7 3 ) are also used for a/d converter analog input (an 0 to an 3 ).
section 8 i/o ports rev. 3.00 mar 17, 2006 page 208 of 706 rej09b0303-0300 8.9 port c [h8/3567 group version with on-chip usb only] 8.9.1 overview port c is an 8-bit i/o port. port c is provided only in the h8/3567 group version with an on-chip usb. port c is also used for input/output to control the usb hub downstream port power supply ic. figure 8.8 shows the port c pin configuration. pc 7 (input/output) / ocp 5 (input) pc 6 (input/output) / ocp 4 (input) pc 5 (input/output) / ocp 3 (input) pc 4 (input/output) / ocp 2 (input) pc 3 (input/output) / enp 5 (output) pc 2 (input/output) / enp 4 (output) pc 1 (input/output) / enp 3 (output) pc 0 (input/output) / enp 2 (output) port c figure 8.8 port c pin functions 8.9.2 register configuration table 8.17 shows the port c register configuration. table 8.17 port c registers name abbreviation r/w initial value address * port c data direction register pcddr w h'00 h'fe4e port c output data register pcodr r/w h'00 h'fe4c port c input data register pcpin r undefined h'fe4e note: * pcpin and pcddr have the same address.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 209 of 706 rej09b0303-0300 port c data direction register (pcddr) bit 76543210 pc 7 ddr pc 6 ddr pc 5 ddr pc 4 ddr pc 3 ddr pc 2 ddr pc 1 ddr pc 0 ddr initial value00000000 read/write w wwwwwww pcddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port c. pcddr cannot be read; if it is, an undefined value will be returned. setting a pcddr bit to 1 makes the corresponding port c pin an output port, while clearing the bit to 0 makes the pin an input port. pcddr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. port c data output register (pcodr) bit 76543210 pc 7 odr pc 6 odr pc 5 odr pc 4 odr pc 3 odr pc 2 odr pc 1 odr pc 0 odr initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pcodr is an 8-bit readable/writable register that stores output data for the port c pins (pc 7 to pc 0 ). pcodr can be read and written to at all times, regardless of the contents of pcddr. pcodr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. port c input data register (pcpin) bit 76543210 pc 7 pin pc 6 pin pc 5 pin pc 4 pin pc 3 pin pc 2 pin pc 1 pin pc 0 pin initial value ? * ? * ? * ? * ? * ? * ? * ? * read/write r rrrrrrr note: * determined by the state of pins pc 7 to pc 0 . when a pcpin read is performed, the pin states are always read.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 210 of 706 rej09b0303-0300 pcpin and pcddr have the same address. when a write is performed, data is written to pcddr and the port c setting changes. 8.9.3 pin functions port c pins pc 7 to pc 4 are also used as input pins ( ocp 5 to ocp 2 ) that receive overcurrent detection signals (overcurrent signals) output from the usb hub downstream port power supply ic. port c pins pc 3 to pc 0 are also used as output pins ( enp 5 to enp 2 ) for power supply output enable signals (enable signals) input to the usb hub downstream port power supply ic. the power supply ic control pin function can be enabled or disabled for each ocp / enp pair by means of bits 3 to 0 (hoc5e to hoc2e) in the usb?s hoccr register. when the power supply ic control pin function is disabled, port c is used as an i/o port, with input or output specifiable individually for each pin. setting a pcddr bit to 1 makes the corresponding port c pin an output port, while clearing the bit to 0 makes the pin an input port.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 211 of 706 rej09b0303-0300 8.10 port d [h8/3567 group version with on-chip usb only] 8.10.1 overview port d is an 8-bit i/o port. port d is provided only in the h8/3567 group version with an on-chip usb. port d is also used for usb hub downstream data input/output. port d input/output characteristics are prescribed by the usb bus driver/receiver power supply (drvcc) voltage. figure 8.9 shows the port d pin configuration. pd 7 (input/output) / ds5d ? + ? + ? + ? + figure 8.9 port d pin functions 8.10.2 register configuration table 8.18 shows the port d register configuration. table 8.18 port d registers name abbreviation r/w initial value address * port d data direction register pdddr w h'00 h'fe4f port d output data register pdodr r/w h'00 h'fe4d port d input data register pdpin r undefined h'fe4f note: * pdpin and pdddr have the same address.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 212 of 706 rej09b0303-0300 port d data direction register (pdddr) bit 76543210 pd 7 ddr pd 6 ddr pd 5 ddr pd 4 ddr pd 3 ddr pd 2 ddr pd 1 ddr pd 0 ddr initial value00000000 read/write w wwwwwww pdddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port d. pdddr cannot be read; if it is, an undefined value will be returned. setting a pdddr bit to 1 makes the corresponding port d pin an output port, while clearing the bit to 0 makes the pin an input port. pdddr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. port d data output register (pdodr) bit 76543210 pd 7 odr pd 6 odr pd 5 odr pd 4 odr pd 3 odr pd 2 odr pd 1 odr pd 0 odr initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pdodr is an 8-bit readable/writable register that stores output data for the port d pins (pd 7 to pd 0 ). pdodr can be read and written to at all times, regardless of the contents of pdddr. pdodr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in software standby mode. port d input data register (pdpin) bit 76543210 pd 7 pin pd 6 pin pd 5 pin pd 4 pin pd 3 pin pd 2 pin pd 1 pin pd 0 pin initial value ? * ? * ? * ? * ? * ? * ? * ? * read/write r rrrrrrr note: * determined by the state of pins pd 7 to pd 0 . when a pdpin read is performed, the pin states are always read.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 213 of 706 rej09b0303-0300 pdpin and pdddr have the same address. when a write is performed, data is written to pdddr and the port d setting changes. 8.10.3 pin functions port d pins are also used for usb hub downstream data input/output. when the fonly bit is cleared to 1 in the usbcr register, port d is used as an i/o port, with input or output specifiable individually for each pin. setting a pdddr bit to 1 makes the corresponding port d pin an output port, while clearing the bit to 0 makes the pin an input port. when the fonly bit is cleared to 0, port d is used for usb hub downstream data input/output. the usb provided in the h8/3567 group has a built-in bus driver/receiver, and port d operates on the bus driver/receiver power supply (drv cc ) regardless of the setting of the fonly bit. therefore, port d input/output characteristics are prescribed by the drv cc voltage.
section 8 i/o ports rev. 3.00 mar 17, 2006 page 214 of 706 rej09b0303-0300
section 9 8-bit pwm timers rev. 3.00 mar 17, 2006 page 215 of 706 rej09b0303-0300 section 9 8-bit pwm timers 9.1 overview the h8/3577 group and h8/3567 group have an on-chip pwm (pulse width modulation) timer, with sixteen (h8/3577 group) or eight (h8/3567 group) outputs. sixteen output waveforms are generated from a common time base, enabling pwm output with a high carrier frequency to be produced using pulse division. the pwm timer module has sixteen 8-bit pwm data registers (pwdrs), and an output pulse with a duty cycle of 0 to 100% can be obtained as specified by pwdr and the port data register (p1dr or p2dr). 9.1.1 features the pwm timer module has the following features. ? operable at a maximum carrier frequency of 1.25 mhz using pulse division (at 20 mhz operation) ? duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output) ? direct or inverted pwm output, and pwm output enable/disable control
section 9 8-bit pwm timers rev. 3.00 mar 17, 2006 page 216 of 706 rej09b0303-0300 9.1.2 block diagram figure 9.1 shows a block diagram of the pwm timer module. pwdr0 pwdr1 pwdr2 pwdr3 pwdr4 pwdr5 pwdr6 pwdr7 pwdr8 pwdr9 pwdr10 pwdr11 pwdr12 pwdr13 pwdr14 pwdr15 p1 0 /pw 0 p1 1 /pw 1 p1 2 /pw 2 p1 3 /pw 3 p1 4 /pw 4 p1 5 /pw 5 p1 6 /pw 6 p1 7 /pw 7 p2 0 /pw 8 p2 1 /pw 9 p2 2 /pw 10 p2 3 /pw 11 p2 4 /pw 12 p2 5 /pw 13 p2 6 /pw 14 p2 7 /pw 15 port/pwm output control comparator 0 comparator 1 comparator 2 comparator 3 comparator 4 comparator 5 comparator 6 comparator 7 comparator 8 comparator 9 comparator 10 comparator 11 comparator 12 comparator 13 comparator 14 comparator 15 pwdprb pwoerb p2ddr p2dr pwdpra pwoera p1ddr p1dr module data bus bus interface internal data bus pwsl clock selection internal clock /2 legend: pwsl: pwdr: pwdpra: pwdprb: pwoera: pwoerb: pcsr: p1ddr: p2ddr: p1dr: p2dr: pwm register select pwm data register pwm data polarity register a pwm data polarity register b pwm output enable register a pwm output enable register b peripheral clock select register port 1 data direction register port 2 data direction register port 1 data register port 2 data register tcnt h8/3577 group only pcsr /4 /8 /16 figure 9.1 block diagram of pwm timer module
section 9 8-bit pwm timers rev. 3.00 mar 17, 2006 page 217 of 706 rej09b0303-0300 9.1.3 pin configuration table 9.1 shows the pwm output pin. table 9.1 pin configuration name abbreviation i/o function pwm output pin 0 to 7 pw 0 to pw 7 output pwm timer pulse output 0 to 7 pwm output pin 8 to 15 pw 8 to pw 15 output pwm timer pulse output 8 to 15 (h8/3577 group only) 9.1.4 register configuration table 9.2 lists the registers of the pwm timer module. table 9.2 pwm timer module registers name abbreviation r/w initial value address pwm register select pwsl r/w h'20 h'ffd6 pwm data registers 0 to 15 pwdr0 to pwdr15 r/w h'00 h'ffd7 pwm data polarity register a pwdpra r/w h'00 h'ffd5 pwm data polarity register b pwdprb r/w h'00 h'ffd4 pwm output enable register a pwoera r/w h'00 h'ffd3 pwm output enable register b pwoerb r/w h'00 h'ffd2 port 1 data direction register p1ddr w h'00 h'ffb0 port 2 data direction register p2ddr w h'00 h'ffb1 port 1 data register p1dr r/w h'00 h'ffb2 port 2 data register p2dr r/w h'00 h'ffb3 peripheral clock select register pcsr r/w h'00 h'ff82 module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87
section 9 8-bit pwm timers rev. 3.00 mar 17, 2006 page 218 of 706 rej09b0303-0300 9.2 register descriptions 9.2.1 pwm register select (pwsl) bit 76543210 pwcke pwcks ? ? rs3 rs2 rs1 rs0 initial value00100000 read/write r/w r/w ? ? r/w r/w r/w r/w pwsl is an 8-bit readable/writable register used to select the pwm timer input clock and the pwm data register. pwsl is initialized to h'20 by a reset, and in the standby modes, and module stop mode. bits 7 and 6?pwm clock enable, pwm clock select (pwcke, pwcks): these bits, together with bits pwcka and pwckb in pcsr, select the internal clock input to tcnt in the pwm timer. pwsl pcsr bit 7 bit 6 bit 2 bit 1 pwcke pwcks pwckb pwcka description 0 ? ? ? clock input is disabled (initial value) 10 ?? (system clock) is selected 100 /2 is selected 1 /4 is selected 10 /8 is selected 1 /16 is selected the pwm resolution, pwm conversion period, and carrier frequency depend on the selected internal clock, and can be found from the following equations. resolution (minimum pulse width) = 1/internal clock frequency pwm conversion period = resolution 256 carrier frequency = 16/pwm conversion period thus, with a 20 mhz system clock ( ), the resolution, pwm conversion period, and carrier frequency are as shown below.
section 9 8-bit pwm timers rev. 3.00 mar 17, 2006 page 219 of 706 rej09b0303-0300 table 9.3 resolution, pwm conversion period, and carrier frequency when = 20 mhz internal clock frequency resolution pwm conversion period carrier frequency 50 ns 12.8 s 1250 khz /2 100 ns 25.6 s 625 khz /4 200 ns 51.2 s 312.5 khz /8 400 ns 102.4 s 156.3 khz /16 800 ns 204.8 s 78.1 khz bit 5?reserved: this bit is always read as 1 and cannot be modified. bit 4?reserved: this bit is always read as 0 and cannot be modified. bits 3 to 0?register select (rs3 to rs0): these bits select the pwm data register. bit 3 bit 2 bit 1 bit 0 rs3 rs2 rs1 rs0 register selection 0000 pwdr0 selected 1 pwdr1 selected 1 0 pwdr2 selected 1 pwdr3 selected 1 0 0 pwdr4 selected 1 pwdr5 selected 1 0 pwdr6 selected 1 pwdr7 selected 1000 pwdr8 selected 1 pwdr9 selected 1 0 pwdr10 selected 1 pwdr11 selected 1 0 0 pwdr12 selected 1 pwdr13 selected 1 0 pwdr14 selected 1 pwdr15 selected
section 9 8-bit pwm timers rev. 3.00 mar 17, 2006 page 220 of 706 rej09b0303-0300 9.2.2 pwm data registers (pwdr0 to pwdr15) bit 76543210 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w each pwdr is an 8-bit readable/writable register that specifies the duty cycle of the basic pulse to be output, and the number of additional pulses. the value set in pwdr corresponds to a 0 or 1 ratio in the conversion period. the upper 4 bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. the lower 4 bits specify how many extra pulses are to be added within the conversion period comprising 16 basic pulses. thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios within the conversion period. for 256/256 (100%) output, port output should be used. pwdr is initialized to h'00 by a reset, and in the standby modes, and module stop mode. 9.2.3 pwm data polarity registers a and b (pwdpra and pwdprb) pwdpra bit 76543210 os7 os6 os5 os4 os3 os2 os1 os0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pwdprb bit 76543210 os15 os14 os13 os12 os11 os10 os9 os8 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w each pwdpr is an 8-bit readable/writable register that controls the polarity of the pwm output. bits os0 to os15 correspond to outputs pw 0 to pw 15 .
section 9 8-bit pwm timers rev. 3.00 mar 17, 2006 page 221 of 706 rej09b0303-0300 pwdpr is initialized to h'00 by a reset and in hardware standby mode. os description 0 pwm direct output (pwdr value corresponds to high width of output) (initial value) 1 pwm inverted output (pwdr value corresponds to low width of output) 9.2.4 pwm output enable registers a and b (pwoera and pwoerb) pwoera bit 76543210 oe7 oe6 oe5 oe4 oe3 oe2 oe1 oe0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w pwoerb bit 76543210 oe15 oe14 oe13 oe12 oe11 oe10 oe9 oe8 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w each pwoer is an 8-bit readable/writable register that switches between pwm output and port output. bits oe15 to oe0 correspond to outputs pw 15 to pw 0 . to set a pin in the output state, a setting in the port direction register is also necessary. bits p1 7 ddr to p1 0 ddr correspond to outputs pw 7 to pw 0 , and bits p2 7 ddr to p2 0 ddr correspond to outputs pw 15 to pw 8 . pwoer is initialized to h'00 by a reset and in hardware standby mode. ddr oe description 0 0 port input (initial value) 1 port input 1 0 port output or pwm 256/256 output 1 pwm output (0 to 255/256 output)
section 9 8-bit pwm timers rev. 3.00 mar 17, 2006 page 222 of 706 rej09b0303-0300 9.2.5 peripheral clock select register (pcsr) bit 76543210 ?????pwckbpwcka? initial value00000000 read/write ? ????r/wr/wr/w pcsr is an 8-bit readable/writable register that selects the pwm timer input clock. pcsr is initialized to h'00 by a reset, and in hardware standby mode. bits 7 to 3?reserved: these bits cannot be modified and are always read as 0. bits 2 and 1?pwm clock select (pwckb, pwcka): together with bits pwcke and pwcks in pwsl, these bits select the internal clock input to tcnt in the pwm timer. for details, see section 9.2.1, pwm register select (pwsl). bit 0?reserved: do not set this bit to 1. 9.2.6 port 1 data direction register (p1ddr) bit 76543210 p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr initial value00000000 read/write w wwwwwww p1ddr is an 8-bit write-only register that specifies the input/output direction and pwm output for each pin of port 1 on a bit-by-bit basis. port 1 pins are multiplexed with pins pw 0 to pw 7 . the bit corresponding to a pin to be used for pwm output should be set to 1. for details on p1ddr, see section 8.2, port 1.
section 9 8-bit pwm timers rev. 3.00 mar 17, 2006 page 223 of 706 rej09b0303-0300 9.2.7 port 2 data direction register (p2ddr) bit 76543210 p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr initial value00000000 read/write w wwwwwww p2ddr is an 8-bit write-only register that specifies the input/output direction and pwm output for each pin of port j on a bit-by-bit basis. port 2 pins are multiplexed with pins pw 8 to pw 15 . the bit corresponding to a pin to be used for pwm output should be set to 1. for details on p2ddr, see section 8.3, port 2. 9.2.8 port 1 data register (p1dr) bit 76543210 p1 7 dr p1 6 dr p1 5 dr p1 4 dr p1 3 dr p1 2 dr p1 1 dr p1 0 dr initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w p1dr is an 8-bit readable/writable register used to fix pwm output at 1 (when os = 0) or 0 (when os = 1). for details on p1dr, see section 8.2, port 1. 9.2.9 port 2 data register (p2dr) bit 76543210 p2 7 dr p2 6 dr p2 5 dr p2 4 dr p2 3 dr p2 2 dr p2 1 dr p2 0 dr initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w p2dr is an 8-bit readable/writable register used to fix pwm output at 1 (when os = 0) or 0 (when os = 1). for details on p2dr, see section 8.3, port 2.
section 9 8-bit pwm timers rev. 3.00 mar 17, 2006 page 224 of 706 rej09b0303-0300 9.2.10 module stop control register (mstpcr) mstpcrh mstpcrl bit 7654321076543210 mstp 15 mstp 14 mstp 13 mstp 12 mstp 11 mstp 10 mstp 9 mstp 8 mstp 7 mstp 6 mstp 5 mstp 4 mstp 3 mstp 2 mstp 1 mstp 0 initial value 0011111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w mstpcr comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. when the mstp11 bit is set to 1, 8-bit pwm timer operation is halted and a transition is made to module stop mode. for details, see section 21.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrh bit 3?module stop (mstp11): specifies pwm module stop mode. mstpcrh bit 3 mstp11 description 0 pwm module stop mode is cleared 1 pwm module stop mode is set (initial value)
section 9 8-bit pwm timers rev. 3.00 mar 17, 2006 page 225 of 706 rej09b0303-0300 9.3 operation 9.3.1 correspondence between pwm data register contents and output waveform the upper 4 bits of pwdr specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16, as shown in table 9.4. table 9.4 duty cycle of basic pulse 0123456789abc d ef0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 upper 6 bits basic pulse waveform (internal)
section 9 8-bit pwm timers rev. 3.00 mar 17, 2006 page 226 of 706 rej09b0303-0300 the lower 4 bits of pwdr specify the position of pulses added to the 16 basic pulses, as shown in table 9.5. an additional pulse consists of a high period (when os = 0) with a width equal to the resolution, added before the rising edge of a basic pulse. when the upper 4 bits of pwdr are 0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same. table 9.5 position of pulses added to basic pulses basic pulse no. lower 4 bits0123456789101112131415 0000 0001 yes 0010 yes yes 0011 yes yes yes 0100 yes yes yes yes 0101 yes yes yes yes yes 0110 yes yes yes yes yes yes 0111 yes yes yes yes yes yes yes 1000 yes yes yes yes yes yes yes yes 1001 yes yes yes yes yes yes yes yes yes 1010 yes yes yes yes yes yes yes yes yes yes 1011 yes yes yes yes yes yes yes yes yes yes yes 1100 yes yes yes yes yes yes yes yes yes yes yes yes 1101 yes yes yes yes yes yes yes yes yes yes yes yes yes 1110 yes yes yes yes yes yes yes yes yes yes yes yes yes yes 1111 yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes additional pulse provided no additional pulse resolution width additional pulse figure 9.2 example of additional pulse timing (when upper 4 bits of pwdr = 1000)
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 227 of 706 rej09b0303-0300 section 10 14-bit pwm timer 10.1 overview the h8/3577 group and h8/3567 group have an on-chip 14-bit pwm (pulse width modulator) with two output channels. each channel can be connected to an external low-pass filter to operate as a 14-bit d/a converter. both channels share the same counter (dacnt) and control register (dacr). 10.1.1 features the features of the 14-bit pwm d/a are listed below. ? the pulse is subdivided into multiple base cycles to reduce ripple. ? two resolution settings and two base cycle settings are available the resolution can be set equal to one or two system clock cycles. the base cycle can be set equal to t 64 or t 256, where t is the resolution. ? four operating rates the two resolution settings and two base cycle settings combine to give a selection of four operating rates.
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 228 of 706 rej09b0303-0300 10.1.2 block diagram figure 10.1 shows a block diagram of the pwm d/a module. internal clock /2 pwx 0 pwx 1 dadra dadrb dacnt dacr legend: dacr: pwm d/a control register ( 6 bits) dadra: pwm d/a data register a (15 bits) dadrb: pwm d/a data register b (15 bits) dacnt: pwm d/a counter (14 bits) control logic clock selection clock internal data bus basic cycle compare-match a fine-adjustment pulse addition a basic cycle compare-match b fine-adjustment pulse addition b basic cycle overflow comparator a comparator b bus interface module data bus figure 10.1 pwm d/a block diagram
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 229 of 706 rej09b0303-0300 10.1.3 pin configuration table 10.1 lists the pins used by the pwm d/a module. table 10.1 input and output pins channel name abbr. i/o function a pwm output pin 0 pwx 0 output pwm output, channel a b pwm output pin 1 pwx 1 output pwm output, channel b 10.1.4 register configuration table 10.2 lists the registers of the pwm d/a module. table 10.2 register configuration name abbreviation r/w initial value address pwm d/a control register dacr r/w h'30 h'ffa0 * pwm d/a data register a high dadrah r/w h'ff h'ffa0 * pwm d/a data register a low dadral r/w h'ff h'ffa1 * pwm d/a data register b high dadrbh r/w h'ff h'ffa6 * pwm d/a data register b low dadrbl r/w h'ff h'ffa7 * pwm d/a counter high dacnth r/w h'00 h'ffa6 * pwm d/a counter low dacntl r/w h'03 h'ffa7 * module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 note: * the registers of the 14-bit pwm timer are assigned to the same addresses as other registers. selection of each register is performed by the iice bit of the serial timer control register (stcr). also, the same addresses are shared by dadrah and dacr, and by dadrb and dacnt. switching is performed by the regs bit in dacnt or dadrb.
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 230 of 706 rej09b0303-0300 10.2 register descriptions 10.2.1 pwm d/a counter (dacnt) dacnth dacntl bit (cpu) 1514131211109876543210 bit (counter) 765432108910111213?? ? regs initial value 0000000000000011 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ? r/w dacnt is a 14-bit readable/writable up-counter that increments on an input clock pulse. the input clock is selected by the clock select bit (cks) in dacr. the cpu can read and write the dacnt value, but since dacnt is a 16-bit register, data transfers between it and the cpu are performed using a temporary register (temp). see section 10.3, bus master interface, for details. dacnt functions as the time base for both pwm d/a channels. when a channel operates with 14-bit precision, it uses all dacnt bits. when a channel operates with 12-bit precision, it uses the lower 12 (counter) bits and ignores the upper two (counter) bits. dacnt is initialized to h'0003 by a reset, in the standby modes, and module stop mode, and by the pwme bit. bit 1 of dacntl (cpu) is not used, and is always read as 1. dacntl bit 0?register select (regs): dadra and dacr, and dadrb and dacnt, are located at the same addresses. the regs bit specifies which registers can be accessed. the regs bit can be accessed regardless of whether dadrb or dacnt is selected. bit 0 regs description 0 dadra and dadrb can be accessed 1 dacr and dacnt can be accessed (initial value)
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 231 of 706 rej09b0303-0300 10.2.2 d/a data registers a and b (dadra and dadrb) dadrh dadrl bit (cpu) 1514131211109876543210 bit (data) 131211109876543210?? dadra da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 cfs ? initial value 1111111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ? dadrb da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 cfs regs initial value 1111111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w there are two 16-bit readable/writable d/a data registers: dadra and dadrb. dadra corresponds to pwm d/a channel a, and dadrb to pwm d/a channel b. the cpu can read and write the pwm d/a data register values, but since dadra and dadrb are 16-bit registers, data transfers between them and the cpu are performed using a temporary register (temp). see section 10.3, bus master interface, for details. the least significant (cpu) bit of dadra is not used and is always read as 1. dadr is initialized to h'ffff by a reset, and in the standby modes, and module stop mode. bits 15 to 2?pwm d/a data 13 to 0 (da13 to da0): the digital value to be converted to an analog value is set in the upper 14 bits of the pwm d/a data register. in each base cycle, the dacnt value is continually compared with these upper 14 bits to determine the duty cycle of the output waveform, and to decide whether to output a fine- adjustment pulse equal in width to the resolution. to enable this operation, the data register must be set within a range that depends on the carrier frequency select bit (cfs). if the dadr value is outside this range, the pwm output is held constant. a channel can be operated with 12-bit precision by keeping the two lowest data bits (da0 and da1) cleared to 0 and writing the data to be converted in the upper 12 bits. the two lowest data bits correspond to the two highest counter (dacnt) bits.
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 232 of 706 rej09b0303-0300 bit 1?carrier frequency select (cfs) bit 1 cfs description 0 base cycle = resolution (t) 64 dadr range = h'0401 to h'fffd 1 base cycle = resolution (t) 256 dadr range = h'0103 to h'ffff (initial value) dadra bit 0?reserved: this bit cannot be modified and is always read as 1. dadrb bit 0?register select (regs): dadra and dacr, and dadrb and dacnt, are located at the same addresses. the regs bit specifies which registers can be accessed. the regs bit can be accessed regardless of whether dadrb or dacnt is selected. bit 0 regs description 0 dadra and dadrb can be accessed 1 dacr and dacnt can be accessed (initial value) 10.2.3 pwm d/a control register (dacr) bit 76543210 test pwme ? ? oeb oea os cks initial value00110000 read/write r/w r/w ? ? r/w r/w r/w r/w dacr is an 8-bit readable/writable register that selects test mode, enables the pwm outputs, and selects the output phase and operating speed. dacr is initialized to h'30 by a reset, and in the standby modes, and module stop mode. bit 7?test mode (test): selects test mode, which is used in testing the chip. normally this bit should be cleared to 0.
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 233 of 706 rej09b0303-0300 bit 7 test description 0 pwm (d/a) in user state: normal operation (initial value) 1 pwm (d/a) in test state: correct conversion results unobtainable bit 6?pwm enable (pwme): starts or stops the pwm d/a counter (dacnt). bit 6 pwme description 0 dacnt operates as a 14-bit up-counter (initial value) 1 dacnt halts at h'0003 bits 5 and 4?reserved: these bits cannot be modified and are always read as 1. bit 3?output enable b (oeb): enables or disables output on pwm d/a channel b. bit 3 oeb description 0 pwm (d/a) channel b output (at the pwx 1 pin) is disabled (initial value) 1 pwm (d/a) channel b output (at the pwx 1 pin) is enabled bit 2?output enable a (oea): enables or disables output on pwm d/a channel a. bit 2 oea description 0 pwm (d/a) channel a output (at the pwx 0 pin) is disabled (initial value) 1 pwm (d/a) channel a output (at the pwx 0 pin) is enabled bit 1?output select (os): selects the phase of the pwm d/a output. bit 1 os description 0 direct pwm output (initial value) 1 inverted pwm output
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 234 of 706 rej09b0303-0300 bit 0?clock select (cks): selects the pwm d/a resolution. if the system clock ( ) frequency is 10 mhz, resolutions of 100 ns and 200 ns can be selected. bit 0 cks description 0 operates at resolution (t) = system clock cycle time (t cyc ) (initial value) 1 operates at resolution (t) = system clock cycle time (t cyc ) 2 10.2.4 module stop control register (mstpcr) mstpcrh mstpcrl bit 7654321076543210 mstp 15 mstp 14 mstp 13 mstp 12 mstp 11 mstp 10 mstp 9 mstp 8 mstp 7 mstp 6 mstp 5 mstp 4 mstp 3 mstp 2 mstp 1 mstp 0 initial value 0011111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w mstpcr comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. when the mstp11 bit is set to 1, 14-bit pwm timer operation is halted and a transition is made to module stop mode. for details, see section 21.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrh bit 3?module stop (mstp11): specifies pwmx module stop mode. mstpcrh bit 3 mstp11 description 0 pwmx module stop mode is cleared 1 pwmx module stop mode is set (initial value)
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 235 of 706 rej09b0303-0300 10.3 bus master interface dacnt, dadra, and dadrb are 16-bit registers. the data bus linking the bus master and the on-chip supporting modules, however, is only 8 bits wide. when the bus master accesses these registers, it therefore uses an 8-bit temporary register (temp). these registers are written and read as follows (taking the example of the cpu interface). ? write when the upper byte is written, the upper-byte write data is stored in temp. next, when the lower byte is written, the lower-byte write data and temp value are combined, and the combined 16-bit value is written in the register. ? read when the upper byte is read, the upper-byte value is transferred to the cpu and the lower-byte value is transferred to temp. next, when the lower byte is read, the lower-byte value in temp is transferred to the cpu. these registers should always be accessed 16 bits at a time (by word access or two consecutive byte accesses), and the upper byte should always be accessed before the lower byte. correct data will not be transferred if only the upper byte or only the lower byte is accessed. figure 10.2 shows the data flow for access to dacnt. the other registers are accessed similarly. example 1: write to dacnt mov.w r0, @dacnt ; write r0 contents to dacnt example 2: read dadra mov.w @dadra, r0 ; copy contents of dadra to r0 table 10.3 read and write access methods for 16-bit registers read write register name word byte word byte dadra and dadrb yes yes yes dacnt yes yes notes: yes: permitted type of access. word access includes successive byte accesses to the upper byte (first) and lower byte (second). : this type of access may give incorrect results.
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 236 of 706 rej09b0303-0300 cpu (h'aa) upper byte bus interface module data bus upper-byte write temp (h'aa) dacntl ( ) dacnth ( ) cpu (h'57) lower byte bus interface module data bus lower-byte write temp (h'aa) dacntl (h'57) dacnth (h'aa) figure 10.2 (a) access to dacnt (cpu writes h'aa57 to dacnt)
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 237 of 706 rej09b0303-0300 cpu (h'aa) upper byte bus interface module data bus upper-byte read temp (h'57) dacntl (h'57) dacnth (h'aa) cpu (h'57) lower byte bus interface module data bus lower-byte read temp (h'57) dacntl ( ) dacnth ( ) figure 10.2 (b) access to dacnt (cpu reads h'aa57 from dacnt)
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 238 of 706 rej09b0303-0300 10.4 operation a pwm waveform like the one shown in figure 10.3 is output from the pwmx pin. when os = 0, the value in dadr corresponds to the total width (t l ) of the low (0) pulses output in one conversion cycle (256 pulses when cfs = 0, 64 pulses when cfs = 1). when os = 1, the output waveform is inverted and the dadr value corresponds to the total width (t h ) of the high (1) output pulses. figure 10.4 shows the types of waveform output available. t f t l t l = t ln (when os = 0) m n = 1 1 conversion cycle (t 2 14 (= 16384)) basic cycle (t 64 or t 256) t: resolution (when cfs = 0, m = 256; when cfs = 1, m = 64) figure 10.3 pwm d/a operation table 10.4 summarizes the relationships of the cks, cfs, and os bit settings to the resolution, base cycle, and conversion cycle. the pwm output remains flat unless dadr contains at least a certain minimum value. table 10.4 indicates the range of dadr settings that give an output waveform like the one in figure 10.3, and lists the conversion cycle length when low-order dadr bits are kept cleared to 0, reducing the conversion precision to 12 bits or 10 bits.
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 239 of 706 rej09b0303-0300 table 10.4 settings and operation (examples when = 10 mhz) fixed dadr bits bit data cks resolution t (s) cfs base cycle (s) conversion cycle (s) t l (if os = 0) t h (if os = 1) precision (bits) 3210 conversion cycle * (s) 14 1638.4 12 0 0 409.6 0 6.4 1638.4 1. always low (or high) (dadr = h'0001 to h'03fd) 2. (data value) t (dadr = h'0401 to h'fffd) 10 0000 102.4 14 1638.4 12 0 0 409.6 00.1 1 25.6 1638.4 1. always low (or high) (dadr = h'0003 to h'00ff) 2. (data value) t (dadr = h'0103 to h'ffff) 10 0000 102.4 14 3276.8 12 0 0 819.2 0 12.8 3276.8 1. always low (or high) (dadr = h'0001 to h'03fd) 2. (data value) t (dadr = h'0401 to h'fffd) 10 0000 204.8 14 3276.8 12 0 0 819.2 10.2 1 51.2 3276.8 1. always low (or high) (dadr = h'0003 to h'00ff) 2. (data value) t (dadr = h'0103 to h'ffff) 10 0000 204.8 note: * this column indicates the conversion cycle when specific dadr bits are fixed.
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 240 of 706 rej09b0303-0300 1. os = 0 (dadr corresponds to t l ) a. cfs = 0 [base cycle = resolution (t) 64] t l1 t l2 t l3 t l255 t l256 t f1 t f2 t f255 t f256 1 conversion cycle t f1 = t f2 = t f3 = = t f255 = t f256 = t 64 t l1 + t l2 + t l3 + + t l255 + t l256 = t l figure 10.4 (1) output waveform b. cfs = 1 [base cycle = resolution (t) 256] t l1 t l2 t l3 t l63 t l64 t f1 t f2 t f63 t f64 1 conversion cycle t f1 = t f2 = t f3 = = t f63 = t f64 = t 256 t l1 + t l2 + t l3 + + t l63 + t l64 = t l figure 10.4 (2) output waveform
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 241 of 706 rej09b0303-0300 2. os = 1 (dadr corresponds to t h ) a. cfs = 0 [base cycle = resolution (t) 64] t h1 t h2 t h3 t h255 t h256 t f1 t f2 t f255 t f256 1 conversion cycle t f1 = t f2 = t f3 = = t f255 = t f256 = t 64 t h1 + t h2 + t h3 + + t h255 + t h256 = t h figure 10.4 (3) output waveform b. cfs = 1 [base cycle = resolution (t) 256] t h1 t h2 t h3 t h63 t h64 t f1 t f2 t f63 t f64 1 conversion cycle t f1 = t f2 = t f3 = = t f63 = t f64 = t 256 t h1 + t h2 + t h3 + + t h63 + t h64 = t h figure 10.4 (4) output waveform
section 10 14-bit pwm timer rev. 3.00 mar 17, 2006 page 242 of 706 rej09b0303-0300
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 243 of 706 rej09b0303-0300 section 11 16-bit free-running timer 11.1 overview the h8/3577 group and h8/3567 group have a single-channel on-chip 16-bit free-running timer (frt). applications of the frt module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods. 11.1.1 features the features of the free-running timer module are listed below. ? selection of four clock sources ? the free-running counter can be driven by an internal clock source ( /2, /8, or /32), or an external clock input (enabling use as an external event counter). ? two independent comparators ? each comparator can generate an independent waveform. ? four input capture channels ? the current count can be captured on the rising or falling edge (selectable) of an input signal. ? the four input capture registers can be used separately, or in a buffer mode. ? counter can be cleared under program control ? the free-running counters can be cleared on compare-match a. ? seven independent interrupts ? two compare-match interrupts, four input capture interrupts, and one overflow interrupt can be requested independently. ? special functions provided by automatic addition function ? the contents of ocrar and ocraf can be added to the contents of ocra automatically, enabling a periodic waveform to be generated without software intervention. ? the contents of icrd can be added automatically to the contents of ocrdm 2, enabling input capture operations in this interval to be restricted.
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 244 of 706 rej09b0303-0300 11.1.2 block diagram figure 11.1 shows a block diagram of the free-running timer. external clock source internal clock sources clock select comparator a ocra (h/l) comparator b ocrb (h/l) bus interface internal data bus /2 /8 /32 ftci compare- match a clear clock ftoa ftob overflow icra (h/l) compare- match b input capture frc (h/l) tcsr ftia ftib ftic ftid control logic module data bus tier tcr tocr interrupt signals icia icib icic icid ocia ocib fovi legend: ocra, b: frc: icra, b, c, d: tcsr: output compare register a, b (16 bits) free-running counter (16 bits) input capture register a, b, c, d (16 bits) timer control/status register (8 bits) tier: tcr: tocr: timer interrupt enable register (8 bits) timer control register (8 bits) timer output compare control register (8 bits) icrb (h/l) icrc (h/l) icrd (h/l) ocra r/f (h/l) + + ocrdm l 1 2 comparator m compare-match m figure 11.1 block diagram of 16-bit free-running timer
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 245 of 706 rej09b0303-0300 11.1.3 input and output pins table 11.1 lists the input and output pins of the free-running timer module. table 11.1 input and output pins of free-running timer module name abbreviation i/o function counter clock input ftci input frc counter clock input output compare a ftoa output output compare a output output compare b ftob output output compare b output input capture a ftia input input capture a input input capture b ftib input input capture b input input capture c ftic input input capture c input input capture d ftid input input capture d input
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 246 of 706 rej09b0303-0300 11.1.4 register configuration table 11.2 lists the registers of the free-running timer module. table 11.2 register configuration name abbreviation r/w initial value address timer interrupt enable register tier r/w h'01 h'ff90 timer control/status register tcsr r/(w) * 1 h'00 h'ff91 free-running counter frc r/w h'0000 h'ff92 output compare register a ocra r/w h'ffff h'ff94 * 2 output compare register b ocrb r/w h'ffff h'ff94 * 2 timer control register tcr r/w h'00 h'ff96 timer output compare control register tocr r/w h'00 h'ff97 input capture register a icra r h'0000 h'ff98 * 3 input capture register b icrb r h'0000 h'ff9a * 3 input capture register c icrc r h'0000 h'ff9c * 3 input capture register d icrd r h'0000 h'ff9e output compare register ar ocrar r/w h'ffff h'ff98 * 3 output compare register af ocraf r/w h'ffff h'ff9a * 3 output compare register dm ocrdm r/w h'0000 h'ff9c * 3 module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 notes: 1. bits 7 to 1 are read-only; only 0 can be written to clear the flags. bit 0 is readable/writable. 2. ocra and ocrb share the same address. access is controlled by the ocrs bit in tocr. 3. icra, icrb, and icrc share the same addresses with ocrar, ocraf, and ocrdm. access is controlled by the icrs bit in tocr.
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 247 of 706 rej09b0303-0300 11.2 register descriptions 11.2.1 free-running counter (frc) bit 1514131211109876543210 initial value0000000000000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w frc is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. the clock source is selected by bits cks1 and cks0 in tcr. frc can also be cleared by compare-match a. when frc overflows from h'ffff to h'0000, the overflow flag (ovf) in tcsr is set to 1. frc is initialized to h'0000 by a reset and in hardware standby mode. 11.2.2 output compare registers a and b (ocra, ocrb) bit 1514131211109876543210 initial value1111111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ocra and ocrb are 16-bit readable/writable registers, the contents of which are continually compared with the value in the frc. when a match is detected, the corresponding output compare flags (ocfa or ocfb) is set in tcsr. in addition, if the output enable bit (oea or oeb) in tocr is set to 1, when ocr and frc values match, the logic level selected by the output level bit (olvla or olvlb) in tocr is output at the output compare pin (ftoa or ftob). following a reset, the ftoa and ftob output levels are 0 until the first compare-match. ocr is initialized to h'ffff by a reset and in hardware standby mode.
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 248 of 706 rej09b0303-0300 11.2.3 input capture registers a to d (icra to icrd) bit 1514131211109876543210 initial value0000000000000000 read/write r rrrrrrrrrrrrrrr there are four input capture registers, a to d, each of which is a 16-bit read-only register. when the rising or falling edge of the signal at an input capture input pin (ftia to ftid) is detected, the current frc value is copied to the corresponding input capture register (icra to icrd). at the same time, the corresponding input capture flag (icfa to icfd) in tcsr is set to 1. the input capture edge is selected by the input edge select bits (iedga to iedgd) in tcr. icrc and icrd can be used as icra and icrb buffer registers, respectively, and made to perform buffer operations, by means of buffer enable bits a and b (bufea, bufeb) in tcr. figure 11.2 shows the connections when icrc is specified as the icra buffer register (bufea = 1). when icrc is used as the icra buffer, both rising and falling edges can be specified as transitions of the external input signal by setting iedga iedgc. when iedga = iedgc, either the rising or falling edge is designated. see table 11.3. note: the frc contents are transferred to the input capture register regardless of the value of the input capture flag (icf). bufea iedga iedgc ftia edge detect and capture signal generating circuit frc icrc icra figure 11.2 input capture buffering (example)
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 249 of 706 rej09b0303-0300 table 11.3 buffered input capture edge selection (example) iedga iedgc description 0 0 captured on falling edge of input capture a (ftia) (initial value) 1 captured on both rising and falling edges of input capture a (ftia) 10 1 captured on rising edge of input capture a (ftia) to ensure input capture, the width of the input capture pulse should be at least 1.5 system clock periods ( ). when triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clock periods ( ). icr is initialized to h'0000 by a reset and in hardware standby mode. 11.2.4 output compare registers ar and af (ocrar, ocraf) bit 1514131211109876543210 initial value1111111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ocrar and ocraf are 16-bit readable/writable registers. when the ocrams bit in tocr is set to 1, the operation of ocra is changed to include the use of ocrar and ocraf. the contents of ocrar and ocraf are automatically added alternately to ocra, and the result is written to ocra. the write operation is performed on the occurrence of compare-match a. in the 1st compare-match a after setting the ocrams bit to 1, ocraf is added. the operation due to compare-match a varies according to whether the compare-match follows addition of ocrar or ocraf. the value of the olvla bit in tocr is ignored, and 1 is output on a compare-match a following addition of ocraf, while 0 is output on a compare-match a following addition of ocrar. when using the ocra automatic addition function, do not select internal clock /2 as the frc counter input clock together with a set value of h'0001 or less for ocrar (or ocraf). ocrar and ocraf are initialized to h'ffff by a reset and in hardware standby mode.
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 250 of 706 rej09b0303-0300 11.2.5 output compare register dm (ocrdm) bit 1514131211109876543210 initial value0000000000000000 read/write r rrrrrrrr/wr/wr/wr/wr/wr/wr/wr/w ocrdm is a 16-bit readable/writable register in which the upper 8 bits are fixed at h'00. when the icrdms bit in tocr is set to 1 and the contents of ocrdm are other than h'0000, the operation of icrd is changed to include the use of ocrdm. the point at which input capture d occurs is taken as the start of a mask interval. next, twice the contents of ocrdm is added to the contents of icrd, and the result is compared with the frc value. the point at which the values match is taken as the end of the mask interval. new input capture d events are disabled during the mask interval. a mask interval is not generated when the icrdms bit is set to 1 and the contents of ocrdm are h'0000. ocrdm is initialized to h'0000 by a reset and in hardware standby mode. 11.2.6 timer interrupt enable register (tier) bit 76543210 iciae icibe icice icide ociae ocibe ovie ? initial value00000001 read/write r/w r/w r/w r/w r/w r/w r/w ? tier is an 8-bit readable/writable register that enables and disables interrupts. tier is initialized to h'01 by a reset and in hardware standby mode. bit 7?input capture interrupt a enable (iciae): selects whether to request input capture interrupt a (icia) when input capture flag a (icfa) in tcsr is set to 1.
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 251 of 706 rej09b0303-0300 bit 7 iciae description 0 input capture interrupt request a (icia) is disabled (initial value) 1 input capture interrupt request a (icia) is enabled bit 6?input capture interrupt b enable (icibe): selects whether to request input capture interrupt b (icib) when input capture flag b (icfb) in tcsr is set to 1. bit 6 icibe description 0 input capture interrupt request b (icib) is disabled (initial value) 1 input capture interrupt request b (icib) is enabled bit 5?input capture interrupt c enable (icice): selects whether to request input capture interrupt c (icic) when input capture flag c (icfc) in tcsr is set to 1. bit 5 icice description 0 input capture interrupt request c (icic) is disabled (initial value) 1 input capture interrupt request c (icic) is enabled bit 4?input capture interrupt d enable (icide): selects whether to request input capture interrupt d (icid) when input capture flag d (icfd) in tcsr is set to 1. bit 4 icide description 0 input capture interrupt request d (icid) is disabled (initial value) 1 input capture interrupt request d (icid) is enabled bit 3?output compare interrupt a enable (ociae): selects whether to request output compare interrupt a (ocia) when output compare flag a (ocfa) in tcsr is set to 1. bit 3 ociae description 0 output compare interrupt request a (ocia) is disabled (initial value) 1 output compare interrupt request a (ocia) is enabled
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 252 of 706 rej09b0303-0300 bit 2?output compare interrupt b enable (ocibe): selects whether to request output compare interrupt b (ocib) when output compare flag b (ocfb) in tcsr is set to 1. bit 2 ocibe description 0 output compare interrupt request b (ocib) is disabled (initial value) 1 output compare interrupt request b (ocib) is enabled bit 1?timer overflow interrupt enable (ovie): selects whether to request a free-running timer overflow interrupt (fovi) when the timer overflow flag (ovf) in tcsr is set to 1. bit 1 ovie description 0 timer overflow interrupt request (fovi) is disabled (initial value) 1 timer overflow interrupt request (fovi) is enabled bit 0?reserved: this bit cannot be modified and is always read as 1. 11.2.7 timer control/status register (tcsr) bit 76543210 icfa icfb icfc icfd ocfa ocfb ovf cclra initial value00000000 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/w note: * only 0 can be written in bits 7 to 1 to clear these flags. tcsr is an 8-bit register used for counter clear selection and control of interrupt request signals. tcsr is initialized to h'00 by a reset and in hardware standby mode. timing is described in section 11.3, operation. bit 7?input capture flag a (icfa): this status flag indicates that the frc value has been transferred to icra by means of an input capture signal. when bufea = 1, icfa indicates that the old icra value has been moved into icrc and the new frc value has been transferred to icra. icfa must be cleared by software. it is set by hardware, however, and cannot be set by software.
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 253 of 706 rej09b0303-0300 bit 7 icfa description 0 [clearing condition] read icfa when icfa = 1, then write 0 in icfa (initial value) 1 [setting condition] when an input capture signal causes the frc value to be transferred to icra bit 6?input capture flag b (icfb): this status flag indicates that the frc value has been transferred to icrb by means of an input capture signal. when bufeb = 1, icfb indicates that the old icrb value has been moved into icrd and the new frc value has been transferred to icrb. icfb must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 6 icfb description 0 [clearing condition] read icfb when icfb = 1, then write 0 in icfb (initial value) 1 [setting condition] when an input capture signal causes the frc value to be transferred to icrb bit 5?input capture flag c (icfc): this status flag indicates that the frc value has been transferred to icrc by means of an input capture signal. when bufea = 1, on occurrence of the signal transition in ftic (input capture signal) specified by the iedgc bit, icfc is set but data is not transferred to icrc. therefore, in buffer operation, icfc can be used as an external interrupt signal (by setting the icice bit to 1). icfc must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 5 icfc description 0 [clearing condition] read icfc when icfc = 1, then write 0 in icfc (initial value) 1 [setting condition] when an input capture signal is received
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 254 of 706 rej09b0303-0300 bit 4?input capture flag d (icfd): this status flag indicates that the frc value has been transferred to icrd by means of an input capture signal. when bufeb = 1, on occurrence of the signal transition in ftid (input capture signal) specified by the iedgd bit, icfd is set but data is not transferred to icrd. therefore, in buffer operation, icfd can be used as an external interrupt by setting the icide bit to 1. icfd must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 4 icfd description 0 [clearing condition] read icfd when icfd = 1, then write 0 in icfd (initial value) 1 [setting condition] when an input capture signal is received bit 3?output compare flag a (ocfa): this status flag indicates that the frc value matches the ocra value. this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 3 ocfa description 0 [clearing condition] read ocfa when ocfa = 1, then write 0 in ocfa (initial value) 1 [setting condition] when frc = ocra bit 2?output compare flag b (ocfb): this status flag indicates that the frc value matches the ocrb value. this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 2 ocfb description 0 [clearing condition] read ocfb when ocfb = 1, then write 0 in ocfb (initial value) 1 [setting condition] when frc = ocrb
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 255 of 706 rej09b0303-0300 bit 1?timer overflow flag (ovf): this status flag indicates that the frc has overflowed (changed from h'ffff to h'0000). this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 1 ovf description 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf (initial value) 1 [setting condition] when frc changes from h'ffff to h'0000 bit 0?counter clear a (cclra): this bit selects whether the frc is to be cleared at compare- match a (when the frc and ocra values match). bit 0 cclra description 0 frc clearing is disabled (initial value) 1 frc is cleared at compare-match a 11.2.8 timer control register (tcr) bit 76543210 iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w tcr is an 8-bit readable/writable register that selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the frc clock source. tcr is initialized to h'00 by a reset and in hardware standby mode bit 7?input edge select a (iedga): selects the rising or falling edge of the input capture a signal (ftia).
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 256 of 706 rej09b0303-0300 bit 7 iedga description 0 capture on the falling edge of ftia (initial value) 1 capture on the rising edge of ftia bit 6?input edge select b (iedgb): selects the rising or falling edge of the input capture b signal (ftib). bit 6 iedgb description 0 capture on the falling edge of ftib (initial value) 1 capture on the rising edge of ftib bit 5?input edge select c (iedgc): selects the rising or falling edge of the input capture c signal (ftic). bit 5 iedgc description 0 capture on the falling edge of ftic (initial value) 1 capture on the rising edge of ftic bit 4?input edge select d (iedgd): selects the rising or falling edge of the input capture d signal (ftid). bit 4 iedgd description 0 capture on the falling edge of ftid (initial value) 1 capture on the rising edge of ftid bit 3?buffer enable a (bufea): selects whether icrc is to be used as a buffer register for icra. bit 3 bufea description 0 icrc is not used as a buffer register for input capture a (initial value) 1 icrc is used as a buffer register for input capture a
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 257 of 706 rej09b0303-0300 bit 2?buffer enable b (bufeb): selects whether icrd is to be used as a buffer register for icrb. bit 2 bufeb description 0 icrd is not used as a buffer register for input capture b (initial value) 1 icrd is used as a buffer register for input capture b bits 1 and 0?clock select (cks1, cks0): select external clock input or one of three internal clock sources for the frc. external clock pulses are counted on the rising edge of signals input to the external clock input pin (ftci). bit 1 bit 0 cks1 cks0 description 00 /2 internal clock source (initial value) 1 /8 internal clock source 10 /32 internal clock source 1 external clock source (rising edge) 11.2.9 timer output compare control register (tocr) bit 76543210 icrdms ocrams icrs ocrs oea oeb olvla olvlb initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w tocr is an 8-bit readable/writable register that enables output from the output compare pins, selects the output levels, switches access between output compare registers a and b, controls the icrd and ocra operating mode, and switches access to input capture registers a, b, and c. tocr is initialized to h'00 by a reset and in hardware standby mode.
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 258 of 706 rej09b0303-0300 bit 7?input capture d mode select (icrdms): specifies whether icrd is used in the normal operating mode or in the operating mode using ocrdm. bit 7 icrdms description 0 the normal operating mode is specified for icrd (initial value) 1 the operating mode using ocrdm is specified for icrd bit 6?output compare a mode select (ocrams): specifies whether ocra is used in the normal operating mode or in the operating mode using ocrar and ocraf. bit 6 ocrams description 0 the normal operating mode is specified for ocra (initial value) 1 the operating mode using ocrar and ocraf is specified for ocra bit 5?input capture register select (icrs): the same addresses are shared by icra and ocrar, by icrb and ocraf, and by icrc and ocrdm. the icrs bit determines which registers are selected when the shared addresses are read or written to. the operation of icra, icrb, and icrc is not affected. bit 5 icrs description 0 the icra, icrb, and icrc registers are selected (initial value) 1 the ocrar, ocraf, and ocrdm registers are selected bit 4?output compare register select (ocrs): ocra and ocrb share the same address. when this address is accessed, the ocrs bit selects which register is accessed. this bit does not affect the operation of ocra or ocrb. bit 4 ocrs description 0 the ocra register is selected (initial value) 1 the ocrb register is selected
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 259 of 706 rej09b0303-0300 bit 3?output enable a (oea): enables or disables output of the output compare a signal (ftoa). bit 3 oea description 0 output compare a output is disabled (initial value) 1 output compare a output is enabled bit 2?output enable b (oeb): enables or disables output of the output compare b signal (ftob). bit 2 oeb description 0 output compare b output is disabled (initial value) 1 output compare b output is enabled bit 1?output level a (olvla): selects the logic level to be output at the ftoa pin in response to compare-match a (signal indicating a match between the frc and ocra values). when the ocrams bit is 1, this bit is ignored. bit 1 olvla description 0 0 output at compare-match a (initial value) 1 1 output at compare-match a bit 0?output level b (olvlb): selects the logic level to be output at the ftob pin in response to compare-match b (signal indicating a match between the frc and ocrb values). bit 0 olvlb description 0 0 output at compare-match b (initial value) 1 1 output at compare-match b
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 260 of 706 rej09b0303-0300 11.2.10 module stop control register (mstpcr) mstpcrh mstpcrl bit 7654321076543210 mstp 15 mstp 14 mstp 13 mstp 12 mstp 11 mstp 10 mstp 9 mstp 8 mstp 7 mstp 6 mstp 5 mstp 4 mstp 3 mstp 2 mstp 1 mstp 0 initial value 0011111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w mstpcr, comprising two 8-bit readable/writable registers, performs module stop mode control. when the mstp13 bit is set to 1, frt operation is stopped at the end of the bus cycle, and module stop mode is entered. for details, see section 21.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrh bit 5?module stop (mstp13): specifies the frt module stop mode. bit 5 mstpcrh description 0 frt module stop mode is cleared 1 frt module stop mode is set (initial value) 11.3 operation 11.3.1 frc increment timing frc increments on a pulse generated once for each period of the selected (internal or external) clock source. internal clock: any of three internal clocks ( /2, /8, or /32) created by division of the system clock ( ) can be selected by making the appropriate setting in bits cks1 and cks0 in tcr. figure 11.3 shows the increment timing.
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 261 of 706 rej09b0303-0300 n ? 1 frc input clock frc internal clock n n + 1 figure 11.3 increment timing with internal clock source external clock: if external clock input is selected by bits cks1 and cks0 in tcr, frc increments on the rising edge of the external clock signal. the pulse width of the external clock signal must be at least 1.5 system clock ( ) periods. the counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods. figure 11.4 shows the increment timing. n + 1 n frc input clock frc external clock input pin figure 11.4 increment timing with external clock source
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 262 of 706 rej09b0303-0300 11.3.2 output compare output timing when a compare-match occurs, the logic level selected by the output level bit (olvla or olvlb) in tocr is output at the output compare pin (ftoa or ftob). figure 11.5 shows the timing of this operation for compare-match a. n + 1 n n + 1 n n ocra compare-match a signal frc olvla output compare a output pin ftoa clear * note: * vertical arrows ( ) indicate instructions executed by software. n figure 11.5 timing of output compare a output
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 263 of 706 rej09b0303-0300 11.3.3 frc clear timing frc can be cleared when compare-match a occurs. figure 11.6 shows the timing of this operation. n h'0000 frc compare-match a signal figure 11.6 clearing of frc by compare-match a 11.3.4 input capture input timing input capture input timing: an internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin, as selected by the corresponding iedga to iedgd bit in tcr. figure 11.7 shows the usual input capture timing when the rising edge is selected (iedga to iedgd = 1). input capture signal input capture input pin figure 11.7 input capture signal timing (usual case) if the upper byte of icra to icrad is being read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one system clock ( ) period. figure 11.8 shows the timing for this case.
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 264 of 706 rej09b0303-0300 input capture signal input capture input pin t 1 t 2 icra to icrd read cycle t 3 figure 11.8 input capture signal timing (input capture input when icra to icrd is read) buffered input capture input timing: icrc and icrd can operate as buffers for icra and icrb. figure 11.9 shows how input capture operates when icra and i crc are used in buffer mode (bufea = 1) and iedga and iedgc are set to different values (iedga = 0 and iedgc = 1, or iedg a = 1 and iedgc = 0), so that input capture is performed on both the rising and falling edges of ftia.
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 265 of 706 rej09b0303-0300 n n + 1 n n + 1 m n n n mm mn ftia input capture signal frc icra icrc figure 11.9 buffered input capture timing (usual case) when icrc or icrd is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. for example, if icrc is used to buffer icra, when the edge transition selected by the iedgc bit occurs on the ftic input capture line, icfc will be set, and if the iciec bit is set, an interrupt will be requested. the frc value will not be transferred to icrc, however. in buffered input capture, if the upper byte of either of the two registers to which data will be transferred (icra and icrc, or icrb and icrd) is being read when the input signal arrives, input capture is delayed by one system clock ( ) period. figure 11.10 shows the timing when bufea = 1.
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 266 of 706 rej09b0303-0300 input capture signal ftia t 1 t 2 read cycle: cpu reads icra or icrc t 3 figure 11.10 buffered input capture timing (input capture input when icra or icrc is read) 11.3.5 timing of input capture flag (icfa to icfd) setting the input capture flag icfa to icfd is set to 1 by the internal input capture signal. the frc value is simultaneously transferred to the corresponding input capture register (icrx). figure 11.11 shows the timing of this operation. icfa/b/c/d frc input capture signal n n icra/b/c/d figure 11.11 setting of input capture flag (icfa to icfd)
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 267 of 706 rej09b0303-0300 11.3.6 setting of output compare flags a and b (ocfa, ocfb) the output compare flags are set to 1 by an internal compare-match signal generated when the frc value matches the ocra or ocrb value. this compare-match signal is generated at the last state in which the two values match, just before frc increments to a new value. accordingly, when the frc and ocr values match, the compare-match signal is not generated until the next period of the clock source. figure 11.12 shows the timing of the setting of ocfa and ocfb. ocra or ocrb compare-match signal frc nn + 1 n ocfa or ocfb figure 11.12 setting of output compare flag (ocfa, ocfb)
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 268 of 706 rej09b0303-0300 11.3.7 setting of frc overflow flag (ovf) the frc overflow flag (ovf) is set to 1 when frc overflows (changes from h'ffff to h'0000). figure 11.13 shows the timing of this operation. h'ffff h'0000 overflow signal frc ovf figure 11.13 setting of overflow flag (ovf) 11.3.8 automatic addition of ocra and ocrar/ocraf when the ocrams bit in tocr is set to 1, the contents of ocrar and ocraf are automatically added to ocra alternately, and when an ocra compare-match occurs a write to ocra is performed. the ocra write timing is shown in figure 11.14. ocrar, ocraf ocra frc a n n+a compare-match signal n n+1 figure 11.14 ocra automatic addition timing
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 269 of 706 rej09b0303-0300 11.3.9 icrd and ocrdm mask signal generation when the icrdms bit in tocr is set to 1 and the contents of ocrdm are other than h'0000, a signal that masks the icrd input capture function is generated. the mask signal is set by the input capture signal. the mask signal setting timing is shown in figure 11.15. the mask signal is cleared by the sum of the icrd contents and twice the ocrdm contents, and an frc compare-match. the mask signal clearing timing is shown in figure 11.16. input capture mask signal input capture signal figure 11.15 input capture mask signal setting timing compare-match signal icrd + ocrdm 2 frc n input capture mask signal n n+1 figure 11.16 input capture mask signal clearing timing
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 270 of 706 rej09b0303-0300 11.4 interrupts the free-running timer can request seven interrupts (three types): input capture a to d (icia, icib, icic, icid), output compare a and b (ocia and ocib), and overflow (fovi). each interrupt can be enabled or disabled by an enable bit in tier. independent signals are sent to the interrupt controller for each interrupt. table 11.4 lists information about these interrupts. table 11.4 free-running timer interrupts interrupt description priority icia requested by icfa high icib requested by icfb icic requested by icfc icid requested by icfd ocia requested by ocfa ocib requested by ocfb fovi requested by ovf low
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 271 of 706 rej09b0303-0300 11.5 sample application in the example below, the free-running timer is used to generate pulse outputs with a 50% duty cycle and arbitrary phase relationship. the programming is as follows: ? the cclra bit in tcsr is set to 1. ? each time a compare-match interrupt occurs, software inverts the corresponding output level bit in tocr (olvla or olvlb). frc counter clear h'ffff ocra ocrb h'0000 ftoa ftob figure 11.17 pulse output (example)
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 272 of 706 rej09b0303-0300 11.6 usage notes application programmers should note that the following types of contention can occur in the free- running timer. contention between frc write and clear: if an internal counter clear signal is generated during the state after an frc write cycle, the clear signal takes priority and the write is not performed. figure 11.18 shows this type of contention. t 1 t 2 t 3 frc write cycle address frc address internal write signal counter clear signal frc n h'0000 figure 11.18 frc write-clear contention
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 273 of 706 rej09b0303-0300 contention between frc write and increment: even if an increment pulse is generated in the t 3 state during frc write cycle, it is not incremented and the count write takes priority. figure 11.19 shows this type of contention. t 1 t 2 t 3 frc write cycle address internal write signal frc input clock frc n m write data frc address figure 11.19 frc write-increment contention
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 274 of 706 rej09b0303-0300 contention between ocr write and compare-match: if a compare-match occurs in the t 3 state during the ocra or ocrb write cycle, the ocr write takes priority and the compare-match signal is inhibited. figure 11.20 shows this type of contention. when the automatic addition of ocrar/ocraf to ocra is selected and a compare-match occurs in the t 3 state during the ocra, ocrar or ocraf write cycle, the ocra, ocrar or ocraf write takes priority and the compare-match signal is inhibited. consequently, the result of automatic addition is not written. t 1 t 2 t 3 ocra or ocrb write cycle address internal write signal frc ocr n m write data ocr address n n + 1 compare-match signal inhibited figure 11.20 contention between ocr write and compare-match (when not using the function of automatic addition)
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 275 of 706 rej09b0303-0300 address ocrar(ocraf) address internal write signal ocrar (ocraf) old data new data compare-match signal frc since the compare-match signal is inhibited, automatic addition does not occur. inhibited ocra n n n+1 figure 11.21 contention between ocrar/ocraf write and compare-match (when using automatic addition) switching of internal clock and frc operation: when the internal clock is changed, the changeover may cause frc to increment. this depends on the time at which the clock select bits (cks1 and cks0) are rewritten, as shown in table 11.5. when an internal clock is used, the frc clock is generated on detection of the falling edge of the internal clock scaled from the system clock ( ). if the clock is changed when the old source is high and the new source is low, as in case no. 3 in table 11.5, the changeover is regarded as a falling edge that triggers the frc increment clock pulse. switching between an internal and external clock can also cause frc to increment.
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 276 of 706 rej09b0303-0300 table 11.5 switching of internal clock and frc operation no. timing of switchover by means of cks1 and cks0 bits frc operation 1 switching from low to low n + 1 clock before switchover clock after switchover frc clock frc cks bit rewrite n 2 switching from low to high n + 1 n + 2 clock before switchover clock after switchover frc clock frc cks bit rewrite n
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 277 of 706 rej09b0303-0300 no. timing of switchover by means of cks1 and cks0 bits frc operation 3 switching from high to low n + 1 n n + 2 * clock before switchover clock after switchover frc clock frc cks bit rewrite 4 switching from high to high n + 1 n + 2 n clock before switchover clock after switchover frc clock cks bit rewrite frc note: * generated on the assumption that the switchover is a falling edge; frc is incremented.
section 11 16-bit free-running timer rev. 3.00 mar 17, 2006 page 278 of 706 rej09b0303-0300
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 279 of 706 rej09b0303-0300 section 12 8-bit timers 12.1 overview the h8/3577 group and h8/3567 group have an on-chip 8-bit timer module with two channels (tmr 0 and tmr 1 ). each channel has an 8-bit counter (tcnt) and two time constant registers (tcora and tcorb) that are constantly compared with the tcnt value to detect compare- matches. the 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of a rectangular-wave output with an arbitrary duty cycle. the h8/3577 group and h8/3567 group also have two similar 8-bit timer channels (tmrx and tmry) that can be used in a connected configuration using the timer connection function. tmrx and tmry have greater input/output and interrupt function related restrictions than tmr 0 and tmr 1 . 12.1.1 features ? selection of clock sources ? tmr 0 , tmr 1 : the counter input clock can be selected from six internal clocks and an external clock (enabling use as an external event counter). ? tmrx, tmry: the counter input clock can be selected from three internal clocks and an external clock (enabling use as an external event counter). ? selection of three ways to clear the counters ? the counters can be cleared on compare-match a or b, or by an external reset signal. ? timer output controlled by two compare-match signals ? the timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or pwm output with an arbitrary duty cycle. (note: tmry does not have a timer output pin.) ? cascading of the two channels (tmr 0 , tmr 1 ) ? operation as a 16-bit timer can be performed using channel 0 as the upper half and channel 1 as the lower half (16-bit count mode). ? channel 1 can be used to count channel 0 compare-match occurrences (compare-match count mode). ? multiple interrupt sources for each channel ? tmr 0 , tmr 1 , tmry: two compare-match interrupts and one overflow interrupt can be requested independently. ? tmrx: one input capture source is available.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 280 of 706 rej09b0303-0300 12.1.2 block diagram figure 12.1 shows a block diagram of the 8-bit timer module (tmr 0 and tmr 1 ). tmrx and tmry have a similar configuration, but cannot be cascaded. tmrx also has an input capture function. for details, see section 13, timer connection. external clock sources internal clock sources tmr 0 /8, /2 /64, /32 /1024, /256 clock 1 clock 0 compare-match a1 compare-match a0 clear 1 cmia0 cmib0 ovi0 cmia1 cmib1 ovi1 interrupt signals tmo 0 tmri 0 internal bus tcora0 comparator a0 comparator b0 tcorb0 tcsr0 tcr0 tcora1 comparator a1 tcnt1 comparator b1 tcorb1 tcsr1 tcr1 tmci 0 tmci 1 tcnt0 overflow 1 overflow 0 compare-match b1 compare-match b0 tmo 1 tmri 1 clock select control logic clear 0 tmr 1 /8, /2 /64, /128 /1024, /2048 tmrx /2 /4 tmry /4 /256 /2048 figure 12.1 block diagram of 8-bit timer module
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 281 of 706 rej09b0303-0300 12.1.3 pin configuration table 12.1 summarizes the input and output pins of the 8-bit timer module. table 12.1 8-bit timer input and output pins channel name symbol * i/o function 0 timer output tmo 0 output output controlled by compare-match timer clock input tmci 0 input external clock input for the counter timer reset input tmri 0 input external reset input for the counter 1 timer output tmo 1 output output controlled by compare-match timer clock input tmci 1 input external clock input for the counter timer reset input tmri 1 input external reset input for the counter x timer output tmox output output controlled by compare-match timer clock/ reset input hfbacki/tmix (tmcix/tmrix) input external clock/reset input for the counter y timer clock/reset input vsynci/tmiy (tmciy/tmriy) input external clock/reset input for the counter note: * the abbreviations tmo, tmci, and tmri are used in the text, omitting the channel number. channel x and y i/o pins have the same internal configuration as channels 0 and 1, and therefore the same abbreviations are used.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 282 of 706 rej09b0303-0300 12.1.4 register configuration table 12.2 summarizes the registers of the 8-bit timer module. table 12.2 8-bit timer registers channel name abbreviation * 2 r/w initial value address 0 timer control register 0 tcr0 r/w h'00 h'ffc8 timer control/status register 0 tcsr0 r/(w) * 1 h'00 h'ffca time constant register a0 tcora0 r/w h'ff h'ffcc time constant register b0 tcorb0 r/w h'ff h'ffce time counter 0 tcnt0 r/w h'00 h'ffd0 1 timer control register 1 tcr1 r/w h'00 h'ffc9 timer control/status register 1 tcsr1 r/(w) * 1 h'10 h'ffcb time constant register a1 tcora1 r/w h'ff h'ffcd time constant register b1 tcorb1 r/w h'ff h'ffcf timer counter 1 tcnt1 r/w h'00 h'ffd1 common serial timer control register stcr r/w h'00 h'ffc3 module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 timer connection register s tconrs r/w h'00 h'fffe x timer control register x tcrx r/w h'00 h'fff0 timer control/status register x tcsrx r/(w) * 1 h'00 h'fff1 time constant register ax tcorax r/w h'ff h'fff6 time constant register bx tcorbx r/w h'ff h'fff7 timer counter x tcntx r/w h'00 h'fff4 time constant register c tcorc r/w h'ff h'fff5 input capture register r ticrr r h'00 h'fff2 input capture register f ticrf r h'00 h'fff3 y timer control register y tcry r/w h'00 h'fff0 timer control/status register y tcsry r/(w) * 1 h'00 h'fff1 time constant register ay tcoray r/w h'ff h'fff2 time constant register by tcorby r/w h'ff h'fff3 timer counter y tcnty r/w h'00 h'fff4 timer input select register tisr r/w h'fe h'fff5 notes: 1. only 0 can be written in bits 7 to 5, to clear these flags. 2. the abbreviations tcr, tcsr, tcora, tcorb, and tcnt are used in the text, omitting the channel designation (0, 1, x, or y).
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 283 of 706 rej09b0303-0300 each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the upper 8 bits for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word access. (access is not divided into two 8-bit accesses.) certain of the channel x and channel y registers are assigned to the same address. the tmrx/y bit in tconrs determines which register is accessed. 12.2 register descriptions 12.2.1 timer counter (tcnt) tcnt0 tcnt1 bit 1514131211109876543210 initial value0000000000000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tcntx, tcnty bit 76543210 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w each tcnt is an 8-bit readable/writable up-counter. tcnt0 and tcnt1 comprise a single 16-bit register, so they can be accessed together by word access. tcnt increments on pulses generated from an internal or external clock source. this clock source is selected by clock select bits cks2 to cks0 in tcr. tcnt can be cleared by an external reset input signal or compare-match signal. counter clear bits cclr1 and cclr0 in tcr select the method of clearing. when tcnt overflows from h'ff to h'00, the overflow flag (ovf) in tcsr is set to 1. the timer counters are initialized to h'00 by a reset and in hardware standby mode.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 284 of 706 rej09b0303-0300 12.2.2 time constant register a (tcora) tcora0 tcora1 bit 1514131211109876543210 initial value1111111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tcorax, tcoray bit 76543210 initial value11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w tcora is an 8-bit readable/writable register. tcora0 and tcora1 comprise a single 16-bit register, so they can be accessed together by word access. tcora is continually compared with the value in tcnt. when a match is detected, the corresponding compare-match flag a (cmfa) in tcsr is set. note, however, that comparison is disabled during the t2 state of a tcora write cycle. the timer output can be freely controlled by these compare-match signals and the settings of output select bits os1 and os0 in tcsr. tcora is initialized to h'ff by a reset and in hardware standby mode.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 285 of 706 rej09b0303-0300 12.2.3 time constant register b (tcorb) tcorb0 tcorb1 bit 1514131211109876543210 initial value1111111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w tcorbx, tcorby bit 76543210 initial value11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w tcorb is an 8-bit readable/writable register. tcorb0 and tcorb1 comprise a single 16-bit register, so they can be accessed together by word access. tcorb is continually compared with the value in tcnt. when a match is detected, the corresponding compare-match flag b (cmfb) in tcsr is set. note, however, that comparison is disabled during the t2 state of a tcorb write cycle. the timer output can be freely controlled by these compare-match signals and the settings of output select bits os3 and os2 in tcsr. tcorb is initialized to h'ff by a reset and in hardware standby mode.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 286 of 706 rej09b0303-0300 12.2.4 timer control register (tcr) bit 76543210 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w tcr is an 8-bit readable/writable register that selects the clock source and the time at which tcnt is cleared, and enables interrupts. tcr is initialized to h'00 by a reset and in hardware standby mode. for details of the timing, see section 12.3, operation. bit 7?compare-match interrupt enable b (cmieb): selects whether the cmfb interrupt request (cmib) is enabled or disabled when the cmfb flag in tcsr is set to 1. note that a cmib interrupt is not requested by tmrx, regardless of the cmieb value. bit 7 cmieb description 0 cmfb interrupt request (cmib) is disabled (initial value) 1 cmfb interrupt request (cmib) is enabled bit 6?compare-match interrupt enable a (cmiea): selects whether the cmfa interrupt request (cmia) is enabled or disabled when the cmfa flag in tcsr is set to 1. note that a cmia interrupt is not requested by tmrx, regardless of the cmiea value. bit 6 cmiea description 0 cmfa interrupt request (cmia) is disabled (initial value) 1 cmfa interrupt request (cmia) is enabled
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 287 of 706 rej09b0303-0300 bit 5?timer overflow interrupt enable (ovie): selects whether the ovf interrupt request (ovi) is enabled or disabled when the ovf flag in tcsr is set to 1. note that an ovi interrupt is not requested by tmrx, regardless of the ovie value. bit 5 ovie description 0 ovf interrupt request (ovi) is disabled (initial value) 1 ovf interrupt request (ovi) is enabled bits 4 and 3?counter clear 1 and 0 (cclr1, cclr0): these bits select the method by which the timer counter is cleared: by compare-match a or b, or by an external reset input. bit 4 bit 3 cclr1 cclr0 description 0 0 clearing is disabled (initial value) 1 cleared on compare-match a 1 0 cleared on compare-match b 1 cleared on rising edge of external reset input bits 2 to 0?clock select 2 to 0 (cks2 to cks0): these bits select whether the clock input to tcnt is an internal or external clock. the input clock can be selected from either six or three clocks, all divided from the system clock ( ). the falling edge of the selected internal clock triggers the count. when use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. some functions differ between channel 0 and channel 1, because of the cascading function.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 288 of 706 rej09b0303-0300 tcr stcr bit 2 bit 1 bit 0 bit 1 bit 0 channel cks2 cks1 cks0 icks1 icks0 description 0 0 0 0 ? ? clock input disabled (initial value) 001 ?0 /8 internal clock source, counted on the falling edge 001 ?1 /2 internal clock source, counted on the falling edge 010 ?0 /64 internal clock source, counted on the falling edge 010 ?1 /32 internal clock source, counted on the falling edge 011 ?0 /1024 internal clock source, counted on the falling edge 011 ?1 /256 internal clock source, counted on the falling edge 1 0 0 ? ? counted on tcnt1 overflow signal * 1 0 0 0 ? ? clock input disabled (initial value) 001 0 ? /8 internal clock source, counted on the falling edge 001 1 ? /2 internal clock source, counted on the falling edge 010 0 ? /64 internal clock source, counted on the falling edge 010 1 ? /128 internal clock source, counted on the falling edge 011 0 ? /1024 internal clock source, counted on the falling edge 011 1 ? /2048 internal clock source, counted on the falling edge 1 0 0 ? ? counted on tcnt0 compare-match a * note: * if the count input of channel 0 is the tcnt1 overflow signal and that of channel 1 is the tcnt0 compare-match signal, no incrementing clock will be generated. do not use this setting.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 289 of 706 rej09b0303-0300 tcr stcr bit 2 bit 1 bit 0 bit 1 bit 0 channel cks2 cks1 cks0 icks1 icks0 description x 0 0 0 ? ? clock input disabled (initial value) 0 0 1 ? ? counted on internal clock source 010 ?? /2 internal clock source, counted on the falling edge 011 ?? /4 internal clock source, counted on the falling edge 1 0 0 ? ? clock input disabled y 0 0 0 ? ? clock input disabled (initial value) 001 ?? /4 internal clock source, counted on the falling edge 010 ?? /256 internal clock source, counted on the falling edge 011 ?? /2048 internal clock source, counted on the falling edge 1 0 0 ? ? clock input disabled common 1 0 1 ? ? external clock source, counted at rising edge 1 1 0 ? ? external clock source, counted at falling edge 1 1 1 ? ? external clock source, counted at both rising and falling edges
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 290 of 706 rej09b0303-0300 12.2.5 timer control/status register (tcsr) tcsr0 bit 76543210 cmfb cmfa ovf adte os3 os2 os1 os0 initial value00000000 read/write r/(w) * r/(w) * r/(w) * r/w r/w r/w r/w r/w tcsr1 bit 76543210 cmfb cmfa ovf ? os3 os2 os1 os0 initial value00010000 read/write r/(w) * r/(w) * r/(w) * ? r/w r/w r/w r/w tcsrx bit 76543210 cmfb cmfa ovf icf os3 os2 os1 os0 initial value00000000 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/w r/w r/w r/w tcsry bit 76543210 cmfb cmfa ovf icie os3 os2 os1 os0 initial value00000000 read/write r/(w) * r/(w) * r/(w) * r/w r/w r/w r/w r/w note: * only 0 can be written in bits 7 to 5, and in bit 4 in tcsrx, to clear these flags. tcsr is an 8-bit register that indicates compare-match and overflow statuses (and input capture status in tmrx only), and controls compare-match output. tcsr0, tcsrx, and tcsry are initialized to h'00, and tcsr1 is initialized to h'10, by a reset and in hardware standby mode.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 291 of 706 rej09b0303-0300 bit 7?compare-match flag b (cmfb): status flag indicating whether the values of tcnt and tcorb match. bit 7 cmfb description 0 [clearing condition] read cmfb when cmfb = 1, then write 0 in cmfb (initial value) 1 [setting condition] when tcnt = tcorb bit 6?compare-match flag a (cmfa): status flag indicating whether the values of tcnt and tcora match. bit 6 cmfa description 0 [clearing condition] read cmfa when cmfa = 1, then write 0 in cmfa (initial value) 1 [setting condition] when tcnt = tcora bit 5 ?timer overflow flag (ovf): status flag indicating that tcnt has overflowed (changed from h'ff to h'00). bit 5 ovf description 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf (initial value) 1 [setting condition] when tcnt overflows from h'ff to h'00
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 292 of 706 rej09b0303-0300 tcsr0 bit 4?a/d trigger enable (adte): enables or disables a/d converter start requests by compare-match a. tcsr0 bit 4 adte description 0 a/d converter start requests by compare-match a are disabled (initial value) 1 a/d converter start requests by compare-match a are enabled tcsr1 bit 4?reserved: this bit cannot be modified and is always read as 1. tcsrx bit 4?input capture flag (icf): status flag that indicates detection of a rising edge followed by a falling edge in the external reset signal after the icst bit in tconri has been set to 1. tcsrx bit 4 icf description 0 [clearing condition] read icf when icf = 1, then write 0 in icf (initial value) 1 [setting condition] when a rising edge followed by a falling edge is detected in the external reset signal after the icst bit in tconri has been set to 1 tcsry bit 4?input capture interrupt enable (icie): selects enabling or disabling of the interrupt request by icf (icix) when the icf bit in tcsrx is set to 1. tcsry bit 4 icie description 0 interrupt request by icf (icix) is disabled (initial value) 1 interrupt request by icf (icix) is enabled
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 293 of 706 rej09b0303-0300 bits 3 to 0?output select 3 to 0 (os3 to os0): these bits specify how the timer output level is to be changed by a compare-match of tcor and tcnt. os3 and os2 select the effect of compare-match b on the output level, os1 and os0 select the effect of compare-match a on the output level, and both of them can be controlled independently. note, however, that priorities are set such that: trigger output > 1 output > 0 output. if compare- matches occur simultaneously, the output changes according to the compare-match with the higher priority. timer output is disabled when bits os3 to os0 are all 0. after a reset, the timer output is 0 until the first compare-match occurs. bit 3 bit 2 os3 os2 description 0 0 no change when compare-match b occurs (initial value) 1 0 is output when compare-match b occurs 1 0 1 is output when compare-match b occurs 1 output is inverted when compare-match b occurs (toggle output) bit 1 bit 0 os1 os0 description 0 0 no change when compare-match a occurs (initial value) 1 0 is output when compare-match a occurs 1 0 1 is output when compare-match a occurs 1 output is inverted when compare-match a occurs (toggle output)
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 294 of 706 rej09b0303-0300 12.2.6 serial timer control register (stcr) bit 76543210 ? iicx1 iicx0 iice ? usbe icks1 icks0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w stcr is an 8-bit readable/writable register that controls register access, the iic operating mode (when the on-chip iic option is included), and on-chip flash memory (in f-ztat versions), and also selects the tcnt input clock. for details on functions not related to the 8-bit timers, see section 3.2.3, serial timer control register (stcr), and the descriptions of the relevant modules. if a module controlled by stcr is not used, do not write 1 to the corresponding bit. stcr is initialized to h'00 by a reset and in hardware standby mode. bit 7?reserved: do not write 1 to this bit. bits 6 to 4?i 2 c control (iicx1, iicx0, iice): these bits control the operation of the i 2 c bus interface when the iic option is included on-chip. see section 16, i 2 c bus interface, for details. bit 3?reserved: this bit must not be set to 1. bit 2?usb enable (usbe): this bit controls cpu access to the usb data register and control register. bit 2 usbe description 0 prohibition of the above register access (initial value) 1 permission of the above register access bits 1 and 0?internal clock select 1 and 0 (icks1, icks0): these bits, together with bits cks2 to cks0 in tcr, select the clock to be input to tcnt. for details, see section 12.2.4, timer control register.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 295 of 706 rej09b0303-0300 12.2.7 system control register (syscr) bit 76543210 cs2e iose intm1 intm0 xrst nmieg hie rame initial value00001001 read/write r/w r/w r r r r/w r/w r/w only bit 1 is described here. for details on functions not related to the 8-bit timers, see sections 3.2.2 and 5.2.1, system control register (syscr), and the descriptions of the relevant modules. bit 1?host interface enable (hie): controls cpu access to 8-bit timer (channel x and y) data registers and control registers, and timer connection control registers. bit 1 hie description 0 cpu access to 8-bit timer (channel x and y) data registers and control registers, and timer connection control registers, is enabled (initial value) 1 cpu access to 8-bit timer (channel x and y) data registers and control registers, and timer connection control registers, is disabled 12.2.8 timer connection register s (tconrs) bit 76543210 tmrx/y isgene homod1 homod0 vomod1 vomod0 clmod1 clmod0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w tconrs is an 8-bit readable/writable register that controls access to the tmrx and tmry registers and timer connection operation. tconrs is initialized to h'00 by a reset and in hardware standby mode. bit 7?tmrx/tmry access select (tmrx/y): the tmrx and tmry registers can only be accessed when the hie bit in syscr is cleared to 0. in the h8/3577 group and h8/3567 group, some of the tmrx registers and the tmry registers are assigned to the same memory space addresses (h'fff0 to h'fff5), and the tmrx/y bit determines which registers are accessed.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 296 of 706 rej09b0303-0300 bit 7 accessible registers tmrx/y h'fff0 h'fff1 h'fff2 h'fff3 h'fff4 h'fff5 h'fff6 h'fff7 0 (initial value) tcrx (tmrx) tcsrx (tmrx) ticrr (tmrx) ticrf (tmrx) tcntx (tmrx) tcorc (tmrx) tcorax (tmrx) tcorbx (tmrx) 1 tcry (tmry) tcsry (tmry) tcoray (tmry) tcorby (tmry) tcnty (tmry) tisr (tmry) 12.2.9 input capture register (ticr) [tmrx additional function] bit 76543210 initial value00000000 read/write ? ??????? ticr is an 8-bit internal register to which the contents of tcnt are transferred on the falling edge of external reset input. the cpu cannot read or write to ticr directly. the ticr function is used in timer connection. for details, see section 13, timer connection. 12.2.10 time constant register c (tcorc) [tmrx additional function] bit 76543210 initial value11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w tcorc is an 8-bit readable/writable register. the sum of the contents of tcorc and ticr is continually compared with the value in tcnt. when a match is detected, a compare-match c signal is generated. note, however, that comparison is disabled during the t2 state of a tcorc write cycle and a ticr input capture cycle. tcorc is initialized to h'ff by a reset and in hardware standby mode. the tcorc function is used in timer connection. for details, see section 13, timer connection.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 297 of 706 rej09b0303-0300 12.2.11 input capture registers r and f (ticrr, ticrf) [tmrx additional functions] bit 76543210 initial value00000000 read/write r rrrrrrr ticrr and ticrf are 8-bit read-only registers. when the icst bit in tconri is set to 1, ticrr and ticrf capture the contents of tcnt successively on the rise and fall of the external reset input. when one capture operation ends, the icst bit is cleared to 0. ticrr and ticrf are each initialized to h'00 by a reset and in hardware standby mode. the ticrr and ticrf functions are used in timer c onnection. for details, see section 13, timer connection. 12.2.12 timer input select register (tisr) [tmry additional function] bit 76543210 ???????is initial value11111110 read/write ? ??????r/w tisr is an 8-bit readable/writable register that selects the external clock/reset signal source for the counter. tisr is initialized to h'fe by a reset and in hardware standby mode. bits 7 to 1?reserved: do not write 0. bit 0?input select (is): selects the internal synchronization signal (ivg signal) or the timer clock/reset input pin (tmiy (tmciy/tmriy)) as the external clock/reset signal source for the counter. bit 0 is description 0 ivg signal is selected (initial value) 1 tmiy (tmciy/tmriy) is selected
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 298 of 706 rej09b0303-0300 12.2.13 module stop control register (mstpcr) mstpcrh mstpcrl bit 7654321076543210 mstp 15 mstp 14 mstp 13 mstp 12 mstp 11 mstp 10 mstp 9 mstp 8 mstp 7 mstp 6 mstp 5 mstp 4 mstp 3 mstp 2 mstp 1 mstp 0 initial value 0011111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w mstpcr comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. when the mstp12 bit or mstp8 bit is set to 1, at the end of the bus cycle 8-bit timer operation is halted on channels 0 and 1 or channels x and y, respectively, and a transition is made to module stop mode. for details, see section 21.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrh bit 4?module stop (mstp12): specifies 8-bit timer (channel 0/1) module stop mode. mstpcrh bit 4 mstp12 description 0 8-bit timer (channel 0/1) module stop mode is cleared 1 8-bit timer (channel 0/1) module stop mode is set (initial value) mstpcrh bit 0?module stop (mstp8): specifies 8-bit timer (channel x/y) and timer connection module stop mode. mstpcrh bit 0 mstp8 description 0 8-bit timer (channel x/y) and timer connection module stop mode is cleared 1 8-bit timer (channel x/y) and timer connection module stop mode is set (initial value)
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 299 of 706 rej09b0303-0300 12.3 operation 12.3.1 tcnt incrementation timing tcnt is incremented by input clock pulses (either internal or external). internal clock: an internal clock created by dividing the system clock ( ) can be selected by setting bits cks2 to cks0 in tcr. figure 12.2 shows the count timing. ? 1 n n + 1 figure 12.2 count timing for internal clock input external clock: three incrementation methods can be selected by setting bits cks2 to cks0 in tcr: at the rising edge, the falling edge, and both rising and falling edges. note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. the counter will not increment correctly if the pulse width is less than these values. figure 12.3 shows the timing of incrementation at both edges of an external clock signal.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 300 of 706 rej09b0303-0300 ? 1 n n + 1 figure 12.3 count timing for external clock input 12.3.2 compare-match timing setting of compare-match flags a and b (cmfa, cmfb): the cmfa and cmfb flags in tcsr are set to 1 by a compare-match signal generated when the tcor and tcnt values match. the compare-match signal is generated at the last state in which the match is true, just before the timer counter is updated. therefore, when tcor and tcnt match, the compare-match signal is not generated until the next incrementation clock input. figure 12.4 shows this timing. figure 12.4 timing of cmf setting
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 301 of 706 rej09b0303-0300 timer output timing: when compare-match a or b occurs, the timer output changes as specified by the output select bits (os3 to os0) in tcsr. depending on these bits, the output can remain the same, be set to 0, be set to 1, or toggle. figure 12.5 shows the timing when the output is set to toggle at compare-match a. figure 12.5 timing of timer output timing of compare-match clear: tcnt is cleared when compare-match a or b occurs, depending on the setting of the cclr1 and cclr0 bits in tcr. figure 12.6 shows the timing of this operation. figure 12.6 timing of compare-match clear
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 302 of 706 rej09b0303-0300 12.3.3 tcnt external reset timing tcnt is cleared at the rising edge of an external reset input, depending on the settings of the cclr1 and cclr0 bits in tcr. the width of the clearing pulse must be at least 1.5 states. figure 12.7 shows the timing of this operation. ? 1 figure 12.7 timing of clearing by external reset input 12.3.4 timing of overflow flag (ovf) setting ovf in tcsr is set to 1 when the timer count overflows (changes from h'ff to h'00). figure 12.8 shows the timing of this operation. figure 12.8 timing of ovf setting
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 303 of 706 rej09b0303-0300 12.3.5 operation with cascaded connection if bits cks2 to cks0 in either tcr0 or tcr1 are set to b'100, the 8-bit timers of the two channels are cascaded. with this configuration, a single 16-bit timer can be used (16-bit timer mode) or compare-matches of 8-bit channel 0 can be counted by the timer of channel 1 (compare- match count mode). in this case, the timer operates as described below. 16-bit count mode: when bits cks2 to cks0 in tcr0 are set to b'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. ? setting of compare-match flags ? the cmf flag in tcsr0 is set to 1 when a 16-bit compare-match occurs. ? the cmf flag in tcsr1 is set to 1 when a lower 8-bit compare-match occurs. ? counter clear specification ? if the cclr1 and cclr0 bits in tcr0 have been set for counter clear at compare-match, the 16-bit counter (tcnt0 and tcnt1 together) is cleared when a 16-bit compare-match occurs. the 16-bit counter (tcnt0 and tcnt1 together) is cleared even if counter clear by the tmri0 pin has also been set. ? the settings of the cclr1 and cclr0 bits in tcr1 are ignored. the lower 8 bits cannot be cleared independently. ? pin output ? control of output from the tmo0 pin by bits os3 to os0 in tcsr0 is in accordance with the 16-bit compare-match conditions. ? control of output from the tmo1 pin by bits os3 to os0 in tcsr1 is in accordance with the lower 8-bit compare-match conditions. compare-match count mode: when bits cks2 to cks0 in tcr1 are b'100, tcnt1 counts compare-match a?s for channel 0. channels 0 and 1 are controlled independently. conditions such as setting of the cmf flag, generation of interrupts, output from the tmo pin, and counter clearing are in accordance with the settings for each channel. usage note: if the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for tcnt0 and tcnt1 are not generated and thus the counters will stop operating. simultaneous setting of these two modes should therefore be avoided.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 304 of 706 rej09b0303-0300 12.4 interrupt sources the tmr 0 , tmr 1 , and tmry 8-bit timers can generate three types of interrupt: compare-match a and b (cmia and cmib), and overflow (ovi). tmrx can generate only an icix interrupt. an interrupt is requested when the corresponding interrupt enable bit is set in tcr or tcsr. independent signals are sent to the interrupt controller for each interrupt. an overview of 8-bit timer interrupt sources is given in tables 12.3 to 12.5. table 12.3 tmr 0 and tmr 1 8-bit timer interrupt sources interrupt source description interrupt priority cmia requested by cmfa high cmib requested by cmfb ovi requested by ovf low table 12.4 tmrx 8-bit timer interrupt source interrupt source description icix requested by icf table 12.5 tmry 8-bit timer interrupt sources interrupt source description interrupt priority cmia requested by cmfa high cmib requested by cmfb ovi requested by ovf low
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 305 of 706 rej09b0303-0300 12.5 8-bit timer application example in the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 12.9. the control bits are set as follows: ? in tcr, cclr1 is cleared to 0 and cclr0 is set to 1 so that the timer counter is cleared by a tcora compare-match. ? in tcsr, bits os3 to os0 are set to b'0110, causing 1 output at a tcora compare-match and 0 output at a tcorb compare-match. with these settings, the 8-bit timer provides output of pulses at a rate determined by tcora with a pulse width determined by tcorb. no software intervention is required. tcnt h'ff counter clear tcora tcorb h'00 tmo figure 12.9 pulse output (example)
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 306 of 706 rej09b0303-0300 12.6 usage notes application programmers should note that the following kinds of contention can occur in the 8-bit timer module. 12.6.1 contention between tcnt write and clear if a timer counter clock pulse is generated during the t 2 state of a tcnt write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. figure 12.10 shows this operation. figure 12.10 contention between tcnt write and clear
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 307 of 706 rej09b0303-0300 12.6.2 contention between tcnt write and increment if a timer counter clock pulse is generated during the t 2 state of a tcnt write cycle, the write takes priority and the counter is not incremented. figure 12.11 shows this operation. figure 12.11 contention between tcnt write and increment
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 308 of 706 rej09b0303-0300 12.6.3 contention between tcor write and compare-match during the t2 state of a tcor write cycle, the tcor write has priority even if a compare-match occurs and the compare-match signal is disabled. figure 12.12 shows this operation. with tmrx, an icr input capture contends with a compare-match in the same way as with a write to tcorc. in this case, the input capture has priority and the compare-match signal is inhibited. figure 12.12 contention between tcor write and compare-match
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 309 of 706 rej09b0303-0300 12.6.4 contention between compare-matches a and b if compare-matches a and b occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match a and compare-match b, as shown in table 12.6. table 12.6 timer output priorities output setting priority toggle output high 1 output 0 output no change low 12.6.5 switching of internal clocks and tcnt operation tcnt may increment erroneously when the internal clock is switched over. table 12.7 shows the relationship between the timing at which the internal clock is switched (by writing to the cks1 and cks0 bits) and the tcnt operation when the tcnt clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. if clock switching causes a change from high to low level, as shown in no. 3 in table 12.7, a tcnt clock pulse is generated on the assumption that the switchover is a falling edge. this increments tcnt. erroneous incrementation can also happen when switching between internal and external clocks.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 310 of 706 rej09b0303-0300 table 12.7 switching of internal clock and tcnt operation no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 1 switching from low to low * 1 clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite n n + 1 2 switching from low to high * 2 clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite n n + 1 n + 2
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 311 of 706 rej09b0303-0300 no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 3 switching from high to low * 3 clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite n n + 1 n + 2 * 4 4 switching from high to high clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite n n + 1 n + 2 notes: 1. includes switching from low to stop, and from stop to low. 2. includes switching from stop to high. 3. includes switching from high to stop. 4. generated on the assumption that the switchover is a falling edge; tcnt is incremented.
section 12 8-bit timers rev. 3.00 mar 17, 2006 page 312 of 706 rej09b0303-0300
section 13 timer connection rev. 3.00 mar 17, 2006 page 313 of 706 rej09b0303-0300 section 13 timer connection 13.1 overview the h8/3577 group and h8/3567 group allow interconnection between a combination of input signals, the single free-running timer (frt) channel, and the three 8-bit timer channels (tmr 1 , tmrx, and tmry). this capability can be used to implement complex functions such as pwm decoding and clamp waveform output. all the timers are initially set for independent operation. 13.1.1 features the features of the timer connection facility are as follows. ? five input pins and four output pins, all of which can be designated for phase inversion. positive logic is assumed for all signals used within the timer connection facility. ? an edge-detection circuit is connected to the input pins, simplifying signal input detection. ? tmrx can be used for pwm input signal decoding. ? tmrx can be used for clamp waveform generation. ? an external clock signal divided by tmr 1 can be used as the frt capture input signal. ? an internal synchronization signal can be generated using the frt and tmry. ? a signal generated/modified using an input signal and timer connection can be selected and output.
section 13 timer connection rev. 3.00 mar 17, 2006 page 314 of 706 rej09b0303-0300 13.1.2 block diagram figure 13.1 shows a block diagram of the timer connection facility. edge detection edge detection vsynci/ ftia/tmiy vfbacki/ ftib/tmri 0 ftic phase inversion phase inversion phase inversion phase inversion phase inversion phase inversion ivi signal selection read flag edge detection edge detection edge detection phase inversion phase inversion phase inversion read flag ivi signal frt input selec- tion set sync res vertical sync signal modify ftia ftib ftic ftid 16-bit frt ocra +vr, +vf icrd +1m, +2m compare-match ftoa cma(r) cma(f) ftob cm2m cm1m res set 2f h mask generation 2f h mask/flag blanking waveform generation tmr 1 input selection tmci 8-bit tmr1 tmri cmb tmo set ivg signal ivo signal res vertical sync signal generation ivo signal selection tmiy signal selection frt output selection vsynco/ ftoa tmri/tmci tmo 8-bit tmry ihg signal cblank hsynco / tmo 1 / tmox tmox tmo1 output selection iho signal selection cl 4 generation cl 4 signal clamp0/ ftic/ tmo 0 clo signal selection pdc signal pwm decoding 8-bit tmrx cmb tmo cma icr icr +1c compare-match clamp waveform generation tmci tmri cm1c cl 1 signal cl 2 signal cl 3 signal ihi signal ihi signal selection hsynci/ tmci 1 /ftid csynci/ tmri 1 /ftob hfbacki/ ftci/tmix/ tmci 0 figure 13.1 block diagram of timer connection facility
section 13 timer connection rev. 3.00 mar 17, 2006 page 315 of 706 rej09b0303-0300 13.1.3 input and output pins table 13.1 lists the timer connection input and output pins. table 13.1 timer connection input and output pins name abbreviation input/ output function vertical synchronization signal input pin vsynci input vertical synchronization signal input pin or ftia input pin/tmiy input pin horizontal synchronization signal input pin hsynci input horizontal synchronization signal input pin or ftid input pin/tmci 1 input pin composite synchronization signal input pin csynci input composite synchronization signal input pin or tmri 1 input pin/ftob output pin spare vertical synchronization signal input pin vfbacki input spare vertical synchronization signal input pin or ftib input pin/tmri 0 input pin spare horizontal synchronization signal input pin hfbacki input spare horizontal synchronization signal input pin or ftci input pin/tmci 0 input pin/tmix input pin vertical synchronization signal output pin vsynco output vertical synchronization signal output pin or ftoa output pin horizontal synchronization signal output pin hsynco output horizontal synchronization signal output pin or tmo 1 output pin/tmox output pin clamp waveform output pin clampo output clamp waveform output pin or tmo 0 output pin/ftic input pin blanking waveform output pin cblank output blanking waveform output pin
section 13 timer connection rev. 3.00 mar 17, 2006 page 316 of 706 rej09b0303-0300 13.1.4 register configuration table 13.2 lists the timer connection registers. timer connection registers can only be accessed when the hie bit in syscr is 0. table 13.2 register configuration name abbreviation r/w initial value address timer connection register i tconri r/w h'00 h'fffc timer connection register o tconro r/w h'00 h'fffd timer connection register s tconrs r/w h'00 h'fffe edge sense register sedgr r/(w) * 1 h'00 * 2 h'ffff module stop control register mstprh r/w h'3f h'ff86 mstprl r/w h'ff h'ff87 notes: 1. bits 7 to 2: only 0 can be written to clear the flags. 2. bits 1 and 0: undefined (reflect the pin states). 13.2 register descriptions 13.2.1 timer connection register i (tconri) bit 76543210 simod1 simod0 scone icst hfinv vfinv hiinv viinv initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w tconri is an 8-bit readable/writable register that controls connection between timers, the signal source for synchronization signal input, phase inversion, etc. tconr1 is initialized to h'00 by a reset and in hardware standby mode.
section 13 timer connection rev. 3.00 mar 17, 2006 page 317 of 706 rej09b0303-0300 bits 7 and 6?input synchronization mode select 1 and 0 (simod1, simod0): these bits select the signal source of the ihi and ivi signals. bit 7 bit 6 description simod1 simod0 mode ihi signal ivi signal 0 0 no signal (initial value) hfbacki input vfbacki input 1 s-on-g mode csynci input pdc input 1 0 composite mode hsynci input pdc input 1 separate mode hsynci input vsynci input bit 5?synchronization signal connection enable (scone): selects the signal source of the frt fti input and the tmr1 tmci1/tmri1 input. bit 5 description scone mode ftia ftib ftic ftid tmci 1 tmri 1 0 normal connection (initial value) ftia input ftib input ftic input ftid input tmci 1 input tmri 1 input 1 synchronization signal connection mode ivi signal tmo 1 signal vfbacki input ihi signal ihi signal ivi inverse signal bit 4?input capture start bit (icst): the tmrx external reset input (tmrix) is connected to the ihi signal. tmrx has input capture registers (ticr, ticrr, and ticrf). ticrr and ticrf can measure the width of a short pulse by means of a single capture operation under the control of the icst bit. when a rising edge followed by a falling edge is detected on tmrix after the icst bit is set to 1, the contents of tcnt at those points are captured into ticrr and ticrf, respectively, and the icst bit is cleared to 0. bit 4 icst description 0 the ticrr and ticrf input capture functions are stopped [clearing condition] when a rising edge followed by a falling edge is detected on tmrix (initial value) 1 the ticrr and ticrf input capture functions are operating (waiting for detection of a rising edge followed by a falling edge on tmrix) [setting condition] when 1 is written in icst after reading icst = 0
section 13 timer connection rev. 3.00 mar 17, 2006 page 318 of 706 rej09b0303-0300 bits 3 to 0?input synchronization signal inversion (hfinv, vfinv, hiinv, viinv): these bits select inversion of the input phase of the spare horizontal synchronization signal (hfbacki), the spare vertical synchronization signal (vfbacki), the horizontal synchronization signal and composite synchronization signal (hsynci, csynci), and the vertical synchronization signal (vsynci). bit 3 hfinv description 0 the hfbacki pin state is used directly as the hfbacki input (initial value) 1 the hfbacki pin state is inverted before use as the hfbacki input bit 2 vfinv description 0 the vfbacki pin state is used directly as the vfbacki input (initial value) 1 the vfbacki pin state is inverted before use as the vfbacki input bit 1 hiinv description 0 the hsynci and csynci pin states are used directly as the hsynci and csynci inputs (initial value) 1 the hsynci and csynci pin states are inverted before use as the hsynci and csynci inputs bit 0 viinv description 0 the vsynci pin state is used directly as the vsynci input (initial value) 1 the vsynci pin state is inverted before use as the vsynci input 13.2.2 timer connection register o (tconro) bit 76543210 hoe voe cloe cboe hoinv voinv cloinv cboinv initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w
section 13 timer connection rev. 3.00 mar 17, 2006 page 319 of 706 rej09b0303-0300 tconro is an 8-bit readable/writable register that controls output signal output, phase inversion, etc. tconro is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 4?output enable (hoe, voe, cloe, cboe): these bits control enabling/disabling of horizontal synchronization signal (hsynco), vertical synchronization signal (vsynco), clamp waveform (clampo), and blanking waveform (cblank) output. when output is disabled, the state of the relevant pin is determined by the port dr and ddr, frt, tmr, and pwm settings. output enabling/disabling control does not affect the port, frt, or tmr input functions, but some frt and tmr input signal sources are determined by the scone bit in tconri. bit 7 hoe description 0 the p6 7 /tmo 1 /tmox/hsynco pin functions as the p6 7 /tmo 1 /tmox pin (initial value) 1 the p6 7 /tmo 1 /tmox/hsynco pin functions as the hsynco pin bit 6 voe description 0 the p6 1 /ftoa/vsynco pin functions as the p6 1 /ftoa pin (initial value) 1 the p6 1 /ftoa/vsynco pin functions as the vsynco pin bit 5 cloe description 0 the p6 4 /ftic/tmo 0 /clampo pin functions as the p6 4 /ftic/tmo 0 pin (initial value) 1 the p6 4 /ftic/tmo 0 /clampo pin functions as the clampo pin bit 4 cboe description 0 [h8/3577 group] p2 7 /pw 15 /cblank pin functions as the p2 7 /pw 15 pin [h8/3567 group] p1 5 /pw 5 /cblank pin functions as the p1 5 /pw 5 pin (initial value) 1 [h8/3577 group] p2 7 /pw 15 /cblank pin functions as the cblank pin [h8/3567 group] p1 5 /pw 5 /cblank pin functions as the cblank pin
section 13 timer connection rev. 3.00 mar 17, 2006 page 320 of 706 rej09b0303-0300 bits 3 to 0?output synchronization signal inversion (hoinv, voinv, cloinv, cboinv): these bits select inversion of the output phase of the horizontal synchronization signal (hsynco), the vertical synchronization signal (vsynco), the clamp waveform (clampo), and the blank waveform (cblank). bit 3 hoinv description 0 the iho signal is used directly as the hsynco output (initial value) 1 the iho signal is inverted before use as the hsynco output bit 2 voinv description 0 the ivo signal is used directly as the vsynco output (initial value) 1 the ivo signal is inverted before use as the vsynco output bit 1 cloinv description 0 the clo signal (cl 1 , cl 2 , cl 3 , or cl 4 signal) is used directly as the clampo output (initial value) 1 the clo signal (cl 1 , cl 2 , cl 3 , or cl 4 signal) is inverted before use as the clampo output bit 0 cboinv description 0 the cblank signal is used directly as the cblank output (initial value) 1 the cblank signal is inverted before use as the cblank output 13.2.3 timer connection register s (tconrs) bit 76543210 tmrx/y isgene homod1 homod0 vomod1 vomod0 clmod1 clmod0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w
section 13 timer connection rev. 3.00 mar 17, 2006 page 321 of 706 rej09b0303-0300 tconrs is an 8-bit readable/writable register that selects 8-bit timer tmrx/tmry access and the synchronization signal output signal source and generation method. tconrs is initialized to h'00 by a reset and in hardware standby mode. bit 7?tmrx/tmry access select (tmrx/y): the tmrx and tmry registers can only be accessed when the hie bit in syscr is cleared to 0. in the h8/3577 group and h8/3567 group, some of the tmrx registers and the tmry registers are assigned to the same memory space addresses (h'fff0 to h'fff5), and the tmrx/y bit determines which registers are accessed. bit 7 tmrx/y description 0 the tmrx registers are accessed at addresses h'fff0 to h'fff5 (initial value) 1 the tmry registers are accessed at addresses h'fff0 to h'fff5 bit 6?internal synchronization signal select (isgene): selects internal synchronization signals (ihg, ivg, and cl 4 signals) as the signal sources for the iho, ivo, and clo signals. bits 5 and 4?horizontal synchronization output mode select 1 and 0 (homod1, homod0): these bits select the signal source and generation method for the iho signal. bit 6 bit 5 bit 4 isgene vomod1 vomod0 description 0 0 0 the ihi signal (without 2fh modification) is selected (initial value) 1 the ihi signal (with 2fh modification) is selected 1 0 the cl 1 signal is selected 1 1 0 0 the ihg signal is selected 1 10 1
section 13 timer connection rev. 3.00 mar 17, 2006 page 322 of 706 rej09b0303-0300 bits 3 and 2?vertical synchronization output mode select 1 and 0 (vomod1, vomod0): these bits select the signal source and generation method for the ivo signal. bit 6 bit 3 bit 2 isgene vomod1 vomod0 description 0 0 0 the ivi signal (without fall modification or ihi synchronization) is selected (initial value) 1 the ivi signal (without fall modification, with ihi synchronization) is selected 1 0 the ivi signal (with fall modification, without ihi synchronization) is selected 1 the ivi signal (with fall modification and ihi synchronization) is selected 1 0 0 the ivg signal is selected 1 10 1 bits 1 and 0?clamp waveform mode select 1 and 0 (clmod1, clmod0): these bits select the signal source for the clo signal (clamp waveform). bit 6 bit 1 bit 0 isgene clmod1 clmod2 description 0 0 0 the cl 1 signal is selected (initial value) 1 the cl 2 signal is selected 1 0 the cl 3 signal is selected 1 1 0 0 the cl 4 signal is selected 1 10 1
section 13 timer connection rev. 3.00 mar 17, 2006 page 323 of 706 rej09b0303-0300 13.2.4 edge sense register (sedgr) bit 76543210 vedg hedg cedg hfedg vfedg preqf ihi ivi initial value000000? * 2 ? * 2 read/write r/(w) * 1 r/(w) * 1 r/(w) * 1 r/(w) * 1 r/(w) * 1 r/(w) * 1 rr notes: 1. only 0 can be written, to clear the flags. 2. the initial value is undefined since it depends on the pin states. sedgr is an 8-bit readable/writable register used to detect a rising edge on the timer connection input pins and the occurrence of 2fh modification, and to determine the phase of the ivi and ihi signals. the upper 6 bits of sedgr are initialized to 0 by a reset and in hardware standby mode. the initial value of the lower 2 bits is undefined, since it depends on the pin states. bit 7?vsynci edge (vedg): detects a rising edge on the vsynci pin. bit 7 vedg description 0 [clearing condition] when 0 is written in vedg after reading vedg = 1 (initial value) 1 [setting condition] when a rising edge is detected on the vsynci pin bit 6?hsynci edge (hedg): detects a rising edge on the hsynci pin. bit 6 hedg description 0 [clearing condition] when 0 is written in hedg after reading hedg = 1 (initial value) 1 [setting condition] when a rising edge is detected on the hsynci pin
section 13 timer connection rev. 3.00 mar 17, 2006 page 324 of 706 rej09b0303-0300 bit 5?csynci edge (cedg): detects a rising edge on the csynci pin. bit 5 cedg description 0 [clearing condition] when 0 is written in cedg after reading cedg = 1 (initial value) 1 [setting condition] when a rising edge is detected on the csynci pin bit 4?hfbacki edge (hfedg): detects a rising edge on the hfbacki pin. bit 4 hfedg description 0 [clearing condition] when 0 is written in hfedg after reading hfedg = 1 (initial value) 1 [setting condition] when a rising edge is detected on the hfbacki pin bit 3?vfbacki edge (vfedg): detects a rising edge on the vfbacki pin. bit 3 vfedg description 0 [clearing condition] when 0 is written in vfedg after reading vfedg = 1 (initial value) 1 [setting condition] when a rising edge is detected on the vfbacki pin bit 2?pre-equalization flag (preqf): detects the occurrence of an ihi signal 2fh modification condition. the generation of a falling/rising edge in the ihi signal during a mask interval is expressed as the occurrence of a 2fh modification condition. for details, see section 13.3.4, ihi signal 2fh modification.
section 13 timer connection rev. 3.00 mar 17, 2006 page 325 of 706 rej09b0303-0300 bit 2 preqf description 0 [clearing condition] when 0 is written in preqf after reading preqf = 1 (initial value) 1 [setting condition] when an ihi signal 2fh modification condition is detected bit 1?ihi signal level (ihi): indicates the current level of the ihi signal. signal source and phase inversion selection for the ihi signal depends on the contents of tconri. read this bit to determine whether the input signal is positive or negative, then maintain the ihi signal at positive phase by modifying tconri. bit 1 ihi description 0 the ihi signal is low 1 the ihi signal is high bit 0?ivi signal level (ivi): indicates the current level of the ivi signal. signal source and phase inversion selection for the ivi signal depends on the contents of tconri. read this bit to determine whether the input signal is positive or negative, then maintain the ivi signal at positive phase by modifying tconri. bit 0 ivi description 0 the ivi signal is low 1 the ivi signal is high 13.2.5 module stop control register (mstpcr) mstpcrh mstpcrl bit 7654321076543210 mstp 15 mstp 14 mstp 13 mstp 12 mstp 11 mstp 10 mstp 9 mstp 8 mstp 7 mstp 6 mstp 5 mstp 4 mstp 3 mstp 2 mstp 1 mstp 0 initial value 0011111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
section 13 timer connection rev. 3.00 mar 17, 2006 page 326 of 706 rej09b0303-0300 mstpcr, comprising two 8-bit readable/writable registers, performs module stop mode control. when the mstp13, mstp12, and mstp8 bits are set to 1, the 16-bit free-running timer, 8-bit timer channels 0 and 1 and channels x and y, and timer connection, respectively, halt and enter module stop mode at the end of the bus cycle. see section 21.5, module stop mode, for details. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrh bit 5?module stop (mstp13): specifies frt module stop mode. mstpcrh bit 5 mstp13 description 0 frt module stop mode is cleared 1 frt module stop mode is set (initial value) mstpcrh bit 4?module stop (mstp12): specifies 8-bit timer channel 0 and 1 module stop mode. mstpcrh bit 4 mstp12 description 0 8-bit timer channel 0 and 1 module stop mode is cleared 1 8-bit timer channel 0 and 1 module stop mode is set (initial value) mstpcrh bit 0?module stop (mstp8): specifies 8-bit timer channel x and y and timer connection module stop mode. mstpcrh bit 0 mstp8 description 0 8-bit timer channel x and y and timer connection module stop mode is cleared 1 8-bit timer channel x and y and timer connection module stop mode is set (initial value)
section 13 timer connection rev. 3.00 mar 17, 2006 page 327 of 706 rej09b0303-0300 13.3 operation 13.3.1 pwm decoding (pdc signal generation) the timer connection facility and tmrx can be used to decode a pwm signal in which 0 and 1 are represented by the pulse width. to do this, a signal in which a rising edge is generated at regular intervals must be selected as the ihi signal. the timer counter (tcnt) in tmrx is set to count the internal clock pulses and to be cleared on the rising edge of the external reset signal (ihi signal). the value to be used as the threshold for deciding the pulse width is written in tcorb. the pwm decoder contains a delay latch which uses the ihi signal as data and compare-match signal b (cmb) as a clock, and the state of the ihi signal (the result of the pulse width decision) at the compare-match signal b timing after tcnt is reset by the rise of the ihi signal is output as the pdc signal. the pulse width setting using ticrr and ticrf of tmrx can be used to determine the pulse width decision threshold. examples of tcr and tcorb in tmrx settings are shown in tables 13.3 and 13.4, and the timing chart is shown in figure 13.2. table 13.3 examples of tcr settings bit(s) abbreviation contents description 7 6 5 cmieb cmiea ovie 0 0 0 interrupts due to compare-match and overflow are disabled 4 and 3 cclr1, cclr0 11 tcnt is cleared by the rising edge of the external reset signal (ihi signal) 2 to 0 cks2 to cks0 001 incremented on internal clock: table 13.4 examples of tcorb (pulse width threshold) settings h'07 0.8 s 0.67 s 0.5 s 0.4 s h'0f 1.6 s 1.33 s 1 s 0.8 s h'1f 3.2 s 2.67 s 2 s 1.6 s h'3f 6.4 s 5.33 s 4 s 3.2 s h'7f 12.8 s 10.67 s 8 s 6.4 s
section 13 timer connection rev. 3.00 mar 17, 2006 page 328 of 706 rej09b0303-0300 ihi signal counter reset by ihi signal counter clear upon tcnt overflow the ihi signal state is not judged in the 2nd compare-match. judgment of ihi signal state in compare-match pdc signal tcnt tcorb (threshold) figure 13.2 timing chart for pwm decoding 13.3.2 clamp waveform generation (cl 1 /cl 2 /cl 3 signal generation) the timer connection facility and tmrx can be used to generate signals with different duty cycles and rising/falling edges (clamp waveforms) in synchronization with the input signal (ihi signal). three clamp waveforms can be generated: the cl 1 , cl 2 , and cl 3 signals. in addition, the cl 4 signal can be generated using tmry. the cl 1 signal rises simultaneously with the rise of the ihi signal, and when the cl 1 signal is high, the cl 2 signal rises simultaneously with the fall of the ihi signal. the fall of both the cl 1 and the cl 2 signal can be specified by tcora. the rise of the cl 3 signal can be specified as simultaneous with the sampling of the fall of the ihi signal using the system clock, and the fall of the cl 3 signal can be specified by tcorc. the cl 3 signal falls at the rise of the ihi signal. tcnt in tmrx is set to count internal clock pulses and to be cleared on the rising edge of the external reset signal (ihi signal). the value to be used as the cl 1 signal pulse width is written in tcora. write a value of h'02 or more in tcora when internal clock is selected as the tmrx counter clock, and a value or h'01 or more when /2 is selected. when internal clock is selected, the cl 1 signal pulse width is (tcora set value + 3 0.5). when the cl 2 signal is used, the setting must be made so that this pulse width is greater than the ihi signal pulse width. the value to be used as the cl 3 signal pulse width is written in tcorc. the ticr register in tmrx captures the value of tcnt at the inverse of the external reset signal edge (in this case, the falling edge of the ihi signal). the timing of the fall of the cl 3 signal is determined by the sum of
section 13 timer connection rev. 3.00 mar 17, 2006 page 329 of 706 rej09b0303-0300 the contents of ticr and tcorc. caution is required if the rising edge of the ihi signal precedes the fall timing set by the contents of tcorc, since the ihi signal will cause the cl 3 signal to fall. examples of tmrx tcr settings are the same as those in table 13.3. the clamp waveform timing charts are shown in figures 13.3 and 13.4. since the rise of the cl 1 and cl 2 signals is synchronized with the edge of the ihi signal, and their fall is synchronized with the system clock, the pulse width variation is equivalent to the resolution of the system clock. both the rise and the fall of the cl 3 signal are synchronized with the system clock and the pulse width is fixed, but there is a variation in the phase relationship with the ihi signal equivalent to the resolution of the system clock. ihi signal cl 1 signal cl 2 signal tcnt tcora figure 13.3 timing chart for clamp waveform generation (cl 1 and cl 2 signals) ihi signal cl 3 signal tcnt ticr+tcorc ticr figure 13.4 timing chart for clamp waveform generation (cl 3 signal)
section 13 timer connection rev. 3.00 mar 17, 2006 page 330 of 706 rej09b0303-0300 13.3.3 measurement of 8-bit timer divided waveform period the timer connection facility, tmr 1 , and the free-running timer (frt) can be used to measure the period of an ihi signal divided waveform. since tmr 1 can be cleared by a rising edge of the ivi signal, the rise and fall of the ihi signal divided waveform can be virtually synchronized with the ivi signal. this enables period measurement to be carried out efficiently. to measure the period of an ihi signal divided waveform, tcnt in tmr 1 is set to count the external clock (ihi signal) pulses and to be cleared on the rising edge of the external reset signal (ivi signal). the value to be used as the division factor is written in tcora, and the tmo output method is specified by the os bits in tcsr. examples of tmr 1 tcr and tcsr settings are shown in table 13.5, and the timing chart for measurement of the ivi signal and ihi signal divided waveform periods is shown in figure 13.5. the period of the ihi signal divided waveform is given by (icrd(3) ? icrd(2)) the resolution.
section 13 timer connection rev. 3.00 mar 17, 2006 page 331 of 706 rej09b0303-0300 table 13.5 examples of tcr and tcsr settings register bit(s) abbreviation contents description tcr in tmr 1 7cmieb 0 6cmiea 0 5ovie 0 interrupts due to compare-match and overflow are disabled 4, 3 cclr1, cclr0 11 tcnt is cleared by the rising edge of the external reset signal (ivi signal) 2 to 0 cks2 to cks0 101 tcnt is incremented on the rising edge of the external clock (ihi signal) tcsr in tmr 1 3 to 0 os3 to os0 0011 not changed by compare-match b; output inverted by compare-match a (toggle output): division by 512 1001 or when tcorb < tcora, 1 output on compare-match b, and 0 output on compare-match a: division by 256 tcr in frt 6 iedgb 0/1 0: frc value is transferred to icrb on falling edge of input capture input b (ihi divided signal waveform) 1: frc value is transferred to icrb on rising edge of input capture input b (ihi divided signal waveform) 1, 0 cks1, cks0 01 frc is incremented on internal clock:
section 13 timer connection rev. 3.00 mar 17, 2006 page 332 of 706 rej09b0303-0300 ivi signal ihi signal divided waveform frc icrb icrb(1) icrb(2) icrb(3) icrb(4) figure 13.5 timing chart for measurement of ivi signal and ihi signal divided waveform periods 13.3.4 ihi signal and 2fh modification by using the timer connection frt, even if there is a part of the ihi signal with twice the frequency, this can be eliminated. in order for this function to operate properly, the duty cycle of the ihi signal must be approximately 30% or less, or approximately 70% or above. the 8-bit ocrdm contents or twice the ocrdm contents can be added automatically to the data captured in icrd in the frt, and compare-matches generated at these points. the interval between the two compare-matches is called a mask interval. a value equivalent to approximately 1/3 the ihi signal period is written in ocrdm. icrd is set so that capture is performed on the rise of the ihi signal. since the ihi signal supplied to the iho signal selection circuit is normally set on the rise of the ihi signal and reset on the fall, its waveform is the same as that of the original ihi signal. when 2fh modification is selected, ihi signal edge detection is disabled during mask intervals. capture is also disabled during these intervals. examples of frt tcr settings are shown in table 13.6, and the 2fh modification timing chart is shown in figure 13.6.
section 13 timer connection rev. 3.00 mar 17, 2006 page 333 of 706 rej09b0303-0300 table 13.6 examples of tcr, tcsr, tcor, and ocrdm settings register bit(s) abbreviation contents description tcr in frt 4 iedgd 1 frc value is transferred to icrd on the rising edge of input capture input d (ihi signal) 1, 0 cks1, cks0 01 frc is incremented on internal clock: figure 13.6 2fh modification timing chart
section 13 timer connection rev. 3.00 mar 17, 2006 page 334 of 706 rej09b0303-0300 13.3.5 ivi signal fall modification and ihi synchronization by using the timer connection tmr 1 , the fall of the ivi signal can be shifted backward by the specified number of ihi signal waveforms. also, the fall of the ivi signal can be synchronized with the rise of the ihi signal. to perform 8-bit timer divided waveform period measurement, tcnt in tmr 1 is set to count external clock (ihi signal) pulses, and to be cleared on the rising edge of the external reset signal (inverse of the ivi signal). the number of ihi signal pulses until the fall of the ivi signal is written in tcorb. since the ivi signal supplied to the ivo signal selection circuit is normally set on the rise of the ivi signal and reset on the fall, its waveform is the same as that of the original ivi signal. when fall modification is selected, a reset is performed on a tmr 1 tcorb compare-match. the fall of the waveform generated in this way can be synchronized with the rise of the ihi signal, regardless of whether or not fall modification is selected. examples of tmr 1 tcorb, tcr, and tcsr settings are shown in table 13.7, and the fall modification/ihi synchronization timing chart is shown in figure 13.7.
section 13 timer connection rev. 3.00 mar 17, 2006 page 335 of 706 rej09b0303-0300 table 13.7 examples of tcorb, tcr, and tcsr settings register bit(s) abbreviation contents description 7cmieb 0 6cmiea 0 5ovie 0 interrupts due to compare-match and overflow are disabled 4, 3 cclr1, cclr0 11 tcnt is cleared by the rising edge of the external reset signal (inverse of the ivi signal) tcr in tmr 1 2 to 0 cks2 to cks0 101 tcnt is incremented on the rising edge of the external clock (ihi signal) tcsr in tmr 1 3 to 0 os3 to os0 0011 not changed by compare-match b; output inverted by compare-match a (toggle output) 1001 or when tcorb < tcora, 1 output on compare-match b, 0 output on compare- match a tocrb in tmr 1 h'03 (example) compare-match on the 4th (example) rise of the ihi signal after the rise of the inverse of the ivi signal 0 1 2 3 4 5 tcnt tcnt = tcorb (3) ihi signal ivi signal (pdc signal) ivo signal (without fall modification, with ihi synchronization) ivo signal (with fall modification, without ihi synchronization) ivo signal (with fall modification and ihi synchronization) figure 13.7 fall modification/ihi synchronization timing chart
section 13 timer connection rev. 3.00 mar 17, 2006 page 336 of 706 rej09b0303-0300 13.3.6 internal synchronization signal generation (ihg/ivg/cl 4 signal generation) by using the timer connection frt and tmry, it is possible to automatically generate internal signals (ihg and ivg signals) corresponding to the ihi and ivi signals. as the ihg signal is synchronized with the rise of the ivg signal, the ihg signal period must be made a divisor of the ivg signal period in order to keep it constant. in addition, the cl 4 signal can be generated in synchronization with the ihg signal. the contents of ocra in the frt are updated by the automatic addition of the contents of ocrar or ocraf, alternately, each time a compare-match occurs. a value corresponding to the 0 interval of the ivg signal is written in ocrar, and a value corresponding to the 1 interval of the ivg signal is written in ocraf. the ivg signal is set by a compare-match after an ocrar addition, and reset by a compare-match after an ocraf addition. the ihg signal is the tmry 8-bit timer output. tmry is set to count internal clock pulses, and to be cleared on tcora compare-match, to fix the period and set the timer output. tcorb is set so as to reset the timer output. the ivg signal is connected as the tmry reset input (tmri), and the rise of the ivg signal can be treated in the same way as a tcora compare-match. the cl 4 signal is a waveform that rises within one system clock period after the fall of the ihg signal, and has a 1 interval of 6 system clock periods. examples of settings of tcora, tcorb, tcr, and tcsr in tmry, and ocrar, ocraf, and tcr in the frt, are shown in table 13.8, and the ihg signal/ivg signal timing chart is shown in figure 13.8.
section 13 timer connection rev. 3.00 mar 17, 2006 page 337 of 706 rej09b0303-0300 table 13.8 examples of ocrar, ocraf, tocr, tcora, tcorb, tcr, and tcsr settings register bit(s) abbreviation contents description 7cmieb 0 6cmiea 0 5ovie 0 interrupts due to compare-match and overflow are disabled 4, 3 cclr1, cclr0 01 tcnt is cleared by compare-match a tcr in tmry 2 to 0 cks2 to cks0 001 tcnt is incremented on internal clock:
section 13 timer connection rev. 3.00 mar 17, 2006 page 338 of 706 rej09b0303-0300 6 system clocks 6 system clocks 6 system clocks ocra (4) = ocra (3) + ocrar ocra (3) = ocra (2) + ocraf ocra (2) = ocra (1) + ocrar ocra (1) = ocra (0) + ocraf ocra frc cl 4 signal ihg signal tcora tcorb tcnt ivg signal figure 13.8 ivg signal/ihg signal/cl 4 signal timing chart
section 13 timer connection rev. 3.00 mar 17, 2006 page 339 of 706 rej09b0303-0300 13.3.7 hsynco output with the hsynco output, the meaning of the signal source to be selected and use or non-use of modification varies according to the ihi signal source and the waveform required by external circuitry. the meaning of the hsynco output in each mode is shown in table 13.9. table 13.9 meaning of hsynco output in each mode mode ihi signal iho signal meaning of iho signal no signal hfbacki input ihi signal (without 2fh modification) hfbacki input is output directly ihi signal (with 2fh modification) meaningless unless there is a double-frequency part in the hfbacki input cl 1 signal hfbacki input 1 interval is changed before output ihg signal internal synchronization signal is output s-on-g mode csynci input ihi signal (without 2fh modification) csynci input (composite synchronization signal) is output directly ihi signal (with 2fh modification) double-frequency part of csynci input (composite synchronization signal) is eliminated before output cl 1 signal csynci input (composite synchronization signal) horizontal synchronization signal part is separated before output ihg signal internal synchronization signal is output composite mode hsynci input ihi signal (without 2fh modification) hsynci input (composite synchronization signal) is output directly ihi signal (with 2fh modification) double-frequency part of hsynci input (composite synchronization signal) is eliminated before output cl 1 signal hsynci input (composite synchronization signal) horizontal synchronization signal part is separated before output ihg signal internal synchronization signal is output separate mode hsynci input ihi signal (without 2fh modification) hsynci input (horizontal synchronization signal) is output directly ihi signal (with 2fh modification) meaningless unless there is a double-frequency part in the hsynci input (horizontal synchronization signal) cl 1 signal hsynci input (horizontal synchronization signal) 1 interval is changed before output ihg signal internal synchronization signal is output
section 13 timer connection rev. 3.00 mar 17, 2006 page 340 of 706 rej09b0303-0300 13.3.8 vsynco output with the vsynco output, the meaning of the signal source to be selected and use or non-use of modification varies according to the ivi signal source and the waveform required by external circuitry. the meaning of the vsynco output in each mode is shown in table 13.10. table 13.10 meaning of vsynco output in each mode mode ivi signal ivo signal meaning of ivo signal no signal vfbacki input ivi signal (without fall modification or ihi synchronization) vfbacki input is output directly ivi signal (without fall modification, with ihi synchronization) meaningless unless vfbacki input is synchronized with hfbacki input ivi signal (with fall modification, without ihi synchronization) vfbacki input fall is modified before output ivi signal (with fall modification and ihi synchronization) vfbacki input fall is modified and signal is synchronized with hfbacki input before output ivg signal internal synchronization signal is output s-on-g mode or composite mode pdc signal ivi signal (without fall modification or ihi synchronization) csynci/hsynci input (composite synchronization signal) vertical synchronization signal part is separated before output ivi signal (without fall modification, with ihi synchronization) csynci/hsynci input (composite synchronization signal) vertical synchronization signal part is separated, and signal is synchronized with csynci/hsynci input before output ivi signal (with fall modification, without ihi synchronization) csynci/hsynci input (composite synchronization signal) vertical synchronization signal part is separated, and fall is modified before output ivi signal (with fall modification and ihi synchronization) csynci/hsynci input (composite synchronization signal) vertical synchronization signal part is separated, fall is modified, and signal is synchronized with csynci/hsynci input before output ivg signal internal synchronization signal is output
section 13 timer connection rev. 3.00 mar 17, 2006 page 341 of 706 rej09b0303-0300 mode ivi signal ivo signal meaning of ivo signal separate mode vsynci input ivi signal (without fall modification or ihi synchronization) vsynci input (vertical synchronization signal) is output directly ivi signal (without fall modification, with ihi synchronization) meaningless unless vsynci input (vertical synchronization signal) is synchronized with hsynci input (horizontal synchronization signal) ivi signal (with fall modification, without ihi synchronization) vsynci input (vertical synchronization signal) fall is modified before output ivi signal (with fall modification and ihi synchronization) vsynci input (vertical synchronization signal) fall is modified and signal is synchronized with hsynci input (horizontal synchronization signal) before output ivg signal internal synchronization signal is output 13.3.9 cblank output using the signals generated/selected with timer connection, it is possible to generate a waveform based on the composite synchronization signal (blanking waveform). one kind of blanking waveform is generated by combining hfbacki and vfbacki inputs, with the phase polarity made positive by means of bits hfinv and vfinv in tconri, with the ivo signal. the composition logic is shown in figure 13.9. set reset cblank signal (positive) hfbacki input (positive) vfbacki input (positive) ivo signal (positive) q falling edge sensing rising edge sensing figure 13.9 cblank output waveform generation
section 13 timer connection rev. 3.00 mar 17, 2006 page 342 of 706 rej09b0303-0300
section 14 watchdog timer (wdt) rev. 3.00 mar 17, 2006 page 343 of 706 rej09b0303-0300 section 14 watchdog timer (wdt) 14.1 overview the h8/3577 group and h8/3567 group have an on-chip watchdog timer (wdt0). the wdt outputs an overflow signal if a system crash prevents the cpu from writing to the timer counter, allowing it to overflow. at the same time, the wdt can also generate an internal reset signal or internal nmi interrupt signal. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer mode, an interval timer interrupt is generated each time the counter overflows. 14.1.1 features ? switchable between watchdog timer mode and interval timer mode ? wovi interrupt generation in interval timer mode ? internal reset or internal interrupt generated when the timer counter overflows ? choice of internal reset or nmi interrupt generation in watchdog timer mode ? choice of 8 counter input clocks ? maximum wdt interval: system clock period 131072 256
section 14 watchdog timer (wdt) rev. 3.00 mar 17, 2006 page 344 of 706 rej09b0303-0300 14.1.2 block diagram figure 14.1 shows block diagram of wdt0. overflow wovi (interrupt request signal) internal reset signal * tcnt tcsr /2 /64 /128 /512 /2048 /8192 /32768 /131072 clock clock select internal clock source bus interface module bus internal bus wdt legend: tcsr: timer control/status register tcnt: timer counter note: * the internal reset signal can be generated by means of a register setting. internal nmi interrupt request signal interrupt control reset control figure 14.1 block diagram of wdt0
section 14 watchdog timer (wdt) rev. 3.00 mar 17, 2006 page 345 of 706 rej09b0303-0300 14.1.3 register configuration the wdt has four registers, as summarized in table 14.1. these registers control clock selection, wdt mode switching, the reset signal, etc. table 14.1 wdt registers address channel name abbreviation r/w initial value write * 1 read 0 timer control/status register 0 tcsr0 r/(w) * 2 h'00 h'ffa8 h'ffa8 timer counter 0 tcnt0 r/w h'00 h'ffa8 h'ffa9 common system control register syscr r/w h'09 h'ffc4 h'ffc4 notes: 1. for details of write operations, see section 14.2.4, notes on register access. 2. only 0 can be written in bit 7, to clear the flag. 14.2 register descriptions 14.2.1 timer counter (tcnt) bit 76543210 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w tcnt is an 8-bit readable/writable * up-counter. when the tme bit is set to 1 in tcsr, tcnt starts counting pulses generated from the internal clock source selected by bits cks2 to cks0 in tcsr. when the tcnt value overflows (changes from h'ff to h'00), the ovf flag in tcsr is set to 1. tcnt is initialized to h'00 by a reset, in hardware standby mode, or when the tme bit is cleared to 0. it is not initialized in software standby mode. note: * the method of writing to tcnt is more complicated than for most other registers, to prevent accidental overwriting. for details see section 14.2.4, notes on register access.
section 14 watchdog timer (wdt) rev. 3.00 mar 17, 2006 page 346 of 706 rej09b0303-0300 14.2.2 timer control/status register (tcsr0) bit 76543210 ovf wt/ it tme rsts rst/ nmi cks2 cks1 cks0 initial value00000000 read/write r/(w) * r/w r/w r/w r/w r/w r/w r/w note: * only 0 can be written, to clear the flag. tcsr is an 8-bit readable/writable * register. its functions include selecting the clock source to be input to tcnt, and the timer mode. tcsr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. note: * the method of writing to tcsr is more complicated than for most other registers, to prevent accidental overwriting. for details see section 14.2.4, notes on register access. bit 7?overflow flag (ovf): a status flag that indicates that tcnt has overflowed from h'ff to h'00. bit 7 ovf description 0 [clearing conditions] ? write 0 in the tme bit ? read tcsr when ovf = 1 * , then write 0 in ovf (initial value) 1 [setting condition] when tcnt overflows (changes from h'ff to h'00) (when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset.) note: * when the interval timer interrupt is disabled and ovf is polled, reading ovf while set to 1 should be performed at least twice.
section 14 watchdog timer (wdt) rev. 3.00 mar 17, 2006 page 347 of 706 rej09b0303-0300 bit 6?timer mode select (wt/ it it it it ): selects whether the wdt is used as a watchdog timer or interval timer. if used as an interval timer, the wdt generates an interval timer interrupt request (wovi) when tcnt overflows. if used as a watchdog timer, the wdt generates a reset or nmi interrupt when tcnt overflows. bit 6 wt/ it it it it description 0 interval timer: sends the cpu an interval timer interrupt request (wovi) when tcnt overflows (initial value) 1 watchdog timer: generates a reset or nmi interrupt when tcnt overflows bit 5?timer enable (tme): selects whether tcnt runs or is halted. bit 5 tme description 0 tcnt is initialized to h'00 and halted (initial value) 1 tcnt counts tcsr0 bit 4?reset select (rsts): reserved. this bit should not be set to 1. bit 3?reset or nmi (rst/ nmi nmi nmi nmi ): specifies whether an internal reset or nmi interrupt is requested on tcnt overflow in watchdog timer mode. bit 3 rst/ nmi nmi nmi nmi description 0 an nmi interrupt is requested (initial value) 1 an internal reset is requested
section 14 watchdog timer (wdt) rev. 3.00 mar 17, 2006 page 348 of 706 rej09b0303-0300 bits 2 to 0?clock select 2 to 0 (cks2 to cks0): these bits select the clock to be input to tcnt from internal clocks obtained by dividing the system clock. bit 2 bit 1 bit 0 description cks2 cks1 cks0 clock overflow period * (when = 20 mhz) 000 /2 (initial value) 25.6 s 1 /64 819.2 s 10 /128 1.6 ms 1 /512 6.6 ms 100 /2048 26.2 ms 1 /8192 104.9 ms 10 /32768 419.4 ms 1 /131072 1.68 s note: * the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs. 14.2.3 system control register (syscr) bit 76543210 cs2e iose intm1 intm0 xrst nmieg hie rame initial value00001001 read/write r/w r/w r r r r/w r/w r/w only bit 3 is described here. for details on functions not related to the watchdog timer, see sections 3.2.2 and 5.2.1, system control register (syscr), and the descriptions of the relevant modules. bit 3?external reset (xrst): indicates the reset source. when the watchdog timer is used, a reset can be generated by watchdog timer overflow in addition to external reset input. xrst is a read-only bit. it is set to 1 by an external reset, and cleared to 0 by watchdog timer overflow. bit 3 xrst description 0 reset is generated by watchdog timer overflow 1 reset is generated by external reset input (initial value)
section 14 watchdog timer (wdt) rev. 3.00 mar 17, 2006 page 349 of 706 rej09b0303-0300 14.2.4 notes on register access the watchdog timer?s tcnt and tcsr registers differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. writing to tcnt and tcsr: these registers must be written to by a word transfer instruction. they cannot be written to with byte transfer instructions. figure 14.2 shows the format of data written to tcnt and tcsr. tcnt and tcsr both have the same write address. for a write to tcnt, the upper byte of the written word must contain h'5a and the lower byte must contain the write data. for a write to tcsr, the upper byte of the written word must contain h'a5 and the lower byte must contain the write data. this transfers the write data from the lower byte to tcnt or tcsr. tcnt write tcsr write address: h'ffa8 address: h'ffa8 h'5a write data 15 8 7 0 h'a5 write data 15 8 7 0 figure 14.2 format of data written to tcnt and tcsr reading tcnt and tcsr: these registers are read in the same way as other registers. the read addresses are h'ffa8 for tcsr, and h'ffa9 for tcnt. 14.3 operation 14.3.1 watchdog timer operation to use the wdt as a watchdog timer, set the wt/ it and tme bits in tcsr to 1. software must prevent tcnt overflows by rewriting the tcnt value (normally by writing h'00) before overflow occurs. this ensures that tcnt does not overflow while the system is operating normally. if tcnt overflows without being rewritten because of a system crash or other error, an internal reset or nmi interrupt request is generated. when the rst/ nmi bit is set to 1, the chip is reset for 518 system clock periods (518 ) by a counter overflow. this is illustrated in figure 14.3.
section 14 watchdog timer (wdt) rev. 3.00 mar 17, 2006 page 350 of 706 rej09b0303-0300 an internal reset request from the watchdog timer and reset input from the res pin are handled via the same vector. the reset source can be identified from the value of the xrst bit in syscr. if a reset caused by an input signal from the res pin and a reset caused by wdt overflow occur simultaneously, the res pin reset has priority, and the xrst bit in syscr is set to 1. an nmi interrupt request from the watchdog timer and an interrupt request from the nmi pin are handled via the same vector. simultaneous handling of a watchdog timer nmi interrupt request and an nmi pin interrupt request must therefore be avoided. tcnt value h'00 time h'ff wt/it = 1 tme = 1 h'00 written to tcnt wt/it = 1 tme = 1 h'00 written to tcnt 518 system clock periods internal reset signal overflow ovf = 1 * internal reset generated legend: wt/ it : timer mode select bit tme: timer enable bit note: * cleared to 0 by an internal reset when ovf is set to 1. xrst is cleared to 0. figure 14.3 operation in watchdog timer mode 14.3.2 interval timer operation to use the wdt as an interval timer, clear the wt/ it bit in tcsr to 0 and set the tme bit to 1. an interval timer interrupt (wovi) is generated each time tcnt overflows, provided that the wdt is operating as an interval timer, as shown in figure 14.4. this function can be used to generate interrupt requests at regular intervals.
section 14 watchdog timer (wdt) rev. 3.00 mar 17, 2006 page 351 of 706 rej09b0303-0300 tcnt count h'00 time h'ff wt/it = 0 tme = 1 wovi overflow overflow overflow overflow legend: wovi: interval timer interrupt request generation wovi wovi wovi figure 14.4 operation in interval timer mode 14.3.3 timing of setting of overflow flag (ovf) the ovf bit in tcsr is set to 1 if tcnt overflows during interval timer operation. at the same time, an interval timer interrupt (wovi) is requested. this timing is shown in figure 14.5. if nmi request generation is selected in watchdog timer mode, when tcnt overflows the ovf bit in tcsr is set to 1 and at the same time an nmi interrupt is requested. tcnt h'ff h'00 overflow signal (internal signal) ovf figure 14.5 timing of ovf setting
section 14 watchdog timer (wdt) rev. 3.00 mar 17, 2006 page 352 of 706 rej09b0303-0300 14.4 interrupts during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. ovf must be cleared to 0 in the interrupt handling routine. when nmi interrupt request generation is selected in watchdog timer mode, an overflow generates an nmi interrupt request. 14.5 usage notes 14.5.1 contention between timer counter (tcnt) write and increment if a timer counter clock pulse is generated during the t 2 state of a tcnt write cycle, the write takes priority and the timer counter is not incremented. figure 14.6 shows this operation. address internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle counter write data t 3 figure 14.6 contention between tcnt write and increment
section 14 watchdog timer (wdt) rev. 3.00 mar 17, 2006 page 353 of 706 rej09b0303-0300 14.5.2 changing value of cks2 to cks0 if bits cks2 to cks0 in tcsr are written to while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before changing the value of bits cks2 to cks0. 14.5.3 switching between watchdog timer mode and interval timer mode if the mode is switched from watchdog timer to interval timer, or vice versa, while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before switching the mode.
section 14 watchdog timer (wdt) rev. 3.00 mar 17, 2006 page 354 of 706 rej09b0303-0300
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 355 of 706 rej09b0303-0300 section 15 serial communication interface (sci) 15.1 overview the h8/3577 group and h8/3567 group are equipped with a single-channel serial communication interface (sci). the sci can handle both asynchronous and clocked synchronous serial communication. a function is also provided for serial communication between processors (multiprocessor communication function). 15.1.1 features sci features are listed below. ? choice of asynchronous or synchronous serial communication mode asynchronous mode ? serial data communication is executed using an asynchronous system in which synchronization is achieved character by character serial data communication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia) ? a multiprocessor communication function is provided that enables serial data communication with a number of processors ? choice of 12 serial data transfer formats data length: 7 or 8 bits stop bit length: 1 or 2 bits parity: even, odd, or none multiprocessor bit: 1 or 0 ? receive error detection: parity, overrun, and framing errors ? break detection: break can be detected by reading the rxd pin level directly in case of a framing error synchronous mode ? serial data communication is synchronized with a clock serial data communication can be carried out with other chips that have a synchronous communication function ? one serial data transfer format data length: 8 bits ? receive error detection: overrun errors detected
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 356 of 706 rej09b0303-0300 ? full-duplex communication capability ? the transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously ? double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data ? lsb-first or msb-first transfer can be selected ? this selection can be made regardless of the communication mode (with the exception of 7-bit data transfer in asynchronous mode) * note: * lsb-first transfer is used in the examples in this section. ? built-in baud rate generator allows any bit rate to be selected ? choice of serial clock source: internal clock from baud rate generator or external clock from sck pin ? four interrupt sources ? four interrupt sources (transmit-data-empty, transmit-end, receive-data-full, and receive error) that can issue requests independently
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 357 of 706 rej09b0303-0300 15.1.2 block diagram figure 15.1 shows a block diagram of the sci. bus interface tdr rsr rdr module data bus tsr ssr scmr scr smr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity generation parity check clock external clock /4 /16 /64 txi tei rxi eri legend: rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register scr: serial control register ssr: serial status register scmr: serial interface mode register brr: bit rate register figure 15.1 block diagram of sci
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 358 of 706 rej09b0303-0300 15.1.3 pin configuration table 15.1 shows the serial pins used by the sci. table 15.1 sci pins channel pin name symbol i/o function 0 serial clock pin 0 sck 0 i/o sci0 clock input/output receive data pin 0 rxd 0 input sci0 receive data input transmit data pin 0 txd 0 output sci0 transmit data output note: the abbreviations sck, rxd, and txd are used in the text, omitting the channel number. 15.1.4 register configuration the sci has the internal registers shown in table 15.2. these registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the transmitter/receiver. table 15.2 sci registers channel name abbreviation r/w initial value address 0 serial mode register 0 smr0 r/w h'00 h'ffd8 * 2 bit rate register 0 brr0 r/w h'ff h'ffd9 * 2 serial control register 0 scr0 r/w h'00 h'ffda transmit data register 0 tdr0 r/w h'ff h'ffdb serial status register 0 ssr0 r/(w) * 1 h'84 h'ffdc receive data register 0 rdr0 r h'00 h'ffdd serial interface mode register 0 scmr0 r/w h'f2 h'ffde * 3 common module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 notes: 1. only 0 can be written, to clear flags. 2. some serial communication interface registers are assigned to the same addresses as other registers. in this case, register selection is performed by the iice bit in the serial timer control register (stcr).
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 359 of 706 rej09b0303-0300 15.2 register descriptions 15.2.1 receive shift register (rsr) bit 76543210 read/write ? ??????? rsr is a register used to receive serial data. the sci sets serial data input from the rxd pin in rsr in the order received, starting with the lsb (bit 0), and converts it to parallel data. when one byte of data has been received, it is transferred to rdr automatically. rsr cannot be directly read or written to by the cpu. 15.2.2 receive data register (rdr) bit 76543210 initial value00000000 read/write r rrrrrrr rdr is a register that stores received serial data. when the sci has received one byte of serial data, it transfers the received serial data from rsr to rdr where it is stored, and completes the receive operation. after this, rsr is receive-enabled. since rsr and rdr function as a double buffer in this way, continuous receive operations can be performed. rdr is a read-only register, and cannot be written to by the cpu. rdr is initialized to h'00 by a reset, and in standby mode, and module stop mode.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 360 of 706 rej09b0303-0300 15.2.3 transmit shift register (tsr) bit 76543210 read/write ? ??????? tsr is a register used to transmit serial data. to perform serial data transmission, the sci first transfers transmit data from tdr to tsr, then sends the data to the txd pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from tdr to tsr, and transmission started, automatically. however, data transfer from tdr to tsr is not performed if the tdre bit in ssr is set to 1. tsr cannot be directly read or written to by the cpu. 15.2.4 transmit data register (tdr) bit 76543210 initial value11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w tdr is an 8-bit register that stores data for serial transmission. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts serial transmission. continuous serial transmission can be carried out by writing the next transmit data to tdr during serial transmission of the data in tsr. tdr can be read or written to by the cpu at all times. tdr is initialized to h'ff by a reset, and in standby mode, and module stop mode. 15.2.5 serial mode register (smr) bit 76543210 c/ a chr pe o/ e stop mp cks1 cks0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 361 of 706 rej09b0303-0300 smr is an 8-bit register used to set the sci?s serial transfer format and select the baud rate generator clock source. smr can be read or written to by the cpu at all times. smr is initialized to h'00 by a reset, and in standby mode, and module stop mode. bit 7?communication mode (c/ a a a a ): selects asynchronous mode or synchronous mode as the sci operating mode. bit 7 c/ a a a a description 0 asynchronous mode (initial value) 1 synchronous mode bit 6?character length (chr): selects 7 or 8 bits as the data length in asynchronous mode. in synchronous mode, a fixed data length of 8 bits is used regardless of the chr setting. bit 6 chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and lsb- first/msb-first selection is not available. bit 5?parity enable (pe): in asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. in synchronous mode, or when a multiprocessor format is used, parity bit addition and checking is not performed, regardless of the pe bit setting. bit 5 pe description 0 parity bit addition and checking disabled (initial value) 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 362 of 706 rej09b0303-0300 bit 4?parity mode (o/ e e e e ): selects either even or odd parity for use in parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. the o/ e bit setting is invalid in synchronous mode, when parity bit addition and checking is disabled in asynchronous mode, and when a multiprocessor format is used. bit 4 o/ e e e e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. bit 3?stop bit length (stop): selects 1 or 2 bits as the stop bit length in asynchronous mode. the stop bit setting is only valid in asynchronous mode. if synchronous mode is set the stop bit setting is invalid since stop bits are not added. bit 3 stop description 01 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. in transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 2. in transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 363 of 706 rej09b0303-0300 bit 2?multiprocessor mode (mp): selects multiprocessor format. when multiprocessor format is selected, the pe bit and o/ e bit parity settings are invalid. the mp bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. for details of the multiprocessor communication function, see section 15.3.3, multiprocessor communication function. bit 2 mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected bits 1 and 0?clock select 1 and 0 (cks1, cks0): these bits select the clock source for the baud rate generator. the clock source can be selected from , /4, /16, and /64, according to the setting of bits cks1 and cks0. for the relation between the clock source, the bit rate register setting, and the baud rate, see section 15.2.8, bit rate register. bit 1 bit 0 cks1 cks0 description 00 clock (initial value) 1 /4 clock 10 /16 clock 1 /64 clock 15.2.6 serial control register (scr) bit 76543210 tie rie te re mpie teie cke1 cke0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w scr is a register that performs enabling or disabling of sci transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. scr can be read or written to by the cpu at all times.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 364 of 706 rej09b0303-0300 scr is initialized to h'00 by a reset, and in standby mode, and module stop mode. bit 7?transmit interrupt enable (tie): enables or disables transmit-data-empty interrupt (txi) request generation when serial transmit data is transferred from tdr to tsr and the tdre flag in ssr is set to 1. bit 7 tie description 0 transmit-data-empty interrupt (txi) request disabled * (initial value) 1 transmit-data-empty interrupt (txi) request enabled note: * txi interrupt request cancellation can be performed by reading 1 from the tdre flag, then clearing it to 0, or clearing the tie bit to 0. bit 6?receive interrupt enable (rie): enables or disables receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request generation when serial receive data is transferred from rsr to rdr and the rdrf flag in ssr is set to 1. bit 6 rie description 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled * (initial value) 1 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled note: * rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf, fer, per, or orer flag, then clearing the flag to 0, or clearing the rie bit to 0. bit 5?transmit enable (te): enables or disables the start of serial transmission by the sci. bit 5 te description 0 transmission disabled * 1 (initial value) 1 transmission enabled * 2 notes: 1. the tdre flag in ssr is fixed at 1. 2. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transmission format before setting the te bit to 1.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 365 of 706 rej09b0303-0300 bit 4?receive enable (re): enables or disables the start of serial reception by the sci. bit 4 re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: 1. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 2. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. smr setting must be performed to decide the reception format before setting the re bit to 1. bit 3?multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie bit setting is only valid in asynchronous mode when receiving with the mp bit in smr set to 1. the mpie bit setting is invalid in synchronous mode or when the mp bit is cleared to 0. bit 3 mpie description 0 multiprocessor interrupts disabled (normal reception performed) (initial value) [clearing conditions] ? when the mpie bit is cleared to 0 ? when data with mpb = 1 is received 1 multiprocessor interrupts enabled * receive interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. note: * when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr, is not performed. when receive data with mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. bit 2?transmit end interrupt enable (teie): enables or disables transmit-end interrupt (tei) request generation if there is no valid transmit data in tdr when the msb is transmitted.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 366 of 706 rej09b0303-0300 bit 2 teie description 0 transmit-end interrupt (tei) request disabled * (initial value) 1 transmit-end interrupt (tei) request enabled * note: * tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0. bits 1 and 0?clock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. the combination of the cke1 and cke0 bits determines whether the sck pin functions as an i/o port, the serial clock output pin, or the serial clock input pin. the setting of the cke0 bit, however, is only valid for internal clock operation (cke1 = 0) in asynchronous mode. the cke0 bit setting is invalid in synchronous mode, and in the case of external clock operation (cke1 = 1). the setting of bits cke1 and cke0 must be carried out before the sci?s operating mode is determined using smr. for details of clock source selection, see table 15.9 in section 15.3, operation. bit 1 bit 0 cke1 cke0 description 0 0 asynchronous mode internal clock/sck pin functions as i/o port * 1 synchronous mode internal clock/sck pin functions as serial clock output * 1 1 asynchronous mode internal clock/sck pin functions as clock output * 2 synchronous mode internal clock/sck pin functions as serial clock output 1 0 asynchronous mode external clock/sck pin functions as clock input * 3 synchronous mode external clock/sck pin functions as serial clock input 1 asynchronous mode external clock/sck pin functions as clock input * 3 synchronous mode external clock/sck pin functions as serial clock input notes: 1. initial value 2. outputs a clock of the same frequency as the bit rate. 3. inputs a clock with a frequency 16 times the bit rate.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 367 of 706 rej09b0303-0300 15.2.7 serial status register (ssr) bit 76543210 tdre rdrf orer fer per tend mpb mpbt initial value10000100 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * rrr/w note: * only 0 can be written, to clear the flag. ssr is an 8-bit register containing status flags that indicate the operating status of the sci, and multiprocessor bits. ssr can be read or written to by the cpu at all times. however, 1 cannot be written to flags tdre, rdrf, orer, per, and fer. also note that in order to clear these flags they must be read as 1 beforehand. the tend flag and mpb flag are read-only flags and cannot be modified. ssr is initialized to h'84 by a reset, and in standby mode, and module stop mode. bit 7?transmit data register empty (tdre): indicates that data has been transferred from tdr to tsr and the next serial data can be written to tdr. bit 7 tdre description 0 [clearing condition] when 0 is written in tdre after reading tdre = 1 1 [setting conditions] (initial value) ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 368 of 706 rej09b0303-0300 bit 6?receive data register full (rdrf): indicates that the received data is stored in rdr. bit 6 rdrf description 0 [clearing condition] (initial value) when 0 is written in rdrf after reading rdrf = 1 1 [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr note: rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. bit 5?overrun error (orer): indicates that an overrun error occurred during reception, causing abnormal termination. bit 5 orer description 0 [clearing condition] (initial value) * 1 when 0 is written in orer after reading orer = 1 1 [setting condition] when the next serial reception is completed while rdrf = 1 * 2 notes: 1. the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. in synchronous mode, serial transmission cannot be continued, either.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 369 of 706 rej09b0303-0300 bit 4?framing error (fer): indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. bit 4 fer description 0 [clearing condition] (initial value) * 1 when 0 is written in fer after reading fer = 1 1 [setting condition] when the sci checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 2 notes: 1. the fer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. in 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the fer flag is set to 1. in synchronous mode, serial transmission cannot be continued, either. bit 3?parity error (per): indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. bit 3 per description 0 [clearing condition] (initial value) * 1 when 0 is written in per after reading per = 1 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr * 2 notes: 1. the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in synchronous mode, serial transmission cannot be continued, either.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 370 of 706 rej09b0303-0300 bit 2?transmit end (tend): indicates that there is no valid data in tdr when the last bit of the transmit character is sent, and transmission has been ended. the tend flag is read-only and cannot be modified. bit 2 tend description 0 [clearing condition] when 0 is written in tdre after reading tdre = 1 1 [setting conditions] (initial value) ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character bit 1?multiprocessor bit (mpb): when reception is performed using a multiprocessor format in asynchronous mode, mpb stores the multiprocessor bit in the receive data. mpb is a read-only bit, and cannot be modified. bit 1 mpb description 0 [clearing condition] (initial value) * when data with a 0 multiprocessor bit is received 1 [setting condition] when data with a 1 multiprocessor bit is received note: * retains its previous state when the re bit in scr is cleared to 0 with multiprocessor format. bit 0?multiprocessor bit transfer (mpbt): when transmission is performed using a multiprocessor format in asynchronous mode, mpbt stores the multiprocessor bit to be added to the transmit data. the mpbt bit setting is invalid when a multiprocessor format is not used, when not transmitting, and in synchronous mode. bit 0 mpbt description 0 data with a 0 multiprocessor bit is transmitted (initial value) 1 data with a 1 multiprocessor bit is transmitted
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 371 of 706 rej09b0303-0300 15.2.8 bit rate register (brr) bit 76543210 initial value11111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w brr is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in smr. brr can be read or written to by the cpu at all times. brr is initialized to h'ff by a reset, and in standby mode, and module stop mode. as baud rate generator control is performed independently for each channel, different values can be set for each channel. table 15.3 shows sample brr settings in asynchronous mode, and table 15.4 shows sample brr settings in synchronous mode.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 372 of 706 rej09b0303-0300 table 15.3 brr settings for various bit rates (asynchronous mode) operating frequency (mhz) = 2 mhz = 2.097152 mhz = 2.4576 mhz = 3 mhz bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 ?0.04 1 174 ?0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 ?0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 ?2.48 0 15 0.00 0 19 ?2.34 9600 ? ? ? 0 6 ?2.48 0 7 0.00 0 9 ?2.34 19200 ? ? ? ? ? ? 0 3 0.00 0 4 ?2.34 31250 0 1 0.00 ? ? ? ? ? ? 0 2 0.00 38400 ? ? ? ? ? ? 0 1 0.00 ? ? ? operating frequency (mhz) = 3.6864 mhz = 4 mhz = 4.9152 mhz = 5 mhz bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 ?0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 ? ? ? 0 7 0.00 0 7 1.73 31250 ? ? ? 0 3 0.00 0 4 ?1.70 0 4 0.00 38400 0 2 0.00 ? ? ? 0 3 0.00 0 3 1.73
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 373 of 706 rej09b0303-0300 operating frequency (mhz) = 6 mhz = 6.144 mhz = 7.3728 mhz = 8 mhz bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 ?0.44 2 108 0.08 2 130 ?0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 ?2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ?2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 ? ? ? 0 7 0.00 38400 0 4 ?2.34 0 4 0.00 0 5 0.00 ? ? ? operating frequency (mhz) = 9.8304 mhz = 10 mhz = 12 mhz = 12.288 mhz bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 174 ?0.26 2 177 ?0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ?1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 ?2.34 0 19 0.00 31250 0 9 ?1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 ?2.34 0 9 0.00
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 374 of 706 rej09b0303-0300 operating frequency (mhz) = 14 mhz = 14.7456 mhz = 16 mhz = 17.2032 mhz bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 248 ?0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.00 2400 0 181 0.16 0 191 0.00 0 207 0.16 0 223 0.00 4800 0 90 0.16 0 95 0.00 0 103 0.16 0 111 0.00 9600 0 45 ?0.93 0 47 0.00 0 51 0.16 0 55 0.00 19200 0 22 ?0.93 0 23 0.00 0 25 0.16 0 27 0.00 31250 0 13 0.00 0 14 ?1.70 0 15 0.00 0 16 1.20 38400 ? ? ? 0 11 0.00 0 12 0.16 0 13 0.00 operating frequency (mhz) = 18 mhz = 19.6608 mhz = 20 mhz bit rate (bits/s) n n error (%) n n error (%) n n error (%) 110 3 79 ?0.12 3 86 0.31 3 88 ?0.25 150 2 233 0.16 2 255 0.00 3 64 0.16 300 2 116 0.16 2 127 0.00 2 129 0.16 600 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 58 ?0.69 0 63 0.00 0 64 0.16 19200 0 28 1.02 0 31 0.00 0 32 ?1.36 31250 0 17 0.00 0 19 ?1.70 0 19 0.00 38400 0 14 ?2.34 0 15 0.00 0 15 1.73
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 375 of 706 rej09b0303-0300 table 15.4 brr settings for various bit rates (synchronous mode) operating frequency (mhz) bit rate = 2 mhz = 4 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz (bits/s) nnnnnnnnnnnn 110 3 70 ? ? 250 2 124 2 249 3 124 ? ? 3 249 500 1 249 2 124 2 249 ? ? 3 124 ? ? 1 k 1 124 1 249 2 124 ? ? 2 249 ? ? 2.5 k 0 199 1 99 1 199 1 249 2 99 2 124 5 k 0 99 0 199 1 99 1 124 1 199 1 249 10 k 0 49 0 99 0 199 0 249 1 99 1 124 25 k 0 19 0 39 0 79 0 99 0 159 0 199 50 k 0 9 0 19 0 39 0 49 0 79 0 99 100 k 0 4 0 9 0 19 0 24 0 39 0 49 250 k 0 1 0 3 0 7 0 9 0 15 0 19 500 k 0 0 * 0103040709 1 m 0 0 * 01 0304 2.5 m 0 0 * 01 5 m 00 * legend: blank: cannot be set. ?: can be set, but there will be a degree of error. * : continuous transfer is not possible. note: as far as possible, the setting should be made so that the error is no more than 1%.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 376 of 706 rej09b0303-0300 the brr setting is f ound from the following equations. asynchronous mode: n = 10 6 ? 1 64 2 2n ? 1 b synchronous mode: n = 10 6 ? 1 8 2 2n ? 1 b where b: bit rate (bits/s) n: brr setting for baud rate generator (0 n 255) : operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) smr setting n clock cks1 cks0 0 00 1 /4 0 1 2 /16 1 0 3 /64 1 1 the bit rate error in asynchronous mode is found from the following equation: error (%) = ? 1 100 (n + 1) b 64 2 2n ? 1 10 6 ? ? ? ? ? ?
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 377 of 706 rej09b0303-0300 table 15.5 shows the maximum bit rate for each frequency in asynchronous mode. tables 15.6 and 15.7 show the maximum bit rates with external clock input. table 15.5 maximum bit rate for each frequency (asynchronous mode) (mhz) maximum bit rate (bits/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.6608 614400 0 0 20 625000 0 0
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 378 of 706 rej09b0303-0300 table 15.6 maximum bit rate with external clock input (asynchronous mode) (mhz) external input clock (mhz) maximum bit rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 379 of 706 rej09b0303-0300 table 15.7 maximum bit rate with external clock input (synchronous mode) (mhz) external input clock (mhz) maximum bit rate (bits/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 380 of 706 rej09b0303-0300 15.2.9 serial interface mode register (scmr) bit 76543210 ???? sdir sinv ? smif initial value11110010 read/write ???? r/w r/w ? r/w scmr is an 8-bit readable/writable register used to select sci functions. scmr is initialized to h'f2 by a reset, and in standby mode, and module stop mode. bits 7 to 4?reserved: these bits cannot be modified and are always read as 1. bit 3?data transfer direction (sdir): selects the serial/parallel conversion format. bit 3 sdir description 0 tdr contents are transmitted lsb-first (initial value) receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first bit 2?data invert (sinv): specifies inversion of the data logic level. the sinv bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the o/ e bit in smr. bit 2 sinv description 0 tdr contents are transmitted without modification (initial value) receive data is stored in rdr without modification 1 tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form bit 1?reserved: this bit cannot be modified and is always read as 1.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 381 of 706 rej09b0303-0300 bit 0?serial communication interface mode select (smif): reserved bit. 1 should not be written in this bit. bit 0 smif description 0 normal sci mode (initial value) 1 reserved mode 15.2.10 module stop control register (mstpcr) mstpcrh mstpcrl bit 7654321076543210 mstp 15 mstp 14 mstp 13 mstp 12 mstp 11 mstp 10 mstp 9 mstp 8 mstp 7 mstp 6 mstp 5 mstp 4 mstp 3 mstp 2 mstp 1 mstp 0 initial value 0011111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w mstpcr, comprising two 8-bit readable/writable registers, performs module stop mode control. when bits mstp7 is set to 1, sci0 operation, respectively, stops at the end of the bus cycle and a transition is made to module stop mode. for details, see section 21.5., module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?module stop (mstp7): specifies the sci0 module stop mode. bit 7 mstp7 description 0 sci0 module stop mode is cleared 1 sci0 module stop mode is set (initial value )
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 382 of 706 rej09b0303-0300 15.3 operation 15.3.1 overview the sci can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. selection of asynchronous or synchronous mode and the transmission format is made using smr as shown in table 15.8. the sci clock is determined by a combination of the c/ a bit in smr and the cke1 and cke0 bits in scr, as shown in table 15.9. asynchronous mode ? data length: choice of 7 or 8 bits ? choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) ? detection of framing, parity, and overrun errors, and breaks, during reception ? choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output ? when external clock is selected: a clock with a frequency of 16 times the bit rate must be input (the built-in baud rate generator is not used) synchronous mode ? transfer format: fixed 8-bit data ? detection of overrun errors during reception ? choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a serial clock is output off-chip ? when external clock is selected: the built-in baud rate generator is not used, and the sci operates on the input serial clock
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 383 of 706 rej09b0303-0300 table 15.8 smr settings and serial transfer format selection smr settings sci transfer format bit 7 bit 6 bit 2 bit 5 bit 3 c/ a a a a chr mp pe stop mode data length multi- processor bit parity bit stop bit length 00000 8-bit datano no1 bit 12 bits 10 yes1 bit 12 bits 1 0 0 7-bit data no 1 bit 12 bits 10 yes1 bit 1 asynchronous mode 2 bits 01 ? 0 8-bit data yes no 1 bit ? 12 bits 1 ? 0 7-bit data 1 bit ? 1 asynchronous mode (multi- processor format) 2 bits 1 ???? synchronous mode 8-bit data no none table 15.9 smr and scr settings and sci clock source selection smr scr setting sci transfer clock bit 7 bit 1 bit 0 c/ a a a a cke1 cke0 mode clock source sck pin function 0 0 0 internal sci does not use sck pin 1 outputs clock with same frequency as bit rate 10 external 1 asynchronous mode inputs clock with frequency of 16 times the bit rate 1 0 0 internal outputs serial clock 1 1 0 external inputs serial clock 1 synchronous mode
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 384 of 706 rej09b0303-0300 15.3.2 operation in asynchronous mode in asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. serial communication is thus carried out with synchronization established on a character-by- character basis. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 15.2 shows the general format for asynchronous serial communication. in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. one serial communication character consists of a start bit (low level), followed by data (in lsb- first order), a parity bit (high or low level), and finally one or two stop bits (high level). in asynchronous mode, the sci performs synchronization at the falling edge of the start bit in reception. the sci samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. lsb start bit msb idle state (mark state) stop bit(s) 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 15.2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits)
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 385 of 706 rej09b0303-0300 data transfer format table 15.10 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected by settings in smr. table 15.10 serial transfer formats (asynchronous mode) smr settings serial transfer format and frame length chrpe mpstop 123456789101112 0000 s 8-bit data stop 0001 s 8-bit data stop stop 0100 s 8-bit data p stop 0101 s 8-bit data p stop stop 1000 s 7-bit data stop 1001 s 7-bit data stop stop 1100 s 7-bit data p stop 1101 s 7-bit data p stop stop 0 ? 1 0 s 8-bit data mpb stop 0 ? 1 1 s 8-bit data mpb stop stop 1 ? 1 0 s 7-bit data mpb stop 1 ? 1 1 s 7-bit data mpb stop stop legend: s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 386 of 706 rej09b0303-0300 clock either an internal clock generated by the built-in baud rate generator or an external clock input at the sck pin can be selected as the sci?s serial clock, according to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. for details of sci clock source selection, see table 15.9. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.3. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 figure 15.3 relation between output clock and transfer data phase (asynchronous mode) data transfer operations sci initialization (asynchronous mode): before transmitting and receiving data, first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. when an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 387 of 706 rej09b0303-0300 figure 15.4 shows a sample sci initialization flowchart. wait start initialization set data transfer format in smr and scmr [1] set cke1 and cke0 bits in scr (te, re bits 0) no yes set value in brr clear te and re bits in scr to 0 [2] [3] set te and re bits in scr to 1, and set rie, tie, teie, and mpie bits [4] 1-bit interval elapsed? [1] set the clock selection in scr. be sure to clear bits rie, tie, teie, and mpie, and bits te and re, to 0. when the clock is selected in asynchronous mode, it is output immediately after scr settings are made. [2] set the data transfer format in smr and scmr. [3] write a value corresponding to the bit rate to brr. this is not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr to 1. also set the rie, tie, teie, and mpie bits. setting the te and re bits enables the txd and rxd pins to be used. figure 15.4 sample sci initialization flowchart
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 388 of 706 rej09b0303-0300 serial data transmission (asynchronous mode): figure 15.5 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr [3] no yes [4] clear dr to 0 and set ddr to 1 clear te bit in scr to 0 tdre = 1? all data transmitted? tend = 1? break output? [1] sci initialization: the txd pin is automatically designated as the transmit data output pin. after the te bit is set to 1, one frame of 1s is output and transmission is enabled. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. [4] break output at the end of serial transmission: to output a break in serial transmission, set ddr for the port corresponding to the txd pin to 1, clear dr to 0, then clear the te bit in scr to 0. figure 15.5 sample serial transmission flowchart
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 389 of 706 rej09b0303-0300 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if it is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. parity bit or multiprocessor bit: one parity bit (even or odd parity), or one multiprocessor bit is output. a format in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 390 of 706 rej09b0303-0300 figure 15.6 shows an example of the operation for transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt handling routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 15.6 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit)
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 391 of 706 rej09b0303-0300 serial data reception (asynchronous mode): figure 15.7 shows a sample flowchart for serial reception. the following procedure should be used for serial data reception. yes [1] no initialization start reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 read orer, per, and fer flags in ssr error handling (continued on next page) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes per fer orer= 1? rdrf = 1? all data received? sci initialization: the rxd pin is automatically designated as the receive data input pin. receive error handling and break detection: if a receive error occurs, read the orer, per, and fer flags in ssr to identify the error. after performing the appropriate error handling, ensure that the orer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. in the case of a framing error, a break can be detected by reading the value of the input port corresponding to the rxd pin. sci status check and receive data read : read ssr and check that rdrf = 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial reception continuation procedure: to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag, read rdr, and clear the rdrf flag to 0. [1] [2] [3] [4] [5] figure 15.7 sample serial reception data flowchart
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 392 of 706 rej09b0303-0300 [3] error handling parity error handling yes no clear orer, per, and fer flags in ssr to 0 no yes no yes framing error handling no yes overrun error handling orer = 1? fer = 1? break? per = 1? clear re bit in scr to 0 figure 15.7 sample serial reception data flowchart (cont)
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 393 of 706 rej09b0303-0300 in serial reception, the sci operates as described below. 1. the sci monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. 2. the received data is stored in rsr in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, the sci carries out the following checks. a. parity check: the sci checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the o/ e bit in smr. b. stop bit check: the sci checks whether the stop bit is 1. if there are two stop bits, only the first is checked. c. status check: the sci checks whether the rdrf flag is 0, indicating that the receive data can be transferred from rsr to rdr. if all the above checks are passed, the rdrf flag is set to 1, and the receive data is stored in rdr. if a receive error * is detected in the error check, the operation is as shown in table 15.11. note: * subsequent receive operations cannot be performed when a receive error has occurred. also note that the rdrf flag is not set to 1 in reception, and so the error flags must be cleared to 0. 4. if the rie bit in scr is set to 1 when the rdrf flag changes to 1, a receive-data-full interrupt (rxi) request is generated. also, if the rie bit in scr is set to 1 when the orer, per, or fer flag changes to 1, a receive-error interrupt (eri) request is generated.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 394 of 706 rej09b0303-0300 table 15.11 receive errors and conditions for occurrence receive error abbreviation occurrence condition data transfer overrun error orer when the next data reception is completed while the rdrf flag in ssr is set to 1 receive data is not transferred from rsr to rdr framing error fer when the stop bit is 0 receive data is transferred from rsr to rdr parity error per when the received data differs from the parity (even or odd) set in smr receive data is transferred from rsr to rdr figure 15.8 shows an example of the operation for reception in asynchronous mode. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit rxi interrupt request generated eri interrupt request generated by framing error idle state (mark state) rdr data read and rdrf flag cleared to 0 in rxi interrupt handling routine figure 15.8 example of sci operation in reception (example with 8-bit data, parity, one stop bit)
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 395 of 706 rej09b0303-0300 15.3.3 multiprocessor communication function the multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. use of this function enables data transfer to be performed among a number of processors sharing transmission lines. when multiprocessor communication is carried out, each receiving station is addressed by a unique id code. the serial communication cycle consists of two component cycles: an id transmission cycle which specifies the receiving station, and a data transmission cycle. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. the transmitting station first sends the id of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. the receiving station skips the data until data with a 1 multiprocessor bit is sent. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matches then receives the data sent next. stations whose id does not match continue to skip the data until data with a 1 multiprocessor bit is again received. in this way, data communication is carried out among a number of processors. figure 15.9 shows an example of inter-processor communication using a multiprocessor format. data transfer format there are four data transfer formats. when a multiprocessor format is specified, the parity bit specification is invalid. for details, see table 15.10.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 396 of 706 rej09b0303-0300 clock see the section on asynchronous mode. transmitting station receiving station a (id = 01) receiving station b (id = 02) receiving station c (id = 03) receiving station d (id = 04) serial communication line serial data id transmission cycle: receiving station specification data transmission cycle: data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa legend: mpb: multiprocessor bit figure 15.9 example of inter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a) data transfer operations multiprocessor serial data transmission: figure 15.10 shows a sample flowchart for multiprocessor serial data transmission. the following procedure should be used for multiprocessor serial data transmission.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 397 of 706 rej09b0303-0300 no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and set mpbt bit in ssr no yes no yes read tend flag in ssr [3] no yes [4] clear dr to 0 and set ddr to 1 clear te bit in scr to 0 tdre = 1? all data transmitted? tend = 1? break output? clear tdre flag to 0 sci initialization: the txd pin is automatically designated as the transmit data output pin. after the te bit is set to 1, one frame of 1s is output and transmission is enabled. sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. set the mpbt bit in ssr to 0 or 1. finally, clear the tdre flag to 0. serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. break output at the end of serial transmission: to output a break in serial transmission, set the port ddr to 1, clear dr to 0, then clear the te bit in scr to 0. [1] [2] [3] [4] figure 15.10 sample multiprocessor serial transmission flowchart
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 398 of 706 rej09b0303-0300 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if it is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit-data-empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. multiprocessor bit one multiprocessor bit (mpbt value) is output. d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. if the teie bit in scr is set to 1 at this time, a transmit-end interrupt (tei) request is generated.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 399 of 706 rej09b0303-0300 figure 15.11 shows an example of sci operation for transmission using a multiprocessor format. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit multi- proce- ssor bit stop bit start bit data multi- proces- sor bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt handling routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 15.11 example of sci operation in transmission (example with 8-bit data, multiprocessor bit, one stop bit) multiprocessor serial data reception: figure 15.12 shows a sample flowchart for multiprocessor serial reception. the following procedure should be used for multiprocessor serial data reception.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 400 of 706 rej09b0303-0300 yes [1] no initialization start reception no yes [4] clear re bit in scr to 0 error handling (continued on next page) [5] no yes fer orer = 1? rdrf = 1? all data received? read mpie bit in scr [2] read orer and fer flags in ssr read rdrf flag in ssr [3] read receive data in rdr no yes this station's id? read orer and fer flags in ssr yes no read rdrf flag in ssr no yes fer orer = 1? read receive data in rdr rdrf = 1? sci initialization: the rxd pin is automatically designated as the receive data input pin. id reception cycle: set the mpie bit in scr to 1. sci status check, id reception and comparison: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and compare it with this station ? s id. if the data is not this station ? s id, set the mpie bit to 1 again, and clear the rdrf flag to 0. if the data is this station ? s id, clear the rdrf flag to 0. sci status check and data reception: read ssr and check that the rdrf flag is set to 1, then read the data in rdr. receive error handling and break detection: if a receive error occurs, read the orer and fer flags in ssr to identify the error. after performing the appropriate error handling, ensure that the orer and fer flags are both cleared to 0. reception cannot be resumed if either of these flags is set to 1. in the case of a framing error, a break can be detected by reading the rxd pin value. [1] [2] [3] [4] [5] figure 15.12 sample multiprocessor serial reception flowchart
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 401 of 706 rej09b0303-0300 error handling yes no clear orer, per, and fer flags in ssr to 0 no yes no yes framing error handling overrun error handling orer = 1? fer = 1? break? clear re bit in scr to 0 [5] figure 15.12 sample multiprocessor serial reception flowchart (cont)
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 402 of 706 rej09b0303-0300 figure 15.13 shows an example of sci operation for multiprocessor format reception. mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id1) start bit mpb stop bit start bit data (data1) mpb stop bit rxi interrupt request (multiprocessor interrupt) generated mpie = 0 idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt handling routine if not this station ? s id, mpie bit is set to 1 again rxi interrupt request is not generated, and rdr retains its state id1 (a) data does not match station?s id mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id2) start bit mpb stop bit start bit data (data2) mpb stop bit rxi interrupt request (multiprocessor interrupt) generated mpie = 0 idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt handling routine matches this station ? s id, so reception continues, and data is received in rxi interrupt handling routine mpie bit set to 1 again id2 (b) data matches station?s id data2 id1 figure 15.13 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit)
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 403 of 706 rej09b0303-0300 15.3.4 operation in synchronous mode in synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 15.14 shows the general format for synchronous serial communication. don ? t care don ? t care one unit of transfer data (character or frame) bit 0 serial data serial clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * note: * high except in continuous transfer * figure 15.14 data format in synchronous communication in synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. data is guaranteed valid at the rising edge of the serial clock. in synchronous serial communication, one character consists of data output starting with the lsb and ending with the msb. after the msb is output, the transmission line holds the msb state. in synchronous mode, the sci receives data in synchronization with the rising edge of the serial clock. data transfer format a fixed 8-bit data format is used. no parity or multiprocessor bits are added.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 404 of 706 rej09b0303-0300 clock either an internal clock generated by the built-in baud rate generator or an external serial clock input at the sck pin can be selected, according to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. for details on sci clock source selection, see table 15.9. when the sci is operated on an internal clock, the serial clock is output from the sck pin. eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. when only receive operations are performed, however, the serial clock is output until an overrun error occurs or the re bit is cleared to 0. to perform receive operations in units of one character, select an external clock as the clock source. data transfer operations sci initialization (synchronous mode): before transmitting and receiving data, first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr is initialized. note that clearing the re bit to 0 does not change the settings of the rdrf, per, fer, and orer flags, or the contents of rdr. figure 15.15 shows a sample sci initialization flowchart.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 405 of 706 rej09b0303-0300 wait start initialization set data transfer format in smr and scmr no yes set value in brr clear te and re bits in scr to 0 [2] [3] set te and re bits in scr to 1, and set rie, tie, teie, and mpie bits note: in simultaneous transmitting and receiving, the te and re bits should both be cleared to 0 or set to 1 simultaneously. [4] 1-bit interval elapsed? set cke1 and cke0 bits in scr (te, re bits 0) [1] [1] set the clock selection in scr. be sure to clear bits rie, tie, teie, and mpie, te and re, to 0. [2] set the data transfer format in smr and scmr. [3] write a value corresponding to the bit rate to brr. this is not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr to 1. also set the rie, tie, teie, and mpie bits. setting the te and re bits enables the txd and rxd pins to be used. figure 15.15 sample sci initialization flowchart
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 406 of 706 rej09b0303-0300 serial data transmission (synchronous mode): figure 15.16 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr [3] clear te bit in scr to 0 tdre = 1? all data transmitted? tend = 1? [1] sci initialization: the txd pin is automatically designated as the transmit data output pin. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. figure 15.16 sample serial transmission flowchart
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 407 of 706 rej09b0303-0300 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if it is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit-data-empty interrupt (txi) is generated. when clock output mode has been set, the sci outputs 8 serial clock pulses. when use of an external clock has been specified, data is output synchronized with the input clock. the serial transmit data is sent from the txd pin starting with the lsb (bit 0) and ending with the msb (bit 7). 3. the sci checks the tdre flag at the timing for sending the msb (bit 7). if the tdre flag is cleared to 0, data is transferred from tdr to tsr, and serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the msb (bit 7) is sent, and the txd pin maintains its state. if the teie bit in scr is set to 1 at this time, a transmit-end interrupt (tei) request is generated. 4. after completion of serial transmission, the sck pin is held in a constant state. figure 15.17 shows an example of sci operation in transmission.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 408 of 706 rej09b0303-0300 transfer direction bit 0 serial data serial clock 1 frame tdre tend bit 1 bit 7 bit 0 bit 1 bit 7 bit 6 data written to tdr and tdre flag cleared to 0 in txi interrupt handling routine tei interrupt request generated txi interrupt request generated txi interrupt request generated figure 15.17 example of sci operation in transmission serial data reception (synchronous mode): figure 15.18 shows a sample flowchart for serial reception. the following procedure should be used for serial data reception. when changing the operating mode from asynchronous to synchronous, be sure to check that the orer, per, and fer flags are all cleared to 0. the rdrf flag will not be set if the fer or per flag is set to 1, and neither transmit nor receive operations will be possible.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 409 of 706 rej09b0303-0300 yes [1] no initialization start reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 error handling (continued below) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes orer = 1? rdrf = 1? all data received? read orer flag in ssr [1] [2] [3] [4] [5] sci initialization: the rxd pin is automatically designated as the receive data input pin. receive error handling: if a receive error occurs, read the orer flag in ssr , and after performing the appropriate error handling, clear the orer flag to 0. transfer cannot be resumed if the orer flag is set to 1. sci status check and receive data read: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial reception continuation procedure: to continue serial reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr, and clearing the rdrf flag to 0. error handling overrun error handling [3] clear orer flag in ssr to 0 figure 15.18 sample serial reception flowchart
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 410 of 706 rej09b0303-0300 in serial reception, the sci operates as described below. 1. the sci performs internal initialization in synchronization with serial clock input or output. 2. the received data is stored in rsr in lsb-to-msb order. after reception, the sci checks whether the rdrf flag is 0 and the receive data can be transferred from rsr to rdr. if this check is passed, the rdrf flag is set to 1, and the receive data is stored in rdr. if a receive error is detected in the error check, the operation is as shown in table 15.11. neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. 3. if the rie bit in scr is set to 1 when the rdrf flag changes to 1, a receive-data-full interrupt (rxi) request is generated. also, if the rie bit in scr is set to 1 when the orer flag changes to 1, a receive-error interrupt (eri) request is generated. figure 15.19 shows an example of sci operation in reception. bit 7 serial data serial clock 1 frame rdrf orer bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 rxi interrupt request generated rdr data read and rdrf flag cleared to 0 in rxi interrupt handling routine rxi interrupt request generated eri interrupt request generated by overrun error figure 15.19 example of sci operation in reception simultaneous serial data transmission and reception (synchronous mode): figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 411 of 706 rej09b0303-0300 yes [1] no initialization start transmission/reception [5] error handling [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes orer = 1? all data received? [2] read tdre flag in ssr no yes tdre = 1? write transmit data to tdr and clear tdre flag in ssr to 0 no yes rdrf = 1? read orer flag in ssr [4] read rdrf flag in ssr clear te and re bits in scr to 0 note: when switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the te bit and re bit to 0, then set both these bits to 1 simultaneously. [1] [2] [3] [4] [5] sci initialization: the txd pin is designated as the transmit data output pin, and the rxd pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. transition of the tdre flag from 0 to 1 can also be identified by a txi interrupt. receive error handling: if a receive error occurs, read the orer flag in ssr , and after performing the appropriate error handling, clear the orer flag to 0. transmission/reception cannot be resumed if the orer flag is set to 1. sci status check and receive data read: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial transmission/reception continuation procedure: to continue serial transmission/ reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr, and clearing the rdrf flag to 0. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr and clear the tdre flag to 0. figure 15.20 sample flowchart of simultaneous serial transmit and receive operations
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 412 of 706 rej09b0303-0300 15.4 sci interrupts the sci has four interrupt sources: the transmit-end interrupt (tei) request, receive-error interrupt (eri) request, receive-data-full interrupt (rxi) request, and transmit-data-empty interrupt (txi) request. table 15.12 shows the interrupt sources and their relative priorities. individual interrupt sources can be enabled or disabled with the tie, rie, and teie bits in scr. each kind of interrupt request is sent to the interrupt controller independently. table 15.12 sci interrupt sources interrupt source description priority eri receive error (orer, fer, or per) high rxi receive data register full (rdrf) txi transmit data register empty (tdre) tei transmit end (tend) low the tei interrupt is requested when the tend flag is set to 1 while the teie bit is set to 1. the tend flag is cleared at the same time as the tdre flag. consequently, if a tei interrupt and a txi interrupt are requested simultaneously, the txi interrupt will have priority for acceptance, and the tdre flag and tend flag may be cleared. note that the tei interrupt will not be accepted in this case.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 413 of 706 rej09b0303-0300 15.5 usage notes the following points should be noted when using the sci. relation between writes to tdr and the tdre flag: the tdre flag in ssr is a status flag that indicates that transmit data has been transferred from tdr to tsr. when the sci transfers data from tdr to tsr, the tdre flag is set to 1. data can be written to tdr regardless of the state of the tdre flag. however, if new data is written to tdr when the tdre flag is cleared to 0, the data stored in tdr will be lost since it has not yet been transferred to tsr. it is therefore essential to check that the tdre flag is set to 1 before writing transmit data to tdr. operation when multiple receive errors occur simultaneously: if a number of receive errors occur at the same time, the state of the status flags in ssr is as shown in table 15.13. if there is an overrun error, data is not transferred from rsr to rdr, and the receive data is lost. table 15.13 state of ssr status flags and transfer of receive data ssr status flags rdrf orer fer per receive data transfer rsr to rdr receive errors 1100x overrun error 0 0 1 0 o framing error 0001o parity error 1 1 1 0 x overrun error + framing error 1 1 0 1 x overrun error + parity error 0 0 1 1 o framing error + parity error 1 1 1 1 x overrun error + framing error + parity error legend: o: receive data is transferred from rsr to rdr. x: receive data is not transferred from rsr to rdr. break detection and processing: when a framing error (fer) is detected, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, and so the fer flag is set, and the parity error flag (per) may also be set. note that, since the sci continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 414 of 706 rej09b0303-0300 sending a break: the txd pin has a dual function as an i/o port whose direction (input or output) is determined by dr and ddr. this feature can be used to send a break. between serial transmission initialization and setting of the te bit to 1, the mark state is replaced by the value of dr (the pin does not function as the txd pin until the te bit is set to 1). consequently, ddr and dr for the port corresponding to the txd pin should first be set to 1. to send a break during serial transmission, first clear dr to 0, then clear the te bit to 0. when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. receive error flags and transmit operations (synchronous mode only): transmission cannot be started when a receive error flag (orer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. receive data sampling timing and reception margin in asynchronous mode: in asynchronous mode, the sci operates on a base clock with a frequency of 16 times the transfer rate. in reception, the sci samples the falling edge of the start bit using the base clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the base clock. this is illustrated in figure 15.21. internal base clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 07 figure 15.21 receive data sampling timing in asynchronous mode
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 415 of 706 rej09b0303-0300 thus the receive margin in asynchronous mode is given by equation (1) below. m = 0.5 ? 1 2n d ? 0.5 n ? (l ? 0.5)f ? (1 + f) 100% .......... (1) where m: receive margin (%) n: ratio of bit rate to clock (n = 16) d: clock duty (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute value of clock rate deviation assuming values of f = 0 and d = 0.5 in equation (1), a receive margin of 46.875% is given by equation (2) below. when d = 0.5 and f = 0, m = 1 2 16 100% = 46.875% 0.5 ? .......... (2) however, this is only a theoretical value, and a margin of 20% to 30% should be allowed in system design.
section 15 serial communication interface (sci) rev. 3.00 mar 17, 2006 page 416 of 706 rej09b0303-0300
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 417 of 706 rej09b0303-0300 section 16 i 2 c bus interface (iic) 16.1 overview the h8/3577 group and h8/3567 group have an on-chip two-channel i 2 c bus interface. the i 2 c bus interface conforms to and provides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register configuration that controls the i 2 c bus differs partly from the philips configuration, however. each i 2 c bus interface channel uses only one data line (sda) and one clock line (scl) to transfer data, saving board and connector space. 16.1.1 features ? selection of addressing format or non-addressing format ? i 2 c bus format: addressing format with acknowledge bit, for master/slave operation ? serial format: non-addressing format without acknowledge bit, for master operation only ? conforms to philips i 2 c bus interface (i 2 c bus format) ? two ways of setting slave address (i 2 c bus format) ? start and stop conditions generated automatically in master mode (i 2 c bus format) ? selection of acknowledge output levels when receiving (i 2 c bus format) ? automatic loading of acknowledge bit when transmitting (i 2 c bus format) ? wait function in master mode (i 2 c bus format) a wait can be inserted by driving the scl pin low after data transfer, excluding acknowledgement. the wait can be cleared by clearing the interrupt flag. ? wait function in slave mode (i 2 c bus format) a wait request can be generated by driving the scl pin low after data transfer, excluding acknowledgement. the wait request is cleared when the next transfer becomes possible. ? three interrupt sources ? data transfer end (including transmission mode transition with i 2 c bus format and address reception after loss of master arbitration) ? address match: when any slave address matches or the general call address is received in slave receive mode (i 2 c bus format) ? stop condition detection ? selection of 16 internal clocks (in master mode)
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 418 of 706 rej09b0303-0300 ? direct bus drive (with scl and sda pins) ? two pins?p5 2 /scl 0 and p4 7 /sda 0 ?(normally nmos push-pull outputs) function as nmos open-drain outputs when the bus drive function is selected. ? two pins?p2 4 /scl 1 and p2 3 /sda 1 in the h8/3577 group, and p1 7 /scl 1 and p1 6 /sda 1 in the h8/3567 group?(normally cmos pins) function as nmos-only outputs when the bus drive function is selected. ? automatic switching from formatless mode to i 2 c bus format (channel 0 only) ? formatless operation (no start/stop conditions, non-addressing mode) in slave mode ? operation using a common data pin (sda) and independent clock pins (vsynci, scl) ? automatic switching from formatless mode to i 2 c bus format on the fall of the scl pin 16.1.2 block diagram figure 16.1 shows a block diagram of the i 2 c bus interface. figure 16.2 shows an example of i/o pin connections to external circuits. channel 0 i/o pins and channel 1 i/o pins differ in structure, and have different specifications for permissible applied voltages. for details, see section 22, electrical characteristics.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 419 of 706 rej09b0303-0300 ps noise canceler noise canceler clock control formatless dedicated clock (channel 0 only) bus state decision circuit arbitration decision circuit output data control circuit address comparator sar, sarx interrupt generator icdrs icdrr icdrt icsr icmr iccr internal data bus interrupt request scl sda legend: iccr: icmr: icsr: icdr: sar: sarx: ps: i 2 c bus control register i 2 c bus mode register i 2 c bus status register i 2 c bus data register slave address register slave address register x prescaler figure 16.1 block diagram of i 2 c bus interface
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 420 of 706 rej09b0303-0300 scl in scl out sda in sda out (slave 1) scl sda scl in scl out sda in sda out (slave 2) scl sda scl in scl out sda in sda out (master) h8/3577 group or h8/3567 group chip scl sda vcc vcc scl sda figure 16.2 i 2 c bus interface connections (example: h8/3577 group or h8/3567 group chip as master) 16.1.3 input/output pins table 16.1 summarizes the input/output pins used by the i 2 c bus interface. table 16.1 i 2 c bus interface pins channel name abbreviation * i/o function 0 serial clock scl 0 i/o iic0 serial clock input/output serial data sda 0 i/o iic0 serial data input/output formatless serial clock vsynci input iic0 formatless serial clock input 1 serial clock scl 1 i/o iic1 serial clock input/output serial data sda 1 i/o iic1 serial data input/output note: * in the text, the channel subscript is omitted, and only scl and sda are used.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 421 of 706 rej09b0303-0300 16.1.4 register configuration table 16.2 summarizes the registers of the i 2 c bus interface. table 16.2 register configuration channel name abbreviation r/w initial value address 0i 2 c bus control register iccr0 r/w h'01 h'ffd8 i 2 c bus status register icsr0 r/w h'00 h'ffd9 i 2 c bus data register icdr0 r/w ? h'ffde * i 2 c bus mode register icmr0 r/w h'00 h'ffdf * slave address register sar0 r/w h'00 h'ffdf * second slave address register sarx0 r/w h'01 h'ffde * 1i 2 c bus control register iccr1 r/w h'01 h'ff88 i 2 c bus status register icsr1 r/w h'00 h'ff89 i 2 c bus data register icdr1 r/w ? h'ff8e * i 2 c bus mode register icmr1 r/w h'00 h'ff8f * slave address register sar1 r/w h'00 h'ff8f * second slave address register sarx1 r/w h'01 h'ff8e * common serial timer control register stcr r/w h'00 h'ffc3 ddc switch register ddcswr r/w h'0f h'fee6 module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 note: * the register that can be written or read depends on the ice bit in the i 2 c bus control register. the slave address register can be accessed when ice = 0, and the i 2 c bus mode register can be accessed when ice = 1. the i 2 c bus interface registers are assigned to the same addresses as other registers. register selection is performed by means of the iice bit in the serial timer control register (stcr).
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 422 of 706 rej09b0303-0300 16.2 register descriptions 16.2.1 i 2 c bus data register (icdr) bit 76543210 icdr7 icdr6 icdr5 icdr4 icdr3 icdr2 icdr1 icdr0 initial value???????? read/write r/w r/w r/w r/w r/w r/w r/w r/w ? icdrr bit 76543210 icdrr7 icdrr6 icdrr5 icdrr4 icdrr3 icdrr2 icdrr1 icdrr0 initial value???????? read/write r r rrrrrr ? icdrs bit 76543210 icdrs7 icdrs6 icdrs5 icdrs4 icdrs3 icdrs2 icdrs1 icdrs0 initial value???????? read/write ? ? ?????? ? icdrt bit 76543210 icdrt7 icdrt6 icdrt5 icdrt4 icdrt3 icdrt2 icdrt1 icdrt0 initial value???????? read/write w w wwwwww ? tdre, rdrf (internal flags) bit ?? tdre rdrf initial value 0 0 read/write ? ?
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 423 of 706 rej09b0303-0300 icdr is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. icdr is divided internally into a shift register (icdrs), receive buffer (icdrr), and transmit buffer (icdrt). icdrs cannot be read or written by the cpu, icdrr is read-only, and icdrt is write-only. data transfers among the three registers are performed automatically in coordination with changes in the bus state, and affect the status of internal flags such as tdre and rdrf. if iic is in transmit mode and the next data is in icdrt (the tdre flag is 0) following transmission of one frame of data using icdrs, data is transferred automatically from icdrt to icdrs. if the iic is in receive mode and none of the previous data remains in icdrr (the rdrf flag is 0), after one frame of data has been received normally in icdrs, the data is transferred automatically from icdrs to icdrr. if the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. transmit data should be written justified toward the msb side when mls = 0, and toward the lsb side when mls = 1. receive data bits read from the lsb side should be treated as valid when mls = 0, and bits read from the msb side when mls = 1. icdr is assigned to the same address as sarx, and can be written and read only when the ice bit is set to 1 in iccr. the value of icdr is undefined after a reset. the tdre and rdrf flags are set and cleared under the conditions shown below. setting the tdre and rdrf flags affects the status of the interrupt flags.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 424 of 706 rej09b0303-0300 tdre description 0 the next transmit data is in icdr (icdrt), or transmission cannot (initial value) be started [clearing conditions] ? when transmit data is written in icdr (icdrt) in transmit mode (trs = 1) ? when a stop condition is detected in the bus line state after a stop condition is issued with the i 2 c bus format or serial format selected ? when a stop condition is detected with the i 2 c bus format selected ? in receive mode (trs = 0) (a 0 write to trs during transfer is valid after reception of a frame containing an acknowledge bit) 1 the next transmit data can be written in icdr (icdrt) [setting conditions] ? in transmit mode (trs = 1), when a start condition is detected in the bus line state after a start condition is issued in master mode with the i 2 c bus format or serial format selected ? when using formatless mode in transmit mode (trs = 1) ? when data is transferred from icdrt to icdrs (data transfer from icdrt to icdrs when trs = 1 and tdre = 0, and icdrs is empty) ? when a switch is made from receive mode (trs = 0) to transmit mode (trs = 1 ) after detection of a start condition rdrf description 0 the data in icdr (icdrr) is invalid (initial value) [clearing condition] when icdr (icdrr) receive data is read in receive mode 1 the icdr (icdrr) receive data can be read [setting condition] when data is transferred from icdrs to icdrr (data transfer from icdrs to icdrr in case of normal termination with trs = 0 and rdrf = 0)
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 425 of 706 rej09b0303-0300 16.2.2 slave address register (sar) bit 76543210 sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w sar is an 8-bit readable/writable register that stores the slave address and selects the communication format. when the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of sar match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. sar is assigned to the same address as icmr, and can be written and read only when the ice bit is cleared to 0 in iccr. sar is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 1?slave address (sva6 to sva0): set a unique address in bits sva6 to sva0, differing from the addresses of other slave devices connected to the i 2 c bus. bit 0?format select (fs): used together with the fsx bit in sarx and the sw bit in ddcswr to select the communication format. ? i 2 c bus format: addressing format with acknowledge bit ? synchronous serial format: non-addressing format without acknowledge bit, for master mode only ? formatless mode (channel 0 only): non-addressing format with or without acknowledge bit, slave mode only, start/stop conditions not detected the fs bit also specifies whether or not sar slave address recognition is performed in slave mode.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 426 of 706 rej09b0303-0300 ddcswr bit 6 sar bit 0 sarx bit 0 sw fs fsx operating mode 000 i 2 c bus format ? sar and sarx slave addresses recognized 1i 2 c bus format ? sar slave address recognized ? sarx slave address ignored (initial value) 10 i 2 c bus format ? sar slave address ignored ? sarx slave address recognized 1 synchronous serial format ? sar and sarx slave addresses ignored 100 1 10 formatless mode (start/stop conditions not detected) ? acknowledge bit used 1 formatless mode * (start/stop conditions not detected) ? no acknowledge bit note: * do not set this mode when automatic switching to the i 2 c bus format is performed by means of the ddcswr setting.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 427 of 706 rej09b0303-0300 16.2.3 second slave address register (sarx) bit 76543210 svax6 svax5 svax4 svax3 svax2 svax1 svax0 fsx initial value00000001 read/write r/w r/w r/w r/w r/w r/w r/w r/w sarx is an 8-bit readable/writable register that stores the second slave address and selects the communication format. when the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of sarx match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. sarx is assigned to the same address as icdr, and can be written and read only when the ice bit is cleared to 0 in iccr. sarx is initialized to h'01 by a reset and in hardware standby mode. bits 7 to 1?second slave address (svax6 to svax0): set a unique address in bits svax6 to svax0, differing from the addresses of other slave devices connected to the i 2 c bus. bit 0?format select x (fsx): used together with the fs bit in sar and the sw bit in ddcswr to select the communication format. ? i 2 c bus format: addressing format with acknowledge bit ? synchronous serial format: non-addressing format without acknowledge bit, for master mode only ? formatless mode: non-addressing format with or without acknowledge bit, slave mode only, start/stop conditions not detected the fsx bit also specifies whether or not sarx slave address recognition is performed in slave mode. for details, see the description of the fs bit in sar.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 428 of 706 rej09b0303-0300 16.2.4 i 2 c bus mode register (icmr) bit 76543210 mls wait cks2 cks1 cks0 bc2 bc1 bc0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w icmr is an 8-bit readable/writable register that selects whether the msb or lsb is transferred first, performs master mode wait control, and selects the master mode transfer clock frequency and the transfer bit count. icmr is assigned to the same address as sar. icmr can be written and read only when the ice bit is set to 1 in iccr. icmr is initialized to h'00 by a reset and in hardware standby mode. bit 7?msb-first/lsb-first select (mls): selects whether data is transferred msb-first or lsb-first. if the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. transmit data should be written justified toward the msb side when mls = 0, and toward the lsb side when mls = 1. receive data bits read from the lsb side should be treated as valid when mls = 0, and bits read from the msb side when mls = 1. do not set this bit to 1 when the i 2 c bus format is used. bit 7 mls description 0 msb-first (initial value) 1 lsb-first bit 6?wait insertion bit (wait): selects whether to insert a wait between the transfer of data and the acknowledge bit, in master mode with the i 2 c bus format. when wait is set to 1, after the fall of the clock for the final data bit, the iric flag is set to 1 in iccr, and a wait state begins (with scl at the low level). when the iric flag is cleared to 0 in iccr, the wait ends and the acknowledge bit is transferred. if wait is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. the iric flag in iccr is set to 1 on completion of the acknowledge bit transfer, regardless of the wait setting. the setting of this bit is invalid in slave mode.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 429 of 706 rej09b0303-0300 bit 6 wait description 0 data and acknowledge bits transferred consecutively (initial value) 1 wait inserted between data and acknowledge bits bits 5 to 3?serial clock select (cks2 to cks0): these bits, together with the iicx1 (channel 1) or iicx0 (channel 0) bit in the stcr register, select the serial clock frequency in master mode. they should be set according to the required transfer rate. stcr bit 5 or 6 bit 5 bit 4 bit 3 transfer rate iicx cks2 cks1 cks0 clock = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz 0 000 /28 179 khz 286 khz 357 khz 571 khz * 714 khz * 1 /40 125 khz 200 khz 250 khz 400 khz 500 khz * 10 /48 104 khz 167 khz 208 khz 333 khz 417 khz * 1 /64 78.1 khz 125 khz 156 khz 250 khz 313 khz 100 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 1 /100 50.0 khz 80.0 khz 100 khz 160 khz 200 khz 10 /112 44.6 khz 71.4 khz 89.3 khz 143 khz 179 khz 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 1 000 /56 89.3 khz 143 khz 179 khz 286 khz 357 khz 1 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 10 /96 52.1 khz 83.3 khz 104 khz 167 khz 208 khz 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 100 /160 31.3 khz 50.0 khz 62.5 khz 100 khz 125 khz 1 /200 25.0 khz 40.0 khz 50.0 khz 80.0 khz 100 khz 10 /224 22.3 khz 35.7 khz 44.6 khz 71.4 khz 89.3 khz 1 /256 19.5 khz 31.3 khz 39.1 khz 62.5 khz 78.1 khz note: * outside the i 2 c bus interface specification range (normal mode: max. 100 khz; high- speed mode: max. 400 khz). bits 2 to 0?bit counter (bc2 to bc0): bits bc2 to bc0 specify the number of bits to be transferred next. with the i 2 c bus format (when the fs bit in sar or the fsx bit in sarx is 0), the data is transferred with one addition acknowledge bit. bits bc2 to bc0 settings should be made during an interval between transfer frames. if bits bc2 to bc0 are set to a value other than 000, the setting should be made while the scl line is low.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 430 of 706 rej09b0303-0300 the bit counter is initialized to 000 by a reset and when a start condition is detected. the value returns to 000 at the end of a data transfer, including the acknowledge bit. bit 2 bit 1 bit 0 bits/frame bc2 bc1 bc0 synchronous serial format i 2 c bus format 0 0 0 8 9 (initial value) 11 2 10 2 3 13 4 100 4 5 15 6 10 6 7 17 8 16.2.5 i 2 c bus control register (iccr) bit 76543210 ice ieic mst trs acke bbsy iric scp initial value00000001 read/write r/w r/w r/w r/w r/w r/w r/(w) * w note: * only 0 can be written, to clear the flag. iccr is an 8-bit readable/writable register that enables or disables the i 2 c bus interface, enables or disables interrupts, selects master or slave mode and transmission or reception, enables or disables acknowledgement, confirms the i 2 c bus interface bus status, issues start/stop conditions, and performs interrupt flag confirmation. iccr is initialized to h'01 by a reset and in hardware standby mode. bit 7?i 2 c bus interface enable (ice): selects whether or not the i 2 c bus interface is to be used. when ice is set to 1, port pins function as scl and sda input/output pins and transfer operations are enabled. when ice bit is cleared to 0, the module stops the functions and clears the internal state. the sar and sarx registers can be accessed when ice is 0. the icmr and icdr registers can be accessed when ice is 1.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 431 of 706 rej09b0303-0300 bit 7 ice description 0i 2 c bus interface module disabled, with scl and sda signal pins set to port function (initial value) initialization of iic module internal state sar and sarx can be accessed 1i 2 c bus interface module enabled for transfer operations (pins scl and sca are driving the bus) icmr and icdr can be accessed bit 6?i 2 c bus interface interrupt enable (ieic): enables or disables interrupts from the i 2 c bus interface to the cpu. bit 6 ieic description 0 interrupts disabled (initial value) 1 interrupts enabled bit 5?master/slave select (mst) bit 4?transmit/receive select (trs) mst selects whether the i 2 c bus interface operates in master mode or slave mode. trs selects whether the i 2 c bus interface operates in transmit mode or receive mode. in master mode with the i 2 c bus format, when arbitration is lost, mst and trs are both reset by hardware, causing a transition to slave receive mode. in slave receive mode with the addressing format (fs = 0 or fsx = 0), hardware automatically selects transmit or receive mode according to the r/w bit in the first frame after a start condition. modification of the trs bit during transfer is deferred until transfer of the frame containing the acknowledge bit is completed, and the changeover is made after completion of the transfer. mst and trs select the operating mode as follows.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 432 of 706 rej09b0303-0300 bit 5 bit 4 mst trs operating mode 0 0 slave receive mode (initial value) 1 slave transmit mode 1 0 master receive mode 1 master transmit mode bit 5 mst description 0 slave mode (initial value) [clearing conditions] 1. when 0 is written by software 2. when bus arbitration is lost after transmission is started in i 2 c bus format master mode 1 master mode [setting conditions] 1. when 1 is written by software (in cases other than clearing condition 2) 2. when 1 is written in mst after reading mst = 0 (in case of clearing condition 2) bit 4 trs description 0 receive mode (initial value) [clearing conditions] 1. when 0 is written by software (in cases other than setting condition 3) 2. when 0 is written in trs after reading trs = 1 (in case of clearing condition 3) 3. when bus arbitration is lost after transmission is started in i 2 c bus format master mode 4. when the sw bit in ddcswr changes from 1 to 0 1 transmit mode [setting conditions] 1. when 1 is written by software (in cases other than clearing conditions 3 and 4) 2. when 1 is written in trs after reading trs = 0 (in case of clearing conditions 3 and 4) 3. when a 1 is received as the r/w bit of the first frame in i 2 c bus format slave mode
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 433 of 706 rej09b0303-0300 bit 3?acknowledge bit judgement selection (acke): specifies whether the value of the acknowledge bit returned from the receiving device when using the i 2 c bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1. when the acke bit is 0, the value of the received acknowledge bit is not indicated by the ackb bit, which is always 0. bit 3 acke description 0 the value of the acknowledge bit is ignored, and continuous transfer is performed (initial value) 1 if the acknowledge bit is 1, continuous transfer is interrupted bit 2?bus busy (bbsy): the bbsy flag can be read to check whether the i 2 c bus (scl, sda) is busy or free. in master mode, this bit is also used to issue start and stop conditions. a high-to-low transition of sda while scl is high is recognized as a start condition, setting bbsy to 1. a low-to-high transition of sda while scl is high is recognized as a stop condition, clearing bbsy to 0. to issue a start condition, write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, use a mov instruction to write 0 in bbsy and 0 in scp. it is not possible to write to bbsy in slave mode; the i 2 c bus interface must be set to master transmit mode before issuing a start condition. mst and trs should both be set to 1 before writing 1 in bbsy and 0 in scp. bit 2 bbsy description 0 bus is free [clearing condition] when a stop condition is detected (initial value) 1bus is busy [setting condition] when a start condition is detected bit 1?i 2 c bus interface interrupt request flag (iric): indicates that the i 2 c bus interface has issued an interrupt request to the cpu. iric is set to 1 at the end of a data transfer, when a slave address or general call address is detected in slave receive mode, when bus arbitration is lost in master transmit mode, and when a stop condition is detected. iric is set at different times depending on the fs bit in sar and the wait bit in icmr. see section 16.3.6, iric setting
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 434 of 706 rej09b0303-0300 timing and scl control. the conditions under which iric is set also differ depending on the setting of the acke bit in iccr. iric is cleared by reading iric after it has been set to 1, then writing 0 in iric. bit 1 iric description 0 waiting for transfer, or transfer in progress (initial value) [clearing condition] when 0 is written in iric after reading iric = 1 1 interrupt requested [setting conditions] ? i 2 c bus format master mode ? when a start condition is detected in the bus line state after a start condition is issued (when the tdre flag is set to 1 because of first frame transmission) ? when a wait is inserted between the data and acknowledge bit when wait = 1 ? at the end of data transfer (at the rise of the 9th transmit/receive clock pulse, and, when a wait is inserted, at the fall of the 8th transmit/receive clock pulse) ? when a slave address is received after bus arbitration is lost (when the al flag is set to 1) ? when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) ? i 2 c bus format slave mode ? when the slave address (sva, svax) matches (when the aas and aasx flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) ? when the general call address is detected (when the fs = 0 and the adz flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) ? when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) ? when a stop condition is detected (when the stop or estp flag is set to 1) ? synchronous serial format, and formatless mode ? at the end of data transfer (when the tdre or rdrf flag is set to 1) ? when a start condition is detected with serial format selected ? when the sw bit is set to 1 in ddcswr besides the above, when a condition that sets the tdre or rdrf internal flag to 1 occurs
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 435 of 706 rej09b0303-0300 when, with the i 2 c bus format selected, iric is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set iric to 1. although each source has a corresponding flag, caution is needed at the end of a transfer. when the tdre or rdrf internal flag is set, the readable irtr flag may or may not be set. the irtr flag is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (sva) or general call address match in i 2 c bus format slave mode. even when the iric flag and irtr flag are set, the tdre or rdrf internal flag may not be set. table 16.3 shows the relationship between the flags and the transfer states. table 16.3 flags and transfer states mst trs bbsy estp stop irtr aasx al aas adz ackb state 1/01/0000000000 idle state (flag clearing required) 11000000000 start c ondition issuance 11100100000 start c ondition established 11/0100000000/1master m ode wait 11/0100100000/1master mode transmit/receive end 0010001/011/01/00 arbitration lost 00100000100 sar match by first frame in slave mode 00100000110 g eneral call address match 00100010000 sarx match 01/0100000000/1slave mode transmit/receive end (except after sarx match) 0 0 1/0 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 slave mode transmit/receive end (after sarx match) 0 1/0 0 1/0 1/0 0 0 0 0 0 0/1 stop condition detected
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 436 of 706 rej09b0303-0300 bit 0?start condition/stop condition prohibit (scp): controls the issuing of start and stop conditions in master mode. to issue a start condition, write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, write 0 in bbsy and 0 in scp. this bit is always read as 1. if 1 is written, the data is not stored. bit 0 scp description 0 writing 0 issues a start or stop condition, in combination with the bbsy flag 1 reading always returns a value of 1 writing is ignored (initial value) 16.2.6 i 2 c bus status register (icsr) bit 76543210 estp stop irtr aasx al aas adz ackb initial value00000000 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/w note: * only 0 can be written, to clear the flags. icsr is an 8-bit readable/writable register that performs flag confirmation and acknowledge confirmation and control. icsr is initialized to h'00 by a reset and in hardware standby mode. bit 7?error stop condition detection flag (estp): indicates that a stop condition has been detected during frame transfer in i 2 c bus format slave mode.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 437 of 706 rej09b0303-0300 bit 7 estp description 0 no error stop condition [clearing conditions] ? when 0 is written in estp after reading estp = 1 ? when the iric flag is cleared to 0 (initial value) 1 ? in i 2 c bus format slave mode error stop condition detected [setting condition] when a stop condition is detected during frame transfer ? in other modes no meaning bit 6?normal stop condition detection flag (stop): indicates that a stop condition has been detected after completion of frame transfer in i 2 c bus format slave mode. bit 6 stop description 0 no normal stop condition [clearing conditions] ? when 0 is written in stop after reading stop = 1 ? when the iric flag is cleared to 0 (initial value) 1 ? in i 2 c bus format slave mode normal stop condition detected [setting condition] when a stop condition is detected after completion of frame transfer ? in other modes no meaning bit 5?i 2 c bus interface continuous transmission/reception interrupt request flag (irtr): indicates that the i 2 c bus interface has issued an interrupt request to the cpu, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which dtc activation is possible. as the h8/3577 group and h8/3567 group do not have an on-chip dtc, the irtr flag is used by the cpu to determine the source that set iric. when the irtr flag is set to 1, the iric flag is also set to 1 at the same time.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 438 of 706 rej09b0303-0300 irtr flag setting is performed when the tdre or rdrf flag is set to 1. irtr is cleared by reading irtr after it has been set to 1, then writing 0 in irtr. irtr is also cleared automatically when the iric flag is cleared to 0. bit 5 irtr description 0 waiting for transfer, or transfer in progress [clearing conditions] ? when 0 is written in irtr after reading irtr = 1 ? when the iric flag is cleared to 0 (initial value) 1 continuous transfer state [setting conditions] ? in i 2 c bus interface slave mode when the tdre or rdrf flag is set to 1 when aasx = 1 ? in other modes when the tdre or rdrf flag is set to 1 bit 4?second slave address recognition flag (aasx): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits svax6 to svax0 in sarx. aasx is cleared by reading aasx after it has been set to 1, then writing 0 in aasx. aasx is also cleared automatically when a start condition is detected. bit 4 aasx description 0 second slave address not recognized [clearing conditions] ? when 0 is written in aasx after reading aasx = 1 ? when a start condition is detected ? in master mode (initial value) 1 second slave address recognized [setting condition] when the second slave address is detected in slave receive mode while fsx = 0
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 439 of 706 rej09b0303-0300 bit 3?arbitration lost (al): this flag indicates that arbitration was lost in master mode. the i 2 c bus interface monitors the sda. when two or more master devices attempt to seize the bus at nearly the same time, if the i 2 c bus interface detects data differing from the data it sent, it sets al to 1 to indicate that the bus has been taken by another master. al is cleared by reading al after it has been set to 1, then writing 0 in al. in addition, al is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode. bit 3 al description 0 bus arbitration won (initial value) [clearing conditions] ? when icdr data is written (transmit mode) or read (receive mode) ? when 0 is written in al after reading al = 1 1 arbitration lost [setting conditions] ? if the internal sda and sda pin disagree at the rise of scl in master transmit mode ? if the internal scl line is high at the fall of scl in master transmit mode bit 2?slave address recognition flag (aas): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits sva6 to sva0 in sar, or if the general call address (h'00) is detected. aas is cleared by reading aas after it has been set to 1, then writing 0 in aas. in addition, aas is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 440 of 706 rej09b0303-0300 bit 2 aas description 0 slave address or general call address not recognized (initial value) [clearing conditions] ? when icdr data is written (transmit mode) or read (receive mode) ? when 0 is written in aas after reading aas = 1 ? in master mode 1 slave address or general call address recognized [setting condition] when the slave address or general call address is detected in slave receive mode while fs = 0 bit 1?general call address recognition flag (adz): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (h'00). adz is cleared by reading adz after it has been set to 1, then writing 0 in adz. in addition, adz is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode. bit 1 adz description 0 general call address not recognized (initial value) [clearing conditions] ? when icdr data is written (transmit mode) or read (receive mode) ? when 0 is written in adz after reading adz = 1 ? in master mode 1 general call address recognized [setting condition] when the general call address is detected in slave receive mode while fsx = 0 or fs = 0
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 441 of 706 rej09b0303-0300 bit 0?acknowledge bit (ackb): stores acknowledge data. in transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ackb. in receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device. when this bit is read, in transmission (when trs = 1), the value loaded from the bus line (returned by the receiving device) is read. in reception (when trs = 0), the value set by internal software is read. also, when this bit is written, the set value of the acknowledge data to be issued upon receiving is rewritten, regardless of the trs value. since the value loaded from the receiving device is held, as is, in this case, care is required when rewriting this register using a bit operation command. bit 0 ackb description 0 receive mode: 0 is output at acknowledge output timing (initial value) transmit mode: indicates that the receiving device has acknowledged the data (signal is 0) 1 receive mode: 1 is output at acknowledge output timing transmit mode: indicates that the receiving device has not acknowledged the data (signal is 1) 16.2.7 serial timer control register (stcr) bit 76543210 ? iicx1 iicx0 iice ? usbe icks1 icks0 initial value00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w stcr is an 8-bit readable/writable register that controls register access, the iic interface operating mode (when the on-chip iic option is included), selects the tcnt input clock source, and controls the usb. for details of functions not related to the i 2 c bus interface, see section 3.2.3, serial timer control register (stcr), and the descriptions of the relevant modules. if a module controlled by stcr is not used, do not write 1 to the corresponding bit. stcr is initialized to h'00 by a reset and in hardware standby mode. bit 7?reserved: this bit must not be set to 1.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 442 of 706 rej09b0303-0300 bits 6 and 5?i 2 c transfer select 1 and 0 (iicx1, iicx0): these bits, together with bits cks2 to cks0 in icmr, select the transfer rate in master mode. for details, see section 16.2.4, i 2 c bus mode register (icmr). bit 4?i 2 c master enable (iice): controls cpu access to the i 2 c bus interface data and control registers (iccr, icsr, icdr/sarx, icmr/sar). bit 4 iice description 0 cpu access to i 2 c bus interface data and control registers is disabled (initial value) 1 cpu access to i 2 c bus interface data and control registers is enabled bit 3?reserved: this bit must not be set to 1. bit 2?usb enable (usbe): this bit controls cpu access to the usb data register and control register. bit 2 usbe description 0 prohibition of the above register access (initial value) 1 permission of the above register access bits 1 and 0?internal clock source select 1 and 0 (icks1, icsk0): these bits, together with bits cks2 to cks0 in tcr, select the clock input to the timer counters (tcnt). for details, see section 12.2.4, timer control register. 16.2.8 ddc switch register (ddcswr) bit 76543210 swe sw ie if clr3 clr2 clr1 clr0 initial value00001111 read/write r/w r/w r/w r/(w) * 1 w * 2 w * 2 w * 2 w * 2 notes: 1. only 0 can be written, to clear the flag. 2. always read as 1. ddcswr is an 8-bit readable/writable register that controls the iic channel 0 automatic format switching function.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 443 of 706 rej09b0303-0300 ddcswr is initialized to h'0f by a reset and in hardware standby mode. bit 7?ddc mode switch enable (swe): selects the function for automatically switching iic channel 0 from formatless mode to the i 2 c bus format. bit 7 swe description 0 automatic switching of iic channel 0 from formatless mode to i 2 c bus format is disabled (initial value) 1 automatic switching of iic channel 0 from formatless mode to i 2 c bus format is enabled bit 6?ddc mode switch (sw): selects either formatless mode or the i 2 c bus format for iic channel 0. bit 6 sw description 0 iic channel 0 is used with the i 2 c bus format [clearing conditions] ? when 0 is written by software ? when a falling edge is detected on the scl pin when swe = 1 (initial value) 1 iic channel 0 is used in formatless mode [setting condition] when 1 is written in sw after reading sw = 0 bit 5?ddc mode switch interrupt enable bit (ie): enables or disables an interrupt request to the cpu when automatic format switching is executed for iic channel 0. bit 5 ie description 0 interrupt when automatic format switching is executed is disabled (initial value) 1 interrupt when automatic format switching is executed is enabled
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 444 of 706 rej09b0303-0300 bit 4?ddc mode switch interrupt flag (if): flag that indicates an interrupt request to the cpu when automatic format switching is executed for iic channel 0. bit 4 if description 0 no interrupt is requested when automatic format switching is executed (initial value) [clearing condition] when 0 is written in if after reading if = 1 1 an interrupt is requested when automatic format switching is executed [setting condition] when a falling edge is detected on the scl pin when swe = 1 bits 3 to 0?iic clear 3 to 0 (clr3 to clr0): these bits control initialization of the internal state of iic0 and iic1. these bits can only be written to; if read they will always return a value of 1. when a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module(s), and the internal state of the iic module(s) is initialized. the write data for these bits is not retained. to perform iic clearance, bits clr3 to clr0 must be written to simultaneously using an mov instruction. do not use a bit manipulation instruction such as bclr. when clearing is required again, all the bits must be writen to in accordance with the setting. bit 3 bit 2 bit 1 bit 0 clr3 clr2 clr1 clr0 description 0 0 ? ? setting prohibited 1 0 0 setting prohibited 1 iic0 internal latch cleared 1 0 iic1 internal latch cleared 1 iic0 and iic1 internal latches cleared 1 ? ? ? invalid setting
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 445 of 706 rej09b0303-0300 16.2.9 module stop control register (mstpcr) mstpcrh mstpcrl bit 7654321076543210 mstp 15 mstp 14 mstp 13 mstp 12 mstp 11 mstp 10 mstp 9 mstp 8 mstp 7 mstp 6 mstp 5 mstp 4 mstp 3 mstp 2 mstp 1 mstp 0 initial value 0011111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w mstpcr comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. when the mstp4 or mstp3 bit is set to 1, operation of the corresponding iic channel is halted at the end of the bus cycle, and a transition is made to module stop mode. for details, see section 21.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrl bit 4?module stop (mstp4): specifies iic channel 0 module stop mode. mstpcrl bit 4 mstp4 description 0 iic channel 0 module stop mode is cleared 1 iic channel 0 module stop mode is set (initial value) mstpcrl bit 3?module stop (mstp3): specifies iic channel 1 module stop mode. mstpcrl bit 3 mstp3 description 0 iic channel 1 module stop mode is cleared 1 iic channel 1 module stop mode is set (initial value)
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 446 of 706 rej09b0303-0300 16.3 operation 16.3.1 i 2 c bus data format the i 2 c bus interface has serial and i 2 c bus formats. the i 2 c bus formats are addressing formats with an acknowledge bit. these are shown in figures 16.3 (a) and (b). the first frame following a start condition always consists of 8 bits. iic channel 0 only is capable of formatless operation, as shown in figure 16.3 (c). the serial format is a non-addressing format with no acknowledge bit. this is shown in figure 16.4. figure 16.5 shows the i 2 c bus timing. the symbols used in figures 16.3 to 16.5 are explained in table 16.4. s sla r/ w a data a a/ a p 1111 n 7 1 m (a) i 2 c bus format (fs = 0 or fsx = 0) (b) i 2 c bus format (start condition retransmission, fs = 0 or fsx = 0) n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) s sla r/ w a data 111 n1 7 1 m1 s sla r/ w a data a/ a p 111 n2 7 1 m2 11 1 a/ a n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) 11 (c) formatless (iic0 only, fs = 0 or fsx = 0) data a a data 11 n 8 1m 1 a/ a n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) figure 16.3 i 2 c bus data formats (i 2 c bus formats)
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 447 of 706 rej09b0303-0300 s data data p 11 n 8 1 m fs = 1 and fsx = 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) figure 16.4 i 2 c bus data format (serial format) sda scl s 1-7 sla 8 r/ w 9 a 1-7 data 89 1-7 89 a data p a/ a figure 16.5 i 2 c bus timing table 16.4 description of i 2 c bus data format symbols s indicates a start condition. when scl is high level, the master device changes sda from high to low level. sla indicates a slave address. the master device selects the slave device. r/ w indicates the transmit/receive direction. when the value of the r/ w bit is 1, data is transferred from the slave device to the master device. when it is 0, data is transferred from the master device to the slave device. a indicates an acknowledge response. the receiving device drives sda low level. (in master transmit mode the slave device, and in master receive mode the master device, returns the acknowledge response.) data indicates transmit/receive data. the bit length of the transmit/receive data is set by bits bc2 to bc0 in icmr. the mls bit in icmr is used to select between msb-first or lsb- first format. p indicates a stop condition. when scl is high level, the master device changes sda from low to high level.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 448 of 706 rej09b0303-0300 16.3.2 master transmit operation in i 2 c bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. the transmission procedure and operations by which data is sequentially transmitted in synchronization with icdr write operations, are described below. [1] set the ice bit in iccr to 1. set bits mls, wait, and cks2 to cks0 in icmr, and bit iicx in stcr, according to the operation mode. [2] read the bbsy flag to confirm that the bus is free. [3] set the mst and trs bits to 1 in iccr to select master transmit mode. [4] write 1 to bbsy and 0 to scp. this switches sda from high to low when scl is high, and generates the start condition. [5] when the start condition is generated, the iric and irtr flags are set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. [6] write data to icdr (slave address + r/ w ) with the i2c bus format (when the fs bit in sar or the fsx bit in sarx is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction. then clear the iric flag to indicate the end of transfer. writing to icdr and clearing of the iric flag must be executed continuously, so that no interrupt is inserted. if a period of time that is equal to transfer one byte has elapsed by the time the iric flag is cleared, the end of transfer cannot be identified. the master device sequentially sends the transmit clock and the data written to icdr with the timing shown in figure 16.6. the selected slave device (i.e., the slave device with the matching slave address) drives sda low at the 9th transmit clock pulse and returns an acknowledge signal. [7] when one frame of data has been transmitted, the iric flag is set to 1 at the rise of the 9th transmit clock pulse. after one frame has been transmitted, scl is automatically fixed low in synchronization with the internal clock until the next transmit data is written. [8] read the ackb bit to confirm that ackb is 0. when the slave device has not returned an acknowledge signal and ackb remains 1, execute the transmit end processing described in step [12] and perform transmit operation again.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 449 of 706 rej09b0303-0300 [9] write the next data to be transmitted in icdr. to identify the end of data transfer, clear the iric flag to 0. as described in step [6] above, writing to icdr and clearing of the iric flag must be executed continuously so that no interrupt is inserted. the next frame is transmitted in synchronization with the internal clock. [10] when one frame of data has been transmitted, the iric flag is set to 1 at the rise of the 9th transmit clock pulse. after one frame has been transmitted, scl is automatically fixed low in synchronization with the internal clock until the next transmit data is written. [11] read the ackb bit of icsr. confirm that the slave device has returned an acknowledge signal and ackb is 0. when more data is to be transmitted, return to step [9] to execute next transmit operation. if the slave device has not returned an acknowledge signal and ackb is 1, execute the transmit end processing described in step [12]. [12] clear the iric flag to 0. write bbsy and csp of iccr to 0. by doing so, sda is changed from low to high while scl is high and the transmit stop condition is generated. sda (master output) sda (slave output) 2 1 r/w 4 36 58 7 12 9 a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 iric irtr icdr normal operation precaution: data set timing to icdr incorrect operation scl (master output) start condition generation slave address data 1 data 1 [9] icdr write [9] iric clear [6] icdr write [6] iric clear [4] write 1 to bbsy and 0 to scp (start condition generation) user processing address + r/ w [7] [5] figure 16.6 example of master transmit mode operating timing (mls = wait = 0)
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 450 of 706 rej09b0303-0300 16.3.3 master receive operation in master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. the slave device transmits data. the transmission procedure and operations by which data is sequentially transmitted in synchronization with icdr write operations, are described below. [1] clear the trs bit of iccr to 0 and switch from transmit mode to receive mode. set the wait bit to 1 and clear the ackb bit of icsr to 0 (acknowledge data setting). [2] when icdr is read (dummy data read), reception is started and the receive clock is output, and data is received, in synchronization with the internal clock. to indicate the wait, clear the iric flag to 0. reading from icdr and clearing of the iric flag must be executed continuously so that no interrupt is inserted. if a period of time that is equal to transfer one byte has elapsed by the time the iric flag is cleared, the end of transfer cannot be identified. [3] the iric flag is set to 1 at the fall of the 8th clock of a one-frame reception clock. at this point, if the ieic bit of iccr is set to 1, an interrupt request is generated to the cpu. scl is automatically fixed low in synchronization with the internal clock until the iric flag is cleared. if the first frame is the final reception frame, execute the end processing as described in [10]. [4] clear the iric flag to 0 to negate the wait. the master device outputs the 9th receive clock pulse, sets sda to low, and returns an acknowledge signal. [5] when one frame of data has been transmitted, the iric and irtr flags are set to 1 at the rise of the 9th transmit clock pulse. the master device continues to output the receive clock for the next receive data. [6] read the icdr receive data. [7] clear the iric flag to indicate the next wait. from clearing of the iric flag to negation of a wait as described in step [4] (and [9]) to clearing of the iric flag as described in steps [5], [6], and [7], must be performed within the time taken to transfer one byte.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 451 of 706 rej09b0303-0300 [8] the iric flag is set to 1 at the fall of the 8th one-frame reception clock pulse. scl is automatically fixed low in synchronization with the internal clock until the iric flag is cleared. if this frame is the final reception frame, execute the end processing as described in [10]. [9] clear the iric flag to 0 to negate the wait. the master device outputs the 9th reception clock pulse, sets sda to low, and returns an acknowledge signal. by repeating steps [5] to [9] above, more data can be received. [10] set the ackb bit of icsr to 1 and set the acknowledge data for the final reception. set the trs bit of iccr to 1 to change receive mode to transmit mode. [11] clear the iric flag to negate the wait. [12] when one frame of data has been received, the iric flag is set to 1 at the rise of the 9th reception clock pulse. [13] clear the wait bit of icmr to 0 to cancel wait mode. read the icdr receive data and clear the iric flag to 0. clear the iric flag only when wait = 0. if the stop-condition generation command is executed after clearing the iric flag to 0 and then clearing the wait bit to 0, the sda line is fixed low and the stop condition cannot be generated. [14] write 0 to bbsy and scp. this changes sda from low to high when scl is high, and generates the stop condition.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 452 of 706 rej09b0303-0300 sda (master output) sda (slave output) 2 1 4 3 6 5 8 7 1 2345 9 9 a a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 iric irtr icdr scl (master output) master transmit mode master receive mode data 1 data 1 data 2 [2] icdr read (dummy read) [1] trs = 0 clear wait = 1 set ackb = 0 clear [2] iric clear [7] iric clear [6] icdr read (data 1) [4] iric clear user processing [5] [3] figure 16.7 (1) example of master receive mode operating timing (mls = ackb = 0 and wait = 1) sda (master output) sda (slave output) 2 1 4 3 6 5 8 7 1 2 9 9 8 a a bit 7 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 iric irtr icdr scl (master output) data 3 data 2 data 1 data 2 data 3 data 4 [9] iric clear [7] iric clear [9] iric clear [7] iric clear user processing [5] [8] [5] [8] [6] icdr read (data 2) [6] icdr read (data 3) figure 16.7 (2) example of master receive mode operating timing (mls = ackb = 0 and wait = 1) 16.3.4 slave receive operation in slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. the reception procedure and operations in slave receive mode are described below. [1] set the ice bit in iccr to 1. set the mls bit in icmr and the mst and trs bits in iccr according to the operating mode. [2] when the start condition output by the master device is detected, the bbsy flag in iccr is set to 1.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 453 of 706 rej09b0303-0300 [3] when the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. if the 8th data bit (r/ w ) is 0, the trs bit in iccr remains cleared to 0, and slave receive operation is performed. [4] at the 9th clock pulse of the receive frame, the slave device drives sda low and returns an acknowledge signal. at the same time, the iric flag in iccr is set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. if the rdrf internal flag has been cleared to 0, it is set to 1, and the receive operation continues. if the rdrf internal flag has been set to 1, the slave device drives scl low from the fall of the receive clock until data is read into icdr. [5] read icdr and clear the iric flag in iccr to 0. the rdrf flag is cleared to 0. receive operations can be performed continuously by repeating steps [4] and [5]. when sda is changed from low to high when scl is high, and the stop condition is detected, the bbsy flag in iccr is cleared to 0. sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) start condition generation scl (slave output) interrupt request generation address + r/ w address + r/ w [5] icdr read [5] iric clearance user processing slave address data 1 [4] a r/ w figure 16.8 example of slave receive mode operation timing (1) (mls = ackb = 0)
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 454 of 706 rej09b0303-0300 sda (master output) sda (slave output) 2 14 36 58 79 8 79 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) scl (slave output) interrupt request generation interrupt request generation data 2 data 2 data 1 data 1 [5] icdr read [5] iric clearance user processing data 2 data 1 [4] [4] a a figure 16.9 example of slave receive mode operation timing (2) (mls = ackb = 0)
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 455 of 706 rej09b0303-0300 16.3.5 slave transmit operation in slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. the transmission procedure and operations in slave transmit mode are described below. [1] set the ice bit in iccr to 1. set the mls bit in icmr and the mst and trs bits in iccr according to the operating mode. [2] when the slave address matches in the first frame following detection of the start condition, the slave device drives sda low at the 9th clock pulse and returns an acknowledge signal. at the same time, the iric flag in iccr is set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. if the 8th data bit (r/ w ) is 1, the trs bit in iccr is set to 1, and the mode changes to slave transmit mode automatically. the tdrf internal flag is set to 1. the slave device drives scl low from the fall of the transmit clock until icdr data is written. [3] after clearing the iric flag to 0, write data to icdr. the tdre internal flag is cleared to 0. the written data is transferred to icdrs, and the tdre internal flag and the iric and irtr flags are set to 1 again. after clearing the iric flag to 0, write the next data to icdr. the slave device sequentially sends the data written into icdr in accordance with the clock output by the master device at the timing shown in figure 16.10. [4] when one frame of data has been transmitted, the iric flag in iccr is set to 1 at the rise of the 9th transmit clock pulse. if the tdre internal flag has been set to 1, this slave device drives scl low from the fall of the transmit clock until data is written to icdr. the master device drives sda low at the 9th clock pulse, and returns an acknowledge signal. as this acknowledge signal is stored in the ackb bit in icsr, this bit can be used to determine whether the transfer operation was performed normally. when the tdre internal flag is 0, the data written into icdr is transferred to icdrs, transmission is started, and the tdre internal flag and the iric and irtr flags are set to 1 again. [5] to continue transmission, clear the iric flag to 0, then write the next data to be transmitted into icdr. the tdre flag is cleared to 0. transmit operations can be performed continuously by repeating steps [4] and [5]. to end transmission, write h'ff to icdr to release sda on the slave side. when sda is changed from low to high when scl is high, and the stop condition is detected, the bbsy flag in iccr is cleared to 0.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 456 of 706 rej09b0303-0300 sda (slave output) sda (master output) scl (slave output) 2 1 2 1 4 36 58 79 9 8 bit 7 bit 6 bit 5 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrt tdre scl (master output) interrupt request generation interrupt request generation slave receive mode slave transmit mode data 1 data 2 [3] iric clearance [5] iric clearance [3] icdr write [3] icdr write [5] icdr write user processing data 1 data 1 data 2 data 2 a r/ w a [3] [2] interrupt request generation figure 16.10 example of slave transmit mode operation timing (mls = 0)
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 457 of 706 rej09b0303-0300 16.3.6 iric setting timing and scl control the interrupt request flag (iric) is set at different times depending on the wait bit in icmr, the fs bit in sar, and the fsx bit in sarx. if the tdre or rdrf internal flag is set to 1, scl is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. figure 16.11 shows the iric set timing and scl control. (a) when wait = 0, and fs = 0 or fsx = 0 (i 2 c bus format, no wait) scl sda iric user processing clear iric write to icdr (transmit) or read icdr (receive) 1 a 8 1 1 a 7 1 89 7 (b) when wait = 1, and fs = 0 or fsx = 0 (i 2 c bus format, wait inserted) scl sda iric user processing clear iric clear iric write to icdr (transmit) or read icdr (receive) scl sda iric user processing (c) when fs = 1 and fsx = 1 (synchronous serial format) clear iric write to icdr (transmit) or read icdr (receive) 8 89 8 7 1 8 7 1 figure 16.11 iric setting timing and scl control
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 458 of 706 rej09b0303-0300 16.3.7 automatic switching from formatless mode to i 2 c bus format setting the sw bit to 1 in ddcswr enables formatless mode to be selected as the iic0 operating mode. switching from formatless mode to the i 2 c bus format (slave mode) is performed automatically when a falling edge is detected on the scl pin. the following four preconditions are necessary for this operation: ? a common data pin (sda) for formatless and i 2 c bus format operation ? separate clock pins for formatless operation (vsynci) and i 2 c bus format operation (scl) ? a fixed 1 level for the scl pin during formatless operation (is not driven to low) ? settings of bits other than trs in iccr that allow i 2 c bus format operation automatic switching is performed from formatless mode to the i 2 c bus format when the sw bit in ddcswr is automatically cleared to 0 on detection of a falling edge on the scl pin. switching from the i 2 c bus format to formatless mode is achieved by having software set the sw bit in ddcswr to 1. in formatless mode, bits (such as msl and trs) that control the i 2 c bus interface operating mode must not be modified. when switching from the i 2 c bus format to formatless mode, set the trs bit to 1 or clear it to 0 according to the transmit data (transmission or reception) in formatless mode, then set the sw bit to 1. after automatic switching from formatless mode to the i 2 c bus format (slave mode), in order to wait for slave address reception, the trs bit is automatically cleared to 0. if a falling edge is detected on the scl pin during formatless operation, i 2 c bus interface operation is deferred until a stop condition is detected.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 459 of 706 rej09b0303-0300 16.3.8 noise canceler the logic levels at the scl and sda pins are routed through noise cancelers before being latched internally. figure 16.12 shows a block diagram of the noise canceler circuit. the noise canceler consists of two cascaded latches and a match detector. the scl (or sda) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. system clock period sampling clock c dq latch c dq latch scl or sda input signal match detector internal scl or sda signal sampling clock figure 16.12 block diagram of noise canceler 16.3.9 sample flowcharts figures 16.13 to 16.16 show sample flowcharts for using the i 2 c bus interface in each mode.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 460 of 706 rej09b0303-0300 start end initialize read bbsy in iccr read iric in iccr read irci in iccr read ackb in icsr write transmit data in icdr clear iric in iccr read ackb in icsr clear iric in iccr clear iric in iccr read iric in iccr write transmit data in icdr master receive mode set mst = 1 and trs = 1 in iccr write bbsy = 0 and scp = 0 in iccr write bbsy = 1 and scp = 0 in iccr bbsy = 0 ? no iric = 1 ? ackb = 0 ? no no yes yes iric = 1 ? no yes yes transmit mode ? iric = 1 ? end of transmission ? or ackb = 1 ? no no no yes yes yes [2] test the status of the scl and sda lines. [3] select master transmit mode. [4] start condition issuance [6] set transmit data for the first byte (slave address + r/ w ). (after writing icdr, clear iric immediately) [1] initialize [8] test the acknowledge bit, transferred from slave device. [5] wait for a start condition [7] wait for 1 byte to be transmitted. [10] wait for 1 byte to be transmitted. [11] test for end of transfer [12] stop condition issuance [9] set transmit data for the second and subsequent bytes. (after writing icdr, clear iric immediately.) figure 16.13 flowchart for master transmit mode (example)
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 461 of 706 rej09b0303-0300 end set trs = 0 in iccr set ackb = 1 in icsr set wait = 0 in icmr read iric in iccr clear iric in iccr clear iric in iccr clear iric in iccr read icdr clear iric in iccr set ackb = 0 in icsr set wait = 1 in icmr write bbsy = 0 and scp = 0 in iccr last receive ? iric = 1 ? no no yes last receive ? no yes yes read iric in iccr iric = 1 ? no yes read iric in iccr iric = 1 ? no yes set trs = 1 in iccr read icdr read icdr clear iric in iccr clear iric in iccr [4] clear iric to trigger the 9th clock. (to end the wait insertion) [7] clear iric. [1] select receive mode. [2] start receiving. the first read is a dummy read. after reading icdr, please clear iric immediately. [3] wait for 1 byte to be received (8th clock falling edge) [9] clear iric to trigger the 9th clock. (to end the wait insertion) [10] set ackb = 1 so as to return no acknowledge, or set trs = 1 so as not to issue extra clock. [11] clear iric to trigger the 9th clock (to end the wait insertion) [5] wait for 1 byte to be received. (9th clock rising edge) [8] wait for the next data to be received. (8th clock falling edge) [6] read the receive data. [13] set wait = 0. read icdr. clear iric. (note: after setting wait = 0, iric should be cleared to 0.) [14] stop condition issuance. master receive operation read iric in iccr iric = 1 ? no yes [12] wait for 1 byte to be received. figure 16.14 flowchart for master receive mode (example)
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 462 of 706 rej09b0303-0300 start initialize set mst = 0 and trs = 0 in iccr set ackb = 0 in icsr read iric in iccr iric = 1? yes no clear iric in iccr read aas and adz in icsr aas = 1 and adz = 0? read trs in iccr trs = 0? no yes no yes yes no yes yes no no [1] [2] [3] [4] [5] [6] [7] [8] last receive? read icdr read iric in iccr iric = 1? clear iric in iccr set ackb = 1 in icsr read icdr read iric in iccr read icdr iric = 1? clear iric in iccr end general call address processing * description omitted slave transmit mode [1] select slave receive mode. [2] wait for the first byte to be received (slave address). [3] start receiving. the first read is a dummy read. [4] wait for the transfer to end. [5] set acknowledge data for the last receive. [6] start the last receive. [7] wait for the transfer to end. [8] read the last receive data. figure 16.15 flowchart for slave receive mode (example)
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 463 of 706 rej09b0303-0300 slave transmit mode write transmit data in icdr read iric in iccr iric = 1? clear iric in iccr clear iric in iccr clear iric in iccr read ackb in icsr set trs = 0 in iccr end of transmission (ackb = 1)? yes no no yes end [1] [2] [3] read icdr [5] [4] [1] set transmit data for the second and subsequent bytes. [2] wait for 1 byte to be transmitted. [3] test for end of transfer. [4] select slave receive mode. [5] dummy read (to release the scl line). figure 16.16 flowchart for slave transmit mode (example) 16.3.10 initialization of internal state the iic has a function for forcible initialization of its internal state if a deadlock occurs during communication. initialization is executed in accordance with the setting of bits clr3 to clr0 in the ddcswr register or clearing ice bit. for details the setting of bits clr3 to clr0, see section 16.2.8, ddc switch register (ddcswr). scope of initialization: the initialization executed by this function covers the following items: ? tdre and rdrf internal flags ? transmit/receive sequencer and internal operating clock counter
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 464 of 706 rej09b0303-0300 ? internal latches for retaining the output state of the scl and sda pins (wait, clock, data output, etc.) the following items are not initialized: ? actual register values (icdr, sar, sarx, icmr, iccr, icsr, ddcswr, stcr) ? internal latches used to retain register read information for setting/clearing flags in the icmr, iccr, icsr, and ddcswr registers ? the value of the icmr register bit counter (bc2 to bc0) ? generated interrupt sources (interrupt sources transferred to the interrupt controller) notes on initialization: ? interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. ? basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. ? when initialization is executed by the ddcswr register, the write data for bits clr3 to clr0 is not retained. to perform iic clearance, bits clr3 to clr0 must be written to simultaneously using an mov instruction. do not use a bit manipulation instruction such as bclr. similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. ? if a flag clearing setting is made during transmission/reception, the iic module will stop transmitting/receiving at that point and the scl and sda pins will be released. when transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. the value of the bbsy bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the scl and sda pins, the bbsy bit may be cleared as a result. similarly, state switching of other bits and flags may also have an effect. to prevent problems caused by these factors, the following procedure should be used when initializing the iic state. 1. execute initialization of the internal state according to the setting of bits clr3 to clr0. 2. execute a stop condition issuance instruction (write 0 to bbsy and scp) to clear the bbsy bit to 0, and wait for two transfer rate clock cycles. 3. re-execute initialization of the internal state according to the setting of bits clr3 to clr0. 4. initialize (re-set) the iic registers.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 465 of 706 rej09b0303-0300 16.4 usage notes ? in master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. to output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that scl and sda are both low, then issue the instruction that generates the stop condition. note that scl may not yet have gone low when bbsy is cleared to 0. ? either of the following two conditions will start the next transfer. pay attention to these conditions when reading or writing to icdr. ? write access to icdr when ice = 1 and trs = 1 (including automatic transfer from icdrt to icdrs) ? read access to icdr when ice = 1 and trs = 0 (including automatic transfer from icdrs to icdrr) ? table 16.5 shows the timing of scl and sda output in synchronization with the internal clock. timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, group resistance, and parallel resistance. table 16.5 i 2 c bus timing (scl and sda output) item symbol output timing unit notes scl output cycle time t sclo 28t cyc to 256t cyc ns scl output high pulse width t sclho 0.5t sclo ns figure 22.18 (reference) scl output low pulse width t scllo 0.5t sclo ns sda output bus free time t bufo 0.5t sclo ? 1t cyc ns start condition output hold time t staho 0.5t sclo ? 1t cyc ns retransmission start condition output setup time t staso 1t sclo ns stop condition output setup time t stoso 0.5t sclo + 2t cyc ns data output setup time (master) t sdaso 1t scllo ? 3t cyc ns data output setup time (slave) 1t scll ? (6t cyc or 12t cyc * ) data output hold time t sdaho 3t cyc ns note: * 6t cyc when iicx is 0, 12t cyc when 1.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 466 of 706 rej09b0303-0300 ? scl and sda input is sampled in synchronization with the internal clock. the ac timing therefore depends on the system clock cycle t cyc , as shown in table 22.8 in section 22, electrical characteristics. note that the i 2 c bus interface ac timing specifications will not be met with a system clock frequency of less than 5 mhz. ? the i 2 c bus interface specification for the scl rise time t sr is under 1000 ns (300 ns for high- speed mode). in master mode, the i 2 c bus interface monitors the scl line and synchronizes one bit at a time during communication. if t sr (the time for scl to go from low to v ih ) exceeds the time determined by the input clock of the i 2 c bus interface, the high period of scl is extended. the scl rise time is determined by the pull-up resistance and load capacitance of the scl line. to insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the scl rise time does not exceed the values given in the table below. table 16.6 permissible scl rise time (t sr ) values time indication iicx t cyc indication i 2 c bus specifi- cation (max.) = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz 07.5t cyc normal mode 1000 ns 1000 ns 937 ns 750 ns 468 ns 375 ns high-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 1 17.5t cyc normal mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns 875 ns high-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns ? the i 2 c bus interface specifications for the scl and sda rise and fall times are under 1000 ns and 300 ns. the i 2 c bus interface scl and sda output timing is prescribed by t cyc , as shown in table 16.6. however, because of the rise and fall times, the i 2 c bus interface specifications may not be satisfied at the maximum transfer rate. table 16.7 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. t bufo fails to meet the i 2 c bus interface specifications at any frequency. the solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the i 2 c bus. t scllo in high-speed mode and t staso in standard mode fail to satisfy the i 2 c bus interface specifications for worst-case calculations of t sr /t sf . possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the i 2 c bus.
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 467 of 706 rej09b0303-0300 table 16.7 i 2 c bus timing (with maximum influence of t sr /t sf ) time indication (at maximum transfer rate) [ns] item t cyc indication t sr /t sf influence (max.) i 2 c bus specifi- cation (min.) = 5 mhz = 8 mhz = 10 mhz = 16 mhz = 20 mhz t sclho standard mode ? 1000 4000 4000 4000 4000 4000 4000 0.5t sclo ( ? t sr ) high-speed mode ? 300 600 950 950 950 950 950 t scllo standard mode ? 250 4700 4750 4750 4750 4750 4750 0.5t sclo ( ? t sf ) high-speed mode ? 250 1300 1000 * 1 1000 * 1 1000 * 1 1000 * 1 1000 * 1 t bufo standard mode ? 1000 4700 3800 * 1 3875 * 1 3900 * 1 3938 * 1 3950 * 1 0.5t sclo ? 1t cyc ( ? t sr ) high-speed mode ? 300 1300 750 * 1 825 * 1 850 * 1 888 * 1 900 * 1 t staho standard mode ? 250 4000 4550 4625 4650 4688 4700 0.5t sclo ? 1t cyc ( ? t sf ) high-speed mode ? 250 600 800 875 900 938 950 t staso standard mode ? 1000 4700 9000 9000 9000 9000 9000 1t sclo ( ? t sr ) high-speed mode ? 300 600 2200 2200 2200 2200 2200 t stoso standard mode ? 1000 4000 4400 4250 4200 4125 4100 0.5t sclo + 2t cyc ( ? t sr ) high-speed mode ? 300 600 1350 1200 1150 1075 1050 standard mode ? 1000 250 3100 3325 3400 3513 3550 t sdaso (master) 1t scllo * 3 ? 3t cyc ( ? t sr ) high-speed mode ? 300 100 400 625 700 813 850 standard mode ? 1000 250 1300 2200 2500 2950 3100 t sdaso (slave) 1t scll * 3 ? 12t cyc * 2 ( ? t sr ) high-speed mode ? 300 100 ? 1400 * 1 ? 500 * 1 ? 200 * 1 250 400 t sdaho standard mode 0 0 600 375 300 188 150 3t cyc high-speed mode 0 0 600 375 300 188 150 notes: 1. does not meet the i 2 c bus interface specification. remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. the values in the above table will vary depending on the settings of the iicx bit and bits cks0 to cks2. depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the i 2 c bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. value when the iicx bit is set to 1. when the iicx bit is cleared to 0, the value is (t scll ? 6t cyc ). 3. calculated using the i 2 c bus specification values (standard mode: 4700 ns min.; high- speed mode: 1300 ns min.).
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 468 of 706 rej09b0303-0300 ? note on icdr read at end of master reception to halt reception at the end of a receive operation in master receive mode, set the trs bit to 1 and write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. after this, receive data can be read by means of an icdr read, but if data remains in the buffer the icdrs receive data will not be transferred to icdr, and so it will not be possible to read the second byte of data. if it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the trs bit cleared to 0). when reading the receive data, first confirm that the bbsy bit in the iccr register is cleared to 0, the stop condition has been generated, and the bus has been released, then read the icdr register with trs cleared to 0. note that if the receive data (icdr data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to bbsy and scp in iccr) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. clearing of the mst bit after completion of master transmission/reception, or other modifications of iic control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 16.17 (after confirming that the bbsy bit has been cleared to 0 in the iccr register). sda scl internal clock bbsy bit master receive mode icdr reading prohibited bit 0 a 8 9 stop condition (a) start condition execution of stop condition issuance instruction (0 written to bbsy and scp) confirmation of stop condition generation (0 read from bbsy) start condition issuance figure 16.17 points for attention concerning reading of master receive data
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 469 of 706 rej09b0303-0300 ? notes on start condition issuance for retransmission figure 16.18 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to icdr, together with the corresponding flowchart. after start condition issuance is done and determined the start condition, write the transmit data to icdr, as shown below. read scl pin write transmit data to icdr clear iric in icsr write bbsy = 1, scp = 0 (icsr) iric = 1 ? no scl = low ? no yes start condition issuance ? no [1] [2] [3] [4] [5] [1] [2] [3] [4] [5] wait for end of 1-byte transfer determine whether scl is low issue restart condition instruction for transmission detremine whether start condition is generated or not set transmit data (slave address + r/ w ) note: program so that processing from [3] to [5] is executed continuously. other processing yes yes iric = 1 ? no yes scl bit7 data output ack 9 iric [1] iric determination [2] determination of scl = low [5] icdr write (next transmit data) sda [3] start condition instruction issuance start condition (retransmission) [4] iric determination figure 16.18 flowchart and timing of start condition instruction issuance for retransmission
section 16 i 2 c bus interface (iic) rev. 3.00 mar 17, 2006 page 470 of 706 rej09b0303-0300 ? notes on i 2 c bus interface stop condition instruction issuance if the rise time of the 9th scl clock exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives scl low to effect a wait, after rising of the 9th scl clock, issue the stop condition after reading scl and determining it to below, as shown below. stop condition scl iric [1] determination of scl = low 9th clock vih high period secured [2] stop condition instruction isuuance sda as waveform rise is late, scl is detected as low figure 16.19 timing of stop condition issuance
section 17 a/d converter rev. 3.00 mar 17, 2006 page 471 of 706 rej09b0303-0300 section 17 a/d converter 17.1 overview the h8/3577 group and h8/3567 group have an on-chip 10-bit successive-approximations a/d converter that allows up to eight analog input channels to be selected. the h8/3577 group has eight analog input channels, and the h8/3567 group has four. 17.1.1 features a/d converter features are listed below. ? 10-bit resolution (analog input) ? input channels ? 8 channels (h8/3577 group) ? 4 channels (h8/3567 group) ? settable analog conversion voltage range ? the analog conversion voltage range is set using the analog power supply voltage pin (avcc) as the analog reference voltage ? high-speed conversion ? minimum conversion time: 6.7 s per channel (at 20 mhz operation) ? choice of single mode or scan mode ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels ? four data registers ? conversion results are held in a 16-bit data register for each channel ? sample and hold function ? three kinds of conversion start ? choice of software or timer conversion start trigger (8-bit timer), or adtrg pin ? a/d conversion end interrupt generation ? an a/d conversion end interrupt (adi) request can be generated at the end of a/d conversion
section 17 a/d converter rev. 3.00 mar 17, 2006 page 472 of 706 rej09b0303-0300 17.1.2 block diagram figure 17.1 shows a block diagram of the a/d converter. module data bus control circuit internal data bus 10-bit d/a comparator + ? sample-and- hold circuit h8/3577 group only /8 /16 adi interrupt signal bus interface adcsr adcr addrd addrc addrb addra av cc av ss an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 adtrg conversion start trigger from 8-bit timer successive approximations register multiplexer legend: adcr: a/d control register adcsr: a/d control/status register addra: a/d data register a addrb: a/d data register b addrc: a/d data register c addrd: a/d data register d figure 17.1 block diagram of a/d converter
section 17 a/d converter rev. 3.00 mar 17, 2006 page 473 of 706 rej09b0303-0300 17.1.3 pin configuration table 17.1 summarizes the input pins used by the a/d converter. the av cc and av ss pins are the power supply pins for the analog block in the a/d converter. table 17.1 a/d converter pins pin name symbol i/o function analog power supply pin av cc input analog block power supply analog ground pin av ss input analog block ground and a/d conversion reference voltage analog input pin 0 an 0 input analog input channel 0 analog input pin 1 an 1 input analog input channel 1 analog input pin 2 an 2 input analog input channel 2 analog input pin 3 an 3 input analog input channel 3 analog input pin 4 an 4 input analog input channel 4 (h8/3577 group only) analog input pin 5 an 5 input analog input channel 5 (h8/3577 group only) analog input pin 6 an 6 input analog input channel 6 (h8/3577 group only) analog input pin 7 an 7 input analog input channel 7 (h8/3577 group only) a/d external trigger input pin adtrg input external trigger input for starting a/d conversion
section 17 a/d converter rev. 3.00 mar 17, 2006 page 474 of 706 rej09b0303-0300 17.1.4 register configuration table 17.2 summarizes the registers of the a/d converter. table 17.2 a/d converter registers name abbreviation r/w initial value address a/d data register ah addrah r h'00 h'ffe0 a/d data register al addral r h'00 h'ffe1 a/d data register bh addrbh r h'00 h'ffe2 a/d data register bl addrbl r h'00 h'ffe3 a/d data register ch addrch r h'00 h'ffe4 a/d data register cl addrcl r h'00 h'ffe5 a/d data register dh addrdh r h'00 h'ffe6 a/d data register dl addrdl r h'00 h'ffe7 a/d control/status register adcsr r/(w) * h'00 h'ffe8 a/d control register adcr r/w h'3f h'ffe9 module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 note: * only 0 can be written in bit 7, to clear the flag. 17.2 register descriptions 17.2.1 a/d data registers a to d (addra to addrd) bit 1514131211109876543210 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? initial value0000000000000000 read/write r rrrrrrrrrrrrrrr there are four 16-bit read-only addr registers, addra to addrd, used to store the results of a/d conversion.
section 17 a/d converter rev. 3.00 mar 17, 2006 page 475 of 706 rej09b0303-0300 the 10-bit data resulting from a/d conversion is transferred to the addr register for the selected channel and stored there. the upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of addr, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. bits 5 to 0 are always read as 0. the correspondence between the analog input channels and addr registers is shown in table 17.3. the addr registers can always be read by the cpu. the upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (temp). for details, see section 17.3, interface to bus master. the addr registers are initialized to h'0000 by a reset, and in standby mode, and module stop mode. table 17.3 analog input channels and corresponding addr registers analog input channel group 0 group 1 a/d data register an 0 an 4 addra an 1 an 5 addrb an 2 an 6 addrc an 3 an 7 addrd 17.2.2 a/d control/status register (adcsr) bit 76543210 adf adie adst scan cks ch2 ch1 ch0 initial value00000000 read/write r/(w) * r/w r/w r/w r/w r/w r/w r/w note: * only 0 can be written in bit 7, to clear the flag. adcsr is an 8-bit readable/writable register that controls a/d conversion operations. adcsr is initialized to h'00 by a reset, and in standby mode, and module stop mode.
section 17 a/d converter rev. 3.00 mar 17, 2006 page 476 of 706 rej09b0303-0300 bit 7?a/d end flag (adf): status flag that indicates the end of a/d conversion. bit 7 adf description 0 [clearing condition] (initial value ) when 0 is written in the adf flag after reading adf = 1 1 [setting conditions] ? single mode: when a/d conversion ends ? scan mode: when a/d conversion ends on all specified channels bit 6?a/d interrupt enable (adie): selects enabling or disabling of interrupt (adi) requests at the end of a/d conversion. bit 6 adie description 0 a/d conversion end interrupt (adi) request is disabled (initial value ) 1 a/d conversion end interrupt (adi) request is enabled bit 5?a/d start (adst): selects starting or stopping of a/d conversion. holds a value of 1 during a/d conversion. the adst bit can be set to 1 by software, a timer conversion start trigger, or the a/d external trigger input pin ( adtrg ). bit 5 adst description 0 a/d conversion stopped (initial value ) 1 single mode: a/d conversion is started. cleared to 0 automatically when conversion on the specified channel ends scan mode: a/d conversion is started. conversion continues sequentially on the selected channels until adst is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode
section 17 a/d converter rev. 3.00 mar 17, 2006 page 477 of 706 rej09b0303-0300 bit 4?scan mode (scan): selects single mode or scan mode as the a/d conversion operating mode. see section 17.4, operation, for single mode and scan mode operation. only set the scan bit while conversion is stopped. bit 4 scan description 0 single mode (initial value ) 1 scan mode bit 3?clock select (cks): sets the a/d conversion time. only change the conversion time while adst = 0. bit 3 cks description 0 conversion time = 266 states (max.) (initial value ) 1 conversion time = 134 states (max.) bits 2 to 0?channel select 2 to 0 (ch2 to ch0): together with the scan bit, these bits select the analog input channel(s). only set the input channel while conversion is stopped. group selection channel selection description ch2 ch1 ch0 single mode scan mode 000an 0 (initial value) an 0 1an 1 an 0 , an 1 10 an 2 an 0 to an 2 h8/3577 group and h8/3567 group 1an 3 an 0 to an 3 100an 4 an 4 1an 5 an 4 , an 5 10 an 6 an 4 , an 5 , an 6 h8/3577 group only 1an 7 an 4 to an 7
section 17 a/d converter rev. 3.00 mar 17, 2006 page 478 of 706 rej09b0303-0300 17.2.3 a/d control register (adcr) bit 76543210 trgs1trgs0?????? initial value00111111 read/write r/w r/w ?????? adcr is an 8-bit readable/writable register that enables or disables external triggering of a/d conversion operations. adcr is initialized to h'3f by a reset, and in standby mode, and module stop mode. bits 7 and 6?timer trigger select 1 and 0 (trgs1, trgs0): these bits select enabling or disabling of the start of a/d conversion by a trigger signal. only set bits trgs1 and trgs0 while conversion is stopped. bit 7 bit 6 trgs1 trgs0 description 0 0 start of a/d conversion by external trigger is disabled (initial value) 1 start of a/d conversion by external trigger is disabled 1 0 start of a/d conversion by external trigger (8-bit timer) is enabled 1 start of a/d conversion by external trigger pin is enabled bits 5 to 0?reserved: these bits cannot be modified and are always read as 1.
section 17 a/d converter rev. 3.00 mar 17, 2006 page 479 of 706 rej09b0303-0300 17.2.4 module stop control register (mstpcr) mstpcrh mstpcrl bit 7654321076543210 mstp 15 mstp 14 mstp 13 mstp 12 mstp 11 mstp 10 mstp 9 mstp 8 mstp 7 mstp 6 mstp 5 mstp 4 mstp 3 mstp 2 mstp 1 mstp 0 initial value 0011111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w mstpcr, comprising two 8-bit readable/writable registers, performs module stop mode control. when the mstp9 bit in mstpcr is set to 1, a/d converter operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 21.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrh bit 1?module stop (mstp9): specifies the a/d converter module stop mode. mstpcrh bit 1 mstp9 description 0 a/d converter module stop mode is cleared 1 a/d converter module stop mode is set (initial value )
section 17 a/d converter rev. 3.00 mar 17, 2006 page 480 of 706 rej09b0303-0300 17.3 interface to bus master addra to addrd are 16-bit registers, but the data bus to the bus master is only 8 bits wide. therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (temp). a data read from addr is performed as follows. when the upper byte is read, the upper byte value is transferred to the cpu and the lower byte value is transferred to temp. next, when the lower byte is read, the temp contents are transferred to the cpu. when reading addr, always read the upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. figure 17.2 shows the data flow for addr access. bus master (h'aa) addrnh (h'aa) addrnl (h'40) lower byte read addrnh (h'aa) addrnl (h'40) temp (h'40) temp (h'40) (n = a to d) (n = a to d) module data bus module data bus bus interface upper byte read bus master (h'40) bus interface figure 17.2 addr access operation (reading h'aa40)
section 17 a/d converter rev. 3.00 mar 17, 2006 page 481 of 706 rej09b0303-0300 17.4 operation the a/d converter operates by successive approximations with 10-bit resolution. it has two operating modes: single mode and scan mode. 17.4.1 single mode (scan = 0) single mode is selected when a/d conversion is to be performed on a single channel only. a/d conversion is started when the adst bit is set to 1 by software, or by external trigger input. the adst bit remains set to 1 during a/d conversion, and is automatically cleared to 0 when conversion ends. on completion of conversion, the adf flag is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. the adf flag is cleared by writing 0 after reading adcsr. when the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the operating mode or input channel is changed. typical operations when channel 1 (an 1 ) is selected in single mode are described next. figure 17.3 shows a timing diagram for this example. 1. single mode is selected (scan = 0), input channel an 1 is selected (ch1 = 0, ch0 = 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). 2. when a/d conversion is completed, the result is transferred to addrb. at the same time the adf flag is set to 1, the adst bit is cleared to 0, and the a/d converter becomes idle. 3. since adf = 1 and adie = 1, an adi interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the routine reads adcsr, then writes 0 to the adf flag. 6. the routine reads and processes the conversion result (addrb). 7. execution of the a/d interrupt handling routine ends. after that, if the adst bit is set to 1, a/d conversion starts again and steps 2 to 7 are repeated.
section 17 a/d converter rev. 3.00 mar 17, 2006 page 482 of 706 rej09b0303-0300 adie adst adf state of channel 0 (an 0 ) a/d conversion starts addra addrb addrc addrd state of channel 1 (an 1 ) state of channel 2 (an 2 ) state of channel 3 (an 3 ) note: * vertical arrows ( ) indicate instructions executed by software. set * set * clear * clear * a/d conversion result 1 a/d conversion 1 a/d conversion result 2 read conversion result read conversion result idle idle idle idle idle idle a/d conversion 2 set * figure 17.3 example of a/d converter operation (single mode, channel 1 selected)
section 17 a/d converter rev. 3.00 mar 17, 2006 page 483 of 706 rej09b0303-0300 17.4.2 scan mode (scan = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit is set to 1 by software, or by timer or external trigger input, a/d conversion starts on the first channel in the group (an 0 when ch2 = 0; an 4 when ch2 = 1). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an 1 or an 5 ) starts immediately. a/d conversion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are transferred for storage into the addr registers corresponding to the channels. when the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the operating mode or input channel is changed. typical operations when three channels (an 0 to an 2 ) are selected in scan mode are described next. figure 17.4 shows a timing diagram for this example. 1. scan mode is selected (scan = 1), scan group 0 is selected (ch2 = 0), analog input channels an 0 to an 2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1) 2. when a/d conversion of the first channel (an 0 ) is completed, the result is transferred to addra. next, conversion of the second channel (an 1 ) starts automatically. 3. conversion proceeds in the same way through the third channel (an 2 ). 4. when conversion of all the selected channels (an 0 to an 2 ) is completed, the adf flag is set to 1 and conversion of the first channel (an 0 ) starts again. if the adie bit is set to 1 at this time, an adi interrupt is requested after a/d conversion ends. 5. steps 2 to 4 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an 0 ).
section 17 a/d converter rev. 3.00 mar 17, 2006 page 484 of 706 rej09b0303-0300 adst adf addra addrb addrc addrd state of channel 0 (an 0 ) state of channel 1 (an 1 ) state of channel 2 (an 2 ) state of channel 3 (an 3 ) set * 1 clear * 1 idle notes: 1. vertical arrows ( ) indicate instructions executed by software. 2. data currently being converted is ignored. clear * 1 idle idle a/d conversion time idle continuous a/d conversion execution a/d conversion 1 idle idle idle idle idle transfer * 2 a/d conversion 3 a/d conversion 2 a/d conversion 5 a/d conversion 4 a/d conversion result 1 a/d conversion result 2 a/d conversion result 3 a/d conversion result 4 figure 17.4 example of a/d converter operation (scan mode, channels an 0 to an 2 selected)
section 17 a/d converter rev. 3.00 mar 17, 2006 page 485 of 706 rej09b0303-0300 17.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit is set to 1, then starts conversion. figure 17.5 shows the a/d conversion timing. table 17.4 indicates the a/d conversion time. as indicated in figure 17.5, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 17.4. in scan mode, the values given in table 17.4 apply to the first conversion time. in the second and subsequent conversions the conversion time is fixed at 256 states when cks = 0 or 128 states when cks = 1. (1) (2) t d t spl t conv input sampling timing adf address write signal legend: (1): adcsr write cycle (2): adcsr address t d : a/d conversion start delay t spl : input sampling time t conv : a/d conversion time figure 17.5 a/d conversion timing
section 17 a/d converter rev. 3.00 mar 17, 2006 page 486 of 706 rej09b0303-0300 table 17.4 a/d conversion time (single mode) cks = 0 cks = 1 item symbol min typ max min typ max a/d conversion start delay t d 10 ? 17 6 ? 9 input sampling time t spl ? 63 ?? 31 ? a/d conversion time t conv 259 ? 266 131 ? 134 note: values in the table are the number of states. 17.4.4 external trigger input timing a/d conversion can be externally triggered. when the trgs1 and trgs0 bits are set to 11 in adcr, external trigger input is enabled at the adtrg pin. a falling edge at the adtrg pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as when the adst bit is set to 1 by software. figure 17.6 shows the timing. adtrg internal trigger signal adst a/d conversion figure 17.6 external trigger input timing 17.5 interrupts the a/d converter generates an interrupt (adi) at the end of a/d conversion. the adi interrupt request can be enabled or disabled by the adie bit in adcsr.
section 17 a/d converter rev. 3.00 mar 17, 2006 page 487 of 706 rej09b0303-0300 17.6 usage notes the following points should be noted when using the a/d converter. setting range of analog power supply and other pins 1. analog input voltage range the voltage applied to the ann analog input pins during a/d conversion should be in the range av ss ann av cc (n = 0 to 7). 2. relation between av cc , av ss and v cc , v ss as the relationship between av cc , av ss and v cc , v ss , set av ss = v ss . if the a/d converter is not used, the av cc and av ss pins must on no account be left open. if conditions 1 and 2 above are not met, the reliability of the device may be adversely affected. notes on board design: in board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting a/d conversion values. also, digital circuitry must be isolated from the analog input signals (an 0 to an 7 ), and analog power supply (av cc ) by the analog ground (av ss ). also, the analog ground (av ss ) should be connected at one point to a stable digital ground (v ss ) on the board. notes on noise countermeasures: a protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (an 0 to an 7 ) should be connected between av cc and av ss as shown in figure 17.7. also, the bypass capacitors connected to av cc and the filter capacitor connected to an 0 to an 7 must be connected to av ss . if a filter capacitor is connected as shown in figure 17.7, the input currents at the analog input pins (an 0 to an 7 ) are averaged, and so an error may arise. also, when a/d conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the a/d converter exceeds the current input via the input impedance (r in ), an error will arise in the analog input pin voltage. careful consideration is therefore required when deciding the circuit constants.
section 17 a/d converter rev. 3.00 mar 17, 2006 page 488 of 706 rej09b0303-0300 av cc * 1 an 0 to an 7 av ss notes: figures are reference values. 1. 2. r in : input impedance r in * 2 100 ? 0.1 f 0.01 f 10 f figure 17.7 example of analog input protection circuit table 17.5 analog pin specifications item min max unit analog input capacitance ? 20 pf permissible signal source impedance ? 10 * k ? note: * when v cc = 4.5 v to 5.5 v and 12 mhz 20 pf to a/d converter an 0 to an 7 10 k ? note: figures are reference values. figure 17.8 analog input pin equivalent circuit
section 17 a/d converter rev. 3.00 mar 17, 2006 page 489 of 706 rej09b0303-0300 a/d conversion precision definitions: a/d conversion precision definitions for the h8/3577 group and h8/3567 group are given below. ? resolution the number of a/d converter digital output codes ? offset error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value b'0000000000 (h'000) to b'0000000001 (h'001) (see figure 17.10). ? full-scale error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from b'1111111110 (h'3fe) to b'111111111 (h'3ff) (see figure 17.10). ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 17.9). ? nonlinearity error the error with respect to the ideal a/d conversion characteristic between the zero voltage and the full-scale voltage. does not include the offset error, full-scale error, or quantization error. ? absolute precision the deviation between the digital value and the analog input value. includes the offset error, full-scale error, quantization error, and nonlinearity error.
section 17 a/d converter rev. 3.00 mar 17, 2006 page 490 of 706 rej09b0303-0300 h'3ff h'3fe h'3fd h'004 h'003 h'002 h'001 h'000 1 1024 2 1024 1023 1024 1022 1024 fs quantization error digital output ideal a/d conversion characteristic analog input voltage figure 17.9 a/d conversion precision definitions (1) fs offset error nonlinearity error actual a/d conversion characteristic analog input voltage digital output ideal a/d conversion characteristic full-scale error figure 17.10 a/d conversion precision definitions (2)
section 17 a/d converter rev. 3.00 mar 17, 2006 page 491 of 706 rej09b0303-0300 permissible signal source impedance: analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k ? (when av cc = 4.5 to 5.5 v and 12 mhz, or when csk = 0) or less. this specification is provided to enable the a/d converter?s sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k ? (when av cc = 4.5 to 5.5 v and 12 mhz, or when csk = 0), charging may be insufficient and it may not be possible to guarantee the a/d conversion precision. however, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 k ? , and the signal source impedance is ignored. but since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/sec or greater). when converting a high-speed analog signal, a low-impedance buffer should be inserted. influences on absolute precision: adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute precision. be sure to make the connection to an electrically stable gnd such as av ss . care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. a/d converter equivalent circuit h8/3577 group or h8s/3567 group chip 20 pf c in = 15 pf 10 k ? low-pass filter c to 0.1 f sensor output impedance, up to 10 k ? sensor input note: figures are reference values. figure 17.11 example of analog input circuit
section 17 a/d converter rev. 3.00 mar 17, 2006 page 492 of 706 rej09b0303-0300
section 18 ram rev. 3.00 mar 17, 2006 page 493 of 706 rej09b0303-0300 section 18 ram 18.1 overview the h8/3577 group and h8/3567 group have 2 kbytes of on-chip high-speed static ram. the on-chip ram is connected to the bus master by a 16-bit data bus, enabling both byte data and word data to be accessed in two states. this makes it possible to perform fast word data transfer. the on-chip ram can be enabled or disabled by means of the ram enable bit (rame) in the system control register (syscr). 18.1.1 block diagram figure 18.1 shows a block diagram of the on-chip ram. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'e080 h'e082 h'e084 h'effe h'e081 h'e083 h'e085 h'efff h'ff00 h'ff7e h'ff01 h'ff7f figure 18.1 block diagram of ram
section 18 ram rev. 3.00 mar 17, 2006 page 494 of 706 rej09b0303-0300 18.1.2 register configuration the on-chip ram is controlled by syscr. table 18.1 shows the register configuration. table 18.1 register configuration name abbreviation r/w initial value address system control register syscr r/w h'09 h'ffc4 18.2 system control register (syscr) bit 76543210 cs2e iose intm1 intm0 xrst nmieg hie rame initial value00001001 read/write r/w r/w r r r r/w r/w r/w the on-chip ram is enabled or disabled by the rame bit in syscr. for details of other bits in syscr, see section 3.2.2, system control register. bit 0?ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset state is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) 18.3 operation when the rame bit is set to 1, accesses to addresses h'e880 to h'efff and h'ff00 to h'ff7f are directed to the on-chip ram. when the rame bit is cleared to 0, the on-chip ram is not accessed; a read will return an undefined value, and writes are invalid. since the on-chip ram is connected to the bus master by a 16-bit data bus, it can be written to and read in byte or word units. each type of access is performed in two states. even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. word data must start at an even address.
section 19 rom rev. 3.00 mar 17, 2006 page 495 of 706 rej09b0303-0300 section 19 rom 19.1 overview the h8/3577, h8/3567, and h8/3567u have 56 kbytes of on-chip rom (prom or mask rom), and the h8/3574, h8/3564, and h8/3564u have 32 kbytes. the rom is connected to the bus master by a 16-bit data bus. the cpu accesses both byte and word data in two states, enabling faster instruction fetches and higher processing speed. figure 19.1 shows a block diagram of the rom. h'0000 h'0002 h'dffe h'0001 h'0003 h'dfff internal data bus (upper 8 bits) internal data bus (lower 8 bits) figure 19.1 rom block diagram (h8/3577, h8/3567, h8/3567u) 19.2 operation the on-chip rom is connected to the cpu by a 16-bit data bus, and both byte and word data is accessed in two states. even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. word data must start at an even address.
section 19 rom rev. 3.00 mar 17, 2006 page 496 of 706 rej09b0303-0300 19.3 writer mode (h8/3577, h8/3567, h8/3567u) 19.3.1 writer mode setup in writer mode the prom versions of the h8/3577, h8/3567, and h8/3567u suspend the usual microcomputer functions to allow the on-chip prom to be programmed. the programming method is the same as for the hn27c101. to select writer mode, apply the signal inputs listed in table 19.1. table 19.1 selection of writer mode pin input h8/3577 mode pin md 1 low mode pin md 0 low stby pin low pins p6 3 and p6 4 high h8/3567, h8/3567u mode pin test low stby pin low pins p4 7 and p5 2 high
section 19 rom rev. 3.00 mar 17, 2006 page 497 of 706 rej09b0303-0300 19.3.2 socket adapter pin assignments and memory map the h8/3577, h8/3567, and h8/3567u can be programmed with a general-purpose prom programmer by using a socket adapter to change the pin-out to 32 pins. see table 19.2. the same socket adapter can be used for h8/3577, h8/3567, and h8/3567u. figures 19.2 to 19.4 show the socket adapter pin assignments. table 19.2 socket adapter package socket adapter 64-pin qfp (h8/3577) hs3297eshs1h 64-pin shrink dip (h8/3577) hs3297esss1h 44-pin qfp (h8/3567) tbd 42-pin shrink dip (h8/3567) tbd 64-pin qfp (h8/3567u) tbd 64-pin shrink dip (h8/3567u) tbd the prom size is 56 kbytes for the h8/3577, h8/3567, and h8/3567u. figure 19.5 shows memory maps of the h8/3577, h8/3567, and h8/3567u in writer mode. h'ff data should be specified for unused address areas in the on-chip prom. when programming with a prom programmer, limit the program address range to h'0000 to h'dfff for the h8/3577, h8/3567, and h8/3567u. specify h'ff data for addresses h'e000 and above. if these addresses are programmed by mistake, it may become impossible to program or verify the prom data. the same problem may occur if an attempt is made to program the chip in page programming mode. note that the prom versions are one-time programmable (otp) microcomputers, packaged in plastic packages, and cannot be reprogrammed.
section 19 rom rev. 3.00 mar 17, 2006 page 498 of 706 rej09b0303-0300 12 13 57 58 59 60 61 62 63 64 56 55 54 53 52 51 50 49 47 46 45 44 43 42 41 40 1 2 3 34 35 30 14, 39 20 19 15 21 16, 48 res nmi p3 p3 p3 p3 p3 p3 p3 p3 p1 p1 p1 p1 p1 p1 p1 p1 p2 p2 p2 p2 p2 p2 p2 p2 p4 0 p4 1 p4 2 p6 p6 av cc v cc md 0 md 1 stby av ss v ss v pp ea eo eo eo eo eo eo eo eo ea ea ea ea ea ea ea ea ea oe ea ea ea ea ea ce ea ea pgm v v ss hn27c101 (32 pins) pin pin 1 26 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 2 3 31 32 16 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 3 4 9 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 cc h8/3577 eprom socket 10 11 12 13 14 16 15 4 5 49 50 51 52 53 54 55 56 48 47 46 45 44 43 42 41 39 38 37 36 35 34 33 32 57 58 59 26 27 22 6, 31 12 11 7 13 8, 40 dp-64s fp-64a note: all pins not listed in this figure should be left open. legend: v pp : eo 7 to eo 0 : ea 16 to ea 0 : oe : ce : pgm : programming power supply (12.5 v) data input/output address input output enable chip enable program enable figure 19.2 socket adapter pin assignments (h8/3577)
section 19 rom rev. 3.00 mar 17, 2006 page 499 of 706 rej09b0303-0300 7 8 21 28 27 26 22 23 24 25 37 36 35 34 33 31 30 29 40 41 42 4 16 17 18 2 1 19 3 5 6 20 9, 10 14 11 15, 32 res nmi p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 p1 p1 p1 p1 p1 p1 p1 p1 p4 3 p4 4 p4 5 p4 6 p7 0 p7 1 p7 2 p4 1 p4 0 p7 3 p4 2 p4 7 p5 2 av cc v cc test stby v ss (/av ss ) v pp ea eo eo eo eo eo eo eo eo ea ea ea ea ea ea ea ea ea oe ea ea ea ea ea ce ea ea pgm v v ss hn27c101 (32 pins) 1 26 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 2 3 31 32 16 0 1 2 3 4 5 6 7 9 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 cc h8/3567 eprom socket 10 11 12 13 14 16 15 2 3 16 24 23 22 18 19 20 21 33 32 31 30 29 27 26 25 36 37 38 43 11 12 13 41 40 14 42 44 1 15 4, 5 9 6 10, 28 dp-42s fp-44a pin pin note: all pins not listed in this figure should be left open. legend: v pp : eo 7 to eo 0 : ea 16 to ea 0 : oe : ce : pgm : programming power supply (12.5 v) data input/output address input output enable chip enable program enable figure 19.3 socket adapter pin assignments (h8/3567)
section 19 rom rev. 3.00 mar 17, 2006 page 500 of 706 rej09b0303-0300 7 8 43 50 49 48 44 45 46 47 59 58 57 56 55 53 52 51 62 63 64 4 16 17 18 2 1 19 3 5 6 20 21 9, 10 14 11 32 15, 54 res nmi p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 p1 p1 p1 p1 p1 p1 p1 p1 p4 3 p4 4 p4 5 p4 6 p7 0 p7 1 p7 2 p4 1 p4 0 p7 3 p4 2 p4 7 p5 2 av cc drv cc v cc test stby drv ss v ss (/av ss ) v pp ea eo eo eo eo eo eo eo eo ea ea ea ea ea ea ea ea ea oe ea ea ea ea ea ce ea ea pgm v v ss hn27c101 (32 pins) 1 26 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 2 3 31 32 16 0 1 2 3 4 5 6 7 9 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 cc h8/3567u eprom socket 10 11 12 13 14 16 15 63 64 35 42 41 40 36 37 38 39 51 50 49 48 47 45 44 43 54 55 56 60 8 9 10 58 57 11 59 61 62 12 13 1, 2 6 3 24 7, 46 dp-64s fp-64a pin pin note: all pins not listed in this figure should be left open. legend: v pp : eo 7 to eo 0 : ea 16 to ea 0 : oe : ce : pgm : programming power supply (12.5 v) data input/output address input output enable chip enable program enable figure 19.4 socket adapter pin assignments (h8/3567u)
section 19 rom rev. 3.00 mar 17, 2006 page 501 of 706 rej09b0303-0300 h'dfff h'dfff undetermined value output * h'1ffff address in writer mode address in mcu mode h'0000 h'0000 on-chip prom note: * if this address area is read in writer mode, the output data is not guaranteed. figure 19.5 memory map in writer mode
section 19 rom rev. 3.00 mar 17, 2006 page 502 of 706 rej09b0303-0300 19.4 prom programming the write, verify, and other sub-modes of the writer mode are selected as shown in table 19.3. table 19.3 selection of sub-modes in writer mode sub-mode ce ce ce ce oe oe oe oe pgm pgm pgm pgm v pp v cc eo 7 to eo 0 ea 16 to ea 0 write low high low v pp v cc data input address input verify low low high v pp v cc data output address input programming inhibited low low high high low high low high low high low high v pp v cc high impedance address input the h8/3577, h8/3567, and h8/3567u prom have the same standard read/write specifications as the hn27c101 eprom. page programming is not supported, however, so do not select page programming mode. prom programmers that provide only page programming cannot be used. when selecting a prom programmer, check that it supports a byte-at-a-time high-speed programming mode. be sure to set the address range to h'0000 to h'dfff for the h8/3577, h8/3567, and h8/3567u. 19.4.1 programming and verification an efficient, high-speed programming procedure can be used to program and verify prom data. this procedure programs data quickly without subjecting the chip to voltage stress and without sacrificing data reliability. it leaves the data undefined in unused addresses. figure 19.6 shows the basic high-speed programming flowchart. tables 19.4 and 19.5 list the electrical characteristics of the chip in writer mode. figure 19.7 shows a program/verify timing chart.
section 19 rom rev. 3.00 mar 17, 2006 page 503 of 706 rej09b0303-0300 start set program/verify mode v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v address = 0 verify ok? program t opw = 0.2n ms last address? set read mode v cc = 5.0 v 0.25 v, v pp = v cc read all addresses end error n < 25? address + 1 address no yes no yes no no go program t pw = 0.2 ms 5% n = 0 n + 1 n yes go figure 19.6 high-speed programming flowchart
section 19 rom rev. 3.00 mar 17, 2006 page 504 of 706 rej09b0303-0300 table 19.4 dc characteristics when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, ta = 25c 5c item symbol min typ max unit test conditions input high voltage eo 7 ?eo 0 , ea 16 ?ea 0 , oe , ce , pgm v ih 2.4 ? v cc + 0.3 v input low voltage eo 7 ?eo 0 , ea 16 ?ea 0 , oe , ce , pgm v il ?0.3 ? 0.8 v output high voltage eo 7 ?eo 0 v oh 2.4 ? ? v i oh = ?200 a output low voltage eo 7 ?eo 0 v ol ? ? 0.45 v i ol = 1.6 ma input leakage current eo 7 ?eo 0 , ea 16 ?ea 0 , oe , ce , pgm |i li |??2 av in = 5.25 v/0.5 v v cc current i cc ??40 ma v pp current i pp ??40 ma
section 19 rom rev. 3.00 mar 17, 2006 page 505 of 706 rej09b0303-0300 table 19.5 ac characteristics when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, ta = 25c 5c item symbol min typ max unit test conditions address setup time t as 2 ? ? s see figure 19.7 * oe setup time t oes 2??s data setup time t ds 2??s address hold time t ah 0??s data hold time t dh 2??s data output disable time t df ? ? 130 ns v pp setup time t vps 2??s program pulse width t pw 0.19 0.20 0.21 ms oe pulse width for overwrite-programming t opw 0.19 ? 5.25 ms v cc setup time t vcs 2??s ce setup time t ces 2??s data output delay time t oe 0 ? 150 ns note: * input pulse level: 0.8 v to 2.2 v input rise/fall time 20 ns timing reference levels: input?1.0 v, 2.0 v; output?0.8 v, 2.0 v
section 19 rom rev. 3.00 mar 17, 2006 page 506 of 706 rej09b0303-0300 address data v pp v cc ce pgm oe v pp v cc v cc v cc write verify input data output data t as t ds t vps t vcs t ces t pw t opw t dh t oes t oe t df t ah + 1 figure 19.7 prom program/verify timing
section 19 rom rev. 3.00 mar 17, 2006 page 507 of 706 rej09b0303-0300 19.4.2 notes on programming (1) program with the specified voltages and timing. the programming voltage (v pp ) is 12.5 v. caution: applied voltages in excess of the specified values can permanently destroy the chip. be particularly careful about the prom programmer?s overshoot characteristics. if the prom programmer is set to hn27c101 specifications, v pp will be 12.5 v. (2) before writing data, check that the socket adapter and chip are correctly mounted in the prom writer. overcurrent damage to the chip can result if the index marks on the prom programmer, socket adapter, and chip are not correctly aligned. (3) don?t touch the socket adapter or chip while writing. touching either of these can cause contact faults and write errors. (4) page programming is not supported. do not select page programming mode. (5) the prom size is 56 kbytes. set the address range to h'0000 to h'dfff for the h8/3577, h8/3567, and h8/3567u. when programming, specify h'ff data for unused address areas (h'e000 to h'1ffff).
section 19 rom rev. 3.00 mar 17, 2006 page 508 of 706 rej09b0303-0300 19.4.3 reliability of programmed data an effective way to assure the data holding characteristics of the programmed chips is to bake them at 150c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 19.8 shows the recommended screening procedure. write and verify program read and check program mount bake with power off 125 to 150 c, 24 to 48hr figure 19.8 recommended screening procedure if a group of write errors occurs while the same prom programmer is in use, stop programming and check the prom programmer and socket adapter for defects. please inform renesas technology of any abnormal conditions noted during programming or in screening of program data after high-temperature baking.
section 20 clock pulse generator rev. 3.00 mar 17, 2006 page 509 of 706 rej09b0303-0300 section 20 clock pulse generator 20.1 overview the h8/3577 group and h8/3567 group have an on-chip clock pulse generator (cpg) that generates the system clock ( ), the bus master clock, and internal clocks. the clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit. 20.1.1 block diagram figure 20.1 shows a block diagram of the clock pulse generator. extal xtal oscillator duty adjustment circuit medium-speed clock divider system clock to pin internal clock to supporting modules bus master cloc k to cpu, dtc /2 to /32 bus master clock selection circuit clock selection circuit figure 20.1 block diagram of clock pulse generator 20.1.2 register configuration the clock pulse generator is controlled by the standby control register (sbycr). table 20.1 shows the register configuration. table 20.1 cpg registers name abbreviation r/w initial value address standby control register sbycr r/w h'00 h'ff84
section 20 clock pulse generator rev. 3.00 mar 17, 2006 page 510 of 706 rej09b0303-0300 20.2 register descriptions 20.2.1 standby control register (sbycr) bit 76543210 ssby sts2 sts1 sts0 ? sck2 sck1 sck0 initial value00000000 read/write r/w r/w r/w r/w ? r/w r/w r/w sbycr is an 8-bit readable/writable register that performs power-down mode control. only bits 0 to 2 are described here. for a description of the other bits, see section 21.2.1, standby control register (sbycr). sbycr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 2 to 0?system clock select 2 to 0 (sck2 to sck0): these bits select the bus master clock for high-speed mode and medium-speed mode. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master is in high-speed mode (initial value) 1 medium-speed clock is /2 1 0 medium-speed clock is /4 1 medium-speed clock is /8 1 0 0 medium-speed clock is /16 1 medium-speed clock is /32 1? ?
section 20 clock pulse generator rev. 3.00 mar 17, 2006 page 511 of 706 rej09b0303-0300 20.3 oscillator clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 20.3.1 connecting a crystal resonator circuit configuration: a crystal resonator can be connected as shown in the example in figure 20.2. select the damping resistance r d according to table 20.2. an at-cut parallel-resonance crystal should be used. extal xtal r d c l2 c l1 c l1 = c l2 = 10 to 22 pf figure 20.2 connection of crystal resonator (example) table 20.2 damping resistance value frequency (mhz)24810121620 r d ( ? ) 1 k5002000000 crystal resonator: figure 20.3 shows the equivalent circuit of the crystal resonator. use a crystal resonator that has the characteristics shown in table 20.3 and the same frequency as the system clock ( ). xtal c l at-cut parallel-resonance type extal c 0 lr s figure 20.3 crystal resonator equivalent circuit
section 20 clock pulse generator rev. 3.00 mar 17, 2006 page 512 of 706 rej09b0303-0300 table 20.3 crystal resonator parameters frequency (mhz)24810121620 r s max ( ? ) 500 120 80 70 60 50 40 c 0 max (pf) 7777777 note on board design: when a crystal resonator is connected, the following points should be noted. other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. see figure 20.4. when designing the board, place the crystal resonator and its load capacitors as close as possible to the xtal and extal pins. c l2 signal a signal b c l1 h8/3577 group or h8/3567 group chip xtal extal avoid figure 20.4 example of incorrect board design
section 20 clock pulse generator rev. 3.00 mar 17, 2006 page 513 of 706 rej09b0303-0300 20.3.2 external clock input circuit configuration: an external clock signal can be input as shown in the examples in figure 20.5. if the xtal pin is left open, make sure that stray capacitance is no more than 10 pf. in example (b), make sure that the external clock is held high in standby mode. extal xtal external clock input open (a) xtal pin left open extal xtal external clock input (b) complementary clock input at xtal pin figure 20.5 external clock input (examples) external clock: the external clock signal should have the same frequency as the system clock ( ). table 20.4 and figure 20.6 show the input conditions for the external clock.
section 20 clock pulse generator rev. 3.00 mar 17, 2006 page 514 of 706 rej09b0303-0300 table 20.4 external clock input conditions v cc = 5.0 v 10% item symbol min max unit test conditions external clock input low pulse width t exl 20 ? ns figure 20.6 external clock input high pulse width t exh 20 ? ns external clock rise time t exr ? 5ns external clock fall time t exf ? 5ns clock low pulse width t cl 0.4 0.6 t cyc 5 mhz figure 22.4 80 ? ns < 5 mhz clock high pulse width t ch 0.4 0.6 t cyc 5 mhz 80 ? ns < 5 mhz t exh t exl t exr t exf v cc 0.5 extal figure 20.6 external clock input timing table 20.5 shows the external clock output settling delay time, and figure 20.7 shows the external clock output settling delay timing. the oscillator and duty adjustment circuit have a function for adjusting the waveform of the external clock input at the extal pin. when the prescribed clock signal is input at the extal pin, internal clock signal output is fixed after the elapse of the external clock output settling delay time (t dext ). as the clock signal output is not fixed during the t dext period, the reset signal should be driven low to maintain the reset state.
section 20 clock pulse generator rev. 3.00 mar 17, 2006 page 515 of 706 rej09b0303-0300 table 20.5 external clock output settling delay time conditions: v cc = 4.5 v to 5.5 v, av cc = 4.5 v to 5.5 v, v ss = av ss = 0 v item symbol min max unit notes external clock output settling delay time t dext * 500 ? s figure 20.7 note: * t dext includes a 10t cyc res pulse width (t resw ). t dext * res (internal or external) extal stby v cc 4.5 v v ih note: * t dext includes a res pulse width (t resw ). figure 20.7 external clock output settling delay timing
section 20 clock pulse generator rev. 3.00 mar 17, 2006 page 516 of 706 rej09b0303-0300 20.4 duty adjustment circuit when the oscillator frequency is 5 mhz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock ( ). 20.5 medium-speed clock divider the medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32 clocks. 20.6 bus master clock selection circuit the bus master clock selection circuit selects the system clock ( ) or one of the medium-speed clocks ( /2, /4, /8, /16, or /32) to be supplied to the bus master, according to the settings of bits sck2 to sck0 in sbycr. 20.7 universal clock pulse generator [h8/3567 group version with on-chip usb] the h8/3567 group version with an on-chip usb has a usb clock pulse generator (ucpg) that generates the 48 mhz usb clock (clk48) from an 8, 12, 16, or 20 mhz input clock. the input clock can be selected from (1) the 12 mhz crystal oscillator or (2) the system clock (only when the system clock is 8, 12, 16, or 20 mhz). the usb clock pulse generator consists of an oscillator, clock selection circuit, and frequency division/multiplication circuit. 20.7.1 block diagram figure 20.8 shows a block diagram of the usb clock pulse generator. oscillator clock selection circuit frequency division/ multiplication circuit extal12 xtal12 (system clock) 12 mhz 48 mhz to usb figure 20.8 block diagram of usb clock pulse generator
section 20 clock pulse generator rev. 3.00 mar 17, 2006 page 517 of 706 rej09b0303-0300 20.7.2 registers table 20.6 usb clock pulse generator registers name abbreviation r/w initial value address usb control/status register 0 usbcsr0 r/w h'00 h'fdf5 usb control register usbcr r/w h'7f h'fdfd usb pll control register upllcr r/w h'01 h'fdfe usb control/status register 0 (usbcsr0) bit 76543210 dp5cnct dp4cnct dp3cnct dp2cnct ep0stop epivld ep0otc ckstop initial value00000000 read/write r r r r r/w r/w r/w r/w usbcsr0 contains flags (dpcnct) that indicate the usb hubs? downstream port connection status, and bits that control the operation of the usb function. only bit 0 is described here. for details of the other bits, see section 7.2.11, usb control/status register 0 (usbcsr0). usbcsr0 is initialized to h'00 by a system reset, and bits 3 to 0 are also cleared to 0 by a function soft reset. bit 0?clock stop (ckstop): controls the usb function operating clock. when the usb function is placed in the suspend state due to a bus idle condition, this bit should be set to 1 after the necessary processing is completed. the clock supply to the usb function is then stopped, reducing power consumption. when the ckstop bit is set to 1, writes to usb module registers are invalid. if these registers are read, the contents of the read data are not guaranteed, but there are no read-related status changes (such as decrementing of fvsr). if a bus idle condition of the specified duration or longer is detected, the suspend in interrupt flag is set, and when a change in the bus status is subsequently detected the suspend out interrupt flag is set. when the suspend out interrupt flag is set, the ckstop bit is simultaneously cleared to 0.
section 20 clock pulse generator rev. 3.00 mar 17, 2006 page 518 of 706 rej09b0303-0300 bit 0 ckstop description 0 clock is supplied to usb function (initial value) [clearing conditions] ? system reset ? function soft reset ? suspend out interrupt flag setting 1 clock supply to usb function is stopped [setting condition] when 1 is written to ckstop after reading ckstop = 0 in the function suspend state. usb control register (usbcr) bit 76543210 fadsel fonly fncstp uifrst hpllrst hsrst fpllrst fsrst initial value01111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w usbcr contains bits (fadsel, fonly, fncstp) that control usb function and usb hub internal connection, and reset control bits for sequential enabling of the operation of each part according to the procedure in usb module initialization. only bits 3 and 1 are described here. for details of the other bits, see section 7.2.18, usb control register (usbcr). usbcr is initialized to h'7f by a system reset [in an h8/3567 reset (by res input or the watchdog timer), and in hardware standby mode]. it is not initialized in software standby mode. bit 3?hub block pll soft reset (hpllrst): resets the usb bus clock synchronization circuit (dpll) in the hub. when hpllrst is set to 1, the dpll circuit in the usb hub block is reset, and bus clock synchronous operation halts. hpllrst is cleared to 0 after pll operation stabilizes.
section 20 clock pulse generator rev. 3.00 mar 17, 2006 page 519 of 706 rej09b0303-0300 bit 3 hpllrst description 0 usb hub block dpll is placed in operational state 1 usb hub block dpll is placed in reset state (initial value) bit 1?function block pll soft reset (fpllrst): resets the usb bus clock synchronization circuit (dpll) in the usb function block. when fpllrst is set to 1, the dpll circuit in the usb function block is reset, and bus clock synchronous operation halts. fpllrst is cleared to 0 after pll operation stabilizes. bit 1 fpllrst description 0 usb function block dpll is placed in operational state 1 usb function block dpll is placed in reset state (initial value) usb pll control register (upllcr) bit 76543210 ??? cksel2 cksel1 cksel0 pfsel1 pfsel0 initial value00000001 read/write r r r r/w r/w r/w r/w r/w upllcr contains bits that control the method of generating the usb function and usb hub operating clock. upllcr is initialized to h'01 by a system reset [in an h8/3567 reset (by res input or the watchdog timer), and in hardware standby mode]. it is not initialized in software standby mode. bits 4 to 2?clock source select 2 to 0 (cksel2 to cksel0): these bits select the source of the clock supplied to the usb operating clock generator (pll). cksel0 selects either the usb clock pulse generator (xtal12) or the system clock pulse generator (xtatl) as the clock source. the usb clock pulse generator starts operating when it is selected as a clock source. it operates with cksel2 = 1, cksel0 = 1. when cksel2 = 1 and cksel1 = 1, the pll operates.
section 20 clock pulse generator rev. 3.00 mar 17, 2006 page 520 of 706 rej09b0303-0300 when cksel1 is cleared to 0, a clock is not input to the pll, and pll operation halts. the 48 mhz signal from the usb clock pulse generator can be input directly as the usb operating clock. when cksel2 is cleared to 0, a clock is not input to the pll, and pll operation halts. bit 4 bit 3 bit 2 cksel2 cksel1 cksel0 description 0 0 0 pll operation halted, clock input halted (initial value) ?? pll operation halted, clock input halted 1 0 0 setting prohibited 1 pll operation halted usb clock pulse generator (xtal12: 48 mhz) used directly instead of pll output 1 0 pll operates with system clock pulse generator (xtal) as clock source 1 pll operates with usb clock pulse generator (xtal12) as clock source bits 1 and 0?pll frequency select 1 and 0 (pfsel1, pfsel0): these bits select the frequency of the clock supplied to the usb operating clock generator (pll). the pll generates the 48 mhz usb operating clock using the frequency selected with these bits as the clock source frequency. bit 1 bit 0 pfsel1 pfsel0 description 0 0 pll input clock is 8 mhz 1 pll input clock is 12 mhz (initial value) 1 0 pll input clock is 16 mhz 1 pll input clock is 20 mhz
section 21 power-down state rev. 3.00 mar 17, 2006 page 521 of 706 rej09b0303-0300 section 21 power-down state 21.1 overview in addition to the normal program execution state, the h8/3577 group and h8/3567 group have a power-down state in which operation of the cpu and oscillator is halted and power dissipation is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip supporting modules, and so on. the operating modes are as follows: 1. high-speed mode 2. medium-speed mode 3. sleep mode 4. module stop mode 5. software standby mode 6. hardware standby mode of these, 2 to 6 are power-down modes. sleep mode is a cpu mode, medium-speed mode is a cpu operating clock state, and module stop mode is an on-chip supporting module mode. certain combinations of these modes can be set. after a reset, the mcu is in high-speed mode and module stop mode. table 21.1 shows the internal chip states in each mode, and table 21.2 shows the conditions for transition to the various modes. figure 21.1 shows a mode transition diagram.
section 21 power-down state rev. 3.00 mar 17, 2006 page 522 of 706 rej09b0303-0300 table 21.1 h8/3577 group and h8/3567 group internal states in each mode function high- speed medium- speed sleep module stop software standby hardware standby system clock oscillator functioning functioning functioning functioning halted halted instructions functioning medium- speed halted functioning halted halted cpu operation registers functioning medium- speed retained functioning retained undefined nmi functioning functioning functioning functioning functioning halted irq0 irq1 external interrupts irq2 wdt0 functioning functioning functioning functioning halted (retained) halted (reset) on-chip supporting module operation tmr 0, tmr 1 functioning functioning functioning halted (retained) halted (reset) frt functioning/ halted (retained) tmrx, y timer connection iic0 iic1 sci0 functioning functioning functioning pwm halted (reset) halted (reset) pwmx a/d functioning/ halted (reset) ram functioning functioning functioning functioning retained retained i/o functioning functioning functioning functioning retained high impedance usb functioning functioning functioning functioning/ halted * functioning/ halted * halted (reset) note: ?halted (retained)? means that internal register values are retained. the internal state is ?operation suspended.? ?halted (reset)? means that internal register values and internal states are initialized. in module stop mode, only modules for which a stop setting has been made are halted (reset or retained). * functioning (usb hub part only) when the usb clock (xtal12, extal12) is selected as a usb operating clock, and halted (retained) when not selected.
section 21 power-down state rev. 3.00 mar 17, 2006 page 523 of 706 rej09b0303-0300 hardware standby mode stby pin = low notes: when a transition is made between modes by means of an interrupt, transition cannot be made on interrupt source generation alone. ensure that interrupt handling is performed after accepting the interrupt request. from any state except hardware standby mode, a transition to the reset state occurs whenever res goes low. from any state, a transition to hardware standby mode occurs when stby goes low. sleep mode ssby = 0 software standby mode ssby = 1 medium-speed mode high-speed mode reset state stby pin = high res pin = low res pin = high program execution state sck2 to sck0 0 sck2 to sck0 = 0 program-halted state sleep instruction any interrupt sleep instruction external interrupt * : transition after exception handling : power-down mode * nmi, irq0 to irq2 figure 21.1 mode transitions table 21.2 power-down mode transition conditions control bit states at time of transition state before transition ssby state after transition by sleep instruction state after return by interrupt high-speed/ medium-speed 0 sleep high-speed/ medium-speed 1 software standby high-speed/ medium-speed
section 21 power-down state rev. 3.00 mar 17, 2006 page 524 of 706 rej09b0303-0300 21.1.1 register configuration the power-down state is controlled by the sbycr and mstpcr registers. table 21.3 summarizes these registers. table 21.3 power-down state registers name abbreviation r/w initial value address standby control register sbycr r/w h'00 h'ff84 module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 21.2 register descriptions 21.2.1 standby control register (sbycr) bit 76543210 ssby sts2 sts1 sts0 ? sck2 sck1 sck0 initial value00000000 read/write r/w r/w r/w r/w ? r/w r/w r/w sbycr is an 8-bit readable/writable register that performs power-down mode control. sbycr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?software standby (ssby): determines the operating mode, in combination with other control bits, when a power-down mode transition is made by executing a sleep instruction. the ssby setting is not changed by a mode transition due to an interrupt, etc. bit 7 ssby description 0 transition to sleep mode after execution of sleep instruction in high-speed mode or medium-speed mode (initial value) 1 transition to software standby mode, after execution of sleep instruction in high- speed mode or medium-speed mode
section 21 power-down state rev. 3.00 mar 17, 2006 page 525 of 706 rej09b0303-0300 bits 6 to 4?standby timer select 2 to 0 (sts2 to sts0): these bits select the time the mcu waits for the clock to stabilize when software standby mode is cleared and a transition is made to high-speed mode or medium-speed mode by means of a specific interrupt or instruction. with crystal oscillation, refer to table 21.4 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation settling time). with an external clock, any selection can be made. bit 6 bit 5 bit 4 sts2 sts1 sts0 description 0 0 0 standby time = 8192 states (initial value ) 1 standby time = 16384 states 1 0 standby time = 32768 states 1 standby time = 65536 states 1 0 0 standby time = 131072 states 1 standby time = 262144 states 10reserved 1 standby time = 16 states bit 3?reserved: this bit cannot be modified and is always read as 0. bits 2 to 0?system clock select (sck2 to sck0): these bits select the clock for the bus master in high-speed mode and medium-speed mode. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master is in high-speed mode (initial value ) 1 medium-speed clock is /2 1 0 medium-speed clock is /4 1 medium-speed clock is /8 1 0 0 medium-speed clock is /16 1 medium-speed clock is /32 1 ??
section 21 power-down state rev. 3.00 mar 17, 2006 page 526 of 706 rej09b0303-0300 21.2.2 module stop control register (mstpcr) mstpcrh mstpcrl bit 7654321076543210 mstp 15 mstp 14 mstp 13 mstp 12 mstp 11 mstp 10 mstp 9 mstp 8 mstp 7 mstp 6 mstp 5 mstp 4 mstp 3 mstp 2 mstp 1 mstp 0 initial value 0011111111111111 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w mstpcr comprises two 8-bit readable/writable registers that perform module stop mode control. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstrcrh and mstpcrl bits 7 to 0?module stop (mstp 15 to mstp 0): these bits specify module stop mode. see table 21.3 for the method of selecting on-chip supporting modules. mstpcrh, mstpcrl bits 7 to 0 mstp15 to mstp0 description 0 module stop mode is cleared (initial value of mstp15, mstp14) 1 module stop mode is set (initial value of mstp13 to mstp0) 21.3 medium-speed mode when the sck2 to sck0 bits in sbycr are set to 1 in high-speed mode, the operating mode changes to medium-speed mode at the end of the bus cycle. in medium-speed mode, the cpu operates on the operating clock ( /2, /4, /8, /16, or /32) specified by the sck2 to sck0 bits. on-chip supporting modules other than the bus masters always operate on the high-speed clock ( ). in medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. for example, if /4 is selected as the operating clock, on-chip memory is accessed in 8 states, and internal i/o registers in 12 states. medium-speed mode is cleared by clearing all of bits sck2 to sck0 to 0. a transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
section 21 power-down state rev. 3.00 mar 17, 2006 page 527 of 706 rej09b0303-0300 if a sleep instruction is executed when the ssby bit in sbycr is cleared to 0, a transition is made to sleep mode. when sleep mode is cleared by an interrupt, medium-speed mode is restored. if a sleep instruction is executed when the ssby bit in sbycr is set to 1, a transition is made to software standby mode. when software standby mode is cleared by an external interrupt, medium-speed mode is restored. when the res pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. the same applies in the case of a reset caused by overflow of the watchdog timer. when the stby pin is driven low, a transition is made to hardware standby mode. figure 21.2 shows the timing for transition to and clearance of medium-speed mode. medium-speed mode , supporting module clock bus master clock internal address bus internal write signal sbycr sbycr figure 21.2 medium-speed mode transition and clearance timing
section 21 power-down state rev. 3.00 mar 17, 2006 page 528 of 706 rej09b0303-0300 21.4 sleep mode 21.4.1 sleep mode if a sleep instruction is executed when the ssby bit in sbycr is cleared to 0, the cpu enters sleep mode. in sleep mode, cpu operation stops but the contents of the cpu?s internal registers are retained. other supporting modules do not stop. 21.4.2 clearing sleep mode sleep mode is cleared by any interrupt, or with the res pin or stby pin. clearing with an interrupt: when an interrupt request signal is input, sleep mode is cleared and interrupt exception handling is started. sleep mode will not be cleared if interrupts are disabled, or if interrupts other than nmi have been masked by the cpu. clearing with the res res res res pin: when the res pin is driven low, the reset state is entered. when the res pin is driven high after the prescribed reset input period, the cpu begins reset exception handling. clearing with the stby stby stby stby pin: when the stby pin is driven low, a transition is made to hardware standby mode. 21.5 module stop mode 21.5.1 module stop mode module stop mode can be set for individual on-chip supporting modules. when the corresponding mstp bit in mstpcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. the cpu continues operating independently. table 21.4 shows mstp bits and the corresponding on-chip supporting modules. when the corresponding mstp bit is cleared to 0, module stop mode is cleared and the module starts operating again at the end of the bus cycle. in module stop mode, the internal states of modules other than the sci, a/d converter, 8-bit pwm module, and 14-bit pwm module, are retained. additionally, when the usb clock (xtal12, extal12) is selected as a usb operating clock, the usb module does not stop operating even when the mstp1 bit is set to 1. to stop the
section 21 power-down state rev. 3.00 mar 17, 2006 page 529 of 706 rej09b0303-0300 usb module, initialize upllcr to h'01 before setting the mstp1 bit to 1. also, it is recommended to initialize usbcr to h'7f to prepare for cancellation of the module stop state. after reset release, all modules other than the dtc are in module stop mode. when an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. table 21.4 mstp bits and corresponding on-chip supporting modules register bit module mstpcrh mstp15 * ? mstp14 * ? mstp13 16-bit free-running timer (frt) mstp12 8-bit timers (tmr 0 , tmr 1 ) mstp11 8-bit pwm timer (pwm), 14-bit pwm timer (pwmx) mstp10 * ? mstp9 a/d converter mstp8 8-bit timers (tmrx, tmry), timer connection mstpcrl mstp7 serial communication interface 0 (sci0) mstp6 * ? mstp5 * ? mstp4 i 2 c bus interface (iic) channel 0 mstp3 i 2 c bus interface (iic) channel 1 mstp2 * ? mstp1 universal serial bus interface (usb) mstp0 * ? note: * bits 15, 14, 10, 6, 5, 2, and 0 can be read or written to, must be set to 1. 21.5.2 usage note the mstp bit for modules not included on-chip must be set to 1.
section 21 power-down state rev. 3.00 mar 17, 2006 page 530 of 706 rej09b0303-0300 21.6 software standby mode 21.6.1 software standby mode if a sleep instruction is executed when the ssby bit in sbycr is set to 1, software standby mode is entered. in this mode, the cpu, on-chip supporting modules, and oscillator all stop. however, the contents of the cpu?s internal registers, ram data, and the states of on-chip supporting modules other than the sci, pwm, and pwmx, and of the i/o ports, are retained. * in this mode the oscillator stops, and therefore power dissipation is significantly reduced. note: * when the usb clock (xtal12, extal12) is selected as a usb operating clock, the usb module does not stop operating even under the software standby mode. to realize the power save state, initialize upllcr to h'01 and usbcr to h'7f. 21.6.2 clearing software standby mode software standby mode is cleared by an external interrupt (nmi pin, or pin irq 0 , irq 1 , or irq 2 ), or by means of the res pin or stby pin. clearing with an interrupt: when an nmi, irq0, irq1, or irq2 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits sts2 to sts0 in syscr, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. software standby mode cannot be cleared with an irq0, irq1, or irq2 interrupt if the corresponding enable bit has been cleared to 0 or has been masked by the cpu. clearing with the res res res res pin: when the res pin is driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks are supplied to the entire chip. note that the res pin must be held low until clock oscillation stabilizes. when the res pin goes high, the cpu begins reset exception handling. clearing with the stby stby stby stby pin: when the stby pin is driven low, a transition is made to hardware standby mode.
section 21 power-down state rev. 3.00 mar 17, 2006 page 531 of 706 rej09b0303-0300 21.6.3 setting oscillation settling time after clearing software standby mode bits sts2 to sts0 in sbycr should be set as described below. using a crystal oscillator: set bits sts2 to sts0 so that the standby time is at least 8 ms (the oscillation settling time). table 21.5 shows the standby times for different operating frequencies and settings of bits sts2 to sts0. table 21.5 oscillation settling time settings sts2 sts1 sts0 standby time 20 mhz 16 mhz 12 mhz 10 mhz 8 mhz 6 mhz 4 mhz 2 mhz unit 0 0 0 8192 states 0.41 0.51 0.65 0.8 1.0 1.3 2.0 4.1 ms 1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1 8.2 1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 8.2 16.4 1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 16.4 32.8 1 0 0 131072 states 6.6 8.2 10.9 13.1 16.4 21.8 32.8 65.5 1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 65.6 131.2 10reserved ???????? s 1 16 states 0.8 1.0 1.3 1.6 2.0 2.7 4.0 8.0 legend: : recommended time setting ? : don ? t care using an external clock: any value can be set. normally, use of the minimum time is recommended. 21.6.4 software standby mode application example figure 21.3 shows an example in which a transition is made to software standby mode at the falling edge on the nmi pin, and software standby mode is cleared at the rising edge on the nmi pin. in this example, an nmi interrupt is accepted with the nmieg bit in syscr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, causing a transition to software standby mode. software standby mode is then cleared at the rising edge on the nmi pin.
section 21 power-down state rev. 3.00 mar 17, 2006 page 532 of 706 rej09b0303-0300 oscillator nmi nmieg ssby nmi exception handling nmieg = 1 ssby = 1 sleep instruction software standby mode (power-down state) oscillation settling time t osc2 nmi exception handling figure 21.3 software standby mode application example 21.6.5 usage note in software standby mode, i/o port states are retained. therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. current dissipation increases while waiting for oscillation to settle.
section 21 power-down state rev. 3.00 mar 17, 2006 page 533 of 706 rej09b0303-0300 21.7 hardware standby mode 21.7.1 hardware standby mode when the stby pin is driven low, a transition is made to hardware standby mode from any mode. in hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. as long as the prescribed voltage is supplied, on-chip ram data is retained. i/o ports are set to the high-impedance state. in order to retain on-chip ram data, the rame bit in syscr should be cleared to 0 before driving the stby pin low. do not change the state of the mode pins (md 1 and md 0 , test ) while the chip is in hardware standby mode. hardware standby mode is cleared by means of the stby pin and the res pin. when the stby pin is driven high while the res pin is low, the reset state is set and clock oscillation is started. ensure that the res pin is held low until the clock oscillation settles (at least 8 ms?the oscillation settling time?when using a crystal oscillator). when the res pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state.
section 21 power-down state rev. 3.00 mar 17, 2006 page 534 of 706 rej09b0303-0300 21.7.2 hardware standby mode timing figure 21.4 shows an example of hardware standby mode timing. when the stby pin is driven low after the res pin has been driven low, a transition is made to hardware standby mode. hardware standby mode is cleared by driving the stby pin high, waiting for the oscillation settling time, then changing the res pin from low to high. oscillator res stby oscillation settling time reset exception handling figure 21.4 hardware standby mode timing
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 535 of 706 rej09b0303-0300 section 22 electrical characteristics 22.1 absolute maximum ratings table 22.1 lists the absolute maximum ratings. table 22.1 absolute maximum ratings item symbol value unit power supply voltage v cc ?0.3 to +7.0 v program voltage v pp ?0.3 to +13.5 v bus driver power supply voltage (h8/3567u group only) drv cc ?0.3 to +4.3 v input voltage (except port 7) v in ?0.3 to v cc + 0.3 v input voltage (port 7) v in ?0.3 to av cc + 0.3 v analog power supply voltage av cc ?0.3 to +7.0 v analog input voltage v an ?0.3 to av cc + 0.3 v operating temperature t opr ?20 to +75 c storage temperature t stg ?55 to +125 c caution: permanent damage to the chip may result if absolute maximum ratings are exceeded.
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 536 of 706 rej09b0303-0300 22.2 dc characteristics table 22.2 lists the dc characteristics. table 22.3 lists the permissible output currents. table 22.2 dc characteristics conditions: v cc = 5.0 v 10%, av cc * 1 = 5.0 v 10%, v ss = av ss * 1 = 0 v, t a = ?20 to +75c item symbol min typ max unit test conditions (1) v t ? 1.0 ? ? v v t + ??v cc 0.7 v schmitt trigger input voltage p6 7 to p6 0 * 2 , irq 2 to irq 0 * 3 v t + ? v t ? 0.4 ? ? v input high voltage res , stby , nmi, md 1 * 7 , md 0 * 7 , test * 8 (2) v ih v cc ? 0.7 ? v cc + 0.3 v extal v cc 0.7 ? v cc + 0.3 v port 7 2.0 ? av cc + 0.3 v input pins except (1) and (2) above 2.0 ? v cc + 0.3 v input low voltage res , stby , md 1 * 7 , md 0 * 7 , test * 8 (3) v il ?0.3 ? 0.5 v nmi, extal, input pins except (1) and (3) above ?0.3 ? 0.8 v v oh v cc ? 0.5 ? ? v i oh = ?200 a all output pins (except p4 7 , and p5 2 ) 3.5 ? ? v i oh = ?1 ma output high voltage p4 7 , p5 2 * 4 2.0 ? ? v i oh = ?200 a output low voltage all output pins v ol ??0.4 vi ol = 1.6 ma res ? i in ? ? ? 10.0 a v in = 0.5 to v cc ? 0.5 v input leakage current stby , nmi, md 1 * 7 , md0 * 7 , test * 8 ??1.0 a port 7 ? ? 1.0 a v in = 0.5 to av cc ? 0.5 v
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 537 of 706 rej09b0303-0300 item symbol min typ max unit test conditions three-state leakage current (off state) ports 1 to 6 ? i tsi ? ??1.0 av in = 0.5 to v cc ? 0.5 v input pull-up mos current ports 1 to 3 * 7 ?i p 30 ? 300 a v in = 0 v res (4) c in ? ? 80 pf nmi ? ? 50 pf input capacitance p5 2 , p4 7 , p2 4 * 7 , p2 3 * 7 , p1 7 , p1 6 , test * 8 ? ? 20 pf v in = 0 v f = 1 mhz t a = 25c input pins except (4) above ? ? 15 pf current dissipation * 5 normal operation (with on-chip usb) i cc ? 80 100 ma f = 20 mhz normal operation (other than the above) ?6080 ma sleep mode (with on-chip usb) ?6080 ma sleep mode (other than the above) ?4563 ma standby mode * 6 ?0.25.0 at a 50c ? ? 20.0 a 50c < t a during a/d conversion al cc ?1.53.0 ma analog power supply current idle ? 0.01 5.0 a av cc = 2.0 v to 5.5 v analog power supply voltage * 1 av cc 4.5 ? 5.5 v operating 2.0 ? 5.5 v idle/not used ram standby voltage v ram 2.0 ? ? v notes: 1. do not leave the av cc , and av ss pins open even if the a/d converter is not used. even if the a/d converter is not used, apply a value in the range 2.0 v to 5.5 v to av cc by connection to the power supply (v cc ), or some other method. 2. p6 7 to p6 0 include supporting module inputs multiplexed on those pins. 3. irq 2 includes the adtrg signal multiplexed on that pin.
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 538 of 706 rej09b0303-0300 4. p5 2 /sck 0 /scl 0 and p4 7 /sda 0 are nmos push-pull outputs. an external pull-up resistor is necessary to provide high-level output from scl 0 and sda 0 (ice = 1). p5 2 /sck 0 and p4 7 (ice = 0) high levels are driven by nmos. 5. current dissipation values are for v ih min = v cc ? 0.2 v and v il max = 0.2 v with all output pins unloaded and the on-chip pull-up moss in the off state. 6. the values are for v ram v cc < 4.5 v, v ih min = v cc 0.9, and v il max = 0.3 v. 7. in the h8/3577 8. in the h8/3567 table 22.3 permissible output currents conditions: v cc = 4.0 to 5.5 v, av cc = 4.5 to 5.5 v, v ss = av ss = 0 v, ta = ?20 to +75c item symbol min typ max unit permissible output low current (per pin) scl 1 , scl 0 , sda 1 , sda 0 i ol ??20ma other output pins ? ? 2 ma permissible output low current (total) total of all output pins, including the above i ol ? ? 120 ma permissible output high current (per pin) all output pins ?i oh ??2 ma permissible output high current (total) total of all output pins ?i oh ??40ma notes: 1. to protect chip reliability, do not exceed the output current values in table 22.3. 2. when driving a darlington pair or led, always insert a current-limiting resistor in the output line, as show in figure 22.1.
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 539 of 706 rej09b0303-0300 table 22.4 bus drive characteristics conditions: v cc = 4.5 to 5.5 v, v ss = 0 v, ta = ?20 to +75c applicable pins: scl1, scl0, sda1, sda0 (bus drive function selected) item symbol min typ max unit test conditions v t ? v cc 0.3 ? ? v schmitt trigger input voltage v t + ??v cc 0.7 v t + ? v t ? v cc 0.05 ? ? input high voltage v ih v cc 0.7 ? v cc + 0.5 v input low voltage v il ?0.5 ? v cc 0.3 v output low voltage v ol ??0.8vi ol = 16 ma ??0.5 i ol = 8 ma ??0.4 i ol = 3 ma input capacitance c in ? ? 20 pf v in = 0 v, f = 1 mhz, t a = 25c three-state leakage current (off state) | i tsi | ? ? 1.0 a v in = 0.5 to v cc ? 0.5 v scl, sda output fall time t of 20 + 0.1cb ? 250 ns 2 k ? h8/3577 group or h8/3567 group chip port darlington pair figure 22.1 darlington pair drive circuit (example)
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 540 of 706 rej09b0303-0300 22.3 ac characteristics figure 22.2 shows the test conditions for the ac characteristics. c chip output pin r h r l c = 30 pf: all ports r l = 2.4 k ? r h = 12 k ? i/o timing test levels low level: 0.8 v high level: 2.0 v (except p4 7 and p5 2 ) v cc figure 22.2 output load circuit
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 541 of 706 rej09b0303-0300 22.3.1 clock timing table 22.5 shows the clock timing. the clock timing specified here covers clock ( ) output and clock pulse generator (crystal) and external clock input (extal pin) oscillation settling times. for details of external clock input (extal pin) timing, see section 20, clock pulse generator. table 22.5 clock timing condition a: v cc = 5.0 v 10%, v ss = 0 v, = 2 mhz to maximum operating frequency, t a = ?20 to +75c condition a 20 mhz item symbol min max unit test conditions clock cycle time t cyc 50 500 ns figure 22.3 clock high pulse width t ch 17 ? ns clock low pulse width t cl 17 ? ns clock rise time t cr ? 8ns clock fall time t cf ? 8ns oscillation settling time at reset (crystal) t osc1 10 ? ms figure 22.4 figure 22.5 oscillation settling time in software standby (crystal) t osc2 8 ? ms external clock output stabilization delay time t dext 500 ? s t ch t cyc t cf t cl t cr figure 22.3 system clock timing
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 542 of 706 rej09b0303-0300 t osc1 t osc1 extal v cc stby res t dext t dext figure 22.4 oscillation settling timing nmi irqi (i = 0, 1, 2) t osc2 figure 22.5 oscillation setting timing (exiting software standby mode)
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 543 of 706 rej09b0303-0300 22.3.2 control signal timing table 22.6 shows the control signal timing. table 22.6 control signal timing condition a: v cc = 5.0 v 10%, v ss = 0 v, = 2 mhz to maximum operating frequency, t a = ?20 to +75c condition a 20 mhz item symbol min max unit test conditions res setup time t ress 200 ? ns figure 22.6 res pulse width t resw 20 ? t cyc nmi setup time (nmi) t nmis 150 ? ns figure 22.7 nmi hold time (nmi) t nmih 10 ? nmi pulse width (exiting software standby mode) t nmiw 200 ? ns irq setup time ( irq2 to irq0 )t irqs 150 ? ns irq hold time ( irq2 to irq0 )t irqh 10 ? ns irq pulse width ( irq2 to irq0 ) (exiting software standby mode) t irqw 200 ? ns t resw t ress t ress res figure 22.6 reset input timing
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 544 of 706 rej09b0303-0300 t irqs t nmis t nmih irq edge input nmi t irqs t irqh irq i (i = 2 to 0) irq level input t nmiw t irqw figure 22.7 interrupt input timing
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 545 of 706 rej09b0303-0300 22.3.3 timing of on-chip supporting modules tables 22.7 and 22.8 show the on-chip supporting module timing. table 22.7 timing of on-chip supporting modules condition a: v cc = 5.0 v 10%, v ss = 0 v, = 2 mhz to maximum operating frequency, t a = ?20 to +75c condition a 20 mhz item symbol min max unit test conditions i/o ports output data delay time t pwda , t pwdb ? 50 ns figure 22.8 (1) input data setup time t prsa , t prsb 30 ? figure 22.8 (2) input data hold time t prha , t prhb 30 ? frt timer output delay time t ftod ? 50 ns figure 22.9 timer input setup time t ftis 30 ? timer clock input setup time t ftcs 30 ? figure 22.10 single edge t ftcwh 1.5 ? t cyc timer clock pulse width both edges t ftcwl 2.5 ? tmr timer output delay time t tmod ? 50 ns figure 22.11 timer reset input setup time t tmrs 30 ? figure 22.13 timer clock input setup time t tmcs 30 ? figure 22.12 single edge t tmcwh 1.5 ? t cyc timer clock pulse width both edges t tmcwl 2.5 ? pwm, pwmx pulse output delay time t pwod ? 50 ns figure 22.14 sci asynchronous t scyc 4 ? t cyc figure 22.15 input clock cycle synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ? 1.5 t cyc input clock fall time t sckf ? 1.5 transmit data delay time (synchronous) t txd ? 50 ns figure 22.16 receive data setup time (synchronous) t rxs 50 ?
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 546 of 706 rej09b0303-0300 condition a 20 mhz item symbol min max unit test conditions sci receive data hold time (synchronous) t rxh 50 ? ns figure 22.16 a/d converter trigger input setup time t trgs 30 ? ns figure 22.17 ports 1 to 7 (read) t 2 t 1 t pwda t prha t prsa ports 1 to 6 (write) figure 22.8 (1) i/o port input/output timing ports c and d (read) t 2 t 1 t pwdb t prhb t prsb ports c and d (write) figure 22.8 (2) i/o port input/output timing (usb on-chip version)
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 547 of 706 rej09b0303-0300 t ftis t ftod ftoa, ftob ftia, ftib, ftic, ftid figure 22.9 frt input/output timing t ftcs ftci t ftcwh t ftcwl figure 22.10 frt clock input timing tmo 0 , tmo 1 tmox t tmod figure 22.11 8-bit timer output timing
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 548 of 706 rej09b0303-0300 tmci 0 , tmci 1 tmix, tmiy t tmcs t tmcs t tmcwh t tmcwl figure 22.12 8-bit timer clock input timing tmri 0 , tmri 1 tmix, tmiy t tmrs figure 22.13 8-bit timer reset input timing pw 7 to pw 0 * 1 pw 15 to pw 0 * 2 pwx 1 , pwx 0 t pwod notes: 1. in the h8/3577 2. in the h8/3567 figure 22.14 pwm, pwmx output timing sck 0 , sck 1 t sckw t sckr t sckf t scyc figure 22.15 sck clock input timing
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 549 of 706 rej09b0303-0300 txd 0 (transmit data) rxd 0 (receive data) sck 0 t rxs t rxh t txd figure 22.16 sci input/output timing (synchronous mode) adtrg t trgs figure 22.17 a/d converter external trigger input timing
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 550 of 706 rej09b0303-0300 table 22.8 i 2 c bus timing conditions: v cc = 4.5 v to 5.5 v, v ss = 0 v, ? 20 to +75 c item symbol min typ max unit test conditions notes scl clock cycle time t scl 12 ?? t cyc figure 22.18 scl clock high pulse width t sclh 3 ?? t cyc scl clock low pulse width t scll 5 ?? t cyc scl, sda input rise time t sr ?? 7.5 * t cyc scl, sda input fall time t sf ?? 300 ns scl, sda input spike pulse elimination time t sp ?? 1t cyc sda input bus free time t buf 5 ?? t cyc start condition input hold time t stah 3 ?? t cyc retransmission start condition input setup time t stas 3 ?? t cyc stop condition input setup time t stos 3 ?? t cyc data input setup time t sdas 0.5 ?? t cyc data input hold time t sdah 0 ?? ns scl, sda capacitive load c b ?? 400 pf note: * 17.5t cyc can be set according to the clock selected for use by the i 2 c module. for details, see section 16.4, usage notes.
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 551 of 706 rej09b0303-0300 sda 0 , sda 1 v il v ih t buf p * p * s * t stah t sclh t sr t scll t scl t sf t sdah sr * t sdas t stas t sp t stos note: * s, p, and sr indicate the following conditions. s: p: sr: start condition stop condition retransmission start condition scl 0 , scl 1 figure 22.18 i 2 c bus interface input/output timing
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 552 of 706 rej09b0303-0300 22.4 a/d conversion characteristics table 22.9 lists the a/d conversion characteristics. table 22.9 a/d conversion characteristics (an 7 to an 0 input * 1 : 134/266-state conversion) condition a: v cc = 5.0 v 10%, av cc = 4.5 v to 5.5 v v ss = av ss = 0 v * 2 , ? 20 to +75 c condition a 20 mhz item min typ max unit resolution 10 10 10 bits conversion time (single mode) * 5 ?? 6.7 s analog input capacitance ?? 20 pf permissible signal-source impedance ?? 10 * 3 k ? 5 * 4 nonlinearity error ?? 3.0 lsb offset error ?? 3.5 lsb full-scale error ?? 3.5 lsb quantization error ?? 0.5 lsb absolute accuracy 4.0 lsb notes: 1. in the h8/3577 (an 3 to an 0 in the h8/3567) 2. the voltage applied to the ann analog input pins during a/d conversion must be in the range av ss ann av cc (where n = 0 to 3). for the relationship between av cc /av ss and v cc /v ss , set av ss = v ss . the av cc and av ss pins must not be left open when the a/d converter is not used. 3. when conversion time 11. 17 s (cks = 1 and 12 mhz, or cks = 0) 4. when conversion time < 11. 17 s (cks = 1 and > 12 mhz) 5. value when using the maximum operating frequency.
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 553 of 706 rej09b0303-0300 22.5 usb function pin characteristics table 22.10 shows the usb function pin characteristics. table 22.10 dc characteristics conditions: v cc = 5.0 v 10%, drv cc = 3.3 v 0.3 v, drv ss = v ss = 0 v, ta = ? 20 c to +75 c pin functions: transceiver input/output (usd+, usd ? ? ? ? ? enp 2 to enp 5 , ocp 2 to ocp 5 , extal12, xtal12 item symbol min typ max unit test conditions differential input sensitivity v di 0.2 ?? v| (d+) ? (d ? ) | differential common mode range v cm 0.8 ? 2.5 v including v di ocp 2 to ocp 5 v t ? 1.0 ?? v schmitt trigger input voltages v t + ?? v cc 0.7 v v t + ? v t ? 0.4 ?? v input high * 1 voltage extal12 v ih v cc 0.7 ? v cc + 0.3 v port d 2.0 ? drv cc + 0.3 v other than the above 2.0 ? v cc + 0.3 v input low * 1 voltage extal12 v il ? 0.3 ? v cc 0.2 v other than the above ? 0.3 ? 0.8 v output high voltage transceiver v oh 2.8 ? 3.6 v rl = 15 k ? connected between pin and gnd port d drv cc ? 0.5 ?? vi oh = ? 200 a drv cc ? 1.0 ?? vi oh = ? 1 ma v cc ? 0.5 ?? vi oh = ? 200 a other than the above 3.5 ?? vi oh = ? 1 ma
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 554 of 706 rej09b0303-0300 item symbol min typ max unit test conditions output low voltage transceiver v ol ?? 0.3 v rl = 1.5 k ? connected between pin and power supply other than the above ?? 0.4 v i ol = 1.6 ma output resistance z drv 28 ? 44 ? input pin capacitance c in ?? 35 pf between pin and gnd three-state leakage current i lo ?? 1.0 a 0.5 v < v in < drv cc ? 0.5 v 0.5 v < v in < v cc ? 0.5 v * 2 normal operation di cc ? 510 ma drv cc current dissipation standby mode ? 0.2 5.0 a notes: 1. excluding transceiver input/output (usd + , usd ? , ds2d + , ds2d ? , ds3d + , ds3d ? , ds4d + , ds4d ? , ds5d + , ds5d ? ) 2. upper row applies to transceiver input/output and port d, and lower row to other pins.
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 555 of 706 rej09b0303-0300 table 22.11 ac characteristics conditions: v cc = 5.0 v 10%, drv cc = 3.3 v 0.3 v, drv ss = v ss = 0 v, ta = ? 20 c to +75 c pin functions: transceiver input/output (usd+, usd ? ? ? ? ? enp 2 to enp 5 , ocp 2 to ocp 5 , extal12, xtal12 item symbol min max unit figure notes transceiver full speed rise time t fr 4 20 ns figure 22.19 fall time t ff 420 differential signal time difference t frfm 90.0 111.11 % t fr /t ff transceiver low speed rise time t lr 75 300 ns figure 22.19 fall time t lf 75 300 differential signal time difference t lrfm 80.0 125 % t lr /t lf transceiver output signal crossing voltage v crs 1.3 2.0 v ports c and d output data delay time t pwdb ? 50 ns figure 22.8 (2) input data setup time t prsb 30 ? input data hold time t prhb 30 ? usb clock oscillation settling time (crystal) t oscu 10 ? ms t fr t lr v oh v ol t ff t lf figure 22.19 transceiver output timing
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 556 of 706 rej09b0303-0300 22.6 usage notes ztat version and mask rom version: the ztat and mask rom versions satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip rom, layout patterns, and so on. when system evaluation testing is carried out using the ztat version, the same evaluation testing should also be conducted for the mask rom version when changing over to that version. models with internal step-down circuit: h8/3577, h8/3567, and h8/3567u mask rom models (hd6433577, hd6433574, hd6433567, hd6433564-20, hd6433564-10, hd6433567u, and hd6433564u) incorporate an internal step-down circuit to lower the mcu ? s internal power supply voltage to the optimum level automatically. one or two (in-parallel) 0.47 f internal voltage stabilization capacitors must be connected between the internal step-down pin (v cl ) and the v ss pin. the method of connecting the external capacitor(s) is shown in figure 22.20. do not apply a voltage exceeding 3.6 v to the v cl pin. when switching from a ztat version with no internal step-down capability to a mask rom version with the step-down facility, the differences in the circuitry before and after the changeover must be taken into consideration when designing the board pattern.
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 557 of 706 rej09b0303-0300 v cl v ss v cc vcc power supply v ss external capacitor(s) for power supply stabilization model with internal step-down capability (mask rom version) 10 f bypass capacitor 0.01 f one or two (in-parallel) 0.47 f capacitors do not connect the v cc power supply to the v cl pin of a model with internal step-down capability. (connect the v cc power supply to other v cc pins as usual.) a power supply stabilization capacitor must be connected to the v cl pin. use one or two (in-parallel) 0.47 f laminated ceramic capacitors, placed close to the pin. models with internal step-down capability: hd6433577, hd6433574, hd6433567, hd6433564-20, hd6433564-10, hd6433567u, hd6433564u models with no internal step-down capability have a v cc pin (v cc power supply pin) in the pin position occupied by the v cl pin in internal step-down models. it is recommended that a bypass capacitor be connected to the power supply pins. (values are for reference.) models without internal step-down capability: hd6473577, hd6473567, hd6473567u model without internal step-down capability (ztat version) figure 22.20 method of connecting v cl capacitor(s) to mask rom model with internal step-down capability, and differences between models with and without internal step-down capability
section 22 electrical characteristics rev. 3.00 mar 17, 2006 page 558 of 706 rej09b0303-0300
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 559 of 706 rej09b0303-0300 appendix a cpu instruction set a.1 instruction set list operation notation rd8/16 general register (destination) (8 or 16 bits) rs8/16 general register (source) (8 or 16 bits) rn8/16 general register (8 or 16 bits) ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #xx:3/8/16 immediate data (3, 8, or 16 bits) d:8/16 displacement (8 or 16 bits) @aa:8/16 absolute address (8 or 16 bits) + addition ? subtraction multiplication division logical and logical or exclusive logical or move ? not (logical complement) condition code notation modified according to the instruction result * undetermined (unpredictable) 0 always cleared to 0 ? not affected by the instruction result
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 560 of 706 rej09b0303-0300 table a.1 instruction set mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @?rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states * ihnzvc condition code ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mov.b #xx:8, rd mov.b rs, rd mov.b @rs, rd mov.b @(d:16, rs), rd mov.b @rs+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b rs, @rd mov.b rs, @(d:16, rd) mov.b rs, @ ? rd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.w #xx:16, rd mov.w rs, rd mov.w @rs, rd mov.w @(d:16, rs), rd mov.w @rs+, rd mov.w @aa:16, rd mov.w rs, @rd mov.w rs, @(d:16, rd) mov.w rs, @ ? rd mov.w rs, @aa:16 pop rd push rs #xx:8 rd8 rs8 rd8 @rs16 rd8 @(d:16, rs16) rd8 @rs16 rd8 rs16+1 rs16 @aa:8 rd8 @aa:16 rd8 rs8 @rd16 rs8 @(d:16, rd16) rd16 ? 1 rd16 rs8 @rd16 rs8 @aa:8 rs8 @aa:16 #xx:16 rd16 rs16 rd16 @rs16 rd16 @(d:16, rs16) rd16 @rs16 rd16 rs16+2 rs16 @aa:16 rd16 rs16 @rd16 rs16 @(d:16, rd16) rd16 ? 2 rd16 rs16 @rd16 rs16 @aa:16 @sp rd16 sp+2 sp sp ? 2 sp rs16 @sp b b b b b b b b b b b b w w w w w w w w w w w w 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 4 6 6 4 6 4 6 6 4 6 4 2 4 6 6 6 4 6 6 6 6 6 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2 2
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 561 of 706 rej09b0303-0300 mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @ ? rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states * ihnzvc condition code movfpe @aa:16, rd movtpe rs, @aa:16 add.b #xx:8, rd add.b rs, rd add.w rs, rd addx.b #xx:8, rd addx.b rs, rd adds.w #1, rd adds.w #2, rd inc.b rd daa.b rd sub.b rs, rd sub.w rs, rd subx.b #xx:8, rd subx.b rs, rd subs.w #1, rd subs.w #2, rd dec.b rd das.b rd neg.b rd cmp.b #xx:8, rd cmp.b rs, rd cmp.w rs, rd mulxu.b rs, rd divxu.b rs, rd and.b #xx:8, rd and.b rs, rd b b b b w b b w w b b b w b b w w b b b b b w b b b b not supported not supported rd8+#xx:8 rd8 rd8+rs8 rd8 rd16+rs16 rd16 rd8+#xx:8 +c rd8 rd8+rs8 +c rd8 rd16+1 rd16 rd16+2 rd16 rd8+1 rd8 rd8 decimal adjust rd8 rd8 ? rs8 rd8 rd16 ? rs16 rd16 rd8 ? #xx:8 ? c rd8 rd8 ? rs8 ? c rd8 rd16 ? 1 rd16 rd16 ? 2 rd16 rd8 ? 1 rd8 rd8 decimal adjust rd8 0 ? rd8 rd8 rd8 ? #xx:8 rd8 ? rs8 rd16 ? rs16 rd8 rs8 rd16 rd16 rs8 rd16 (rdh: remainder, rdl: quotient) rd8 #xx:8 rd8 rd8 rs8 rd8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 14 14 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (1) ? ? ? ? (2) ? ? ? (2) ? ? ? ????? ????? ?? ? ? ? ** (3) ? ? ? ? ? ? ? (1) ? ? ? ? (2) ? ? ? ? (2) ? ? ? ? ????? ????? ?? ? ? ? ** ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (1) ? ? ? ? ? ? ? ? ? ? ? ? ? (6) ? (7) ? ? 0 0 ? ? ? ? ? ?
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 562 of 706 rej09b0303-0300 mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @ ? rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states * ihnzvc condition code or.b #xx:8, rd or.b rs, rd xor.b #xx:8, rd xor.b rs, rd not.b rd shal.b rd shar.b rd shll.b rd shlr.b rd rotxl.b rd rotxr.b rd rotl.b rd rotr.b rd rd8 #xx:8 rd8 rd8 rs8 rd8 rd8 #xx:8 rd8 rd8 rs8 rd8 rd8 rd8 b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b 7 b 0 0 c b 7 b 0 0 c c b 7 b 0 b 7 b 0 0c c b 7 b 0 c b 7 b 0 c b 7 b 0 c b 7 b 0
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 563 of 706 rej09b0303-0300 mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @ ? rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states * ihnzvc condition code ? bset #xx:3, rd bset #xx:3, @rd bset #xx:3, @aa:8 bset rn, rd bset rn, @rd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @rd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @rd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @rd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @rd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @rd btst #xx:3, @aa:8 btst rn, rd btst rn, @rd btst rn, @aa:8 (#xx:3 of rd8) 1 (#xx:3 of @rd16) 1 (#xx:3 of @aa:8) 1 (rn8 of rd8) 1 (rn8 of @rd16) 1 (rn8 of @aa:8) 1 (#xx:3 of rd8) 0 (#xx:3 of @rd16) 0 (#xx:3 of @aa:8) 0 (rn8 of rd8) 0 (rn8 of @rd16) 0 (rn8 of @aa:8) 0 (#xx:3 of rd8) (#xx:3 of rd8) (#xx:3 of @rd16) (#xx:3 of @rd16) (#xx:3 of @aa:8) (#xx:3 of @aa:8) (rn8 of rd8) (rn8 of rd8) (rn8 of @rd16) (rn8 of @rd16) (rn8 of @aa:8) (rn8 of @aa:8) (#xx:3 of rd8) z (#xx:3 of @rd16) z (#xx:3 of @aa:8) z (rn8 of rd8) z (rn8 of @rd16) z (rn8 of @aa:8) z b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 ? ? ? ? ?
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 564 of 706 rej09b0303-0300 mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @ ? rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states * ihnzvc condition code ? bld #xx:3, rd bld #xx:3, @rd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @rd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @rd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @rd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @rd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @rd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @rd bor #xx:3, @aa:8 bior #xx:3, rd bior #xx:3, @rd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @rd bxor #xx:3, @aa:8 bixor #xx:3, rd (#xx:3 of rd8) c (#xx:3 of @rd16) c (#xx:3 of @aa:8) c (#xx:3 of rd8) c (#xx:3 of @rd16) c (#xx:3 of @aa:8) c c (#xx:3 of rd8) c (#xx:3 of @rd16) c (#xx:3 of @aa:8) c (#xx:3 of rd8) c (#xx:3 of @rd16) c (#xx:3 of @aa:8) c (#xx:3 of rd8) c c (#xx:3 of @rd16) c c (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @rd16) c c (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @rd16) c c (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @rd16) c c (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @rd16) c c (#xx:3 of @aa:8) c c (#xx:3 of rd8) c b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 565 of 706 rej09b0303-0300 mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @ ? rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states * ihnzvc condition code ? bixor #xx:3, @rd bixor #xx:3, @aa:8 bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 blt d:8 bgt d:8 ble d:8 jmp @rn jmp @aa:16 jmp @@aa:8 bsr d:8 jsr @rn jsr @aa:16 c (#xx:3 of @rd16) c c (#xx:3 of @aa:8) c pc pc+d:8 pc pc+2 if condition is true then pc pc+d:8 else next; b b ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 2 2 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 6 6 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 6 8 6 6 8 c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n v = 0 n v = 1 z (n v) = 0 z (n v) = 1 pc rn16 pc aa:16 pc @aa:8 sp ? 2 sp pc @sp pc pc+d:8 sp ? 2 sp pc @sp pc rn16 sp ? 2 sp pc @sp pc aa:16 ? branching condition
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 566 of 706 rej09b0303-0300 mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @ ? rn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states * ihnzvc condition code jsr @@aa:8 rts rte sleep ldc #xx:8, ccr ldc rs, ccr stc ccr, rd andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop eepmov sp ? 2 sp pc @sp pc @aa:8 pc @sp sp+2 sp ccr @sp sp+2 sp pc @sp sp+2 sp transit to sleep mode. #xx:8 ccr rs8 ccr ccr rd8 ccr #xx:8 ccr ccr #xx:8 ccr ccr #xx:8 ccr pc pc+2 eepmov ? ? ? ? b b b b b b ? ? 2 ?????? 8 8 10 2 2 2 2 2 2 2 2 (5) 2 ? ? 2 ? ? ? ? 2 ?????? ? ? 2 ? ? ? ? ? ? 2 ? ? ? ? 2 ?????? ? ? 2 ? ? ? ? ? ? 2 ? ? ? ? ? ? 2 these cannot be used in this lsi. ? ? ? ? 2 ?????? ?????? notes: * the number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. for other cases, see section a.3, number of instruction execution states. (1) set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) if the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) set to 1 if decimal adjustment produces a carry; otherwise cleared to 0. (5) these instructions are not supported by the h8/3577 group and h8/3567 group. (6) set to 1 if the divisor is negative; otherwise cleared to 0. (7) set to 1 if the divisor is 0; otherwise cleared to 0.
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 567 of 706 rej09b0303-0300 a.2 operation code map table a.2 is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 568 of 706 rej09b0303-0300 table a.2 operation code map high low 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra * 2 mulxu bset shll shal sleep brn * 2 divxu bnot shlr shar stc bhi bclr rotxl rotl ldc bls bts rotxr rotr orc or bcc * 2 rts xorc xor bcs * 2 bsr bor bior bxor bixor band biand andc and bne rte ldc beq not neg bld bild bst bist add sub bvc bvs mov inc dec bpl jmp adds subs bmi eepmov mov cmp bge blt addx subx bgt jsr daa das ble mov add addx cmp subx or xor and mov mov * 1 notes: 1. 2. bit manipulation instructions the movfpe and movtpe instructions are identical to mov instructions in the first byte and first bit of the second byte (bits 1 5 to 7 of the instruction word). the push and pop instructions are identical in machine language to mov instructions. the bt, bf, bhs, and blo instructions are identical in machine language to bra, brn, bcc, and bcs, respectively.
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 569 of 706 rej09b0303-0300 a.3 number of states required for execution the tables below can be used to calculate the number of states required for instruction execution. table a.3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). table a.4 indicates the number of cycles of each type occurring in each instruction. the total number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: mode 1, stack located in external memory, 1 wait state inserted in external memory access. 1. bset #0, @ffc7 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 8, s l = 3 number of states required for execution: 2 8 + 2 3 =22 2. jsr @@30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 8 number of states required for execution: 2 8 + 1 8 + 1 8 = 32 table a.3 number of states taken by each cycle in instruction execution access location execution status (instruction cycle) on-chip memory on-chip reg. field external memory instruction fetch s i 2 6 6 + 2m branch address read s j stack operation s k byte data access s l 33 + m word data access s m 66 + 2m internal operation s n 11 1 note: m: number of wait states inserted in access to external device.
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 570 of 706 rej09b0303-0300 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd 1 add.b rs, rd 1 add.w rs, rd 1 adds adds.w #1/2, rd 1 addx addx.b #xx:8, rd 1 addx.b rs, rd 1 and and.b #xx:8, rd 1 and.b rs, rd 1 andc andc #xx:8, ccr 1 band band #xx:3, rd 1 band #xx:3, @rd 2 1 band #xx:3, @aa:8 2 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bclr bclr #xx:3, rd 1 bclr #xx:3, @rd 2 2 bclr #xx:3, @aa:8 2 2 bclr rn, rd 1 bclr rn, @rd 2 2 bclr rn, @aa:8 2 2
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 571 of 706 rej09b0303-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n biand biand #xx:3, rd 1 biand #xx:3, @rd 2 1 biand #xx:3, @aa:8 2 1 bild bild #xx:3, rd 1 bild #xx:3, @rd 2 1 bild #xx:3, @aa:8 2 1 bior bior #xx:3, rd 1 bior #xx:3, @rd 2 1 bior #xx:3, @aa:8 2 1 bist bist #xx:3, rd 1 bist #xx:3, @rd 2 2 bist #xx:3, @aa:8 2 2 bixor bixor #xx:3, rd 1 bixor #xx:3, @rd 2 1 bixor #xx:3, @aa:8 2 1 bld bld #xx:3, rd 1 bld #xx:3, @rd 2 1 bld #xx:3, @aa:8 2 1 bnot bnot #xx:3, rd 1 bnot #xx:3, @rd 2 2 bnot #xx:3, @aa:8 2 2 bnot rn, rd 1 bnot rn, @rd 2 2 bnot rn, @aa:8 2 2 bor bor #xx:3, rd 1 bor #xx:3, @rd 2 1 bor #xx:3, @aa:8 2 1 bset bset #xx:3, rd 1 bset #xx:3, @rd 2 2 bset #xx:3, @aa:8 2 2 bset rn, rd 1 bset rn, @rd 2 2 bset rn, @aa:8 2 2
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 572 of 706 rej09b0303-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bsr bsr d:8 2 1 bst bst #xx:3, rd 1 bst #xx:3, @rd 2 2 bst #xx:3, @aa:8 2 2 btst btst #xx:3, rd 1 btst #xx:3, @rd 2 1 btst #xx:3, @aa:8 2 1 btst rn, rd 1 btst rn, @rd 2 1 btst rn, @aa:8 2 1 bxor bxor #xx:3, rd 1 bxor #xx:3, @rd 2 1 bxor #xx:3, @aa:8 2 1 cmp cmp.b #xx:8, rd 1 cmp.b rs, rd 1 cmp.w rs, rd 1 daa daa.b rd 1 das das.b rd 1 dec dec.b rd 1 divxu divxu.b rs, rd 1 12 eepmov eepmov this cannot be used in these h8/3577 group and h8/3567 group. inc inc.b rd 1 jmp jmp @rn 2 jmp @aa:16 2 2 jmp @@aa:8 2 1 2 jsr jsr @rn 2 1 jsr @aa:16 2 1 2 jsr @@aa:8 2 1 1 ldc ldc #xx:8, ccr 1 ldc rs, ccr 1
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 573 of 706 rej09b0303-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b #xx:8, rd 1 mov.b rs, rd 1 mov.b @rs, rd 1 1 mov.b @(d:16,rs), rd 21 mov.b @rs+, rd 1 1 2 mov.b @aa:8, rd 1 1 mov.b @aa:16, rd 2 1 mov.b rs, @rd 1 1 mov.b rs, @(d:16, rd) 21 mov.b rs, @ ? rd 1 1 2 mov.b rs, @aa:8 1 1 mov.b rs, @aa:16 2 1 mov.w #xx:16, rd 2 mov.w rs, rd 1 mov.w @rs, rd 1 1 mov.w @(d:16, rs), rd 21 mov.w @rs+, rd 1 1 2 mov.w @aa:16, rd 2 1 mov.w rs, @rd 1 1 mov.w rs, @(d:16, rd) 21 mov.w rs, @ ? rd 1 1 2 mov.w rs, @aa:16 2 1 movfpe movfpe @aa:16, rd not supported movtpe movtpe.rs, @aa:16 not supported mulxu mulxu.b rs, rd 1 12 neg neg.b rd 1 nop nop 1 not not.b rd 1
appendix a cpu instruction set rev. 3.00 mar 17, 2006 page 574 of 706 rej09b0303-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n or or.b #xx:8, rd 1 or.b rs, rd 1 orc orc #xx:8, ccr 1 pop pop rd 1 1 2 push push rd 1 1 2 rotl rotl.b rd 1 rotr rotr.b rd 1 rotxl rotxl.b rd 1 rotxr rotxr.b rd 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd 1 shar shar.b rd 1 shll shll.b rd 1 shlr shlr.b rd 1 sleep sleep 1 stc stc ccr, rd 1 sub sub.b rs, rd 1 sub.w rs, rd 1 subs subs.w #1/2, rd 1 subx subx.b #xx:8, rd 1 subx.b rs, rd 1 xor xor.b #xx:8, rd 1 xor.b rs, rd 1 xorc xorc #xx:8, ccr 1 note: all values left blank are zero.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 575 of 706 rej09b0303-0300 appendix b internal i/o registers b.1 addresses address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'fdc0 uprtcr ? ? dspsel2 dspsel1 dspsel0 pcnmd2 pcnmd1 pcnmd0 usb 8 h'fdc1 utestr0 h'fdc2 utestr1 h'fde1 epdr2 d7 d6 d5 d4 d3 d2 d1 d0 h'fde2fvsr2h??????n9n8 h'fde3 fvsr2l n7 n6 n5 n4 n3 n2 n1 n0 h'fde4 epszr1 ep1sz3 ep1sz2 ep1sz1 ep1sz0 ep2sz3 ep2sz2 ep2sz1 ep2sz0 h'fde5 epdr1 d7 d6 d5 d4 d3 d2 d1 d0 h'fde6fvsr1h??????n9n8 h'fde7 fvsr1l n7 n6 n5 n4 n3 n2 n1 n0 h'fde9epdr0od7d6d5d4d3d2d1d0 h'fdeafvsr0oh??????n9n8 h'fdebfvsr0oln7n6n5n4n3n2n1n0 h'fdedepdr0id7d6d5d4d3d2d1d0 h'fdeefvsr0ih??????n9n8 h'fdeffvsr0iln7n6n5n4n3n2n1n0 h'fdf0 ptter ? ? ? ? ep2te ep1te ep0ite ? h'fdf1 usbier ? ? brste sofe spnde tfe tse setupe h'fdf2 usbifr ts tf ? brstf soff spndof spndif setupf h'fdf3 tsfr ? ? ? ? ep2ts ep1ts ep0its ep0ots h'fdf4 tffr ? ? ? ? ep2tf ep1tf ep0itf ep0otf h'fdf5 usbcsr0 dp5cnct dp4cnct dp3cnct dp2cnce ep0stop epivld ep0otc ckstop h'fdf6 epstlr ? ? ? ? ep2stl ep1stl ? ep0stl h'fdf7 epdir ? ? ? ? ep2dir ep1dir ? ? h'fdf8 eprstr ? ? ? ? ep2rst ep1rst ep0irst ? h'fdf9devrsmr???????dvr h'fdfa intselr0 tselb epibs2 epibs1 epibs0 tselc epics2 epics1 epics0 h'fdfb intselr1 ? ? ? ? ? ? dtcbe dtcce h'fdfc hoccr ? ? pcsp ocdsp hoc5e hoc4e hoc3e hoc2e h'fdfd usbcr fadsel fonly fncstp uifrst hpllrst hsrst fpllrst fsrst h'fdfe upllcr ? ? ? cksel2 cksel1 cksel0 pfsel1 pfsel0 h'fdff utestr2 testa testb testc testd teste testf testg testh
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 576 of 706 rej09b0303-0300 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'fe4c pcodr pc 7 odr pc 6 odr pc 5 odr pc 4 odr pc 3 odr pc 2 odr pc 1 odr pc 0 odr ports 8 h'fe4d pdodr pd 7 odr pd 6 odr pd 5 odr pd 4 odr pd 3 odr pd 2 odr pd 1 odr pd 0 odr h'fe4e pcddr pc 7 ddr pc 6 ddr pc 5 ddr pc 4 ddr pc 3 ddr pc 2 ddr pc 1 ddr pc 0 ddr pcpin pc 7 pin pc 6 pin pc 5 pin pc 4 pin pc 3 pin pc 2 pin pc 1 pin pc 0 pin h'fe4f pdddr pd 7 ddr pd 6 ddr pd 5 ddr pd 4 ddr pd 3 ddr pd 2 ddr pd 1 ddr pd 0 ddr pdpin pd 7 pin pd 6 pin pd 5 pin pd 4 pin pd 3 pin pd 2 pin pd 1 pin pd 0 pin h'fee6 ddcswr swe sw ie if clr3 clr2 clr1 clr0 iic0 8 h'feebisr?????irq2firq1firq0f 8 h'feeciscrh???????? h'feed iscrl ? ? irq2scb irq2sca irq1scb irq1sca irq0scb irq0sca interrupt controller h'ff82 pcsr ? ? ? ? ? pwckb pwcka ? pwm 8 h'ff84 sbycr ssby sts2 sts1 sts0 ? sck2 sck1 sck0 system 8 h'ff86 mstpcrh mstp15 mstp14 mstp13 mstp12 mstp11 mstp10 mstp9 mstp8 h'ff87 mstpcrl mstp7 mstp6 mstp5 mstp4 mstp3 mstp2 mstp1 mstp0 h'ff88 iccr1 ice ieic mst trs acke bbsy iric scp iic1 8 h'ff89 icsr1 estp stop irtr aasx al aas adz ackb h'ff8e icdr1 icdr7 icdr6 icdr5 icdr4 icdr3 icdr2 icdr1 icdr0 sarx svax6 svax5 svax4 svax3 svax2 svax1 svax0 fsx h'ff8f icmr1 mls wait cks2 cks1 cks0 bc2 bc1 bc0 sar sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs h'ff90 tier iciae icibe icice icide ociae ocibe ovie ? frt 8 h'ff91 tcsr icfa icfb icfc icfd ocfa ocfb ovf cclra h'ff92 frch 16 h'ff93 frcl h'ff94 ocrah ocrbh h'ff95 ocral ocrbl h'ff96 tcr iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 h'ff97 tocr icrdms ocrams icrs ocrs oea oeb olvla olvlb h'ff98 icrah ocrarh h'ff99 icral ocrarl h'ff9a icrbh ocrafh
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 577 of 706 rej09b0303-0300 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'ff9b icrbl frt 16 ocrafl h'ff9c icrch ocrdmh h'ff9d icrcl ocrdml h'ff9e icrdh h'ff9f icrdl h'ffa0 dadrah da13 da12 da11 da10 da9 da8 da7 da6 pwmx 8 dacr test pwme ? ? oeb oea os cks h'ffa1 dadral da5 da4 da3 da2 da1 da0 cfs ? h'ffa6 dadrbh da13 da12 da11 da10 da9 da8 da7 da6 dacnth h'ffa7 dadrbl da5 da4 da3 da2 da1 da0 cfs regs dacntl ? regs h'ffa8 tcsr0 ovf wt/ it tme rsts rst/ nmi cks2 cks1 cks0 wdt0 16 tcnt0 (write) h'ffa9 tcnt0 (read) h'ffac p1pcr p1 7 pcr p1 6 pcr p1 5 pcr p1 4 pcr p1 3 pcr p1 2 pcr p1 1 pcr p1 0 pcr port 8 h'ffad p2pcr p2 7 pcr p2 6 pcr p2 5 pcr p2 4 pcr p2 3 pcr p2 2 pcr p2 1 pcr p2 0 pcr h'ffae p3pcr p3 7 pcr p3 6 pcr p3 5 pcr p3 4 pcr p3 3 pcr p3 2 pcr p3 1 pcr p3 0 pcr h'ffb0 p1ddr p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr h'ffb1 p2ddr p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr h'ffb2 p1dr p1 7 dr p1 6 dr p1 5 dr p1 4 dr p1 3 dr p1 2 dr p1 1 dr p1 0 dr h'ffb3 p2dr p2 7 dr p2 6 dr p2 5 dr p2 4 dr p2 3 dr p2 2 dr p2 1 dr p2 0 dr h'ffb4 p3ddr p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr h'ffb5 p4ddr p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr h'ffb6 p3dr p3 7 dr p3 6 dr p3 5 dr p3 4 dr p3 3 dr p3 2 dr p3 1 dr p3 0 dr h'ffb7 p4dr p4 7 dr p4 6 dr p4 5 dr p4 4 dr p4 3 dr p4 2 dr p4 1 dr p4 0 dr h'ffb8p5ddr?????p5 2 ddr p5 1 ddr p5 0 ddr h'ffb9 p6ddr p6 7 ddr p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr h'ffbap5dr?????p5 2 dr p5 1 dr p5 0 dr h'ffbb p6dr p6 7 dr p6 6 dr p6 5 dr p6 4 dr p6 3 dr p6 2 dr p6 1 dr p6 0 dr h'ffbe p7pin p7 7 pin p7 6 pin p7 5 pin p7 4 pin p7 3 pin p7 2 pin p7 1 pin p7 0 pin h'ffc2 ier ? ? ? ? ? irq2e irq1e irq0e interrupts 8
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 578 of 706 rej09b0303-0300 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'ffc3 stcr ? iicx1 iicx0 iice ? usbe icks1 icks0 system 8 h'ffc4 syscr cs2e iose intm1 intm0 xrst nmieg hie rame h'ffc5 mdcr expe ? ? ? ? ? mds1 mds0 h'ffc6 bcr icis1 icis0 brstrm brsts1 brsts0 ? ios1 ios0 h'ffc7 wscr rams ram0 abw ast wms1 wms0 wc1 wc0 h'ffc8 tcr0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 8 h'ffc9 tcr1 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 h'ffca tcsr0 cmfb cmfa ovf adte os3 os2 os1 os0 h'ffcb tcsr1 cmfb cmfa ovf ? os3 os2 os1 os0 tmr 0 , tmr 1 h'ffcc tcora0 16, 8 h'ffcd tcora1 h'ffce tcorb0 h'ffcf tcorb1 h'ffd0 tcnt0 h'ffd1 tcnt1 tmr 0 , tmr 1 h'ffd2 pwoerb oe15 oe14 oe13 oe12 oe11 oe10 oe9 oe8 pwm 8 h'ffd3 pwoera oe7 oe6 oe5 oe4 oe3 oe2 oe1 oe0 h'ffd4 pwdprb os15 os14 os13 os12 os11 os10 os9 os8 h'ffd5 pwdpra os7 os6 os5 os4 os3 os2 os1 os0 h'ffd6 pwsl pwcke pwcks ? ? rs3 rs2 rs1 rs0 h'ffd7 pwdr0 to pwdr15 h'ffd8 smr0 c/ a chr pe o/ e stop mp cks1 cks0 sci0 8 iccr0 ice ieic mst trs acke bbsy iric scp iic0 h'ffd9 brr0 sci0 icsr0 estp stop irtr aasx al aas adz ackb iic0 h'ffda scr0 tie rie te re mpie teie cke1 cke0 sci0 h'ffdb tdr0 h'ffdc ssr0 tdre rdrf orer fer per tend mpb mpbt h'ffdd rdr0 h'ffde scmr0 ? ? ? ? sdir sinv ? smif icdr0 icdr7 icdr6 icdr5 icdr4 icdr3 icdr2 icdr1 icdr0 iic0 sarx0 svax6 svax5 svax4 svax3 svax2 svax1 svax0 fsx h'ffdf icmr0 mls wait cks2 cks1 cks0 bc2 bc1 bc0 sar0 sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs h'ffe0 addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d 8 h'ffe1 addral ad1 ad0 ? ? ? ? ? ?
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 579 of 706 rej09b0303-0300 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'ffe2 addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d 8 h'ffe3 addrbl ad1 ad0 ? ? ? ? ? ? h'ffe4 addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffe5 addrcl ad1 ad0 ? ? ? ? ? ? h'ffe6 addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffe7 addrdl ad1 ad0 ? ? ? ? ? ? h'ffe8 adcsr adf adie adst scan cks ch2 ch1 ch0 h'ffe9 adcr trgs1 trgs0 ? ? ? ? ? ? h'fff0 tcrx cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmrx 8 tcry cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmry h'fff1 tcsrx cmfb cmfa ovf icf os3 os2 os1 os0 tmrx tcsry cmfb cmfa ovf icie os3 os2 os1 os0 tmry h'fff2 ticrr tmrx tcoray tmry h'fff3 ticrf tmrx tcorby tmry h'fff4 tcntx tmrx tcnty tmry h'fff5 tcorc tmrx tisr???????istmry h'fff6 tcorax tmrx h'fff7 tcorbx h'fffc tconri simod1 simod0 scone icst hfinv vfinv hiinv viinv h'fffd tconro hoe voe cloe cboe hoinv voinv cloinv cboinv timer connection h'fffe tconrs tmrx/y isgene homod1 homod0 vomod1 vomod0 clmod1 clmod0 h'ffff sedgr vedg hedg cedg hfedg vfedg preqf ihi ivi
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 580 of 706 rej09b0303-0300 b.2 register selection conditions address register name register selection conditions module name h'fdc0 uprtcr h'fdc1 utestr0 h'fdc2 utestr1 h'fde1 epdr2 h'fde2 fvsr2h h'fde3 fvsr2l h'fde4 epszr1 h'fde5 epdr1 h'fde6 fvsr1h h'fde7 fvsr1l h'fde9 epdr0o h'fdea fvsr0oh h'fdeb fvsr0ol h'fded epdr0i h'fdee fvsr0ih h'fdef fvsr0il h'fdf0 ptter h'fdf1 usbier h'fdf2 usbifr h'fdf3 tsfr0 h'fdf4 tffr0 h'fdf5 usbcsr0 h'fdf6 epstlr h'fdf7 epdir h'fdf8 eprstr h'fdf9 devrsmr h'fdfa intselr0 h'fdfb intselr1 h'fdfc hoccr h'fdfd usbcr h'fdfe upllcr h'fdff utestr2 mstp1 = 0 usbe = 1 in stcr usb
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 581 of 706 rej09b0303-0300 address register name register selection conditions module name h'fe4c pcodr h'fe4d pdodr pcddr h'fe4e pcpin pdddr h'fe4f pdpin port h'fee6 ddcswr mstp4 = 0 iic0 h'feeb isr h'feec iscrh h'feed iscrl no conditions interrupt controller h'ff82 pcsr flshe = 0 in stcr pwm h'ff84 sbycr h'ff86 mstpcrh h'ff87 mstpcrl flshe = 0 in stcr system h'ff88 iccr1 h'ff89 icsr1 mstp3 = 0, iice = 1 in stcr icdr1 ice = 1 in iccr1 h'ff8e sarx1 ice = 0 in iccr1 icmr1 ice = 1 in iccr1 h'ff8f sar1 mstp3 = 0, iice = 1 in stcr ice = 0 in iccr1 iic1 h'ff90 tier h'ff91 tcsr h'ff92 frch h'ff93 frcl ocrah ocrs = 0 in tocr h'ff94 ocrbh ocrs = 1 in tocr ocral ocrs = 0 in tocr h'ff95 ocrbl ocrs = 1 in tocr h'ff96 tcr h'ff97 tocr mstp13 = 0 frt
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 582 of 706 rej09b0303-0300 address register name register selection conditions module name icrah icrs = 0 in tocr h'ff98 ocrarh icrs = 1 in tocr icral icrs = 0 in tocr h'ff99 ocrarl icrs = 1 in tocr icrbh icrs = 0 in tocr h'ff9a ocrafh icrs = 1 in tocr icrbl icrs = 0 in tocr h'ff9b ocrafl icrs = 1 in tocr icrch icrs = 0 in tocr h'ff9c ocrdmh icrs = 1 in tocr icrcl icrs = 0 in tocr h'ff9d ocrdml icrs = 1 in tocr h'ff9e icrdh h'ff9f icrdl mstp13 = 0 frt dadrah regs=0 in dacnt/dadrb h'ffa0 dacr mstp11 = 0, iice = 1 in stcr regs=1 in dacnt/dadrb h'ffa1 dadral mstp11 = 0, iice = 1 in stcr regs=0 in dacnt/dadrb dadrbh regs=0 in dacnt/dadrb h'ffa6 dacnth regs=1 in dacnt/dadrb dadrbl regs=0 in dacnt/dadrb h'ffa7 dacntl mstp11 = 0, iice = 1 in stcr regs=1 in dacnt/dadrb pwmx tcsr0 h'ffa8 tcnt0 (write) h'ffa9 tcnt0 (read) no conditions wdt0 h'ffac p1pcr h'ffad p2pcr h'ffae p3pcr h'ffb0 p1ddr no conditions ports
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 583 of 706 rej09b0303-0300 address register name register selection conditions module name h'ffb1 p2ddr h'ffb2 p1dr h'ffb3 p2dr h'ffb4 p3ddr h'ffb5 p4ddr h'ffb6 p3dr h'ffb7 p4dr h'ffb8 p5ddr h'ffb9 p6ddr h'ffba p5dr h'ffbb p6dr h'ffbe p7pin no conditions ports h'ffc2 ier no conditions interrupts h'ffc3 stcr h'ffc4 syscr h'ffc5 mdcr no conditions system h'ffc6 bcr h'ffc7 wscr no conditions bus controller h'ffc8 tcr0 h'ffc9 tcr1 h'ffca tcsr0 h'ffcb tcsr1 h'ffcc tcora0 h'ffcd tcora1 h'ffce tcorb0 h'ffcf tcorb1 h'ffd0 tcnt0 h'ffd1 tcnt1 mstp12 = 0 tmr 0 , tmr 1 h'ffd2 pwoerb h'ffd3 pwoera h'ffd4 pwdprb h'ffd5 pwdpra no conditions pwm
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 584 of 706 rej09b0303-0300 address register name register selection conditions module name h'ffd6 pwsl mstp11 = 0 h'ffd7 pwdr0 to 15 pwm smr0 mstp7 = 0, iice = 0 in stcr sci0 h'ffd8 iccr0 mstp4 = 0, iice = 1 in stcr iic0 brr0 mstp7 = 0, iice = 0 in stcr sci0 h'ffd9 icsr0 mstp4 = 0, iice = 1 in stcr iic0 h'ffda scr0 h'ffdb tdr0 h'ffdc ssr0 h'ffdd rdr0 mstp7 = 0 scmr0 mstp7 = 0, iice = 0 in stcr sci0 icdr0 ice = 1 in iccr0 h'ffde sarx0 ice = 0 in iccr0 icmr0 ice = 1 in iccr0 h'ffdf sar0 mstp4 = 0, iice = 1 in stcr ice = 0 in iccr0 iic0 h'ffe0 addrah h'ffe1 addral h'ffe2 addrbh h'ffe3 addrbl h'ffe4 addrch h'ffe5 addrcl h'ffe6 addrdh h'ffe7 addrdl h'ffe8 adcsr h'ffe9 adcr mstp9 = 0 a/d tcrx tmrx/y = 0 in tconrs tmrx h'fff0 tcry mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs tmry tcsrx tmrx/y = 0 in tconrs tmrx h'fff1 tcsry mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs tmry ticrr tmrx/y = 0 in tconrs tmrx h'fff2 tcoray mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs tmry
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 585 of 706 rej09b0303-0300 address register name register selection conditions module name ticrf tmrx/y = 0 in tconrs tmrx h'fff3 tcorby mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs tmry tcntx tmrx/y = 0 in tconrs tmrx h'fff4 tcnty mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs tmry tcorc tmrx/y = 0 in tconrs tmrx h'fff5 tisr mstp8 = 0, hie = 0 in syscr tmrx/y = 1 in tconrs tmry h'fff6 tcorax h'fff7 tcorbx mstp8 = 0, hie = 0 in syscr tmrx/y = 0 in tconrs tmrx h'fffc tconri h'fffd tconro h'fffe tconrs h'ffff sedgr mstp8 = 0, hie = 0 in syscr timer connection
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 586 of 706 rej09b0303-0300 b.3 functions ddcswr?ddc switch register h'fee6 iic0 register name address to which the register is mapped name of on-chip supporting module register acronym bit numbers initial bit values names of the bits. dashes (?) indicate reserved bits. full name of bit descriptions of bit settings read only write only read and write r w r/w possible types of access bit initial value read/write 7 swe 0 r/w 6 sw 0 r/w 5 ie 0 r/w 4 if 0 r/(w) * 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? ddc mode switch interrupt flag 0 no interrupt is requested when automatic format switching is executed [clearing condition] when 0 is written in if after reading if = 1 1 an interrupt is requested when automatic format switching is executed [setting condition] when a falling edge is detected on the scl pin when swe = 1 ddc mode switch 0 iic channel 0 is used with the i2c bus format [clearing conditions] when 0 is written by software when a falling edge is detected on the scl pin when swe = 1 1 iic channel 0 is used in formatless mode [setting condition] when 1 is written in sw after reading sw = 0 ddc mode switch enable 0 automatic switching of iic channel 0 from formatless mode to i 2 c bus format is disabled 1 automatic switching of iic channel 0 from formatless mode to i 2 c bus format is enabled ddc mode switch interrupt enable bit 0 interrupt when automatic format switching is executed is disabled 1 interrupt when automatic format switching is executed is enabled note: * only 0 can be written, to clear the flag.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 587 of 706 rej09b0303-0300 uprtcr?usb port control register h'fdc0 usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 dspsel2 0 r/w 4 dspsel1 0 r/w 3 dspsel0 0 r/w 2 pcnmd2 0 r/w 1 pcnmd1 0 r/w 0 pcnmd0 0 r/w port connection mode select 2 to 0 0 user mode 1 0 1 digital upstream mode digital downstream mode digital upstream/downstream mode upstream transceiver/receiver monitor mode downstream transceiver/receiver monitor mode 0 1 0 1 00 1 reserved 1 ? downstream port select 2 to 0 0 downstream port 2 selected 1 0 1 0 1 downstream port 3 selected downstream port 4 selected downstream port 5 selected ? 0 1 ? downstream port 1 selected utestr0?usb test register 0 h'fdc1 usb utestr1?usb test register 1 h'fdc2 usb bit initial value read/write utestr0 7 test15 0 r/w 6 test14 0 r/w 5 test13 0 r/w 4 test12 0 r/w 3 test11 0 r/w 2 test10 0 r/w 1 test9 0 r/w 0 test8 0 r/w bit initial value read/write utestr1 7 test7 0 r/w 6 test6 0 r/w 5 test5 0 r/w 4 test4 0 r/w 3 test3 0 r/w 2 test2 0 r/w 1 test1 0 r/w 0 test0 0 r/w
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 588 of 706 rej09b0303-0300 epdr2?endpoint data register 2 h'fde1 usb bit initial value read/write 7 d7 0 r/w * 6 d6 0 r/w * 5 d5 0 r/w * 4 d4 0 r/w * 3 d3 0 r/w * 2 d2 0 r/w * 1 d1 0 r/w * 0 d0 0 r/w * mediates data transfer between cpu and fifo for each usb function endpoint host input transfer/host output transfer note: * the epdr2 transfer direction is determined by the endpoint direction register. epdr2 is a write-only register when designated for host input transfer, and a read-only register when designated for host output transfer. fvsr2h?fifo valid size register 2h h'fde2 usb fvsr2l?fifo valid size register 2l h'fde3 usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r fvsr2h fvsr2l 3 ? 0 r 2 ? 0 r 1 n9 0 r 0 n8 0 r 7 n7 0 r 6 n6 0 r 5 n5 0 r 4 n4 0 r 3 n3 0 r 2 n2 0 r 1 n1 0 r 0 n0 0 r indicates number of valid data bytes in fifo for each usb function endpoint host input/host output
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 589 of 706 rej09b0303-0300 epszr1?endpoint size register 1 h'fde4 usb bit initial value read/write 7 ep1sz3 0 r/w 6 ep1sz2 1 r/w 5 ep1sz1 0 r/w 4 ep1sz0 0 r/w 3 ep2sz3 0 r/w 2 ep2sz2 1 r/w 1 ep2sz1 0 r/w 0 ep2sz0 0 r/w 0 fifo size = 0 bytes (settable for ep2 only) 1 0 setting prohibited setting prohibited setting prohibited fifo size = 16 bytes (initial value) n = 1, 2 fifo size = 32 bytes (settable for ep1 only) 0 epnsz3 epnsz2 epnsz1 1 10 setting prohibited ? 1 setting prohibited 0 epnsz0 operating mode 1 0 1 0 1 0 1 setting prohibited ?? specifies number of fifo bytes used bits 7 to 4 ep1 fifo size bits 3 to 0 ep2 fifo size epdr1?endpoint data register 1 h'fde5 usb bit initial value read/write 7 d7 0 w 6 d6 0 w 5 d5 0 w 4 d4 0 w 3 d3 0 w 2 d2 0 w 1 d1 0 w 0 d0 0 w mediates data transfer between cpu and fifo for each usb function endpoint host input transfer/host output transfer
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 590 of 706 rej09b0303-0300 fvsr1h?fifo valid size register 1h h'fde6 usb fvsr1l?fifo valid size register 1h h'fde7 usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r fvsr1h fvsr1l 3 ? 0 r 2 ? 0 r 1 n9 0 r 0 n8 0 r 7 n7 0 r 6 n6 0 r 5 n5 0 r 4 n4 0 r 3 n3 0 r 2 n2 0 r 1 n1 0 r 0 n0 0 r indicates number of valid data bytes in fifo for each usb function endpoint host input/host output epdr0o?endpoint data register 0o h'fde9 usb bit initial value read/write 7 d7 0 r 6 d6 0 r 5 d5 0 r 4 d4 0 r 3 d3 0 r 2 d2 0 r 1 d1 0 r 0 d0 0 r mediates data transfer between cpu and fifo for each usb function endpoint host input transfer/host output transfer fvsr0oh?fifo valid size register 0oh h'fdea usb fvsr0ol?fifo valid size register 0ol h'fdeb usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r fvsr0oh fvsr0ol 3 ? 0 r 2 ? 0 r 1 n9 0 r 0 n8 0 r 7 n7 0 r 6 n6 0 r 5 n5 0 r 4 n4 0 r 3 n3 0 r 2 n2 0 r 1 n1 0 r 0 n0 0 r indicates number of valid data bytes in fifo for each usb function endpoint host input/host output
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 591 of 706 rej09b0303-0300 epdr0i?endpoint data register 0i h'fded usb bit initial value read/write 7 d7 0 w 6 d6 0 w 5 d5 0 w 4 d4 0 w 3 d3 0 w 2 d2 0 w 1 d1 0 w 0 d0 0 w mediates data transfer between cpu and fifo for each usb function endpoint host input transfer/host output transfer fvsr0ih?fifo valid size register 0ih h'fdee usb fvsr0il?fifo valid size register 0il h'fdef usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r fvsr0ih fvsr0il 3 ? 0 r 2 ? 0 r 1 n9 0 r 0 n8 0 r 7 n7 0 r 6 n6 0 r 5 n5 0 r 4 n4 0 r 3 n3 0 r 2 n2 0 r 1 n1 0 r 0 n0 0 r indicates number of valid data bytes in fifo for each usb function endpoint host input/host output
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 592 of 706 rej09b0303-0300 ptter?packet transmit enable register h'fdf0 usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ep2te 0 r/(w) * 2 ep1te 0 r/(w) * 1 ep0ite 0 r/(w) * 0 ? 0 r endpoint 0i packet transmit enable 0 initial set value (1) [1 write] endpoint 0 in-fifo fvsr0i is updated endpoint 1 packet transmit enable 0 initial set value (1) [1 write] endpoint 1 in-fifo fvsr1 is updated endpoint 2 packet transmit enable 0 initial set value (1) [1 write] endpoint 2 in-fifo fvsr2 is updated note: * only 1 can be written.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 593 of 706 rej09b0303-0300 usbier?usb interrupt enable register h'fdf1 usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 brste 0 r/w 4 sofe 0 r/w 3 spnde 0 r/w 2 tfe 0 r/w 1 tse 0 r/w 0 setupe 0 r/w setup interrupt enable 0 usb function setup interrupts disabled 1 usb function setup interrupts enabled transfer successful interrupt enable 0 usb function transfer successful interrupts disabled 1 usb function transfer successful interrupts enabled transfer failed interrupt enable 0 usb function transfer failed interrupts disabled 1 usb function transfer failed interrupts enabled suspend interrupt enable 0 usb function suspend out interrupts and suspend in interrupts disabled 1 usb function suspend out interrupts and suspend in interrupts enabled sof interrupt enable 0 usb function sof interrupts disabled 1 usb function sof interrupts enabled bus reset interrupt enable 0 usb function bus reset interrupts disabled 1 usb function bus reset interrupts enabled
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 594 of 706 rej09b0303-0300 usbifr?usb interrupt flag register h'fdf2 usb bit initial value read/write 7 ts 0 r 6 tf 0 r 5 ? 0 r 4 brstf 0 r/(w) * 3 soff 0 r/(w) * 2 spndof 0 r/(w) * 1 spndif 0 r/(w) * 0 setupf 0 r/(w) * 0 1 [clearing condition] when 0 is written in setupf after reading setupf = 1 [setting condition] when usb function endpoint 0 receives setup token setup interrupt flag 0 1 [clearing condition] when 0 is written in spndif after reading spndif = 1 [setting condition] when usb function switches from normal state to suspend state suspend in interrupt flag 0 1 [clearing condition] when 0 is written in spndof after reading spndof = 1 [setting condition] when usb function switches from suspend state to normal state suspend out interrupt flag 0 1 [clearing condition] when 0 is written in soff after reading soff = 1 [setting condition] when usb function detects sof (start of frame) sof interrupt flag 0 1 [clearing condition] when 0 is written in brstf after reading brstf = 1 [setting condition] when usb function detects a bus reset from upstream bus reset interrupt flag 0 1 all bits in transfer fail flag register (tffr) are 0 at least one bit in transfer fail flag register (tffr) is 1 transfer failed interrupt status 0 1 all bits in transfer success flag register (tsfr) are 0 at least one bit in transfer success flag register (tsfr) is 1 transfer successful interrupt status note: * only 0 can be written, after reading 1, to clear the flag.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 595 of 706 rej09b0303-0300 tsfr?transfer success flag register h'fdf3 usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ep2ts 0 r/(w) * 2 ep1ts 0 r/(w) * 1 ep0its 0 r/(w) * 0 ep0ots 0 r/(w) * endpoint 0 host output transfer success flag 0 endpoint 0 is in host output transfer standby state [clearing conditions] when 0 is written in ep0ots after reading ep0ots = 1 when endpoint 0 receives a setup token 1 endpoint 0 host output transfer (out transaction or setup transaction) has ended normally [setting conditions] ack handshake established after out token reception and data transfer (ack transmission) when command received after setup token reception requires processing by the slave cpu endpoint 0 host input transfer success flag 0 endpoint 0 is in host input transfer standby state [clearing conditions] when 0 is written in ep0its after reading ep0its = 1 when endpoint 0 receives a setup token 1 endpoint 0 host input transfer (in transaction) has ended normally [setting condition] ack handshake established after in token reception and data transfer (ack reception) endpoint 1 transfer success flag 0 endpoint 1 is in transfer standby state [clearing condition] when 0 is written in ep1ts after reading ep1ts = 1 1 endpoint 1 host input transfer (in transaction) has ended normally [setting condition] ack handshake established after in token reception and data transfer (ack reception) endpoint 2 transfer success flag 0 endpoint 2 is in transfer standby state) [clearing condition] when 0 is written in ep2ts after reading ep2ts = 1 1 endpoint 2 host input transfer (in transaction) or host output transfer (out transaction) has ended normally [setting conditions] ack handshake established after in token reception and data transfer (ack reception) ack handshake established after out token reception and data transfer (ack transmission) note: * only 0 can be written, after reading 1, to clear the flag.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 596 of 706 rej09b0303-0300 tffr?transfer fail flag register h'fdf4 usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ep2tf 0 r/(w) * 2 ep1tf 0 r/(w) * 1 ep0itf 0 r/(w) * 0 ep0otf 0 r/(w) * endpoint 0 host output transfer fail flag 0 endpoint 0 is in host output transfer standby state [clearing conditions] when 0 is written in ep0otf after reading ep0otf = 1 when endpoint 0 receives a setup token 1 endpoint 0 host output transfer (out transaction or setup transaction) has ended abnormally [setting conditions] data transfer not possible due to fifo full condition after out token reception (nak transmission) data transfer not possible because ep0otc = 1 after out token reception (nak transmission) communication error after out token reception when command received after setup token reception can be processed within the usb function core endpoint 0 host input transfer fail flag 0 endpoint 0 is in host input transfer standby state [clearing conditions] when 0 is written in ep0itf after reading ep0itf = 1 when endpoint 0 receives a setup token 1 endpoint 0 host input transfer (in transaction) has ended abnormally [setting conditions] ack handshake not established after in token reception and data transfer data transfer not possible due to fifo empty condition after in token reception (nak transmission) endpoint 1 transfer fail flag 0 endpoint 1 is in transfer standby state [clearing condition] when 0 is written in ep1tf after reading ep1tf = 1 1 endpoint 1 host input transfer (in transaction) has ended abnormally [setting conditions] ack handshake not established after in token reception and data transfer data transfer not possible due to fifo empty condition after in token reception (nak transmission) endpoint 2 transfer fail flag 0 endpoint 2 is in transfer standby state [clearing condition] when 0 is written to ep2tf after reading ep2tf = 1 1 endpoint 2 host input transfer (in transaction) or host output transfer (out transaction) has ended abnormally [setting conditions] ack handshake not established after in token reception and data transfer data transfer not possible due to fifo empty condition after in token reception (nak transmission) data reception not possible due to fifo full condition after out token reception (nak transmission) data0/data1 pid toggle error after out token reception note: * only 0 can be written, after reading 1, to clear the flag.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 597 of 706 rej09b0303-0300 usbcsr0?usb control/status register 0 h'fdf5 usb bit initial value read/write 7 dp5cnct 0 r 6 dp4cnct 0 r 5 dp3cnct 0 r 4 dp2cnct 0 r 3 ep0stop 0 r/w 2 epivld 0 r/w 1 ep0otc 0 r/w 0 ckstop 0 r/w clock stop 0 clock is supplied to usb function [clearing conditions] system reset function soft reset suspend out interrupt flag setting 1 clock supply to usb function is stopped [setting condition] when 1 is written in ckstop after reading ckstop = 0 endpoint 0o transfer control 0 ep0 out-fifo writing stopped subsequent writes to ep0 out-fifo are invalid [clearing conditions] system reset function soft reset command data reception in setup transaction (ep0ots flag setting) 1 ep0 out-fifo operational [setting conditions] setup token reception when 1 is written in ep0otc after reading ep0otc = 0 endpoint information valid 0 endpoint information (epinfo) has not been set [clearing conditions] system reset function soft reset 1 endpoint information (epinfo) has been set endpoint 0 stop 0 ep0 out-fifo, in-fifo operational [clearing conditions] system reset function soft reset 1 ep0 out-fifo reading stopped fvsr0o contents are not changed by an epdr0o read ep0 in-fifo writing and transfer stopped fifo contents are not changed by an epdr0i write fvsr0i contents are not changed by setting ep0ipte downstream port connect 5 to 2 0 cable is not connected to downstream port [clearing conditions] system reset downstream port disconnect usb hub upstream port disconnect (total downstream disconnect by software in reconnect process) 1 cable is connected to downstream port, and power is being supplied [setting condition] downstream port connect
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 598 of 706 rej09b0303-0300 epstlr?endpoint stall register h'fdf6 usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ep2stl 0 r/w 2 ep1stl 0 r/w 1 ? 0 r 0 ep0stl 0 r/w endpoint 0 stall 0 endpoint 0 is operational [clearing condition] when endpoint 0 receives a setup token 1 endpoint 0 is in stall state [setting condition] when 1 is written in ep0stl after reading ep0stl = 0 endpoint 1 stall 0 endpoint 1 is operational 1 endpoint 1 is in stall state endpoint 2 stall 0 endpoint 2 is operational 1 endpoint 2 is in stall state
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 599 of 706 rej09b0303-0300 epdir?endpoint direction register h'fdf7 usb bit initial value read/write 7 ? 1 r 6 ? 1 r 5 ? 1 r 4 ? 1 r 3 ep2dir 1 r/w 2 ep1dir 1 r/w 1 ? 0 r 0 ? 0 r endpoint 2 data transfer direction control flag 0 endpoint 2 is designated for host output transfer 1 endpoint 2 is designated for host input transfer endpoint 1 data transfer direction control flag 0 setting prohibited 1 endpoint 1 is designated for host input transfer
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 600 of 706 rej09b0303-0300 eprstr?endpoint reset register h'fdf8 usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ep2rst 0 r/(w) * 2 ep1rst 0 r/(w) * 1 ep0irst 0 r/(w) * 0 ? 0 r endpoint 0i reset 0 initial set value (1) [1 write] fvsr0i is initialized to h'0010 endpoint 1 reset 0 initial set value (1) [1 write] ep1 fifo size = 16 bytes: fvsr1 is initialized to h'0010 ep1 fifo size = 32 bytes: fvsr1 is initialized to h'0020 endpoint 2 reset 0 initial set value (1) [1 write] ep2dir = 0: fvsr2 is initialized to h'0000 ep2dir = 1: fvsr2 is initialized to h'0010 note: * only 1 can be written.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 601 of 706 rej09b0303-0300 devrsmr?device resume register h'fdf9 usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 dvr 0 r/(w) * device resume (dvr) 0 (initial value) (1) [1 write] suspend state is cleared (remote wakeup) note: * only 1 can be written.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 602 of 706 rej09b0303-0300 intselr0?interrupt source select register 0 h'fdfa usb bit initial value read/write 7 tselb 0 r/w 6 epibs2 0 r/w 5 epibs1 0 r/w 4 epibs0 0 r/w 3 tselc 0 r/w 2 epics2 0 r/w 1 epics1 0 r/w 0 epics0 0 r/w transfer select c 0 usbic is requested by a ts interrupt; the endpoint constituting the ts interrupt source is specified by bits epics2 to epics0 1 usbic is requested by a tf interrupt; the endpoint constituting the tf interrupt source is specified by bits epics2 to epics0 interrupt c endpoint select 2 to 0 0 initial set value 1 0 1 endpoint 1 selected endpoint 2 selected setting prohibited setting prohibited 0 1 0 1 ?? interrupt b endpoint select 2 to 0 0 initial set value 1 0 1 endpoint 1 selected endpoint 2 selected setting prohibited setting prohibited 0 1 0 1 ?? transfer select b 0 usbib is requested by a ts interrupt; the endpoint constituting the ts interrupt source is specified by bits epibs2 to epibs0 1 usbib is requested by a tf interrupt; the endpoint constituting the tf interrupt source is specified by bits epibs2 to epibs0
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 603 of 706 rej09b0303-0300 intselr1?interrupt source select register 1 h'fdfb usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 dtcbe 0 r/w 0 dtcce 0 r/w note: do not write 1 to the bits in this register.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 604 of 706 rej09b0303-0300 hoccr?hub overcurrent control register h'fdfc usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 pcsp 0 r/w 4 ocdsp 0 r/w 3 hoc5e 0 r/w 2 hoc4e 0 r/w 1 hoc3e 0 r/w 0 hoc2e 0 r/w overcurrent detection control enable 2 0 pins enp 2 and ocp 2 are general ports (pc 4 , pc 0 ) 1 pins enp 2 and ocp 2 have output enable and overcurrent detection functions overcurrent detection control enable 3 0 pins enp 3 and ocp 3 are general ports (pc 5 , pc 1 ) 1 pins enp 3 and ocp 3 have output enable and overcurrent detection functions overcurrent detection control enable 4 0 pins enp 4 and ocp 4 are general ports (pc 6 , pc 2 ) 1 pins enp 4 and ocp 4 have output enable and overcurrent detection functions overcurrent detection control enable 5 0 pins enp 5 and ocp 5 are general ports (pc 7 , pc 3 ) 1 pins enp 5 and ocp 5 have output enable and overcurrent detection functions overcurrent detection polarity 0 power supply control ic outputs low level in case of overcurrent detection 1 power supply control ic outputs high level in case of overcurrent detection power supply enable control polarity 0 power supply control ic requires low-level input for enabling 1 power supply control ic requires high-level input for enabling
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 605 of 706 rej09b0303-0300 usbcr?usb control register h'fdfd usb bit initial value read/write 7 fadsel 0 r/w 6 fonly 1 r/w 5 fncstp 1 r/w 4 uifrst 1 r/w 3 hpllrst 1 r/w 2 hsrst 1 r/w 1 fpllrst 1 r/w 0 fsrst 1 r/w function block internal state soft reset 0 internal state of usb function block is set to operational state 1 internal state of usb function block is set to reset state (excluding dpll) function block pll soft reset 0 function dpll is placed in operational state 1 function dpll is placed in reset state hub block internal state soft reset 0 internal state of usb hub block is set to operational state 1 internal state of usb hub block is set to reset state (excluding dpll) hub block pll soft reset 0 hub dpll is placed in operational state 1 hub dpll is placed in reset state usb interface soft reset 0 epszr1, usbier, epdir, intselr0, and intselr1 are placed in operational state 1 epszr1, usbier, epdir, intselr0, and intselr1 are placed in reset state usb function stop/suspend 0 for usb function block, usb hub downstream port 1 internal connection is set to connected state 1 for usb function block, usb hub downstream port 1 internal connection is set to disconnected state, and power-down state is set usb function select 0 usb function block is connected internally to usb hub downstream port 1; usb hub block is enabled 1 usb function block is directly connected to upstream port; usb hub block is disabled usb function i/o analog/digital select 0 usd+ and usd ? pins are used for usb function block data input/output 1 usb function block data input/output is implemented by multiplexing philips transceiver/receiver (pidusb11a) compatible control input/output with port c pins
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 606 of 706 rej09b0303-0300 upllcr?usb pll control register h'fdfe usb bit initial value read/write 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 cksel2 0 r/w 3 cksel1 0 r/w 2 cksel0 0 r/w 1 pfsel1 0 r/w 0 pfsel0 0 r/w pll frequency select 0 pll input clock is 8 mhz 1 0 1 0 1 pll input clock is 12 mhz pll input clock is 16 mhz pll input clock is 20 mhz clock source select 2 to 0 0 1 pll operation halted, clock input halted 0 ? 0 pll operation halted, clock input halted setting prohibited pll operation halted usb clock pulse generator (xtal12: 48 mhz) used directly instead of pll output pll operates with system clock pulse generator (xtal) as clock source pll operates with usb clock pulse generator (xtal12) as clock source 0 ? 0 1 10 1 utestr2?usb test register 2 h'fdff usb bit initial value read/write utestr2 7 testa 1 r/w 6 testb 1 r/w 5 testc 1 r/w 4 testd 1 r/w 3 teste 1 r/w 2 testf 1 r/w 1 testg 1 r/w 0 testh 1 r/w
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 607 of 706 rej09b0303-0300 pcodr?port c data output register h'fe4c port c bit initial value read/write 7 pc 7 odr 0 r/w 6 pc 6 odr 0 r/w 5 pc 5 odr 0 r/w 4 pc 4 odr 0 r/w output data for port c pins 3 pc 3 odr 0 r/w 2 pc 2 odr 0 r/w 1 pc 1 odr 0 r/w 0 pc 0 odr 0 r/w pdodr?port d data output register h'fe4d port d bit initial value read/write 7 pd 7 odr 0 r/w 6 pd 6 odr 0 r/w 5 pd 5 odr 0 r/w 4 pd 4 odr 0 r/w output data for port d pins 3 pd 3 odr 0 r/w 2 pd 2 odr 0 r/w 1 pd 1 odr 0 r/w 0 pd 0 odr 0 r/w pcddr?port c data direction register h'fe4e port c bit initial value read/write 7 pc 7 ddr 0 w 6 pc 6 ddr 0 w 5 pc 5 ddr 0 w 4 pc 4 ddr 0 w specify input or output for port c pins 3 pc 3 ddr 0 w 2 pc 2 ddr 0 w 1 pc 1 ddr 0 w 0 pc 0 ddr 0 w
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 608 of 706 rej09b0303-0300 pcpin?port c input data register h'fe4e port c bit initial value read/write 7 pc 7 pin ? * r 6 pc 6 pin ? * r 5 pc 5 pin ? * r 4 pc 4 pin ? * r port c pin states 3 pc 3 pin ? * r 2 pc 2 pin ? * r 1 pc 1 pin ? * r 0 pc 0 pin ? * r note: * determined by the state of pins pc 7 to pc 0 . pdddr?port d data direction register h'fe4f port d bit initial value read/write 7 pd 7 ddr 0 w 6 pd 6 ddr 0 w 5 pd 5 ddr 0 w 4 pd 4 ddr 0 w specify input or output for port d pins 3 pd 3 ddr 0 w 2 pd 2 ddr 0 w 1 pd 1 ddr 0 w 0 pd 0 ddr 0 w pdpin?port d input data register h'fe4f port d bit initial value read/write 7 pd 7 pin ? * r 6 pd 6 pin ? * r 5 pd 5 pin ? * r 4 pd 4 pin ? * r port d pin states 3 pd 3 pin ? * r 2 pd 2 pin ? * r 1 pd 1 pin ? * r 0 pd 0 pin ? * r note: * determined by the state of pins pd 7 to pd 0 .
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 609 of 706 rej09b0303-0300 ddcswr?ddc switch register h'fee6 iic0 7 swe 0 r/w 6 sw 0 r/w 5 ie 0 r/w 4 if 0 r/(w) * 1 3 clr3 1 w * 2 0 clr0 1 w * 2 2 clr2 1 w * 2 1 clr1 1 w * 2 bit initial value read/write ddc mode switch interrupt flag 0 no interrupt is requested when automatic format switching is executed [clearing condition] when 0 is written in if after reading if = 1 1 an interrupt is requested when automatic format switching is executed [setting condition] when a falling edge is detected on the scl pin when swe = 1 iic clear 3 to 0 0 setting prohibited setting prohibited iic0 internal latch clearance iic1 internal latch clearance iic0 and iic1 internal latch clearance 1 invalid setting 0 1 ? ? 0 1 ? ? 0 1 0 1 ? ddc mode switch 0 iic channel 0 is used with the i 2 c bus format [clearing conditions] when 0 is written by software when a falling edge is detected on the scl pin when swe = 1 1 iic channel 0 is used in formatless mode [setting condition] when 1 is written in sw after reading sw = 0 ddc mode switch enable 0 automatic switching of iic channel 0 from formatless mode to i 2 c bus format is disabled 1 automatic switching of iic channel 0 from formatless mode to i 2 c bus format is enabled ddc mode switch interrupt enable bit 0 interrupt when automatic format switching is executed is disabled 1 interrupt when automatic format switching is executed is enabled notes: 1. only 0 can be written, to clear the flag. 2. always read as 1.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 610 of 706 rej09b0303-0300 isr?irq status register h'feeb interrupt controller 7 ? 0 r 6 ? 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 0 irq0f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * bit initial value read/write irq2 to irq0 flags 0 1 [clearing conditions] when 0 is written in irqnf after reading irqnf = 1 when interrupt exception handling is executed while low-level detection is set (irqnscb = irqnsca = 0) and irqn input is high when irqn interrupt exception handling is executed while falling, rising, or both-edge detection is set (irqnscb = 1 or irqnsca = 1) [setting conditions] when irqn input goes low while low-level detection is set (irqnscb = irqnsca = 0) when a falling edge occurs in irqn input while falling edge detection is set (irqnscb = 0, irqnsca = 1) when a rising edge occurs in irqn input while rising edge detection is set (irqnscb = 1, irqnsca = 0) when a falling or rising edge occurs in irqn input while both-edge detection is set (irqnscb = irqnsca = 1) notes: n = 2 to 0 * only 0 can be written, to clear the flag.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 611 of 706 rej09b0303-0300 iscrh?irq sense control register h h'feec interrupt controller iscrl?irq sense control register l h'feed interrupt controller 15 ? 0 r/w 14 ? 0 r/w 13 ? 0 r/w 12 ? 0 r/w 11 ? 0 r/w 8 ? 0 r/w 10 ? 0 r/w 9 ? 0 r/w bit initial value read/write iscrh 7 ? 0 r/w 6 ? 0 r/w 5 irq2scb 0 r/w 4 irq2sca 0 r/w 3 irq1scb 0 r/w 0 irq0sca 0 r/w 2 irq1sca 0 r/w 1 irq0scb 0 r/w bit initial value read/write iscrl reserved irq2 to irq0 sense control a and b description iscrl bits 5 to 0 irq2scb to irq0scb irq2sca to irq0sca 0 1 0 1 0 1 interrupt request generated by low level of irq 2 ? irq 0 input interrupt request generated by falling edge of irq 2 ? irq 0 input interrupt request generated by rising edge of irq 2 ? irq 0 input interrupt request generated by rising and falling edges of irq 2 ? irq 0 input
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 612 of 706 rej09b0303-0300 pcsr?peripheral clock select register h'ff82 pwm 7 ? 0 ? 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 ? 0 ? 0 ? 0 r/w 2 pwckb 0 r/w 1 pwcka 0 r/w bit initial value read/write pwm clock select pwsl pcsr bit 7 pwcke 0 1 bit 6 pwcks ? 0 1 bit 2 pwckb ? ? 0 1 bit 1 pwcka ? ? 0 1 0 1 clock input stopped (system clock) selected /2 selected /4 selected /8 selected /16 selected description
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 613 of 706 rej09b0303-0300 sbycr?standby control register h'ff84 system 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ? 0 ? 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value read/write system clock select 2 to 0 0 bus master is in high-speed mode medium-speed clock = /2 medium-speed clock = /4 medium-speed clock = /8 medium-speed clock = /16 medium-speed clock = /32 ? 1 0 1 0 1 0 1 00 1 1 ? standby timer select 2 to 0 0 standby time = 8,192 states standby time = 16,384 states standby time = 32,768 states standby time = 65,536 states standby time = 131,072 states standby time = 262,144 states reserved standby time = 16 states 1 0 1 0 1 0 1 00 1 10 1 software standby 0 transition to sleep mode on execution of sleep instruction in high-speed mode or medium-speed mode 1 transition to software standby mode on execution of sleep instruction in high-speed mode or medium-speed mode
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 614 of 706 rej09b0303-0300 mstpcrh?module stop control register h h'ff86 system mstpcrl?module stop control register l h'ff87 system 7 mstp15 0 r/w bit initial value read/write 6 mstp14 0 r/w 5 mstp13 1 r/w 4 mstp12 1 r/w 3 mstp11 1 r/w 2 mstp10 1 r/w 1 mstp9 1 r/w 0 mstp8 1 r/w 7 mstp7 1 r/w 6 mstp6 1 r/w 5 mstp5 1 r/w 4 mstp4 1 r/w 3 mstp3 1 r/w 2 mstp2 1 r/w 1 mstp1 1 r/w 0 mstp0 1 r/w mstpcrh mstpcrl module stop 0 module stop mode cleared 1 module stop mode set mstp15 * mstp14 * mstp13 mstp12 mstp11 mstp10 * mstp9 mstp8 mstp7 mstp6 * mstp5 * mstp4 mstp3 mstp2 * mstp1 mstp0 * ? ? 16-bit free-running timer (frt) 8-bit timers (tmr0, tmr1) 8-bit pwm timer (pwm), 14-bit pwm timer (pwmx) ? a/d converter 8-bit timers (tmrx, tmry), timer connection serial communication interface 0 (sci0) ? ? i 2 c bus interface (iic) channel 0 i 2 c bus interface (iic) channel 1 ? universal serial bus interface (usb) ? mstpcrh mstpcrl register bit module the correspondence between mstpcr bits and on-chip supporting modules is shown below. note: * bits 15, 14, 10, 6, 5, 2, and 0 can be read and written but must always be set to 1.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 615 of 706 rej09b0303-0300 iccr1?i 2 c bus control register 1 h'ff88 iic1 7 ice 0 r/w 6 ieic 0 r/w 5 mst 0 r/w 4 trs 0 r/w 3 acke 0 r/w 0 scp 1 w 2 bbsy 0 r/w 1 iric 0 r/(w) * bit initial value read/write start condition/stop condition prohibit 0 writing issues a start or stop condition, in combination with the bbsy flag 1 reading always returns a value of 1; writing is invalid i 2 c bus interface interrupt request flag 0 waiting for transfer, or transfer in progress 1 interrupt requested note: for the clearing and setting conditions, see section 16.2.5, i 2 c bus control register (iccr). bus busy 0 bus is free [clearing condition] when a stop condition is detected 1 bus is busy [setting condition] when a start condition is detected acknowledge bit judgement select 0 acknowledge bit is ignored and continuous transfer is performed 1 if acknowledge bit is 1, continuous transfer is interrupted master/slave select (mst), transmit/receive select (trs) 0 slave receive mode slave transmit mode master receive mode master transmit mode 0 1 10 1 i 2 c bus interface interrupt enable 0 interrupt requests disabled 1 interrupt requests enabled note: for details see section 16.2.5, i 2 c bus control register (iccr). i 2 c bus interface enable 0 i 2 c bus interface module disabled, with scl and sda signal pins set to port function sar and sarx can be accessed 1i 2 c bus interface module enabled for transfer operations (pins scl and sda are driving the bus) icmr and icdr can be accessed note: * only 0 can be written, to clear the flag.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 616 of 706 rej09b0303-0300 icsr1?i 2 c bus status register 1 h'ff89 iic1 7 estp 0 r/(w) * 1 6 stop 0 r/(w) * 1 5 irtr 0 r/(w) * 1 4 aasx 0 r/(w) * 1 3 al 0 r/(w) * 1 0 ackb 0 r/w 2 aas 0 r/(w) * 1 1 adz 0 r/(w) * 1 bit initial value read/write acknowledge bit 0 receive mode: 0 is output at acknowledge output timing transmit mode: indicates that the receiving device has acknowledged the data (0 value) 1 receive mode: 1 is output at acknowledge output timing transmit mode: indicates that the receiving device has not acknowledged the data (1 value) notes: general call address recognition flag * 2 0 general call address not recognized 1 general call address recognized slave address recognition flag * 2 0 slave address or general call address not recognized 1 slave address or general call address recognized arbitration lost flag * 2 0 bus arbitration won 1 bus arbitration lost second slave address recognition flag * 2 0 second slave address not recognized 1 second slave address recognized i 2 c bus interface continuous transmission/reception interrupt request flag * 2 0 waiting for transfer, or transfer in progress 1 continuous transfer state normal stop condition detection flag * 2 0 no normal stop condition 1 in i 2 c bus format slave mode: normal stop condition detected in other modes: no meaning error stop condition detection flag * 2 0 no error stop condition 1 in i 2 c bus format slave mode: error stop condition detected in other modes: no meaning 1. only 0 can be written, to clear the flag. 2. for the clearing and setting conditions, see section 16.2.6, i 2 c bus status register (icsr).
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 617 of 706 rej09b0303-0300 icdr1?i 2 c bus data register 1 h'ff8e iic1 7 icdr7 ? r/w 6 icdr6 ? r/w 5 icdr5 ? r/w 4 icdr4 ? r/w 3 icdr3 ? r/w 0 icdr0 ? r/w 2 icdr2 ? r/w 1 icdr1 ? r/w bit initial value read/write 7 icdrr7 ? r 6 icdrr6 ? r 5 icdrr5 ? r 4 icdrr4 ? r 3 icdrr3 ? r 0 icdrr0 ? r 2 icdrr2 ? r 1 icdrr1 ? r bit initial value read/write icdrr icdrs 7 icdrs7 ? ? 6 icdrs6 ? ? 5 icdrs5 ? ? 4 icdrs4 ? ? 3 icdrs3 ? ? 0 icdrs0 ? ? 2 icdrs2 ? ? 1 icdrs1 ? ? bit initial value read/write icdrt 7 icdrt7 ? w 6 icdrt6 ? w 5 icdrt5 ? w 4 icdrt4 ? w 3 icdrt3 ? w 0 icdrt0 ? w 2 icdrt2 ? w 1 icdrt1 ? w bit initial value read/write tdre, rdrf (internal flags) ? rdrf 0 ? ? tdre 0 ? bit initial value read/write note: for details see section 16.2.1, i 2 c bus data register (icdr).
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 618 of 706 rej09b0303-0300 sarx?second slave address register 1 h'ff8e iic1 second slave address 7 svax6 0 r/w 6 svax5 0 r/w 5 svax4 0 r/w 4 svax3 0 r/w 3 svax2 0 r/w 0 fsx 1 r/w 2 svax1 0 r/w 1 svax0 0 r/w bit initial value read/write note: * format select x ddcswr bit 6 sw sar bit 0 fs sarx bit 0 fsx operating mode i 2 c bus format sar and sarx slave addresses recognized 0 00 i 2 c bus format sar slave address recognized sarx slave address ignored i 2 c bus format sar slave address ignored sarx slave address recognized synchronous serial format sar and sarx slave addresses ignored formatless mode (start/stop conditions not detected) acknowledge bit present formatless mode * (start/stop conditions not detected) no acknowledge bit 1 10 1 100 1 10 1 do not select this mode when automatic switching to the i 2 c bus format is performed by means of a ddcswr setting.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 619 of 706 rej09b0303-0300 sar?slave address register h'ff8f iic1 slave address 7 sva6 0 r/w 6 sva5 0 r/w 5 sva4 0 r/w 4 sva3 0 r/w 3 sva2 0 r/w 0 fs 0 r/w 2 sva1 0 r/w 1 sva0 0 r/w bit initial value read/write note: * format select ddcswr bit 6 sw sar bit 0 fs sarx bit 0 fsx operating mode i 2 c bus format sar and sarx slave addresses recognized 0 00 i 2 c bus format sar slave address recognized sarx slave address ignored i 2 c bus format sar slave address ignored sarx slave address recognized synchronous serial format sar and sarx slave addresses ignored formatless mode (start/stop conditions not detected) acknowledge bit present formatless mode * (start/stop conditions not detected) no acknowledge bit 1 10 1 100 1 10 1 do not select this mode when automatic switching to the i 2 c bus format is performed by means of a ddcswr setting.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 620 of 706 rej09b0303-0300 icmr1?i 2 c bus mode register 1 h'ff8f iic1 7 mls 0 r/w 6 wait 0 r/w 5 cks2 0 r/w 4 cks1 0 r/w 3 cks0 0 r/w 0 bc0 0 r/w 2 bc2 0 r/w 1 bc1 0 r/w bit initial value read/write bit counter bc2 bc1 0 1 0 1 0 1 bc0 0 1 0 1 0 1 0 1 note: * do not set this bit to 1 when using the i 2 c bus format. synchronous serial format 8 1 2 3 4 5 6 7 i 2 c bus format 9 2 3 4 5 6 7 8 transfer clock select cks2 cks1 0 1 0 1 0 1 0 1 0 1 0 1 cks0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 iicx 0 1 clock /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 wait insertion bit 0 data and acknowledge transferred consecutively 1 wait inserted between data and acknowledge msb-first/lsb-first select * 0 msb-first 1 lsb-first
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 621 of 706 rej09b0303-0300 tier?timer interrupt enable register h'ff90 frt 7 iciae 0 r/w 6 icibe 0 r/w 5 icice 0 r/w 4 icide 0 r/w 3 ociae 0 r/w 0 ? 1 ? 2 ocibe 0 r/w 1 ovie 0 r/w bit initial value read/write input capture interrupt a enable 0 icfa interrupt request (icia) is disabled 1 icfa interrupt request (icia) is enabled input capture interrupt b enable 0 icfb interrupt request (icib) is disabled 1 icfb interrupt request (icib) is enabled input capture interrupt c enable 0 icfc interrupt request (icic) is disabled 1 icfc interrupt request (icic) is enabled input capture interrupt d enable 0 icfd interrupt request (icid) is disabled 1 icfd interrupt request (icid) is enabled output compare interrupt a enable 0 ocfa interrupt request (ocia) is disabled 1 ocfa interrupt request (ocia) is enabled output compare interrupt b enable 0 ocfb interrupt request (ocib) is disabled 1 ocfb interrupt request (ocib) is enabled timer overflow interrupt enable 0 ovf interrupt request (fovi) is disabled 1 ovf interrupt request (fovi) is enabled
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 622 of 706 rej09b0303-0300 tcsr?timer control/status register h'ff91 frt 7 icfa 0 r/(w) * 6 icfb 0 r/(w) * 5 icfc 0 r/(w) * 4 icfd 0 r/(w) * 3 ocfa 0 r/(w) * 0 cclra 0 r/w 2 ocfb 0 r/(w) * 1 ovf 0 r/(w) * bit initial value read/write input capture flag a note: * only 0 can be written in bits 7 to 1, to clear the flags. 0 [clearing condition] when 0 is written in icfa after reading icfa = 1 1 [setting condition] when an input capture signal causes the frc value to be transferred to icra input capture flag b 0 [clearing condition] when 0 is written in icfb after reading icfb = 1 1 [setting condition] when an input capture signal causes the frc value to be transferred to icrb input capture flag c 0 [clearing condition] when 0 is written in icfc after reading icfc = 1 1 [setting condition] when an input capture signal is generated input capture flag d 0 [clearing condition] when 0 is written in icfd after reading icfd = 1 1 [setting condition] when an input capture signal is generated counter clear a 0 frc clearing is disabled 1 frc is cleared at compare-match a timer overflow 0 [clearing condition] when 0 is written in ovf after reading ovf = 1 1 [setting condition] when the frc value overflows from h'ffff to h'0000 output compare flag b 0 [clearing condition] when 0 is written in ocfb after reading ocfb = 1 1 [setting condition] when frc = ocrb output compare flag a 0 [clearing condition] when 0 is written in ocfa after reading ocfa = 1 1 [setting condition] when frc = ocra
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 623 of 706 rej09b0303-0300 frch?free-running counter h h'ff92 frt frcl?free-running counter l h'ff93 frt 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w up-counter ocrah?output compare register ah h'ff94 frt ocral?output compare register al h'ff95 frt ocrbh?output compare register bh h'ff94 frt ocrbl?output compare register bl h'ff95 frt 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w constantly compared with frc value; ocf is set when ocr = frc
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 624 of 706 rej09b0303-0300 tcr?timer control register h'ff96 frt 7 iedga 0 r/w 6 iedgb 0 r/w 5 iedgc 0 r/w 4 iedgd 0 r/w 3 bufea 0 r/w 0 cks0 0 r/w 2 bufeb 0 r/w 1 cks1 0 r/w bit initial value read/write input edge select a 0 capture on falling edge of input capture input a capture on rising edge of input capture input a 1 input edge select b 0 capture on falling edge of input capture input b capture on rising edge of input capture input b 1 input edge select c 0 capture on falling edge of input capture input c capture on rising edge of input capture input c 1 input edge select d 0 capture on falling edge of input capture input d capture on rising edge of input capture input d 1 buffer enable a 0 icrc is not used as icra buffer register icrc is used as icra buffer register 1 buffer enable b 0 icrd is not used as icrb buffer register 1 clock select 0 /2 internal clock source 0 1 /8 internal clock source /32 internal clock source external clock source (rising edge) 0 1 1 icrd is used as icrb buffer register
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 625 of 706 rej09b0303-0300 tocr?timer output compare control register h'ff97 frt 7 icrdms 0 r/w 6 ocrams 0 r/w 5 icrs 0 r/w 4 ocrs 0 r/w 3 oea 0 r/w 0 olvlb 0 r/w 2 oeb 0 r/w 1 olvla 0 r/w bit initial value read/write output level b 0 0 output at compare- match b 1 1 output at compare- match b output level a 0 0 output at compare- match a 1 1 output at compare- match a output enable b 0 output compare b output disabled 1 output compare b output enabled output enable a 0 output compare a output disabled 1 output compare a output enabled output compare register select 0 ocra register selected 1 ocrb register selected input capture register select 0 icra, icrb, and icrc registers selected 1 ocrar, ocraf, and ocrdm registers selected output compare a mode select 0 ocra set to normal operating mode 1 ocra set to operating mode using ocrar and ocraf input capture d mode select 0 icrd set to normal operating mode 1 icrd set to operating mode using ocrdm
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 626 of 706 rej09b0303-0300 ocrarh?output compare register arh h'ff98 frt ocrarl?output compare register arl h'ff99 frt ocrafh?output compare register afh h'ff9a frt ocrafl?output compare register afl h'ff9b frt 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w used for ocra operation when ocrams = 1 in tocr (for details see section 11.2.4, output compare registers ar and af (ocrar, ocraf).) icrah?input capture register ah h'ff98 frt icral?input capture register al h'ff99 frt icrbh?input capture register bh h'ff9a frt icrbl?input capture register bl h'ff9b frt 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 8 0 r 10 0 r 9 0 r bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r stores frc value when input capture signal is input
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 627 of 706 rej09b0303-0300 ocrdmh?output compare register dmh h'ff9c frt ocrdml?output compare register dml h'ff9d frt 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 8 0 r 10 0 r 9 0 r bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w used for icrd operation when icrdms = 1 in tocr (for details see section 11.2.5, output compare register dm (ocrdm).) icrch?input capture register ch h'ff9c frt icrcl?input capture register cl h'ff9d frt icrdh?input capture register dh h'ff9e frt icrdl?input capture register dl h'ff9f frt 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 8 0 r 10 0 r 9 0 r bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r stores frc value when input capture signal is input (icrc and icrd can be used for buffer operation. for details see section 11.2.3, input capture registers a to d (icra to icrd).)
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 628 of 706 rej09b0303-0300 dacr?pwm (d/a) control register h'ffa0 pwmx 7 test 0 r/w 6 pwme 0 r/w 5 ? 1 ? 4 ? 1 ? 3 oeb 0 r/w 0 cks 0 r/w 2 oea 0 r/w 1 os 0 r/w bit initial value read/write clock select 0 operates at resolution (t) = system clock cycle time (t cyc ) 1 operates at resolution (t) = system clock cycle time (t cyc ) 2 output select 0 direct pwm output 1 inverted pwm output output enable a 0 pwm (d/a) channel a output (pwx0 output pin) disabled 1 pwm (d/a) channel a output (pwx0 output pin) enabled output enable b 0 pwm (d/a) channel b output (pwx1 output pin) disabled 1 pwm (d/a) channel b output (pwx1 output pin) enabled pwm enable 0 dacnt operates as 14-bit up-counter 1 dacnt halts at h'0003 test mode 0 pwm (d/a) in user state, normal operation 1 pwm (d/a) in test state, correct conversion results unobtainable
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 629 of 706 rej09b0303-0300 dadrah?pwm (d/a) data register ah h'ffa0 pwmx dadral?pwm (d/a) data register al h'ffa1 pwmx dadrbh?pwm (d/a) data register bh h'ffa6 pwmx dadrbl?pwm (d/a) data register bl h'ffa7 pwmx 15 13 da13 1 r/w 14 12 da12 1 r/w 13 11 da11 1 r/w 12 10 da10 1 r/w 11 9 da9 1 r/w 8 6 da6 1 r/w 10 8 da8 1 r/w 9 7 da7 1 r/w bit (cpu) bit (data) dadra initial value read/write 7 5 da5 1 r/w 6 4 da4 1 r/w 5 3 da3 1 r/w 4 2 da2 1 r/w 3 1 da1 1 r/w 0 ? ? 1 ? 2 0 da0 1 r/w 1 ? cfs 1 r/w dadrh dadrl da13 1 r/w da12 1 r/w da11 1 r/w da10 1 r/w da9 1 r/w da6 1 r/w da8 1 r/w da7 1 r/w dadrb initial value read/write da5 1 r/w da4 1 r/w da3 1 r/w da2 1 r/w da1 1 r/w regs 1 r/w da0 1 r/w cfs 1 r/w register select (dadrb only) 0 dadra and dadrb can be accessed 1 dacr and dacnt can be accessed carrier frequency select 0 base cycle = resolution (t) 64 dadr range = h'0401 to h'fffd 1 base cycle = resolution (t) 256 dadr range = h'0103 to h'ffff d/a data 13 to 0 d/a conversion data.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 630 of 706 rej09b0303-0300 dacnth?pwm (d/a) counter h h'ffa6 pwmx dacntl?pwm (d/a) counter l h'ffa7 pwmx 15 7 0 r/w 14 6 0 r/w 13 5 0 r/w 12 4 0 r/w 11 3 0 r/w 8 0 0 r/w 10 2 0 r/w 9 1 0 r/w bit (cpu) bit (counter) initial value read/write 7 8 0 r/w 6 9 0 r/w 5 10 0 r/w 4 11 0 r/w 3 12 0 r/w 0 ? regs 1 r/w 2 13 0 r/w 1 ? ? 1 ? dacnth dacntl up-counter register select 0 dadra and dadrb can be accessed 1 dacr and dacnt can be accessed
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 631 of 706 rej09b0303-0300 tcsr0?timer control/status register 0 h'ffa8 wdt0 7 ovf 0 r/(w) * 6 wt/ it 0 r/w 5 tme 0 r/w 4 rsts 0 r/w 3 rst/ nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write clock select 2 to 0 0 1 /2 /64 /128 /512 /2048 /8192 /32768 /131072 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s 0 1 0 1 0 1 0 1 0 1 0 1 clock overflow period (when = 20 mhz) cks0 cks1 cks2 reset or nmi 0 nmi interrupt requested 1 internal reset requested timer enable 0 tcnt is initialized to h'00 and halted 1 tcnt counts timer mode select 0 interval timer mode: sends the cpu an interval timer interrupt request (wovi) when tcnt overflows 1 watchdog timer mode: generates a reset or nmi interrupt when tcnt overflows overflow flag 0 [clearing conditions] when 0 is written in the tme bit when 0 is written in ovf after reading tcsr when ovf = 1 1 [setting condition] when tcnt overflows from h'ff to h'00 (when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset) reserved notes: the method of writing to tcsr is more complicated that for most other registers, to prevent accidental overwriting. for details see section 14.2.4, notes on register access. * only 0 can be written, to clear the flag.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 632 of 706 rej09b0303-0300 tcnt0?timer counter 0 h'ffa8 (w), h'ffa9 (r) wdt0 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write up-counter p1pcr?port 1 mos pull-up control register h'ffac port 1 7 p1 7 pcr 0 r/w 6 p1 6 pcr 0 r/w 5 p1 5 pcr 0 r/w 4 p1 4 pcr 0 r/w 3 p1 3 pcr 0 r/w 0 p1 0 pcr 0 r/w 2 p1 2 pcr 0 r/w 1 p1 1 pcr 0 r/w bit initial value read/write control port 1 mos input pull-ups p2pcr?port 2 mos pull-up control register h'ffad port 2 7 p2 7 pcr 0 r/w 6 p2 6 pcr 0 r/w 5 p2 5 pcr 0 r/w 4 p2 4 pcr 0 r/w 3 p2 3 pcr 0 r/w 0 p2 0 pcr 0 r/w 2 p2 2 pcr 0 r/w 1 p2 1 pcr 0 r/w bit initial value read/write control port 2 mos input pull-ups
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 633 of 706 rej09b0303-0300 p3pcr?port 3 mos pull-up control register h'ffae port 3 7 p3 7 pcr 0 r/w 6 p3 6 pcr 0 r/w 5 p3 5 pcr 0 r/w 4 p3 4 pcr 0 r/w 3 p3 3 pcr 0 r/w 0 p3 0 pcr 0 r/w 2 p3 2 pcr 0 r/w 1 p3 1 pcr 0 r/w bit initial value read/write control port 3 mos input pull-ups p1ddr?port 1 data direction register h'ffb0 port 1 7 p1 7 ddr 0 w 6 p1 6 ddr 0 w 5 p1 5 ddr 0 w 4 p1 4 ddr 0 w 3 p1 3 ddr 0 w 0 p1 0 ddr 0 w 2 p1 2 ddr 0 w 1 p1 1 ddr 0 w bit initial value read/write specify input or output for port 1 pins p2ddr?port 2 data direction register h'ffb1 port 2 7 p2 7 ddr 0 w 6 p2 6 ddr 0 w 5 p2 5 ddr 0 w 4 p2 4 ddr 0 w 3 p2 3 ddr 0 w 0 p2 0 ddr 0 w 2 p2 2 ddr 0 w 1 p2 1 ddr 0 w bit initial value read/write specify input or output for port 2 pins
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 634 of 706 rej09b0303-0300 p1dr?port 1 data register h'ffb2 port 1 7 p1 7 dr 0 r/w 6 p1 6 dr 0 r/w 5 p1 5 dr 0 r/w 4 p1 4 dr 0 r/w 3 p1 3 dr 0 r/w 0 p1 0 dr 0 r/w 2 p1 2 dr 0 r/w 1 p1 1 dr 0 r/w bit initial value read/write output data for port 1 pins p2dr?port 2 data register h'ffb3 port 2 7 p2 7 dr 0 r/w 6 p2 6 dr 0 r/w 5 p2 5 dr 0 r/w 4 p2 4 dr 0 r/w 3 p2 3 dr 0 r/w 0 p2 0 dr 0 r/w 2 p2 2 dr 0 r/w 1 p2 1 dr 0 r/w bit initial value read/write output data for port 2 pins p3ddr?port 3 data direction register h'ffb4 port 3 7 p3 7 ddr 0 w 6 p3 6 ddr 0 w 5 p3 5 ddr 0 w 4 p3 4 ddr 0 w 3 p3 3 ddr 0 w 0 p3 0 ddr 0 w 2 p3 2 ddr 0 w 1 p3 1 ddr 0 w bit initial value read/write specify input or output for port 3 pins
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 635 of 706 rej09b0303-0300 p4ddr?port 4 data direction register h'ffb5 port 4 7 p4 7 ddr 0 w 6 p4 6 ddr 0 w 5 p4 5 ddr 0 w 4 p4 4 ddr 0 w 3 p4 3 ddr 0 w 0 p4 0 ddr 0 w 2 p4 2 ddr 0 w 1 p4 1 ddr 0 w bit initial value read/write specify input or output for port 4 pins p3dr?port 3 data register h'ffb6 port 3 7 p3 7 dr 0 r/w 6 p3 6 dr 0 r/w 5 p3 5 dr 0 r/w 4 p3 4 dr 0 r/w 3 p3 3 dr 0 r/w 0 p3 0 dr 0 r/w 2 p3 2 dr 0 r/w 1 p3 1 dr 0 r/w bit initial value read/write output data for port 3 pins p4dr?port 4 data register h'ffb7 port 4 7 p4 7 dr 0 r/w 6 p4 6 dr ? * r 5 p4 5 dr 0 r/w 4 p4 4 dr 0 r/w 3 p4 3 dr 0 r/w 0 p4 0 dr 0 r/w 2 p4 2 dr 0 r/w 1 p4 1 dr 0 r/w bit initial value read/write note: * determined by the state of pin p4 6 . output data for port 4 pins
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 636 of 706 rej09b0303-0300 p5ddr?port 5 data direction register h'ffb8 port 5 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 p5 0 ddr 0 w 2 p5 2 ddr 0 w 1 p5 1 ddr 0 w bit initial value read/write specify input or output for port 5 pins p6ddr?port 6 data direction register h'ffb9 port 6 7 p6 7 ddr 0 w 6 p6 6 ddr 0 w 5 p6 5 ddr 0 w 4 p6 4 ddr 0 w 3 p6 3 ddr 0 w 0 p6 0 ddr 0 w 2 p6 2 ddr 0 w 1 p6 1 ddr 0 w bit initial value read/write specify input or output for port 6 pins p5dr?port 5 data register h'ffba port 5 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 p5 0 dr 0 r/w 2 p5 2 dr 0 r/w 1 p5 1 dr 0 r/w bit initial value read/write output data for port 5 pins
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 637 of 706 rej09b0303-0300 p6dr?port 6 data register h'ffbb port 6 7 p6 7 dr 0 r/w 6 p6 6 dr 0 r/w 5 p6 5 dr 0 r/w 4 p6 4 dr 0 r/w 3 p6 3 dr 0 r/w 0 p6 0 dr 0 r/w 2 p6 2 dr 0 r/w 1 p6 1 dr 0 r/w bit initial value read/write output data for port 6 pins p7pin?port 7 input data register h'ffbe port 7 7 p7 7 pin ? * r 6 p7 6 pin ? * r 5 p7 5 pin ? * r 4 p7 4 pin ? * r 3 p7 3 pin ? * r 0 p7 0 pin ? * r 2 p7 2 pin ? * r 1 p7 1 pin ? * r bit initial value read/write note: * determined by the state of pins p7 7 to p7 0 . port 7 pin states ier?irq enable register h'ffc2 interrupt controller 7 ? 1 r 6 ? 1 r 5 ? 1 r 4 ? 1 r 3 ? 1 r 0 irq0e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w bit initial value read/write irq2 to irq0 enable 0 irqn interrupt disabled 1 irqn interrupt enabled (n = 2 to 0)
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 638 of 706 rej09b0303-0300 stcr?serial timer control register h'ffc3 system 7 ? 0 r/w 6 iicx1 0 r/w 5 iicx0 0 r/w 4 iice 0 r/w 3 ? 0 r/w 0 icks0 0 r/w 2 usbe 0 r/w 1 icks1 0 r/w bit initial value r/w : : : i 2 c transfer rate select 1 and 0 * 2 0 1 cpu access to i 2 c bus interface data registers and control registers is disabled cpu access to i 2 c bus interface data registers and control registers is enabled 0 1 cpu access to usb data registers and control registers is disabled cpu access to usb data registers and control registers is enabled i 2 c master enable usb enable reserved reserved internal clock source select * 1 notes: 1. used for 8-bit timer input clock selection. for details see section 12.2.4, timer control register (tcr). 2. used for i 2 c bus interface transfer clock selection. for details see section 16.2.4, i 2 c bus mode register (icmr).
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 639 of 706 rej09b0303-0300 syscr?system control register h'ffc4 system 7 cs2e 0 r/w 6 iose 0 r/w 5 intm1 0 r 4 intm0 0 r 3 xrst 1 r 0 rame 1 r/w 2 nmieg 0 r/w 1 hie 0 r/w bit initial value read/write ram enable 0 on-chip ram is disabled 1 on-chip ram is enabled host interface enable 0 in areas h'fff0 to h'fff7 and h'fffc to h'ffff, cpu access to 8-bit timer (channel x and y) data registers and control registers, and timer connection control registers, is permitted 1 in areas h'fff0 to h'fff7 and h'fffc to h'ffff, cpu access to 8-bit timer (channel x and y) data registers and control registers, and timer connection control registers, is not permitted nmi edge select 0 interrupt request generated by nmi falling edge 1 interrupt request generated by nmi rising edge external reset 0 reset generated by watchdog timer overflow 1 reset generated by external reset interrupt control mode 1 and 0 intm1 interrupts are controlled by i bit cannot be used in these groups cannot be used in these groups cannot be used in these groups intm0 interrupt control mode description 0 1 00 1 2 3 1 0 1 ios enable do not set this bit to 1. chip select 2 enable do not set this bit to 1.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 640 of 706 rej09b0303-0300 mdcr?mode control register h'ffc5 system 7 expe 0 * r 6 ? 0 ? 5 ? 0 ? 4 ? 0 ? 3 ? 0 ? 0 mds0 1 * r 2 ? 0 ? 1 mds1 1 * r bit initial value read/write expanded mode enable mode select 1 and 0 mode pin states. note: * determined by the md 1 and md 0 pins (h8/3577 group) or the test pin (h8/3567 group). bcr?bus control register h'ffc6 bus controller 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r 4 brsts1 1 r/w 3 brsts0 0 r 0 ios0 1 r/w 2 ? 1 r/w 1 ios1 1 r/w bit initial value read/write do not write any values other than the initial values. wscr?wait state control register h'ffc7 bus controller 7 rams 0 r/w 6 ram0 0 r/w 5 abw 1 r/w 4 ast 1 r/w 3 wms1 0 r/w 0 wc0 1 r/w 2 wms0 0 r/w 1 wc1 1 r/w bit initial value read/write do not write any values other than the initial values.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 641 of 706 rej09b0303-0300 tcr0?timer control register 0 h'ffc8 tmr 0 tcr1?timer control register 1 h'ffc9 tmr 1 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write clock select 2 to 0 channel bit 2 bit 1 bit 0 cks2 0 1 x y common 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 cks1 cks0 description clock input disabled /8 internal clock source, counted on falling edge /2 internal clock source, counted on falling edge /64 internal clock source, counted on falling edge /32 internal clock source, counted on falling edge /1024 internal clock source, counted on falling edge /256 internal clock source, counted on falling edge counted on tcnt1 overflow signal * 2 clock input disabled /8 internal clock source, counted on falling edge /2 internal clock source, counted on falling edge /64 internal clock source, counted on falling edge /128 internal clock source, counted on falling edge /1024 internal clock source, counted on falling edge /2048 internal clock source, counted on falling edge counted on tcnt0 compare-match a * 2 clock input disabled counted on internal clock source /2 internal clock source, counted on falling edge /4 internal clock source, counted on falling edge clock input disabled clock input disabled /4 internal clock source, counted on falling edge /256 internal clock source, counted on falling edge /2048 internal clock source, counted on falling edge clock input disabled external clock source, counted on rising edge external clock source, counted on falling edge external clock source, counted on both rising and falling edges * 1 * 1 * 1 * 1 * 1 * 1 notes: 1. 2. selected by icks1 and icks0 in stcr. for details see section 12.2.4, timer control register (tcr). if the count input of channel 0 is the tcnt1 overflow signal and that of channel 1 is the tcnt0 compare-match signal, no incrementing clock will be generated. do not use this setting. counter clear 1 and 0 0 clearing is disabled cleared on compare- match a 0 1 1 cleared on compare- match b 0 cleared on rising edge of external reset input 1 timer overflow interrupt enable 0 ovf interrupt request (ovi) is disabled 1 ovf interrupt request (ovi) is enabled compare-match interrupt enable a 0 cmfa interrupt request (cmia) is disabled 1 cmfa interrupt request (cmia) is enabled compare-match interrupt enable b 0 cmfb interrupt request (cmib) is disabled 1 cmfb interrupt request (cmib) is enabled
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 642 of 706 rej09b0303-0300 tcsr0?timer control/status register 0 h'ffca tmr 0 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 adte 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value read/write tcsr0 output select 1 and 0 0 no change when compare-match a occurs 0 0 output when compare-match a occurs 1 1 1 output when compare-match a occurs 0 output inverted when compare-match a occurs (toggle output) 1 note: * only 0 can be written in bits 7 to 5, to clear the flags. output select 3 and 2 0 no change when compare-match b occurs 0 0 output when compare-match b occurs 1 1 1 output when compare-match b occurs 0 output inverted when compare-match b occurs (toggle output) 1 a/d trigger enable 0 a/d converter start requests by compare-match a are disabled 1 a/d converter start requests by compare-match a are enabled timer overflow flag 0 [clearing condition] when 0 is written in ovf after reading ovf = 1 1 [setting condition] when tcnt overflows from h'ff to h'00 compare-match flag a 0 [clearing condition] when 0 is written in cmfa after reading cmfa = 1 1 [setting condition] when tcnt = tcora compare-match flag b 0 [clearing condition] when 0 is written in cmfb after reading cmfb = 1 1 [setting condition] when tcnt = tcorb
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 643 of 706 rej09b0303-0300 tcsr1?timer control/status register 1 h'ffcb tmr 1 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 ? 1 ? 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value read/write tcsr1 output select 1 and 0 0 no change when compare-match a occurs 0 0 output when compare-match a occurs 1 1 1 output when compare-match a occurs 0 output inverted when compare-match a occurs (toggle output) 1 output select 3 and 2 0 no change when compare-match b occurs 0 0 output when compare-match b occurs 1 1 1 output when compare-match b occurs 0 output inverted when compare-match b occurs (toggle output) 1 timer overflow flag 0 [clearing condition] when 0 is written in ovf after reading ovf = 1 1 [setting condition] when tcnt overflows from h'ff to h'00 compare-match flag a 0 [clearing condition] when 0 is written in cmfa after reading cmfa = 1 1 [setting condition] when tcnt = tcora compare-match flag b 0 [clearing condition] when 0 is written in cmfb after reading cmfb = 1 1 [setting condition] when tcnt = tcorb note: * only 0 can be written in bits 7 to 5, to clear the flags.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 644 of 706 rej09b0303-0300 tcora0?time constant register a0 h'ffcc tmr 0 tcora1?time constant register a1 h'ffcd tmr 1 tcorb0?time constant register b0 h'ffce tmr 0 tcorb1?time constant register b1 h'ffcf tmr 1 15 1 r/w bit initial value read/write 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora0 tcorb0 tcora1 tcorb1 compare-match flag (cmf) is set when tcor and tcnt values match tcnt0?timer counter 0 h'ffd0 tmr 0 tcnt1?timer counter 1 h'ffd1 tmr 1 15 0 r/w bit initial value read/write 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w tcnt0 tcnt1 up-counter
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 645 of 706 rej09b0303-0300 pwoerb?pwm output enable register b h'ffd2 pwm pwoera?pwm output enable register a h'ffd3 pwm 7 oe15 0 r/w 6 oe14 0 r/w 5 oe13 0 r/w 4 oe12 0 r/w 3 oe11 0 r/w 0 oe8 0 r/w 2 oe10 0 r/w 1 oe9 0 r/w bit pwoerb initial value read/write 7 oe7 0 r/w 6 oe6 0 r/w 5 oe5 0 r/w 4 oe4 0 r/w 3 oe3 0 r/w switching between pwm output and port output 0 oe0 0 r/w 2 oe2 0 r/w 1 oe1 0 r/w bit pwoera initial value read/write 0 1 0 1 0 1 port input port input port output or pwm 256/256 output pwm output (0 to 255/256 output) ddr oe description
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 646 of 706 rej09b0303-0300 pwdprb?pwm data polarity register b h'ffd4 pwm pwdpra?pwm data polarity register a h'ffd5 pwm 7 os15 0 r/w 6 os14 0 r/w 5 os13 0 r/w 4 os12 0 r/w 3 os11 0 r/w 0 os8 0 r/w 2 os10 0 r/w 1 os9 0 r/w bit pwdprb initial value read/write 7 os7 0 r/w 6 os6 0 r/w 5 os5 0 r/w 4 os4 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit pwdpra initial value read/write pwm output polarity control 0 pwm direct output (pwdr value corresponds to high width of output) 1 pwm inverted output (pwdr value corresponds to low width of output)
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 647 of 706 rej09b0303-0300 pwsl?pwm register select h'ffd6 pwm 7 pwcke 0 r/w 6 pwcks 0 r/w 5 ? 1 ? 4 ? 0 ? 3 rs3 0 r/w 0 rs0 0 r/w 2 rs2 0 r/w 1 rs1 0 r/w bit initial value read/write 0 1 pwdr0 selected pwdr1 selected pwdr2 selected pwdr3 selected pwdr4 selected pwdr5 selected pwdr6 selected pwdr7 selected pwdr8 selected pwdr9 selected pwdr10 selected pwdr11 selected pwdr12 selected pwdr13 selected pwdr14 selected pwdr15 selected register select 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 pwm clock enable, pwm clock select clock input disabled (system clock) selected /2 selected /4 selected /8 selected /16 selected pwsl pcsr bit 2 pwckb ? ? 0 1 bit 1 pwcka ? ? 0 1 0 1 bit 7 pwcke 0 1 bit 6 pwcks ? 0 1 description
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 648 of 706 rej09b0303-0300 pwdr0 to pwdr15?pwm data registers h'ffd7 pwm 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w specifies duty cycle of basic output pulse and number of additional pulses 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 649 of 706 rej09b0303-0300 iccr0?i 2 c bus control register 0 h'ffd8 iic0 7 ice 0 r/w 6 ieic 0 r/w 5 mst 0 r/w 4 trs 0 r/w 3 acke 0 r/w 0 scp 1 w 2 bbsy 0 r/w 1 iric 0 r/(w) * bit initial value read/write start condition/stop condition prohibit 0 writing issues a start or stop condition, in combination with the bbsy flag 1 reading always returns a value of 1; writing is invalid i 2 c bus interface interrupt request flag 0 waiting for transfer, or transfer in progress 1 interrupt requested note: for the clearing and setting conditions, see section 16.2.5, i 2 c bus control register (iccr). bus busy 0 bus is free [clearing condition] when a stop condition is detected 1 bus is busy [setting condition] when a start condition is detected acknowledge bit judgement select 0 acknowledge bit is ignored and continuous transfer is performed 1 if acknowledge bit is 1, continuous transfer is interrupted master/slave select (mst), transmit/receive select (trs) 0 slave receive mode slave transmit mode master receive mode master transmit mode 0 1 10 1 i 2 c bus interface interrupt enable 0 interrupt requests disabled 1 interrupt requests enabled note: for details see section 16.2.5, i 2 c bus control register (iccr). i 2 c bus interface enable 0 i 2 c bus interface module disabled, with scl and sda signal pins set to port function sar and sarx can be accessed 1i 2 c bus interface module enabled for transfer operations (pins scl and sda are driving the bus) icmr and icdr can be accessed note: * only 0 can be written, to clear the flag.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 650 of 706 rej09b0303-0300 smr0?serial mode register 0 h'ffd8 sci0 bit initial value read/write 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and lsb-first/msb-first selection is not available. clock select 1 and 0 0 clock 1 0 1 0 1 /4 clock /16 clock /64 clock multiprocessor mode 0 multiprocessor function disabled 1 multiprocessor format selected stop bit length 0 1 stop bit * 1 1 2 stop bits * 2 parity mode 0 0 even parity * 1 1 odd parity * 2 notes: 1. when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. notes: 1. in transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 2. in transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. parity enable parity bit addition and checking disabled 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. character length 0 8-bit data 1 7-bit data * communication mode 0 asynchronous mode 1 synchronous mode
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 651 of 706 rej09b0303-0300 brr0?bit rate register 0 h'ffd9 sci0 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w sets the serial transmit/receive bit rate 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 652 of 706 rej09b0303-0300 icsr0?i 2 c bus status register 0 h'ffd9 iic0 7 estp 0 r/(w) * 1 6 stop 0 r/(w) * 1 5 irtr 0 r/(w) * 1 4 aasx 0 r/(w) * 1 3 al 0 r/(w) * 1 0 ackb 0 r/w 2 aas 0 r/(w) * 1 1 adz 0 r/(w) * 1 bit initial value read/write acknowledge bit 0 receive mode: 0 is output at acknowledge output timing transmit mode: indicates that the receiving device has acknowledged the data (0 value) 1 receive mode: 1 is output at acknowledge output timing transmit mode: indicates that the receiving device has not acknowledged the data (1 value) notes: general call address recognition flag * 2 0 general call address not recognized 1 general call address recognized slave address recognition flag * 2 0 slave address or general call address not recognized 1 slave address or general call address recognized arbitration lost flag * 2 0 bus arbitration won 1 bus arbitration lost second slave address recognition flag * 2 0 second slave address not recognized 1 second slave address recognized i 2 c bus interface continuous transmission/reception interrupt request flag * 2 0 waiting for transfer, or transfer in progress 1 continuous transfer state normal stop condition detection flag * 2 0 no normal stop condition 1in i 2 c bus format slave mode: normal stop condition detected in other modes: no meaning error stop condition detection flag * 2 0 no error stop condition 1in i 2 c bus format slave mode: error stop condition detected in other modes: no meaning 1. only 0 can be written, to clear the flag. 2. for the clearing and setting conditions, see section 16.2.6, i 2 c bus status register (icsr).
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 653 of 706 rej09b0303-0300 scr0?serial control register 0 h'ffda sci0 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 2 teie 0 r/w 1 cke1 0 r/w 0 cke0 0 r/w 0 asynchronous mode synchronous mode clock enable 1 and 0 asynchronous mode synchronous mode asynchronous mode 1 synchronous mode asynchronous mode synchronous mode 0 0 1 1 internal clock/sck pin functions as i/o port internal clock/sck pin functions as serial clock output internal clock/sck pin functions as clock output internal clock/sck pin functions as serial clock output external clock/sck pin functions as clock input external clock/sck pin functions as serial clock input external clock/sck pin functions as clock input external clock/sck pin functions as serial clock input 0 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit end interrupt enable 1 0 reception disabled reception enabled receive enable 1 0 multiprocessor interrupts disabled (normal reception performed) [clearing conditions] when the mpie bit is cleared to 0 when data with mpb = 1 is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received multiprocessor interrupt enable 1 0 transmission disabled transmission enabled transmit enable 1 0 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled receive interrupt enable 1 0 transmit data empty interrupt (txi) request disabled transmit data empty interrupt (txi) request enabled transmit interrupt enable 1
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 654 of 706 rej09b0303-0300 tdr0?transmit data register 0 h'ffdb sci0 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w serial transmit data 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 655 of 706 rej09b0303-0300 ssr0?serial status register 0 h'ffdc sci0 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value read/write multiprocessor bit transfer 0 data with a 0 multiprocessor bit is transmitted 1 data with a 1 multiprocessor bit is transmitted multiprocessor bit 0 [clearing condition] when data with a 0 multiprocessor bit is received 1 [setting condition] when data with a 1 multiprocessor bit is received transmit end 0 [clearing condition] when 0 is written in tdre after reading tdre = 1 1 [setting conditions] when the te bit in scr is 0 when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character parity error 0 clearing condition] when 0 is written in per after reading per = 1 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr framing error 0 [clearing condition] when 0 is written in fer after reading fer = 1 1 [setting condition] when the sci checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 overrun error 0 [clearing condition] when 0 is written in orer after reading orer = 1 1 [setting condition] when the next serial reception is completed while rdrf = 1 receive data register full 0 [clearing condition] when 0 is written in rdrf after reading rdrf = 1 1 [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 [clearing condition] when 0 is written in tdre after reading tdre = 1 1 [setting conditions] when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written in tdr note: * only 0 can be written, to clear the flag.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 656 of 706 rej09b0303-0300 rdr0?receive data register 0 h'ffdd sci0 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r serial receive data 0 0 r 2 0 r 1 0 r bit initial value read/write scmr0?serial interface mode register 0 h'ffde sci0 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 ? 1 ? bit initial value read/write serial communication interface mode select 0 normal sci mode 1 setting prohibited data invert 0 tdr contents are transmitted without modification receive data is stored in rdr without modification 1 tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form data transfer direction 0 tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 657 of 706 rej09b0303-0300 icdr0?i 2 c bus data register 0 h'ffde iic0 7 icdr7 ? r/w 6 icdr6 ? r/w 5 icdr5 ? r/w 4 icdr4 ? r/w 3 icdr3 ? r/w 0 icdr0 ? r/w 2 icdr2 ? r/w 1 icdr1 ? r/w bit initial value read/write 7 icdrr7 ? r 6 icdrr6 ? r 5 icdrr5 ? r 4 icdrr4 ? r 3 icdrr3 ? r 0 icdrr0 ? r 2 icdrr2 ? r 1 icdrr1 ? r bit initial value read/write icdrr icdrs 7 icdrs7 ? ? 6 icdrs6 ? ? 5 icdrs5 ? ? 4 icdrs4 ? ? 3 icdrs3 ? ? 0 icdrs0 ? ? 2 icdrs2 ? ? 1 icdrs1 ? ? bit initial value read/write icdrt 7 icdrt7 ? w 6 icdrt6 ? w 5 icdrt5 ? w 4 icdrt4 ? w 3 icdrt3 ? w 0 icdrt0 ? w 2 icdrt2 ? w 1 icdrt1 ? w bit initial value read/write tdre, rdrf (internal flags) ? rdrf 0 ? ? tdre 0 ? bit initial value read/write note: for details see section 16.2.1, i 2 c bus data register (icdr).
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 658 of 706 rej09b0303-0300 sarx0?second slave address register 0 h'ffde iic0 second slave address 7 svax6 0 r/w 6 svax5 0 r/w 5 svax4 0 r/w 4 svax3 0 r/w 3 svax2 0 r/w 0 fsx 1 r/w 2 svax1 0 r/w 1 svax0 0 r/w bit initial value read/write note: * format select ddcswr bit 6 sw sar bit 0 fs sarx bit 0 fsx operating mode i 2 c bus format sar and sarx slave addresses recognized 0 00 i 2 c bus format sar slave address recognized sarx slave address ignored i 2 c bus format sar slave address ignored sarx slave address recognized synchronous serial format sar and sarx slave addresses ignored formatless mode (start/stop conditions not detected) acknowledge bit present formatless mode * (start/stop conditions not detected) no acknowledge bit 1 10 1 100 1 10 1 do not select this mode when automatic switching to the i 2 c bus format is performed by means of a ddcswr setting.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 659 of 706 rej09b0303-0300 sar0?slave address register 0 h'ffdf iic0 slave address 7 sva6 0 r/w 6 sva5 0 r/w 5 sva4 0 r/w 4 sva3 0 r/w 3 sva2 0 r/w 0 fs 0 r/w 2 sva1 0 r/w 1 sva0 0 r/w bit initial value read/write note: * format select ddcswr bit 6 sw sar bit 0 fs sarx bit 0 fsx operating mode i 2 c bus format sar and sarx slave addresses recognized 0 00 i 2 c bus format sar slave address recognized sarx slave address ignored i 2 c bus format sar slave address ignored sarx slave address recognized synchronous serial format sar and sarx slave addresses ignored formatless mode (start/stop conditions not detected) acknowledge bit present formatless mode * (start/stop conditions not detected) no acknowledge bit 1 10 1 100 1 10 1 do not select this mode when automatic switching to the i 2 c bus format is performed by means of a ddcswr setting.
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 660 of 706 rej09b0303-0300 icmr0?i 2 c bus mode register 0 h'ffdf iic0 7 mls 0 r/w 6 wait 0 r/w 5 cks2 0 r/w 4 cks1 0 r/w 3 cks0 0 r/w 0 bc0 0 r/w 2 bc2 0 r/w 1 bc1 0 r/w bit initial value read/write bit counter bc2 bc1 0 1 0 1 0 1 bc0 0 1 0 1 0 1 0 1 note: * do not set this bit to 1 when using the i 2 c bus format. synchronous serial format 8 1 2 3 4 5 6 7 i 2 c bus format 9 2 3 4 5 6 7 8 transfer clock select cks2 cks1 0 1 0 1 0 1 0 1 0 1 0 1 cks0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 iicx 0 1 clock /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 wait insertion bit 0 data and acknowledge transferred consecutively 1 wait inserted between data and acknowledge msb-first/lsb-first select * 0 msb-first 1 lsb-first
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 661 of 706 rej09b0303-0300 addrah?a/d data register ah h'ffe0 a/d addral?a/d data register al h'ffe1 a/d addrbh?a/d data register bh h'ffe2 a/d addrbl?a/d data register bl h'ffe3 a/d addrch?a/d data register ch h'ffe4 a/d addrcl?a/d data register cl h'ffe5 a/d addrdh?a/d data register dh h'ffe6 a/d addrdl?a/d data register dl h'ffe7 a/d 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 ? 0 r 4 ? 0 r 2 ? 0 r 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 ? 0 r 5 ? 0 r 3 ? 0 r bit initial value read/write addrh a/d data correspondence between analog input channels and addr registers addrl addra addrb addrc addrd group 0 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 group 1 analog input channel a/d data register
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 662 of 706 rej09b0303-0300 adcsr?a/d control/status register h'ffe8 a/d converter 7 adf 0 r/(w) 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w * bit initial value read/write channel select 0 1 0 1 0 1 0 1 0 1 0 1 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 description an 0 an 0 , an 1 an 0 , an 1 , an 2 an 0 , an 1 , an 2 , an 3 an 4 an 4 , an 5 an 4 , an 5 , an 6 an 4 , an 5 , an 6 , an 7 group selection h8/3577 group / h8/3567 group h8/3577 group only ch1 ch0 single mode scan mode ch2 0 1 note: * only 0 can be written, to clear the flag. channel selection clock select 0 conversion time = 266 states (max.) 1 conversion time = 134 states (max.) scan mode 0 single mode 1 scan mode a/d interrupt enable 0 a/d conversion end interrupt (adi) request disabled 1 a/d conversion end interrupt (adi) request enabled a/d end flag 0 [clearing condition] when 0 is written in adf after reading adf = 1 1 [setting conditions] single mode: when a/d conversion ends scan mode: when a/d conversion ends on all specified channels a/d start 0 a/d conversion stopped 1 single mode: a/d conversion is started. cleared to 0 automatically when conversion on the specified channel ends scan mode: a/d conversion is started. conversion continues consecutively on the selected channels until adst is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 663 of 706 rej09b0303-0300 adcr?a/d control register h'ffe9 a/d 7 trgs1 0 r/w 6 trgs0 0 r/w 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 ? 1 ? 2 ? 1 ? 1 ? 1 ? bit initial value read/write timer trigger select 0 start of a/d conversion by external trigger is disabled start of a/d conversion by external trigger is disabled start of a/d conversion by external trigger (8-bit timer) is enabled start of a/d conversion by external trigger pin is enabled 0 1 10 1
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 664 of 706 rej09b0303-0300 tcrx?timer control register x h'fff0 tmrx tcry?timer control register y h'fff0 tmry 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write clock select 2 to 0 channel bit 2 bit 1 bit 0 cks2 0 1 x y common 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 cks1 cks0 description clock input disabled /8 internal clock source, counted on falling edge /2 internal clock source, counted on falling edge /64 internal clock source, counted on falling edge /32 internal clock source, counted on falling edge /1024 internal clock source, counted on falling edge /256 internal clock source, counted on falling edge counted on tcnt1 overflow signal * 2 clock input disabled /8 internal clock source, counted on falling edge /2 internal clock source, counted on falling edge /64 internal clock source, counted on falling edge /128 internal clock source, counted on falling edge /1024 internal clock source, counted on falling edge /2048 internal clock source, counted on falling edge counted on tcnt0 compare-match a * 2 clock input disabled counted on internal clock source /2 internal clock source, counted on falling edge /4 internal clock source, counted on falling edge clock input disabled clock input disabled /4 internal clock source, counted on falling edge /256 internal clock source, counted on falling edge /2048 internal clock source, counted on falling edge clock input disabled external clock source, counted on rising edge external clock source, counted on falling edge external clock source, counted on both rising and falling edges * 1 * 1 * 1 * 1 * 1 * 1 notes: 1. 2. selected by icks1 and icks0 in stcr. for details see section 12.2.4, timer control register (tcr). if the count input of channel 0 is the tcnt1 overflow signal and that of channel 1 is the tcnt0 compare-match signal, no incrementing clock will be generated. do not use this setting. counter clear 1 and 0 0 clearing is disabled cleared on compare- match a 0 1 1 cleared on compare- match b 0 cleared on rising edge of external reset input 1 timer overflow interrupt enable 0 ovf interrupt request (ovi) is disabled 1 ovf interrupt request (ovi) is enabled compare-match interrupt enable a 0 cmfa interrupt request (cmia) is disabled 1 cmfa interrupt request (cmia) is enabled compare-match interrupt enable b 0 cmfb interrupt request (cmib) is disabled 1 cmfb interrupt request (cmib) is enabled
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 665 of 706 rej09b0303-0300 tcsrx?timer control/status register x h'fff1 tmrx 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 icf 0 r/(w) * 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value read/write tcsrx output select 1 and 0 0 no change when compare-match a occurs 0 0 output when compare-match a occurs 1 1 1 output when compare-match a occurs 0 output inverted when compare-match a occurs (toggle output) 1 note: * only 0 can be written in bits 7 to 4, to clear the flags. output select 3 and 2 0 no change when compare-match b occurs 0 0 output when compare-match b occurs 1 1 1 output when compare-match b occurs 0 output inverted when compare-match b occurs (toggle output) 1 input capture flag 0 [clearing condition] when 0 is written in icf after reading icf = 1 1 [setting condition] when a rising edge followed by a falling edge is detected in the external reset signal after the icst bit in tconri has been set to 1 timer overflow flag 0 [clearing condition] when 0 is written in ovf after reading ovf = 1 1 [setting condition] when tcnt overflows from h'ff to h'00 compare-match flag a 0 [clearing condition] when 0 is written in cmfa after reading cmfa = 1 1 [setting condition] when tcnt = tcora compare-match flag b 0 [clearing condition] when 0 is written in cmfb after reading cmfb = 1 1 [setting condition] when tcnt = tcorb
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 666 of 706 rej09b0303-0300 tcsry?timer control/status register y h'fff1 tmry 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 icie 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value read/write tcsry output select 1 and 0 0 no change when compare-match a occurs 0 0 output when compare-match a occurs 1 1 1 output when compare-match a occurs 0 output inverted when compare-match a occurs (toggle output) 1 note: * only 0 can be written in bits 7 to 5, to clear the flags. output select 3 and 2 0 no change when compare-match b occurs 0 0 output when compare-match b occurs 1 1 1 output when compare-match b occurs 0 output inverted when compare-match b occurs (toggle output) 1 input capture interrupt enable 0 icf interrupt request (icix) is disabled 1 icf interrupt request (icix) is enabled timer overflow flag 0 [clearing condition] when 0 is written in ovf after reading ovf = 1 1 [setting condition] when tcnt overflows from h'ff to h'00 compare-match flag a 0 [clearing condition] when 0 is written in cmfa after reading cmfa = 1 1 [setting condition] when tcnt = tcora compare-match flag b 0 [clearing condition] when 0 is written in cmfb after reading cmfb = 1 1 [setting condition] when tcnt = tcorb
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 667 of 706 rej09b0303-0300 ticrr?input capture register r h'fff2 tmrx ticrf?input capture register f h'fff3 tmrx 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value read/write stores tcnt value at fall of external reset input tcoray?time constant register ay h'fff2 tmry tcorby?time constant register by h'fff3 tmry 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write tcoray, tcorby compare-match flag (cmf) is set when tcor and tcnt values match tcntx?timer counter x h'fff4 tmrx tcnty?timer counter y h'fff4 tmry 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write up-counter
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 668 of 706 rej09b0303-0300 tisr?timer input select register h'fff5 tmry 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 ? 0 is 0 r/w 2 ? 1 ? 1 ? 1 ? bit initial value read/write input select 0 1 ivg signal is selected tmiy (tmciy/tmriy) is selected tcorc?time constant register c h'fff5 tmrx tcorax?time constant register ax h'fff6 tmrx tcorbx?time constant register bx h'fff7 tmrx 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write tcorax, tcorbx compare-match flag (cmf) is set when tcor and tcnt values match 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write tcorc compare-match c signal is generated when sum of tcorc and ticr contents match tcnt value
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 669 of 706 rej09b0303-0300 tconri?timer connection register i h'fffc timer connection bit initial value read/write 7 simod1 0 r/w 6 simod0 0 r/w 5 scone 0 r/w 4 icst 0 r/w 3 hfinv 0 r/w 0 viinv 0 r/w 2 vfinv 0 r/w 1 hiinv 0 r/w input synchronization mode select 1 and 0 0 1 no signal s-on-g mode composite mode separate mode 0 1 0 1 simod1 mode hfbacki input csynci input hsynci input hsynci input ihi signal vfbacki input pdc input pdc input vsynci input ivi signal simod0 synchronization signal connection enable 0 1 ftia input normal connection scone ftia ftib ftic ftid tmci1 tmri1 mode ftib input ftic input tmci1 input tmri1 input ftid input ivi signal synchronization signal connec- tion mode tmo1 signal vfbacki input ihi signal ivi inverse signal ihi signal input synchronization signal inversion 0 the vsynci pin state is used directly as the vsynci input 1 the vsynci pin state is inverted before use as the vsynci input input synchronization signal inversion 0 the hsynci and csynci pin states are used directly as the hsynci and csynci inputs 1 the hsynci and csynci pin states are inverted before use as the hsynci and csynci inputs input synchronization signal inversion 0 the vfbacki pin state is used directly as the vfbacki input 1 the vfbacki pin state is inverted before use as the vfbacki input input capture start bit 0 the ticrr and ticrf input capture functions are stopped [clearing condition] when a rising edge followed by a falling edge is detected on tmrix 1 the ticrr and ticrf input capture functions are operating (waiting for detection of a rising edge followed by a falling edge on tmrix) [setting condition] when 1 is written in icst after reading icst = 0 input synchronization signal inversion 0 the hfbacki pin state is used directly as the hfbacki input 1 the hfbacki pin state is inverted before use as the hfbacki input
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 670 of 706 rej09b0303-0300 tconro?timer connection register o h'fffd timer connection bit initial value read/write 7 hoe 0 r/w 6 voe 0 r/w 5 cloe 0 r/w 4 cboe 0 r/w 3 hoinv 0 r/w 0 cboinv 0 r/w 2 voinv 0 r/w 1 cloinv 0 r/w output synchronization signal inversion 0 the cblank signal is used directly as the cblank output 1 the cblank signal is inverted before use as the cblank output output synchronization signal inversion 0 the clo signal (cl 1 , cl 2 , cl 3 , or cl 4 signal) is used directly as the clampo output 1 the clo signal (cl 1 , cl 2 , cl 3 , or cl 4 signal) is inverted before use as the clampo output output synchronization signal inversion 0 the ivo signal is used directly as the vsynco output 1 the ivo signal is inverted before use as the vsynco output output synchronization signal inversion 0 the iho signal is used directly as the hsynco output 1 the iho signal is inverted before use as the hsynco output output enable 0 [h8/3577 group] the p2 7 /pw 15 /cblank pin functions as the p2 7 /pw 15 pin [h8/3567 group] the p1 5 /pw 5 /cblank pin functions as the p1 5 /pw 5 pin 1 [h8/3577 group] the p2 7 /pw 15 /cblank pin functions as the cblank pin [h8/3567 group] the p1 5 /pw 5 /cblank pin functions as the cblank pin output enable 0 the p6 4 /ftic/tmo 0 /clampo pin functions as the p6 4 /ftic/tmo 0 pin 1 the p6 4 /ftic/tmo 0 /clampo pin functions as the clampo pin output enable 0 the p6 1 /ftoa/vsynco pin functions as the p6 1 /ftoa pin 1 the p6 1 /ftoa/vsynco pin functions as the vsynco pin output enable 0 the p6 7 /tmo 1 /tmox/hsynco pin functions as the p6 7 /tmo 1 /tmox pin 1 the p6 7 /tmo 1 /tmox/hsynco pin functions as the hsynco pin
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 671 of 706 rej09b0303-0300 tconrs?timer connection register s h'fffe timer connection 7 tmrx/y 0 r/w 6 isgene 0 r/w 5 homod1 0 r/w 4 homod0 0 r/w 3 vomod1 0 r/w 0 clmod0 0 r/w 2 vomod0 0 r/w 1 clmod1 0 r/w bit initial value read/write clamp waveform mode select 1 and 0 clmod1 clmod0 0 1 0 1 0 1 0 1 0 1 0 1 description the cl 1 signal is selected the cl 2 signal is selected the cl 3 signal is selected the cl 4 signal is selected isgene 0 1 vertical synchronization output mode select 1 and 0 vomod1 vomod0 0 1 0 1 0 1 0 1 0 1 0 1 description isgene 0 1 horizontal synchronization output mode select 1 and 0 homod1 homod0 0 1 0 1 0 1 0 1 0 1 0 1 description the ihi signal (without 2fh modification) is selected the ihi signal (with 2fh modification) is selected the cl 1 signal is selected the ihg signal is selected isgene 0 1 the ivi signal (without fall modification or ihi synchronization) is selected the ivi signal (without fall modification, with ihi synchronization) is selected the ivi signal (with fall modification, without ihi synchronization) is selected the ivi signal (with fall modification and ihi synchronization) is selected the ivg signal is selected internal synchronization signal select tmrx/tmry access select 0 the tmrx registers are accessed at addresses h'fff0 to h'fff5 1 the tmry registers are accessed at addresses h'fff0 to h'fff5
appendix b internal i/o registers rev. 3.00 mar 17, 2006 page 672 of 706 rej09b0303-0300 sedgr?edge sense register h'ffff timer connection bit initial value read/write 7 vedg 0 r/(w) 6 hedg 0 r/(w) 5 cedg 0 r/(w) 4 hfedg 0 r/(w) 3 vfedg 0 r/(w) 0 ivi ? * 2 r 2 preqf 0 r/(w) 1 ihi ? * 2 r * 1 * 1 * 1 * 1 * 1 * 1 ivi signal level 0 the ivi signal is low 1 the ivi signal is high notes: 1. 2. ihi signal level 0 the ihi signal is low 1 the ihi signal is high pre-equalization flag 0 [clearing condition] when 0 is written in preqf after reading preqf = 1 1 [setting condition] when an ihi signal 2fh modification condition is detected vfbacki edge 0 [clearing condition] when 0 is written in vfedg after reading vfedg = 1 1 [setting condition] when a rising edge is detected on the vfbacki pin hfbacki edge 0 [clearing condition] when 0 is written in hfedg after reading hfedg = 1 1 [setting condition] when a rising edge is detected on the hfbacki pin csynci edge 0 [clearing condition] when 0 is written in cedg after reading cedg = 1 1 [setting condition] when a rising edge is detected on the csynci pin hsynci edge 0 [clearing condition] when 0 is written in hedg after reading hedg = 1 1 [setting condition] when a rising edge is detected on the hsynci pin vsynci edge 0 [clearing condition] when 0 is written in vedg after reading vedg = 1 1 [setting condition] when a rising edge is detected on the vsynci pin only 0 can be written, to clear the flag. the initial value is undefined since it depends on the pin states.
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 673 of 706 rej09b0303-0300 appendix c i/o port block diagrams c.1 port 1 block diagrams d r qd p1ndr c reset r q p1nddr rp1p c reset wp1d d r q p1npcr c reset wp1d wp1 internal data bus 8-bit pwm pwm output enable pwm output output enable 14-bit pwm pwx 0 and pwx 1 output p1n rp1 hardware standby legend: wp1d: write to p1ddr wp1p: write to p1pcr rp1p: read p1pcr wp1: write to port 1 rp1: read port 1 notes: n = 0 or 1 * mos input pull-up applies to the h8/3577 group only. * figure c.1 port 1 block diagram (pins p1 0 and p1 1 )
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 674 of 706 rej09b0303-0300 d r qd p1ndr c reset r q p1nddr c reset wp1d wp1 8-bit pwm pwm output enable pwm output p1n rp1 rp1p d r q p1npcr c reset wp1d * legend: wp1d: write to p1ddr wp1p: write to p1pcr rp1p: read p1pcr wp1: write to port 1 rp1: read port 1 notes: n = 2 to 7 * mos input pull-up applies to the h8/3577 group only. internal data bus hardware standby figure c.2 port 1 block diagram (pins p1 2 to p1 7 in h8/3577 group, pins p1 2 to p1 4 in h8/3567 group)
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 675 of 706 rej09b0303-0300 d r qd p1 5 dr c reset r q p1 5 ddr c reset wp1d wp1 8-bit pwm pwm output enable pwm output timer connection cblank cblank output enable p1 5 rp1 hardware standby legend: wp1d: write to p1ddr wp1: write to port 1 rp1: read port 1 internal data bus figure c.3 port 1 block diagram (pin p1 5 in h8/3567 group)
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 676 of 706 rej09b0303-0300 d r qd p1 6 dr c reset r q p1 6 ddr c reset wp1d wp1 8-bit pwm pwm output enable pwm output iic1 sda 1 output sda 1 input transmit enable p1 6 rp1 hardware standby * 1 * 2 internal data bus legend: wp1d: write to p1ddr wp1: write to port 1 rp1: read port 1 notes: 1. output enable signal 2. open drain control signal figure c.4 port 1 block diagram (pin p1 6 in h8/3567 group)
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 677 of 706 rej09b0303-0300 d r qd p1 7 dr c reset r s q p1 7 ddr c mode 1 reset wp1d wp1 8-bit pwm pwm output enable pwm output iic1 scl 1 output scl 1 input transmit enable p1 7 rp1 legend: wp1d: write to p1ddr wp1: write to port 1 rp1: read port 1 notes: 1. output enable signal 2. open drain control signal * 1 * 2 internal data bus hardware standby figure c.5 port 1 block diagram (pin p1 7 in h8/3567 group)
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 678 of 706 rej09b0303-0300 c.2 port 2 block diagrams port 2 is provided only in the h8/3577 group, and not in the h8/3567 group. d r qd p2ndr c reset r q p2nddr c reset wp2d wp2 8-bit pwm pwm output enable pwm output p2n rp2 legend: wp2d: write to p2ddr wp2p: write to p2pcr rp2p: read p2pcr wp2: write to port 2 rp2: read port 2 note: n = 0 to 2, 5, 6 rp2p d r q p2npcr c reset wp2d internal data bus hardware standby figure c.6 port 2 block diagram (pins p2 0 to p2 2 , p2 5 , and p2 6 in h8/3577 group)
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 679 of 706 rej09b0303-0300 d r qd p2 3 dr c reset r q p2 3 ddr c reset wp2d wp2d wp2 8-bit pwm pwm output enable pwm output iic1 sda 1 output sda 1 input transmit enable p2 3 rp2 * 1 * 2 rp2p d r q p2 3 pcr c reset legend: wp2d: write to p2ddr wp2p: write to p2pcr rp2p: read p2pcr wp2: write to port 2 rp2: read port 2 notes: 1. output enable signal 2. open drain control signal internal data bus hardware standby figure c.7 port 2 block diagram (pin p2 3 in h8/3577 group)
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 680 of 706 rej09b0303-0300 d r qd p2 4 dr c reset r q p2 4 ddr c reset wp2d wp2 8-bit pwm pwm output enable pwm output iic1 scl 1 output scl 1 input transmit enable p2 4 rp2 * 1 * 2 legend: wp2d: write to p2ddr wp2p: write to p2pcr rp2p: read p2pcr wp2: write to port 2 rp2: read port 2 notes: 1. output enable signal 2. open drain control signal rp2p d r q p2 4 pcr c reset wp2d internal data bus hardware standby figure c.8 port 2 block diagram (pin p2 4 in h8/3577 group)
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 681 of 706 rej09b0303-0300 d r qd p2 7 dr c reset r q p2 7 ddr c reset wp2d wp2 8-bit pwm pwm output enable pwm output timer connection cblank cblank output enable p2 7 rp2 rp2p d r q p2 7 pcr wp2d legend: wp2d: write to p2ddr wp2p: write to p2pcr rp2p: read p2pcr wp2: write to port 2 rp2: read port 2 internal data bus hardware standby reset c figure c.9 port 2 block diagram (pin p2 7 in h8/3577 group)
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 682 of 706 rej09b0303-0300 c.3 port 3 block diagram port 3 is provided only in the h8/3577 group, and not in the h8/3567 group. d r qd p3ndr c reset r q p3nddr c reset wp3d wp3 p3n rp3 legend: wp3d: write to p3ddr wp3p: write to p3pcr rp3p: read p3pcr wp3: write to port 3 rp3: read port 3 note: n = 0 to 7 rp3p d r q p3npcr c reset wp3d internal data bus hardware standby figure c.10 port 3 block diagram (pins p3 0 to p3 7 in h8/3577 group)
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 683 of 706 rej09b0303-0300 c.4 port 4 block diagrams d r qd p4 0 dr c reset r q p4 0 ddr c reset wp4d wp4 a/d converter external trigger input p4 0 rp4 legend: wp4d: write to p4ddr wp4: write to port 4 rp4: read port 4 irq2 input internal data bus hardware standby figure c.11 port 4 block diagram (pin p4 0 )
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 684 of 706 rej09b0303-0300 d r qd p4ndr c reset r q p4nddr c reset wp4d wp4 irq1 input irq0 input p4n rp4 legend: wp4d: write to p4ddr wp4: write to port 4 rp4: read port 4 note: n = 1 or 2 internal data bus hardware standby figure c.12 port 4 block diagram (pins p4 1 and p4 2 )
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 685 of 706 rej09b0303-0300 d r qd p4ndr c reset r q p4nddr c reset wp4d wp4 p4n rp4 legend: wp4d: write to p4ddr wp4: write to port 4 rp4: read port 4 note: n = 3 to 5 internal data bus hardware standby figure c.13 port 4 block diagram (pins p4 3 to p4 5 )
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 686 of 706 rej09b0303-0300 d r q p4 6 ddr c reset wp4d output p4 6 legend: wp4d: write to p4ddr rp4: read port 4 rp4 internal data bus hardware standby figure c.14 port 4 block diagram (pin p4 6 )
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 687 of 706 rej09b0303-0300 d r qd p4 7 dr c reset r q p4 7 ddr c reset wp4d wp4 iic0 sda 0 input sda 0 output transmit enable p4 7 rp4 legend: wp4d: write to p4ddr wp4: write to port 4 rp4: read port 4 notes: 1. output enable signal 2. open drain control signal * 1 * 2 internal data bus hardware standby figure c.15 port 4 block diagram (pin p4 7 )
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 688 of 706 rej09b0303-0300 c.5 port 5 block diagrams d r qd p5 0 dr c reset r q p5 0 ddr c reset wp5d wp5 sci0 serial transmit data output enable p5 0 rp5 legend: wp5d: write to p5ddr wp5: write to port 5 rp5: read port 5 internal data bus hardware standby figure c.16 port 5 block diagram (pin p5 0 )
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 689 of 706 rej09b0303-0300 d r qd p5 1 dr c reset r q p5 1 ddr c reset wp5d wp5 sci0 input enable serial receive data p5 1 rp5 legend: wp5d: write to p5ddr wp5: write to port 5 rp5: read port 5 internal data bus hardware standby figure c.17 port 5 block diagram (pin p5 1 )
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 690 of 706 rej09b0303-0300 d r qd p5 2 dr c reset r q p5 2 ddr c reset wp5d * 1 * 2 wp5 sci0 input enable clock output scl 0 output scl 0 input transmit enable output enable clock input iic0 p5 2 rp5 legend: wp5d: write to p5ddr wp5: write to port 5 rp5: read port 5 notes: 1. output enable signal 2. open drain control signal internal data bus hardware standby figure c.18 port 5 block diagram (pin p5 2 )
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 691 of 706 rej09b0303-0300 c.6 port 6 block diagrams d r qd p6ndr c reset r q p6nddr c reset wp6d wp6 16-bit frt ftci input ftia input ftib input ftid input timer connection 8-bit timers 0 and 1 8-bit timers y and x hfbacki input, tmci 0 input tmix input, vsynci input tmiy input, vfbacki input tmri 0 input, hsynci input tmci 1 input p6n rp6 legend: wp6d: write to p6ddr wp6: write to port 6 rp6: read port 6 note: n = 0, 2, 3, 5 internal data bus hardware standby figure c.19 port 6 block diagram (pins p6 0 , p6 2 , p6 3 , and p6 5 )
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 692 of 706 rej09b0303-0300 d r qd p6 1 dr c reset r q p6 1 ddr c reset wp6d wp6 16-bit frt ftoa output output enable timer connection vsynco output output enable p6 1 rp6 legend: wp6d: write to p6ddr wp6: write to port 6 rp6: read port 6 internal data bus hardware standby figure c.20 port 6 block diagram (pin p6 1 )
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 693 of 706 rej09b0303-0300 d r qd p6 4 dr c reset r q p6 4 ddr c reset wp6d wp6 timer connection clampo output output enable 8-bit timer 0 tmo 0 output output enable 16-bit frt ftic input p6 4 rp6 legend: wp6d: write to p6ddr wp6: write to port 6 rp6: read port 6 internal data bus hardware standby figure c.21 port 6 block diagram (pin p6 4 )
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 694 of 706 rej09b0303-0300 d r qd p6 6 dr c reset r q p6 6 ddr c reset wp6d wp6 16-bit frt ftob output output enable 8-bit timer 1 timer connection tmri 1 input csynci input p6 6 rp6 legend: wp6d: write to p6ddr wp6: write to port 6 rp6: read port 6 internal data bus hardware standby figure c.22 port 6 block diagram (pin p6 6 )
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 695 of 706 rej09b0303-0300 d r qd p6 7 dr c reset r q p6 7 ddr c reset wp6d wp6 8-bit timer x tmox output output enable p6 7 rp6 legend: wp6d: write to p6ddr wp6: write to port 6 rp6: read port 6 8-bit timer 1 tmo 1 output output enable timer connection hsynco output output enable internal data bus hardware standby figure c.23 port 6 block diagram (pin p6 7 )
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 696 of 706 rej09b0303-0300 c.7 port 7 block diagram the h8/3577 group has an 8-bit input port (pins p7 0 to p7 7 ) and the h8/3567 group has a 4-bit input port (pins p7 0 to p7 3 ). a/d converter analog input p7n legend: rp7: read port 7 note: n = 0 to 7 rp7 internal data bus figure c.24 port 7 block diagram (pins p7 0 to p7 7 in h8/3577 group, pins p7 0 to p7 3 in h8/3567 group)
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 697 of 706 rej09b0303-0300 c.8 port 8 block diagrams port c is provided only in the h8/3567 group version with an on-chip usb. d r qd pcnodr c reset r q pcnddr c reset wpcd wpc usb enp output output enable pcn rpc rpco legend: wpcd: write to pcddr wpc: write to port c rpc: read port c rpco: read to odr note: n = 0 to 3 internal data bus hardware standby figure c.25 port c block diagram (pins pc 0 to pc 3 in h8/3567 group version with on-chip usb)
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 698 of 706 rej09b0303-0300 d r qd pcnodr c reset r q pcnddr c reset wpcd wpc usb ocp input input enable pcn rpc rpco legend: wpcd: write to pcddr wpc: write to port c rpc: read port c rpco: read to odr note: n = 4 to 7 internal data bus hardware standby figure c.26 port c block diagram (pins pc 4 to pc 7 in h8/3567 group version with on-chip usb)
appendix c i/o port block diagrams rev. 3.00 mar 17, 2006 page 699 of 706 rej09b0303-0300 c.9 port d block diagram port d is provided only in the h8/3567 group version with an on-chip usb. d r qd pdnodr c reset r q pdnddr c reset wpdd wpd pdn rpc dsmd+/dsmd- rpdo legend: wpdd: write to pdddr wpd: write to port d rpd: read port d rpdo: read to odr note: n = 0 to 7 m = 2 to 5 internal data bus hardware standby usb fonly bit usb bus driver/ receiver figure c.27 port d block diagram (pins pd 0 to pd 7 in h8/3567 group version with on-chip usb)
appendix d pin states rev. 3.00 mar 17, 2006 page 700 of 706 rej09b0303-0300 appendix d pin states d.1 port states in each mode table d.1 i/o port states in each processing state port name pin name reset hardware standby mode software standby mode program execution state port 1 t t kept i/o port port 2 t t kept i/o port port 3 t t kept i/o port port 4 7 t t kept i/o port port 4 6 t t [ddr = 1] h [ddr = 0] t clock output/input port port 4 5 to 4 0 t t kept i/o port port 5 t t kept i/o port port 6 t t kept i/o port port 7 t t t input port port c t t functioning (hocne = 1) kept (hocne = 0) usb input/output i/o port port d t t functioning (fonly = 0) kept (fonly = 1) usb input/output i/o port legend: h: high level l: low level t: high impedance kept: input pins are in the high-impedance state (when ddr = 0 and pcr = 1, mos input pull- ups remain in the on state). output ports retain their state. in some cases, the on-chip supporting module is initialized and the pin is an input/output port, determined by the ddr and dr settings. ddr: data direction register hocne: hocne bit in hoccr of usb fonly: fonly bit in usbcr of usb note: n = 2 to 5
appendix e timing of transition to and recovery from hardware standby mode rev. 3.00 mar 17, 2006 page 701 of 706 rej09b0303-0300 appendix e timing of transition to and recovery from hardware standby mode e.1 timing of transition to hardware standby mode (1) to retain ram contents when the rame bit in syscr is set to 1, drive the res signal low 10 system clock cycles before the stby signal goes low, as shown in figure e.1. res must remain low until stby goes low (minimum delay from stby low to res high: 0 ns). stby res t 2 0 ns t 1 10t cyc figure e.1 timing of transition to hardware standby mode (2) when the rame bit in syscr is cleared to 0 or when it is not necessary to retain ram contents, res does not have to be driven low as in (1). e.2 timing of recovery from hardware standby mode drive the res signal low approximately 100 ns or more before stby goes high. stby res t osc t 100 ns figure e.2 timing of recovery from hardware standby mode
appendix f product code lineup rev. 3.00 mar 17, 2006 page 702 of 706 rej09b0303-0300 appendix f product code lineup table f.1 h8/3577 group and h8/3567 group product code lineup product type product code mark code package (package code) h8/3577 ztat version hd6473577 hd6473577p20 64-pin shrink dip (dp-64s) h8/3577 group hd6476577f20 64-pin qfp (fp-64a) mask rom version hd6433577 hd6433577( *** )p20 64-pin shrink dip (dp-64s) hd6433577( *** )f20 64-pin qfp (fp-64a) h8/3574 mask rom version hd6433574 hd6433574( *** )p20 64-pin shrink dip (dp-64s) hd6433574( *** )f20 64-pin qfp (fp-64a) h8/3567 ztat version hd6473567 hd6473567p20 42-pin shrink dip (dp-42s) h8/3567 group hd6476567f20 44-pin qfp (fp-44a) mask rom version hd6433567 hd6433567( *** )p20 42-pin shrink dip (dp-42s) hd6433567( *** )f20 44-pin qfp (fp-44a) h8/3564 mask rom version hd6433564 hd6433564( *** )p20 42-pin shrink dip (dp-42s) hd6433564( *** )f20 44-pin qfp (fp-44a) (10 mhz limit version) hd6433564( *** )p10 42-pin shrink dip (dp-42s) h8/3567u hd6473567u hd6473567up20 64-pin shrink dip (dp-64s) ztat version (on-chip usb) hd6473567uf20 64-pin qfp (fp-64a) hd6433567u hd6433567u( *** )p20 64-pin shrink dip (dp-64s) mask rom version (on-chip usb) hd6433567u( *** )f20 64-pin qfp (fp-64a) h8/3564u hd6433564u hd6433564u( *** )p20 64-pin shrink dip (dp-64s) mask rom version (on-chip usb) hd6433564u( *** )f20 64-pin qfp (fp-64a) note: ( *** ) is the rom code. when ordering, the frequency selection (20 or 10) is not indicated by the model name, but is identified by the rom code.
appendix g package dimensions rev. 3.00 mar 17, 2006 page 703 of 706 rej09b0303-0300 appendix g package dimensions figures g.1 to g.4 show package dimensions of h8/3577 group and h8/3567 group. 1 p 1 3 1 32 64 33 c e z a b b e d e l a 2.54 1.46 0.48 0.38 18.6 58.5 15 0 2.03 1.78 1.53 0.36 0.25 0.20 1.0 0.58 0.51 e 1 l e c b p a e d b 3 z a 1 5.08 17.0 57.6 reference symbol dimension in millimeters min nom max 19.05 p-sdip64-17x57.6-1.78 8.8g mass[typ.] dp-64s/dp-64sv prdp0064bb-a renesas code jeita package code previous code figure g.1 dp-64s package dimensions
appendix g package dimensions rev. 3.00 mar 17, 2006 page 704 of 706 rej09b0303-0300 note) 1. dimensions"*1"and"*2" do not include mold flash 2. dimension"*3"does not include trim offset. * 1 * 2 * 3 p e d e d xm y f 64 1 17 16 49 48 32 33 z z d h e h b 2 1 1 detail f c a a l a l terminal cross section p 1 1 c b c b 0.8 1.0 1.0 0.15 0.10 8 0 0.25 0.10 0.15 0.35 0.00 0.45 0.37 0.29 0.22 0.17 0.12 3.05 16.9 17.2 17.5 d l 1 z e z d y x c b 1 b p a h d a 2 e a 1 c 1 e e l h e 1.1 0.8 0.5 max nom min dimension in millimeters symbol reference 14 2.70 17.5 17.2 16.9 1.6 14 p-qfp64-14x14-0.80 1.2g mass[typ.] fp-64a/fp-64av prqp0064gb-a renesas code jeita package code previous code figure g.2 fp-64a package dimensions
appendix g package dimensions rev. 3.00 mar 17, 2006 page 705 of 706 rej09b0303-0300 1 p 1 3 1 21 42 22 c e z a b b e d e l a 2.54 1.38 0.48 0.38 14.6 38.6 15 0 2.03 1.78 1.53 0.35 0.25 0.20 1.0 0.58 0.51 e 1 l e c b p a e d b 3 z a 1 5.10 14.0 37.3 reference symbol dimension in millimeters min nom max 15.24 p-sdip42-14x37.3-1.78 4.8g mass[typ.] dp-42s/dp-42sv prdp0042bb-a renesas code jeita package code previous code figure g.3 dp-42s package dimensions
appendix g package dimensions rev. 3.00 mar 17, 2006 page 706 of 706 rej09b0303-0300 note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. 3.0 3.0 0.15 0.10 0.8 8 0 0.25 0.10 0.15 0.35 0.00 0.45 0.37 0.29 0.22 0.17 0.12 3.05 17.5 16.9 17.2 l 1 z e z d y x c b 1 b p a h d a 2 e d a 1 c 1 e e l h e 14 1.1 0.8 0.5 max nom min dimension in millimeters symbol reference 14 2.70 17.5 17.2 16.9 1.6 * 1 * 2 * 3 p e d e d y m x 22 23 33 34 12 11 44 1 f z z b h e h d 2 1 1 detail f c a a l a l terminal cross section p 1 1 b c b c p-qfp44-14x14-0.80 1.2g mass[typ.] fp-44a/fp-44av prqp0044gc-a renesas code jeita package code previous code figure g.4 fp-44a package dimensions
renesas 8-bit single-chip microcomputer hardware manual h8/3577 group, h8/3567 group publication date: 1st edition, september 1999 rev.3.00, march 17, 2006 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ?2006. renesas technology corp., all rights reserved. printed in japan.
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