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www.fairchildsemi.com ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/11/08 an-6075 compact green-mode adapter using FSQ500L for low cost 1. introduction this application note describes a detailed design strategy for a compact flyback converter. design considerations and mathematical equations are presented, as well as guidelines for a printed circuit board layout. the FSQ500L is designed for a replacement of linear power supplies to achieve low cost. this device combines current-mode pulse width modulator (pwm) with a single-chip 700v sensefet. the integrated pwm controller features include: fixed operating frequency (130khz), under-voltage lockout (uvlo) protection, soft-start time tuned by external capacitor, overload protection (olp), leading-edge blanking (leb), optimized gate turn-on/turn-off driver, thermal shutdown (tsd) protection with hysteresis, and temperature- compensated precision-current sources for loop compensation. the no-load power consumption can be less than 250mw without auxiliary bias winding and down to 60mw with auxiliary bias winding for universal ac input voltage range to meet the power conservation requirements. when compared to a linear power supply, the FSQ500L reduces total size and weight, while increasing efficiency, productivity, and system reliability. this device provides a platform for cost-effective flyback converters. figure 2. typical application figure 1. sot-223 pin configuration
an-6075 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/11/08 2 2. device block description 2.1 startup circuit and soft start at startup, an internal high-voltage current source supplies the internal bias and charges the external capacitor (c a ) connected to the v cc pin, as illustrated in figure 4. an internal high-voltage regulator (hv/reg) located between the d and vcc pins regulates the v cc to be 6.5v and supplies operating current. FSQ500L needs no auxiliary bias winding. v ref uvlo hv/reg 6.5v 2 d 3 v cc c a transformer i ch i star t figure 3. startup block the soft-start time of FSQ500L is tuned by an external v cc capacitor (c a ), which increases pwm comparator non- inverting input voltage, together with the sensefet current, slowly after it starts up. before v cc reaches v start , c a is charged by the current i ch -i start , where i ch and i start are described in figure 3. after v cc reaches v start , all internal blocks are activated, so that the current consumed inside the ic becomes i op . therefore, c a is charged by the current i ch - i op , which makes the increasing slope of v cc become sluggish. make the soft-start time long or short by selecting c a as described in figure 4. during t s/s , i delay is disabled to avoid unwanted olp. typically, t s/s is around 8ms with 47f of c a . 6v 5v v cc t v start v stop v ccreg t 1 t 2 t 1 =c a 6v/(i ch -i start ) t s/s =c a 0.5v/(i ch -i op ) 6.5v t s/s figure 4. soft-start function the peak value of the drain current of the power switching device is progressively increas ed to establish the correct working conditions for transformers, inductors, and capacitors. the voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. it also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. 2.2 feedback control FSQ500L employs current-mode control, as shown in figure 5. an opto-coupler (such as the fod817a) and shunt regulator (such as the ka 431) are typically used to implement the feedback network. comparing the feedback voltage with the voltage across the r sense resistor makes it possible to control the switching duty cycle. when the reference pin voltage of the shunt regulator exceeds the internal reference voltage of 2.5v, the opto-coupler led current increases, pulling down the feedback voltage and reducing the duty cycle. this typically occurs when the line input voltage increases or the output load current decreases. 2.3 pulse-by-pulse current limit because current-mode control is employed, the peak current through the sensefet is limited by the non-inverting input of pwm comparator (v fb *), as shown in figure 5. assuming that 225a current source flows only thro ugh the internal resistor (8r + r = 12 k ), the cathode voltage of diode d2 is about 2.7v. since d1 is blocked when the feedback voltage (v fb ) exceeds 2.7v, the maximum voltage of the cathode of d2 is clamped at this voltage, clamping v fb *. therefore, the peak value of the current through the sensefet is limited. 2 osc v cc i delay i fb v sd r 8r gate driver olp d1 d2 + v fb * - v fb ka431 c b v o fod817a r sense sensefet r 2 r 1 c f v cc figure 5. pulse-width modulation (pwm) circuit 2.4 leading-edge blanking (leb) at the instant the internal sensefet is turned on, a high- current spike occurs through the sensefet, caused by primary-side capacitance and secondary-side rectifier reverse recovery. excessive voltage across the r sense resistor would lead to incorrect feedback operation in the current mode pwm control. to counter this effect, the FSQ500L employs a leading-edge blanking (leb) circuit. this circuit inhibits the pwm comparator for a short time (t leb =250ns) after the sensefet turns on.
an-6075 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/11/08 3 2.5 protection functions the FSQ500L has two self-protective functions: overload protection (olp) and thermal shutdown (tsd). while olp is implemented as auto-restart mode, there is no switching when tsd triggers. once the overload condition is detected, switching is terminated, the sensefet remains off, and hv/reg turns off. this causes v cc to fall. when v cc falls down to the under-voltage lockout (uvlo) stop voltage of 5.0v, the protection is reset and the startup circuit charges v cc capacitor. when v cc reaches the start voltage of 6.0v, the FSQ500L resumes normal operation. if the fault condition is still not removed, the sensefet and hv/reg remain off and v cc drops to v stop again. in this manner, the auto-restart can alternately enable and disable the switching of the power sensefet until the fault condition, is eliminated, as shown in figure 6. because these protection circuits are fully integrated into the ic without external components, the reliability can be improved without increasing cost. fault situation 5.0v 6.0v v cc v ds t olp occurs olp removed normal operation normal operation power on 6.5v figure 6. auto-restart protection waveforms 2.5.1 overload protection (olp) overload is defined as the load current exceeding normal level due to an unexpected abnormal event. in this situation, the protection circuit should trigger to protect the smps. however, even when the smps is in normal operation, the over load protection circuit can be triggered during the load transition. to avoid this undesired operation, the overload protection circuit is designed to trigger after a specified time to determine whether it is a transient situation or an overload situation. because of the pulse-by-pulse current limit capability, the maximum peak current through the sensefet is limited and, therefore, the maximum input power is restricted with a given input voltage. if the output consumes more than this maximum power, the output voltage (v o ) decreases below the set voltage. this reduces the current through the opto-coupler led, which also reduces the opto-coupler transistor current, increasing the feedback voltage (v fb ). if v fb exceeds 2.7v, d1 is blocked and the 5a current source starts to charge c b slowly up to v cc . in this condition, v fb continues increasing until it reaches 4.5v, when the switching operation is terminated, as shown in figure 7. v fb t 2.7v 4.5v overload protection t 12 =c b *(4.5-2.7)/i de lay t 1 t 2 figure 7. overload protection the olp delay time is: ( ) delay b 12 i 2.7 - 4.5 c t ? = (1) under 50ms delay time (the c b value should be smaller than 138nf) is applied for most applications. this protection is implemented in auto restart mode. 2.5.2 thermal shutdown (tsd) the sensefet and the control ic are built in one package. this makes it easy for the control ic to detect the abnormal over-temperature of the sensefet. when the temperature exceeds approximately 140 c, thermal shutdown triggers. fault situation 5.7v 6.0v v cc v ds t tsd occurs tsd removed normal operation normal operation power on 6.5v figure 8. over-temperature protection when tsd triggers, delay current is disabled, switching operation stops, and v cc through the internal high-voltage current source is set to 5.7v from 6.5v, as shown in figure 8. since the tsd signal prohibits the sensefet from switching, there is no switching until the junction temperature decreases sufficiently. if the junction temperature is lower than 60c typically, the tsd signal is removed and v cc is set to 6.5v again. while v cc increases
an-6075 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/11/08 4 from 5.7v to 6.5v, the soft-start function turns the sensefet on and off with no voltage and/or current stress. 2.6 burst operation to minimize power dissipation in standby mode, the FSQ500L enters burst-mode operation. as the load decreases, the feedback voltage decreases. as shown in figure 10, the device automatically enters burst mode when the feedback voltage drops below v burl (750mv). at this point, switching stops and the output voltages start to drop at a rate dependent on standby current load. this causes the feedback voltage to rise. once it passes v burh (800mv), switching resumes. the feedback voltage then falls and the process repeats. burst-mode operation alternately enables and disables switching of the power sensefet, thereby reducing switching loss in standby mode. v fb v ds 0.75v 0.80v i ds v o vo set time s witching dis abled t 1 t 2 t 3 s witching dis abled t 4 figure 9. burst-mode operation 3. design example the following is design example for 2w compact adapter. 3.1 determine system specifications output power, p o =2.04w (5.1v/0.4a); v ac input range=85 to 264v ac (universal input), line frequency, f l =60hz; efficiency, >50%. 3.2 determine dc link capacitor (c dc ) and dc link voltage range it is typical to select the dc link capacitor as 2-3f per watt of input power for universal input range (85-264v ac ) and 1f per watt of input power for european input range (195- 264v ac ). figure 10 shows the corrected input voltage waveform. the red line shows ripple voltage on the dc link capacitor and the minimum and maximum voltage on the dc link capacitor are expressed in equations 2 and 3. figure 10. bridge rectifier and bulk capacitor voltage waveform 87v 120hz f 5.7 0.5 0.3) - (1 0.4a 5.1v 2 - 85vac 2 2f c ) d - (1 i 2v - 2v v 2 l dc ch o o 2 min ac, min dc, = = = (2) 373v 264v 2 2 v max , max dc, = = = ac v (3) where d ch is dc link capacitor charging duty ratio defined as shown in figure 10, which is typically about 0.3. output power is 2.04w, so the v dc capacitor is 6.08f. select the nearest standard value 5.7f (4.7f+1f) for c dc and substitute it above. therefore; from equation 2 and 3, the v dc,min is 87v and v dc,max is 373v. 3.3 determine the turn ratio the transformer turn ratio (n=n pri /n sec ) is an important parameter of the flyback converter; it affects the maximum duty ratio when the input voltage is at a minimum value. it also influences the voltage stresses on the mosfet and the secondary rectifier. the permissible voltage stresses and the maximum voltage stresses on the mosfet, as well as the secondary rectifier, can be expressed as: 440v ) 7 . 0 1 . 5 ( 5 . 11 373 ) ( v max , max ds, = + + = + + = v v v v v n v f o dc (4) v v v n v o dc 5 . 37 1 . 5 11.5 373v v max , max dr, = + = + = (5) where v f is the forward-voltage of output diode.
an-6075 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/11/08 5 it is typical to set v ds,max as 420v~560v (60%~80% of mosfet rated voltage). select the transformer turn ratio, n, to be 11.5. according to equation 4, v ds,max =440v, which satisfies 60%~80% of mosfet rated voltage. the maximum voltage stress on the secondary rectifier can be calculated from equation 5. select sb260 rectifier diode from equation 5 results. (specification of sb260 as: the maximum reverse voltage, v rrm is 60v and average forward current, i f is 2a). 3.4 determine transformer primary-side inductance (l p ), maximum duty (d max ), and primary rms current (i rms ) the primary-side inductance (l p ) of the transformer is designed specifically for dcm operation and obtained as: () h khz a a v f s 800 130 5 . 0 28 . 0 4 . 0 1 . 5 2 i p 2 l 2 2 pk o p ? = = (6) where i pk is primary-side peak current, given in the datasheet as i lim. the maximum duty ratio (d max ) can be derived as: 33% 87v 0.28a 130khz 800 0 v i f l d min dc, pk s p max = = = (7) the maximum duty ratio should be kept below 50% for dcm operation. the primary-side rms current can be derived as: a 09 . 0 3 33 . 0 28 . 0 3 d i i max pk rms = = = (8) 3.5 determine transformer core size (ae) and minimum primary-side turns (n p,min ) table 1 shows the commonly used cores with output power under 10w. the cores recommended are typical for the universal input range and 130khz switch frequency. choose the ee16 core to meet this output power from table 1. table 1. core quick select table (for universal input, f s =130khz and 5v output) core cross- sectional area (ae) window area (aw) output power range ee13-z 17.1mm 2 33.4mm 2 1-5w ei16-z 19.8mm 2 42.3mm 1-5w ee16-z 19.2mm 2 39.8mm 2 1-10w ei19-z 24.0mm 2 54.4mm 2 1-10w base on faraday?s law and the peak inductor current, the minimum turns for the primary inductance is calculated as: turns 48 10 19.2mm 4t 2 . 0 28 . 0 h 800 10 a b i l n 6 2 6 e max pk p min p, = = = a (9) where b max is the saturation magnetic flux density, typical set 0.2~0.3tesla; a e is the cross-sectional of the core. 3.6 determine secondary-side turns (n p,min ) the number of turns for the secondary winding is defined as: turns 9 11.5 104 n n p s ? = = n (10) select primary-side turns, n p to be 104 turns, so the secondary-side turns is 9 turns, based on equation 10. 3.7 determine primary-side rcd snubber when the mosfet turns off, a high-voltage spike occurs on the drain pin because of a resonance between the leakage inductor (l lk ) of the main transformer and the output capacitor (c oss ) of the mosfet. the excessive voltage on the drain pin may lead to an avalanche breakdown and eventually damage the mosfet. therefore, it is necessary to add an additional circuit to clamp the voltage. the rcd snubber circuit and mosfet drain voltage waveforms are shown in figure 11 and figure 12, respectively. the rcd snubber circuit absorbs the current in the leakage inductor by turning on the snubber diode (d sn ) when v ds exceeds v in +nv o . it is assumed that the snubber capacitance is large enough that its voltage does not change during one switching period. the r sn2 can reduce the spike damping wave and affect emi. figure 11. primary-side rcd snubbber circuit
an-6075 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/11/08 6 figure 12. mosfet drain voltage waveform the snubber capacitor voltage (v sn ) should be determined at the minimum input voltage and full-load condition. once v sn is determined, the power dissipated in the snubber circuit at the minimum input voltage and full-load condition is obtained by: o s pk lk sn nv f i l r ? = = sn sn 2 2 sn sn v v 2 1 v loss (11) where f s is the switching frequency of FSQ500L. v sn should be 2~2.5 times of nv o . very small v sn results in a severe loss in the snubber circuit, as shown equation 11. the resistance is obtained by: o s pk lk sn nv f i l r ? = sn sn 2 2 sn v v 2 1 v = = 20k 5.1 11.55 - 130 130 130khz 0.28a h 90 0.5 130 2 2 (12) the power loss from r sn can be calculated as: w r sn 845 . 0 20k 130 v p 2 sn sn ? = = (13) to reduce the power loss from r sn , the r sn should be selected higher than 20k ? . from equation 12 if the r sn increases, the v sn also increases, the r sn recommended value is between 200k ? and 47k ? . the maximum ripple of the snubber capacitor voltage is obtained as: s sn f r = sn sn sn v v c nf khz k 7 . 0 130 200 130 % 5 130 ? = , selected 1nf (14) where f s is the switching frequency and r sn uses 200k . in general, 5~10% ripple is reasonable. 3.8 external v cc auxiliary winding circuit for improving power saving figure 13 shows an external v cc auxiliary winding circuit for improving power saving. the external v cc auxiliary winding circuit reduces internal circuit power loss to improve power saving. figure 13. external v cc auxiliary winding circuit for improving power saving the number of turns for the v cc auxiliary winding is defined as: turns 13 9 0.7 5.1 0.7 7.7 v n 2 a aux ? + + = + + = s f o f d n v v v (15) where v a is the voltage of v cc auxiliary winding and v d2f is forward-voltage of d 2 diode. because the FSQ500L has an internal high-voltage regulator (hv/reg) located between the d and vcc pins that regulates the v cc to be 6.5v and supplies operating current. if using the auxiliary winding, the v cc should be set higher than 6.5v. assume v a is 7.7v and v cc is 6.8v, according to equation 15, n aux = 13 turns is solved. the r cf is limited operation current; it can be obtained as: = = 1.18k a 760 6.8 - 7.7 i v - v r op cc a f , using 1k ? (16) where i op is operation current, in the datasheet as i op . in this circuit, a smaller capacitor c1 (~1f) can be used to reduce startup time. the energy supporting the FSQ500L after startup is mainly from a larger capacitor c2 (~22f). in this design example, if using the v cc auxiliary winding, the no-load power saving is down to 60mw. note: 1. if using the external v cc auxiliary circuit, the v sd voltage of fb pin follows as v cc voltage.
an-6075 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/11/08 7 4. printed circuit board layout high-frequency switching current / voltage makes printed circuit board layout a very important design issue. good pcb layout minimizes excessive emi helps the power supply survive during surge/esd tests. 4.1 guidelines to improve emi performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitor c dc first, then to the switching circuits. refer to figure 14. ? the high-frequency current loop is in c dc ? transformer ? drain pin ? gnd pin ? c dc . the area enclosed by this current loop should be as small as possible. keep the traces (especially 2 1 ) short, direct, and wide. high- voltage traces related the drain of mosfet and rcd snubber should be kept far way from control circuits to prevent unnecessary interference. if a heatsink is used for mosfet, connect this heatsink to ground. ? as indicated by 2 , the ground of control circuits should be connected first, then to other circuitry. ? place c a close to the controller for good decoupling. two suggestions with different pro and cons for ground connections are recommended. ? gnd 2 1 : this could avoid common impedance interference for the sense signal. ? regarding the esd discharge path, the charges go from secondary, through the transformer stray capacitance, to gnd 1 first, and back to mains. it should be noted that control circuits should not be placed on the discharge path. point discharge for common choke can decrease high-frequency impedance and increase esd immunity. ? 3 should be a point-discharger route to bypass the static electricity energy. as shown in figure 12, it is suggested to map out this discharge route. ? should a y-cap be required between primary and secondary, connect this y-cap to the positive terminal of c dc . if this y-cap is connected to primary gnd, it should be connected to the negative terminal of c dc (gnd 1 ) directly. point discharge of this y-cap helps for esd; however, the creepage between these two pointed ends should be at least 5mm according to safety requirements . figure 14. layout considerations
an-6075 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/11/08 8 5. typical application circuit application output power input voltage range output voltage/maximum current adapter 2.04w universal input (85-264v ac ) 5.1v/0.4a 5.1 features ? single chip 700v sensefet power switch ? soft-start time tuned by external capacitor ? built-in overload protection (olp) and internal thermal shutdown function (tsd) with hysteresis ? low standby mode power consumption (input wattage <0.3w at no-load condition) 5.2 key design notes ? resistors r 1 and inductance l 1 improve emi. ? external v cc auxiliary circuit is from with d 6 , c 9 , c 10 , and r 9 . the external v cc auxiliary winding circuit reduces internal circuit power loss and improves power saving. d 1 d 2 d 4 d 3 c 5 r 4 c 1 d 5 t 1 pwm r sense c 9 c 7 pc817 v fb v cc gnd drain d 7 c 8 c 3 l 3 r 6 r 8 ka431 r 7 c 6 pc817 r 3 FSQ500L v o ac input f 1 2 1 3 4 c 4 l 1 r 1 u 1 u 3 u 2 r 5 c 2 c 12 c 11 r 10 c 10 d 6 v cc external v cc auxiliary circuit r 3 r 9 figure 15. schematic
an-6075 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/11/08 9 table 2. 2w compact green-mode adapter evaluation board part list part# value note part# value note fuse capacitor f1 18 ? 1w c1 1nf/1kv ceramic resistor c2 nc r1 4.7k ? smd 0805+/-5% c3 220f/10v electrolytic r2 1k ? smd 0805+/-5% c4 1f/400v electrolytic r3 30 ? smd 0805+/-5% c5 4.7f/400v electrolytic r4 200k ? smd 1206+/-5% c6 330nf smd 1206 r5 nc c7 22nf smd 1206 r6 2.2k ? smd 0805 +/-5% c8 330f/10v electrolytic r7 300 ? smd 0805 +/-5% c9 47f/16v electrolytic r8 2k ? smd 0805 +/-5% c10 22f/50v electrolytic r9 30 ? smd 0805 +/-5% c11 1f smd 1206 r10 1k ? 1/4w c12 2.2nf/250v y2, ceramic ic d1, d2, d3, d4, d5, in4007 1000v/1a u1 FSQ500L fairchild d6 1n4148 u2 pc817 fairchild d7 sb260 60v/2a u3 tl431 fairchild filter l1 470h resistance l3 3h 5.3 transformer specification figure 16. transformer schema tic figure 17. winding sequence 5.3.1 winding specification no pin(s-f) wire turns winding method shield1 1- 0.15 46ts solenoid winding insulation: polyester tape t = 0.03mm, 4 layers n p 2-1 0.2 104ts solenoid winding insulation: polyester tape t = 0.03mm, 2 layers shield2 1- 0.15 46ts solenoid winding insulation: polyester tape t = 0.03mm, 5 layers n s 10-9 tex-e 0.4 9ts solenoid winding insulation: polyester tape t = 0.03mm, 2 layers
an-6075 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/11/08 10 5.3.2 electrical specification pin value remarks inductance 6-4 800 h5% 1khz, 0.25v leakage 6-4 90 h 2nd shorted ? core and bobbin: ee16 ? ae: 19.2 [mm 2 ] 5.4 experimental results table 3. no-load input wattage, efficiency, ou t current protection, experimental result input voltage input wattage (no load without v cc auxiliary winding ) input wattage (no load with v cc auxiliary winding ) efficiency (without v cc auxiliary winding) efficiency (with v cc auxiliary winding) output current protection 85v/60hz 0.094w 0.04w 65.93% 69.55% 0.611a 120v/60hz 0.116w 0.043w 66.34% 71.08% 0.65a 230v/50hz 0.209w 0.053w 56.62% 63.00% 0.836a 264v/50hz 0.242w 0.06w 53.14% 59.59% 0.881a table 4. experimental waveform figure 18. burst-mode operation at input voltage 85v ac (ch1:v o , ch2: v ds , ch3: v fb ) figure 19. over-current prot ection waveform at input voltage 85v ac ; delay time is ~ 12.7ms (ch1:v o , ch2: v ds , ch3: v fb ) figure 20. voltage stress of mosfet at input voltage 264v ac ; maximum voltage is ~490v (ch2: v ds ) figure 21. short-circuit pr otection at input voltage 120v ac (ch1:v o , ch2: v cc , ch3: v fb , ch4:v ds )
an-6075 application note ? 2008 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 9/11/08 11 6. reference FSQ500L ? compact green-mode fairchild power switch (fps?) an-4137 ? design guidelines for off-line flyback converters using the fps? an-4147 ? design guideline for rcd snubber of flyback converters disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) su pport or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeli ng, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness

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