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rt9203/a preliminary 1 ds9203/a-10 march 2007www.richtek.com features l operates at 5v l 0.8v internal reference l drives two n-mosfet l voltage mode pwm control l fast transient response l fixed 300khz oscillator frequency l dynamic 0 to 100% duty cycle l internal pwm loop compensation l internal soft-start l adaptive non-overlapping gate driver l over-voltage protection uses lower mosfet l rohs compliant and 100% lead (pb)-free pin configurations applications l pc motherboard l cable modems, set-top-box, and dsl modems l dsp and core communications processor supplies l memory power supplies l personal computer peripherals l industrial power supplies l 5v input dc-dc regulators l low voltage distributed power supplies l graphic cards dual regulators - synchronous buck pwm dc-dc and linear controller ordering information general description the rt9203/a is a dual-output power controllers designed for high performance graphics cards and personal computers. the ic integrates a synchronous buck controller, a linear controller and protection functions into a small 8-pin package. the rt9203/a uses an internal compensated voltage mode pwm control for simplying design. an internal 0.8v reference allows the output voltage to be precisely regulated to meet low output voltage requirement. a fixed 300khz oscillation frequency reduces the component size for saving board area. the rt9203/a also features over voltage protection (ovp) and under voltage lock-out (uvlo). (top view) sop-8 boot ugate gnd lgate vcc drv fbl fb 2 3 4 5 6 7 8 note : richtek pb-free and green products are : } rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. } suitable for use in snpb or pb-free soldering processes. } 100%matte tin (sn) plating. rt9203/a package type s : sop-8 operating temperature range p : pb free with commercial standard g : green (halogen free with commer- cial standard) uvp : hiccup mode uvp : latch mode
rt9203/a preliminary 2 ds9203/a-10 march 2007 www.richtek.com typical application circuit figure 1. rt9203/a powered from 5v p h a s e f b l v c c b o o t u g a t e g n d l g a t e r t 9 2 0 3 / a 8 1 2 3 4 5 6 7 f b 3 9 0 1 2 0 + + 1 u f 4 7 0 u f v o u t 2 3 . 4 v v o u t 2 = 0 . 8 v * ( 1 + r 1 / r 2 ) < 1 k 1 0 n f 0 . 8 v 1 0 0 u f 5 v 2 s d 1 8 0 2 s 1 g 1 s 2 g 2 d 1 d 1 d 2 d 2 1 8 7 6 5 4 3 2 0 . 1 u f 1 u f 1 n 5 8 1 9 p h a s e 1 u h 5 v 1 u f + 6 8 0 u f b e c a r e f u l d u r i n g l a y o u t 5 u h 1 u f + 6 8 0 u f l e s r + 6 8 0 u f l e s r v o u t 1 1 . 6 v 2 0 0 2 0 0 1 0 n f v o u t 1 = 0 . 8 v * ( 1 + r 3 / r 4 ) p h a s e p u l l f b t r a c e o u t a f t e r c o u t p h k d 6 n 0 2 l t 5 v
rt9203/a preliminary 3 ds9203/a-10 march 2007www.richtek.com figure 2. rt9203/a powered from 12v p h a s e f b l v c c b o o t u g a t e g n d l g a t e r t 9 2 0 3 / a 8 1 2 3 4 5 6 7 f b 2 5 5 1 2 0 + + 1 u f 3 3 0 u f v o u t 2 2 . 5 v v o u t 2 = 0 . 8 v * ( 1 + r 1 / r 2 ) < 1 k 1 0 n f 0 . 8 v 1 0 0 u f 3 . 3 v 2 s d 5 7 0 6 s 1 g 1 s 2 g 2 d 1 d 1 d 2 d 2 1 8 7 6 5 4 3 2 p h a s e 1 u h 5 v 1 u f + 4 7 0 u f b e c a r e f u l d u r i n g l a y o u t 5 u h 1 u f 5 1 0 u f 4 v o s c o n 1 4 m o h m v o u t 1 1 . 6 v 2 0 0 2 0 0 1 0 n f v o u t 1 = 0 . 8 v * ( 1 + r 3 / r 4 ) p h a s e p u l l f b t r a c e o u t a f t e r c o u t s u g g e s t u s e t r a n s i s t o r 1 u f 0 0 . 1 u f 1 0 5 v 1 2 v + 4 7 0 u f + +
rt9203/a preliminary 4 ds9203/a-10 march 2007 www.richtek.com function block diagram gnd vcc rt9203/a boot c vcc 1uf c boot 0.1uf + c out 1000uf l 5uh mu d g s ml d g s + c1 1uf c2 470uf gnd return layout placement layout notes 1. put c1 & c2 to be near the mu drain and ml source nodes. 2. put rt9203/a to be near the c out 3. put c boot as close as to boot pin 4. put c vcc as close as to vcc pin 0.8 reference power on reset soft start + - ovp + - uvp 1v + - error 0.8v 0.5v error amplifier + - pwm 300khz oscillator control logic vcc 6.0v regulation gnd fb vcc boot ugate lgate + - uvp + - + + ss ldo drv fbl vcc
rt9203/a preliminary 5 ds9203/a-10 march 2007www.richtek.com functional pin description boot (pin 1) this pin provides ground referenced bias voltage to the upper mosfet driver. a bootstrap circuit is used to create a voltage that is suitable for driving a logic-level n-mosfet when operating at a single 5v power supply. this pin also could be powered from atx 12v, in this situation, an internal 6.0v regulator will supply to vcc pin for generating bias required inside the ic. ugate (pin 2) connect the ugate pin to the gate of upper mosfet. this pin provides the gate drive for the upper mosfet. gnd (pin 3) signal and power ground for the ic. all voltage levels are measured with respect to this pin. lgate (pin 4) connect the lgate pin to the gate of lower mosfet. this pin provides the gate drive for the lower mosfet. vcc (pin 5) this is the main bias supply for the rt9203/a. this pin also provides the gate bias charge for the gate of lower mosfet. the voltage at this pin is monitored for ensuring a proper power-on reset (por). this pin is also the out of an internal 6.0v regulator that powered from the boot pin when the boot pin is directly powered from atx 12v. drv (pin 6) this pin is the output of a linear controller. it should be connected to the base of an external bypass npn transistor or the gate of a n-mosfet to form a linear low dropout regulator. fbl (pin 7) this pin is connected to the output resistor-divider of an external power transistor or a n-mosfet based low dropout regulator for regulating and monitoring the output voltage. this pin is also connected to the protection monitor and the invertering input of error amplifier of internal linear regulator inside the ic. fb (pin 8) this pin is connected to the pwm converter's output-divider for regulating and monitoring the output voltage of buck converter. this pin also connects to the protection monitor and the inverting input of internal pwm error amplifier inside the ic.
rt9203/a preliminary 6 ds9203/a-10 march 2007 www.richtek.com absolute maximum ratings electrical characteristics l supply voltage vcc------------------------------------------------------------------------------------------------7v l boot & ugate to gnd-------------------------------------------------------------------------------------------19v l input, output or i/o voltage---------------------------------------------------------------------------------------gnd-0.3v to 7v l power dissipation, p d @ t a = 25 c sop-8------------------------------------------------------------------------------------------------------------------0.625w l package thermal resistance sop-8, q ja -------------------------------------------------------------------------------------------------------------160 c/w l ambient temperature range--------------------------------------------------------------------------------------0 c to +70 c l junction temperature range-------------------------------------------------------------------------------------- - 40 c to +125 c l storage temperature range--------------------------------------------------------------------------------------- - 65 c to +150 c l lead temperature (soldering, 10 sec.)--------------------------------------------------------------------------260 c (v cc = 5v, t a = 25 c, unless otherwise specified.) caution: stresses beyond the ratings specified in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. parameter symbol test conditions min typ max units vcc supply current nominal supply current i cc ugate, lgate open -- 3 -- ma vcc regulated voltage v cc v boot = 12v 5.0 6.0 7.0 v power-on reset rising vcc threshold 3.8 4.1 4.4 v vcc threshold hysteresis -- 0.5 -- v reference reference voltage v fb both pwm and linear regulator 0.784 0.8 0.816 v oscillator free running frequency 250 300 350 khz ramp amplitude d v osc -- 1.75 -- v p-p pwm error amplifier dc gain 32 35 38 db pwm controller gate driver upper drive source r ugate boot = 12v boot-v ugate = 1v -- 7.5 11 w upper drive sink r ugate v ugate = 1v -- 5 8 w lower drive source r lgate vcc - v lgate = 1v -- 3.5 6 w lower drive sink r lgate v lgate = 1v -- 2 5 w linear regulator drv driver source v drv = 2v 100 -- -- ma to be continued
rt9203/a preliminary 7 ds9203/a-10 march 2007www.richtek.com parameter symbol test conditions min typ max units protection fb over-voltage trip fb rising 0.9 1 -- v fb & fbl under-voltage trip fb & fbl falling -- 0.5 0.65 v soft-start interval -- 2.5 -- ms
rt9203/a preliminary 8 ds9203/a-10 march 2007 www.richtek.com typical operating characteristics dead time time (50ns/div) ugate lgate v cc = 5v dead time time (50ns/div) ugate lgate v cc = 5v power on time (2.5ms/div) v cc v out1 v cc = 5v v out1 = 2.5v v out2 = 1.8v v out2 power on time (50ms/div) v cc v out1 v cc = 5v v out1 = 2.5v v out2 = 1.8v v out2 ugate load transient time (5us/div) v out v cc = 5v v out = 2.2v c out = 3000uf ugate load transient time (5us/div) v out v cc = 5v v out = 2.2v c out = 3000uf
rt9203/a preliminary 9 ds9203/a-10 march 2007www.richtek.com ugate short hiccup (latch mode) v out v cc = 5v v out = 2.2v rt9203 time (2ms/div) ugate short hiccup time (2ms/div) v out v cc = 5v v out = 2.2v rt9203a time (1us/div) ugate bootstrap wave form phase v cc = 5v, v out = 2.2v lgate reference vs. temperature 0.796 0.797 0.798 0.799 0.800 0.801 0.802 0.803 -50050100150 temperature r e f e r e n c e ( v ) ( c) i ocset vs. temperature 20 25 30 35 40 45 50 55 -40-10205080110140 temperature i o c s e t ( u a ) 1 ( c) por (rising/falling) vs. temperature 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 -50050100150 temperature p o r ( v ) ( c) falling rising
rt9203/a preliminary 10 ds9203/a-10 march 2007 www.richtek.com oscillator frequency vs. temperature 270 275 280 285 290 295 300 305 310 315 -50050100150 temperature f r e q u e n c y ( k h z ) a ( c)
rt9203/a preliminary 11 ds9203/a-10 march 2007www.richtek.com application information the rt9203/a operates at either single 5v power supply with a bootstrap ugate driver or a 5v/12v dual-power supply form the atx smps. the dual- power supply is recommended for high current applications, the rt9203/ a can deliver higher gate driving current while operating with atx smps based on a dual-power supply. the bootstrap operation in a single power supply system, the ugate driver of rt9203/a is powered by an external bootstrap circuit, as shown in the figure 3. the boot capacitor, c boot , generates a floating reference at the phase pin. typically a 0.1 m f c boot is enough for most of mosfets used with the rt9203/a. the voltage drop between boot and phase is refreshed to a voltage of vcc - diode drop (v d ) while the lower mosfet turning on. figure 3. single 5v power supply operation dual power operation the rt9203/a was designed to supply a regulated 6.0v at vcc pin automatically when boot pin is powered by a 12v. in a system with atx 5v/12v power supply, the rt9203/a is ideal for higher current applications due to the higher gate driving capability, v ugate = 12v and v lgate = 6.0v. a rc (10 w /1 m f) filter is also recommended at boot pin to prevent the ringing induced from fast power- on, as shown in figure 4. figure 4. dual power supply operation power on reset the power-on reset (por) monitors the supply voltage (normal +5v) at the vcc pin and the input voltage at the ocset pin. the vcc por level is set to 4.1v with 0.5v hysteresis and the normal level at ocset pin is set to 1.5v (see over-current protection). the por function initiates soft-start operation after all supply voltages exceed their por thresholds. soft start a built-in soft-start is used to prevent surge current from power supply input during powering on. the soft-start voltage is controlled by an internal digital counter. it slows down and clamps the ramping of reference voltage at the input of error amplifier and the pulse-width of the output driver. the typical soft-start duration is 2.5ms. under voltage and over voltage protection the voltage presents at fb pin is monitored and protected against oc (over current), uv (under voltage), and ov (over voltage). the uv threshold is 0.5v and ov threshold is 1.0v. both uv and ov detection are with 30ms delay after triggered. when oc or uv trigged, a hiccup re-start sequence will be initialized, as shown in figure 5. for rt9203, only 3 times of trigger are allowed before latching off. but for rt9203a, uvp will be kept in hiccup mode. hiccup is disabled during soft-start interval. + 5v vcc lgate phase ugate boot r1 vcc c2 1uf rt9203/a 0.1uf d1 + 5v vcc lgate ugate boot r c2 1uf rt9203/a 1uf 6.0v regulation 10 c 12v vcc
rt9203/a preliminary 12 ds9203/a-10 march 2007 www.richtek.com inductor selection the rt9203/a was designed for v in = 5v, step-down application mainly. figure 6 shows the typical topology and waveforms of step-down converter. the ripple current of inductor can be calculated as follows: because operation frequency is fixed at 300khz, the v out ripple is esr is the equivalent series resistor of output capacitor table 1 shows the ripple voltage of v out at v in = 5v v out 3.3v 2.5v 1.5v inductor 2 m h 5 m h 2 m h 5 m h 2 m h 5 m h 1000 m f (esr=53m w ) 100mv 40mv 110mv 44mv 93mv 37mv 1500 m f (esr=33m w ) 62mv 25mv 68mv 28mv 58mv 23mv 3000 m f (esr=21m w ) 40mv 16mv 43mv 18mv 37mv 15mv *refer to sanyo low esr series (ce, dx, px......) the suggested l and c are as follows: 2 m h with 3 1500 m f c out 5 m h with 3 1000 m f c out 0a 0v 2v 4v i n t e r n a l s s i n d u c t o r c u r r e n t t1t2 t3 time count = 1 count = 2 count = 3 overload applied t0 figure 5 figure 6 v i v o r c d l q c.c.m t on t off t s v l v i - v o - v o uq mi l i l = i o i l i q i q i d i d out ripple on (5v - v) il= t l out on v t = 3.33 5v out rippleripple v = il esr table 1
rt9203/a preliminary 13 ds9203/a-10 march 2007www.richtek.com input / output capacitor high frequency/long life decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance to the pcb trace, as it could eliminate the performance from utilizing these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. the output capacitors are necessary for filtering output and stabilizing the close loop (see the pwm loop stability). for powering advanced high-speed processors, it is required to meet fast load transient requirement. also high esr usually induces ripple that may trigger uv or ov protections. so high frequency capacitors with low esr/ esl capacitors are recommended here. linear regulator driver the linear controller of rt9203/a was designed to drive an external bipolar npn transistor or a mosfet. for a mosfet, normally drv need to provide minimum v out2 +vt+gate-drive voltage to keep v out2 as the set voltage. when driving mosfet operating at a 5v power supply, the gate-drive will be limited at 5v. at this situation, as shown in figure 7, a mosfet with low vt threshold (vt = 1v) and set vout2 below 2.5v are suggested. in v boot = 12v operation condition, as figure 8. shown, vcc is regulated higher than 6v, which providing higher gate- drive capability for driving the mosfet, v out2 can be set as v out2 3.3v. figure 8 pwm loop stability the rt9203/a is a voltage mode buck controller designed for 5v step-down applications. the gain of error amplifier is fixed at 35db for simplifying design. the output amplitude of ramp oscillator is 1.6v, the loop gain and loop pole/zero are calculated as follows: the rt9203/a bode plot is as shown in figure 9. it is stable in most of application conditions. figure 7 figure 9 p p a out o a o 50.8 dc loop gain g = 35db 1.75v 1 lc filter pole p = 2lc error amp pole p = 300khz 1 esr zero z = 2esrc loop gain 40 30 20 10 1m 10k 1k 100 100k v out = 3.3v c out = 1500 m f(33m w ) l = 2 m h v out = 1.5v v out = 2.5v v out = 3.3v p o = 2.9khz z o = 3.2khz boot vcc drv fbl rt9203/a v cc = 5v r4 r3 max. 5v suggest low v t mosfet v out2 < 2.5v + r4<1k boot vcc drv fbl rt9203/a 6v r4 r3 max. 6v suggest low v t mosfet v out2 < 3.3v + r4<1k v boot = 12v
rt9203/a preliminary 14 ds9203/a-10 march 2007 www.richtek.com reference voltage because rt9203/a uses a low 35db gain error amplifier, as shown in figure 10. the voltage regulation is dependent on v in and v out settings. the fb reference voltage of 0.8v were trimmed at v in = 5v and v out = 2.5v. in a fixed v in = 5v application, the fb reference voltage vs. v out voltage can be calculated as figure 11. figure 11 feedback divider the reference of rt9203/a is 0.8v. the output voltage can be set using a resistor-divider as shown in figure 12. put the r1 and r2 as close as possible to fb pin. r2 value should be less than 1 k w to avoid noise coupling issue. the c1 capacitor is a speed-up capacitor for reducing output ripple to meet with the requirement of fast transient load. typically a 1nf ~ 0.1 m f is enough for c1. figure 12 pwm layout considerations mosfets switch very fast in efficiency. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. the voltage spikes can degrade efficiency and radiate noise, that results in over-voltage stress on devices. careful the layout for component placement and printed circuit design can minimize the voltage spikes induced in the converter. consider, as an example, the turn-off transition of the upper mosfet prior to turn-off, the upper mosfet was carrying the full load current. during turn-off, current stops flowing in the upper mosfet and is picked up by the lower mosfet or schottky diode. any inductance in the switched current path generates a large voltage spike during the switching interval. care with component selections, layout of the critical components, and use shorter and wider pcb traces that help in minimizing the magnitude of voltage spikes. there are two sets of critical components in a dc-dc converter using the rt9203/a. the switching power components are most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. the critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. the power components and the pwm controller should be placed firstly. place the input capacitors, especially the high-frequency ceramic decoupling capacitors, close to the power switches. place the output inductor and output capacitors between the mosfets and the load. also locate the pwm controller near by mosfets. + - ea + - pwm r1 56k r1 1k + - fb rep 0.8v ramp 1.75v figure 10 f b ( v ) duty (%) 80 70 60 20304050 0.82 0.78 0.80 0.81 0.79 10 90 v in + r1 c1 fb rt9203/a v out l r2 <1k c out outfb r1 v=v(1+) r2
rt9203/a preliminary 15 ds9203/a-10 march 2007www.richtek.com a multi-layer printed circuit board is recommended. figure 13 shows the connections of the critical components in the converter. note that the capacitors cin and cout represent numerous physical capacitors. use a dedicated grounding plane and use vias to ground all critical components to this layer. apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase node, but it is not necessary to oversize this particular island. since the phase node is subjected to very high dv/dt voltages, the stray capacitance formed between these islands and the surrounding circuitry will tend to couple switching noise. use the remaining printed circuit layers for small signal routing. the pcb traces between the pwm controller and the gate of mosfet and also the traces connecting source of mosfets should be sized to carry 2a peak currents. + + load + vcc gnd rt9203/a fb lgate ugate il iq1 v out q2 q1 iq2 5v gnd figure 13
rt9203/a preliminary 16 ds9203/a-10 march 2007 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 8f, no. 137, lane 235, paochiao road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)89191466 fax: (8862)89191465 email: marketing@richtek.com outline dimension a b j f h m c d i 8-lead sop plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.050 0.254 0.002 0.010 j 5.791 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050

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