a8499-ds high voltage step-down regulator a8499 ? 8 to 50 v input range ? integrated dmos switch ? adjustable fixed off-time ? highly efficient ? adjustable 1.2 to 24 v output package lj, 8-pin soic with exposed thermal pad features ? printer power supplies ? consumer equipment power supplies applications the a8499 is a step down regulator that will handle a wide input operating voltage range. the a8499 is supplied in a low-profile 8-lead soic with exposed pad (package lj ). vin lx boot enb tset gnd vbias fb +42 v 220 f 10 v esr vout cout 3.3 v / 1.2 a 17.8 k r1 l1 d1 r2 10.2 k 0.22 f 0.01 f cboot c3 c3 rtset 121 k 47 h 100 f 50 v a8499 efficiency vs. output current 70.0 72.0 74.0 76.0 78.0 80.0 82.0 84.0 86.0 88.0 90.0 0 200 400 600 800 1000 1200 1400 i out (ma) efficiency % 3.3 5 v out (v) circuit for 42 v step down to 3.3 v at 1.2 a. efficiency data from circuit shown in left panel.data is for reference only. typical application approximate scale 1:1
a8499-ds allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com a8499 high voltage step-down regulator 2 functional block diagram ab so lute max i mum rat ings package thermal characteristics* package r ja (c/w) pcb lj 35 4-layer * additional information is available on the allegro web site supply voltage, v in ......................................................................... 50 v vbias input voltage, v bias ................................................. ?0.3 to 7 v switch voltage, v lx ........................................................................ ?1 v enb input voltage, v enb ...................................................... ?0.3 to 7 v junction temperature, t j(max) ....................................................... 150c storage temperature, t s ............................................... ?55c to 150c operating ambient temperature, t a ............................... ?20c to 85c + C + C + C boot enb tset gnd vin lx fb vbias switch pwm c soft start ramp generation comp 1.2 v boot charge vbias is connected to vout when v out target is between 3.3 and 5 v d1 l1 v in cout vout esr uvlo tsd switch disable bias supply i_peak i_demand clamp use the following complete part number when ordering: part number packing description A8499SLJTR-T 13-in. reel, 3000 pieces/reel surface mount leadframe plating 100% matte-tin.
a8499-ds allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com a8499 high voltage step-down regulator 3 characteristics symbol test conditions min. typ. max. units vin quiescent current i vin(q) v enb = low, i out = 0 ma, v in = 42 v v bias = v out (see note 3 ) ? 0.90 1.35 ma v enb = low, i out = 0 ma, v in = 42 v v bias < 3 v ? 4.4 6.35 ma v enb = high ? ? 100 a vbias input current i bias v bias = v out ? 3.5 5 ma buck switch on resistance r ds(on) t a = 25c, i out = 2 a ? 700 800 m t a = 125c, i out = 2 a ? ? 1.6 fixed off-time proportion based on calculated value ?15 ? 15 % feedback voltage v fb 1.176 1.200 1.224 v output voltage regulation i out = 0 ma to 2 a ?3 ? 3 % feedback input bias current i fb ?400 ?100 100 na soft start time t ss 51015ms buck switch current limit i cl v fb > 0.5 v 2.2 ? 3 a v fb < 0.5 v 0.5 ? 1.2 a enb open circuit voltage v oc output disabled 2.0 ? 7 v enb input voltage threshold v enb(0) low level input (logic 0), output enabled ? ? 1.0 v enb input current i enb(0) v enb = 0 v ?10 ? ?1 a vin undervoltage threshold v uvlo v in rising ? 6.9 7.1 v vin undervoltage hysteresis v uvlohys v in falling 0.7 ? 1.1 v thermal shutdown temperature t jtsd temperature increasing ? 165 ? c thermal shutdown hysteresis t j recovery = t jtsd ? t j ?15?c 1. negative current is defined as coming out of (sourcing) the specified device pin. 2. specifications over the junction temperature range of 0oc to 125oc are assured by design and characterization. 3. vbias is connected to vout node when v out target level is between 3.3 and 5 v. electrical characteristics 1,2 at t a = 25c, v in = 8 to 50 v (unless noted otherwise)
a8499-ds allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com a8499 high voltage step-down regulator 4 functional description the a8499 is a fixed off-time, current-mode?controlled buck switching regulator. the regulator requires an external clamping diode, inductor, and filter capacitor, and operates in both continu- ous and discontinuous modes. an internal blanking circuit is used to filter out transients resulting from the reverse recovery of the external clamp diode. typical blanking time is 200 ns. the value of a resistor between the tset pin and ground deter- mines the fixed off-time (see graph in the t off section). v out . the output voltage is adjustable from 1.2 to 24 v, based on the combination of the value of the external resistor divider and the internal 1.2 v 3% reference. the voltage can be calculated with the following formula: v out = v fb (1 + r1/r2) (1) light load regulation. to maintain voltage regulation during light load conditions, the switching regulator enters a cycle-skip- ping mode. as the output current decreases, there remains some energy that is stored during the power switch minimum on-time. in order to prevent the output voltage from rising, the regulator skips cycles once it reaches the minimum on-time, effectively making the off-time larger. soft start. an internal ramp generator and counter allow the out- put to slowly ramp up. this limits the maximum demand on the external power supply by controlling the inrush current required to charge the external capacitor and any dc load at startup. internally, the ramp is set to 10 ms nominal rise time. during soft start, current limit is 2.2 a minimum. the following conditions are required to trigger a soft start: ? v in > 6 v ? enb pin input falling edge ? reset of a tsd (thermal shut down) event v bias . to improve overall system efficiency, the regulator output, v out , is connected to the vbias input to supply the operating bias current during normal operating conditions. during start up the circuitry is run off of the vin supply. vbias should be con- nected to vout when the v out target level is between 3.3 and 5 v. if the output voltage is less than 3.3 v, then the a8499 can operate with an internal supply and pay a penalty in efficiency, as the bias current will come from the high voltage supply, vin. vbias can also be supplied with an external voltage source. no power-up sequencing is required for normal opperation. on/off control. the enb pin is externally pulled to ground to enable the device and begin the soft start sequence. when the enb is open circuited, the switcher is disabled and the output decays to 0 v. protection. the buck switch will be disabled under one or more of the following fault conditions: ? v in < 6 v ? enb pin = open circuit ? tsd fault when the device comes out of a tsd fault, it will go into a soft start to limit inrush current. t off . the value of a resistor between the tset pin and ground determines the fixed off-time. the formula to calculate t off ( s) is: tset = t off 1. 2 10 10 r , (2) where r tset (k ) is the value of the resistor. results are shown in the following graph: t on . from the volt-second balance of the inductor, the turn-on time, t on , can be calculated approximately by the equation: = t on ( v out + v f + i out r l ) t off v in ? i out r ds(on) ? i out r l ? v ou t (3) where v f is the voltage drop across the external schottky diode, r l is the winding resistance of the inductor, and r ds(on) is the on-resistance of the switching mosfet. resistance vs. off-time 1 3 5 7 9 11 13 15 17 12 36 60 84 108 132 156 180 r tset (k ) t off (s)
a8499-ds allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com a8499 high voltage step-down regulator 5 the switching frequency is calculated as follows: = f sw 1 t on + t off (4) shorted load. if the voltage on the fb pin falls below 0.5 v, the regulator will invoke a 0.8 a typical overcurrent limit to handle shorted load condition at the regulator output. for low output voltages at power up and in the case of a shorted output, the off- time is extended to prevent loss of control of the current limit due to the minimum on-time of the switcher. the extension of the off-time is based on the value of the tset multiplier and the fb voltage, as shown in the following table: v fb (v) tset multiplier < 0.25 8 t off < 0.50 4 t off < 0.75 2 t off > 0.75 t off component selection l1. the inductor must be rated to handle the total load current. the value should be chosen to keep the ripple current to a reason- able value. the ripple current, i ripple , can be calculated by: i ripple = v l(off) t off / l (5) v l(off) = v out + v f + i l(avg) r l (6) example: given v out = 5 v, v f = 0.55 v, v in = 42 v, i load = 0.5 a, power inductor with l = 180 h and r l = 0.5 rdc at 55c, t off = 7 s, and r ds(on) = 1 . substituting into equation 6: v l(off) = 5 v + 0.55 v+ 0.5 a 0.5 = 5.8 v substituting into equation 5: i ripple = 5.8 v 7 s / 180 h = 225 ma the switching frequency, f sw , can then be estimated by: f sw = 1 / ( t on + t off ) (7) t on = i ripple l / v l(on) (8) v l(on) = v in ? i l(avg) r ds(on) ? i l(avg) r l ? v out (9) substituting into equation 9: v l(on) = 42 v ? 0.5 a 1 ? 0.5 a 0.5 ? 5 v = 36 v substituting into equation 8: t on = 225 ma 180 h / 36 v = 1.12 s substituting into equation 7: f sw = 1 / (7 s +1.12 s) = 123 khz higher inductor values can be chosen to lower the ripple cur- rent. this may be an option if it is required to increase the total maximum current available above that drawn from the switching regulator. the maximum total current available, i load(max) , is: i load(max) = i cl(min) t off / l (5) where i cl(min) is 2.2 a, from the electrical chracteristics table. d1. the schottky catch diode should be rated to handle 1.2 times the maximum load current. the voltage rating should be higher than the maximum input voltage expected during all operating conditions. the duty cycle for high input voltages can be very close to 100%. cout. the main consideration in selecting an output capacitor is voltage ripple on the output. for electrolytic output capacitors, a low-esr type is recommended. the peak-to-peak output voltage ripple is simply i ripple esr. note that increasing the inductor value can decrease the ripple current. the minimum voltage rating of the capacitor is 10 v, however, because esr decreases with voltage, the most cost- effective choice may be rated higher in voltage. the esr should be in the range from 50 to 500 m .
a8499-ds allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com a8499 high voltage step-down regulator 6 a 8499 boot enb tset gnd vin lx vbias fb 47 h c1 l1 22 f/ 25 v rtset 30.1 k r1 10 k r2 3.16 k cout 330 f/ 6.3 v (aluminum) +12 v vout 5.0 v / 1.8 a d1 b340 c2 0.1 f cboot 0.01 f 1 2 v step down to 5.0 v at 1.8 a pin name pin description lj soic-8 boot gate drive boost node 1 enb on/off control logic input 2 tset off-time setting 3 gnd ground 4 nc no connect n/a nc no connect n/a fb feedback for adjustable regulator 5 vbias bias supply input 6 lx buck switching node 7 vin supply input 8 pad exposed pad for thermal dissipation pad terminal list table typical application circuit 1 2 3 4 8 7 6 5 boot enb tset gnd vin lx vbias fb pad
a8499-ds allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com a8499 high voltage step-down regulator 7 the products described herein are man u fac tured under one or more patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support ap pli anc es, devices, or systems without e xpress written ap- proval. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no re spo n si bil i ty for its use; nor for any infringements of pat ents or other rights of third parties that may result from its use. copyright ? 2005 allegro microsystems, inc. package lj 8-pin soic 0.25 0.10 .010 .004 1.75 1.35 .069 .053 0.51 0.31 .020 .012 4.00 3.80 .157 .150 3.30 nom .130 2.41 nom .095 0.25 0.17 .010 .007 8o 0o 1.27 0.40 .050 .016 5.00 4.80 .197 .189 c seating plane a b 8x 0.25 [.010] m c a b 6.20 5.80 .244 .228 c 0.10 [.004] 8x 0.25 [.010] m b m 1.27 .050 0.25 .010 2 1 8 gauge plane seating plane b preliminary dimensions, for reference only dimensions in millimeters u.s. customary dimensions (in.) in brackets, for reference only (reference jedec ms-012 aa) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a b terminal #1 mark area exposed thermal pad (bottom surface) a
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