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T6K53 2001-11-07 1 toshiba cmos digital integrated circuit silicon monolithic T6K53 four-grayscale dot matrix graphic lcd driver with built-in ram the T6K53 is a single-chip, stn color lcd driver with built-in ram which can control up to 4096 colors. the T6K53 has 160 output common drivers and 384 output segment drivers. the T6K53 is capable of driving a graphics display with up to 128 rgb colors and up to 160 dots. the mpu interface allows efficient command setting and high-speed access to the display ram via a 16-bit parallel interface by means of the high-speed ram write function. the T6K53 has two grayscale modes: fixed-palette mode (with 16 predetermined gray levels) and selected palette mode. in selected palette mode the T6K53 enables high-quality display characteristics by allowing selection of any 16 gray levels from an lcd?s 32 available levels. the T6K53 lcd driver can be driven using a single power supply, since it incorporates a voltage regulator, a voltage-dividing resistance, an lcd driver op-amp, a dc-dc converter (with 3 to 8 holds) and a contrast (electronic volume) control circuit. since the T6K53 supports various display functions (e.g. a partial display function and area scroll mode), it is suitable for applications which require a long battery lifetime, such as web-capable mobile phones. features driver output : 128 rgb (384 outputs) 160 com display ram : 128 160 12 = 245,760 bits grayscale function : 4096 colors can be displayed with r = 16 levels, g = 16 levels and b = 16 levels pwm grayscale system (with 16-level fixed palette) word length : 8 bits/16 bits display modes : normal display mode full display partial display mode partial display standby mode clock stopped mpu interfaces : 8-bit/16-bit switching, 68/80 series parallel interface and serial interface ram access cycle : 100 ns or lower oscillator : built-in cr oscillator (with built-in oscillation cr). external clock pulses can be input. operating voltage : v dd = 1.7 v to 3.3 v, v in = 2.7 v to 3.3 v display operating voltage : 20.0 v max built-in display power supply circuits: dc-dc converter v in 8 (max) booster op amp v lc1 , v lc2 , v lc3 and v lc4 regulator 0.0%/c 0.02% cmos process : std 0.35 m + 22 v package : cof low power consumption : i ss = 300 a (typ.) target value usage conditions v dd = 3.0 v, display voltage = 20.0 v, no lcd load, ta = 25c, f frame = 70 hz, f osc = 168 khz (with internal oscillator used), no data access please contact toshiba or an authorized toshiba dealer for information on package dimensions. tcp (tape carrier package) lead pitch in out T6K53 unit: mm preliminar y
T6K53 2001-11-07 2 pin assignment com80 com159 segc127 sega0 com79 com0 (input pin layout has yet to be finalized.)
T6K53 2001-11-07 3 pin functions pin name i/o functions sega0 to sega127 o lcd drive segment signal output (red or blue): can be selected using swp. segb0 to segb127 o lcd drive segment signal output (green) segc0 to segc127 o lcd drive segment signal output (red or blue): can be selected using swp. com0 to com159 o lcd drive common signal output db0 to db15 i/o data bus /cs1 i chip select signal input 1 data write data is written on the rising edge of /cs1 data read data is read while /cs1 is low. cs2 i chip select signal input 2 data write data is written on the falling edge of cs2. data read data is read while cs2 is high. rs i register set / instruction data select signal input ? if rs is high, db0 to db15 are read as register number. ? if rs is low, db0 to db15 are read as instruction data. /wr (r/w) i write select signal input (read/write select signal input) ? if the 80 series mpu is selected, data is written when /wr is low. ? if the 68 series mpu is selected, whether read or write is in effect is indicated. /rd (e) i read select signal input ? if the 80 series mpu is selected, data is output on db0 to db7 while /rd is low. ? if the 68 series mpu is selected, this pin is used as an enable signal input (e). mpu i 68/80 series mpu parallel interface select signal input ? if mpu is high, the 68 series mpu parallel interface is selected. ? if mpu is low, the 80 series mpu parallel interface is selected. wls i data bus width select signal input ? 8-bit bus mode if wls is low. ? 16-bit bus mode if wls is high. /rst i reset signal ? a reset occurs if /rst is low. osc1 i/o built-in oscillation monitoring internal oscillation mode: output external oscillation mode: input exp i external power supply mode internal power supply mode if exp is low. external power supply mode if exp is high. in external power supply mode, dcdc and amp will remain off regardless of command settings. p/s i input for parallel/serial interface select signal the serial interface is selected if p/s is low. the parallel interface is selected if p/s is high. sck i serial interface clock input si i serial interface data input so o serial interface data output v ref lv regulator output c11 to c17 booster capacitor connection v out booster output. usually connected to v cc . v cc power supply for lcd drive voltage generation v lc5, v lc4, v lc3, v lc2, v lc1 lcd drive voltage output v dd ,v ss supply voltage
T6K53 2001-11-07 4 lcd power supply configuration draft power supply circuit (preliminary) v cc v out c8 c8 c1 c1 cmp v ref contrast control v lc0 v lc1 v lc2 v lc3 v lc4 v lc5 regulator bias dc-dc
T6K53 2001-11-07 5 signal timing mpu interface 80 series mpu 68 series mpu hi-z d/i /cs1 /rd, /w r /cs1 /rd, /wr db15 to db0 (write) db7 to db0 (read) db15 to db8 (command read) if accessed with /rd or /wr when /cs1 is low. if accessed with /cs1 when /rd or /wr is low. hi-z d/i, r/w cs2 e cs2 e db15 to db0 (write) db7 to db0 (read) db15 to db8 (command read) if accessed with e when cs2 is high. if accessed with cs2 when e is high.
T6K53 2001-11-07 6 display control section signal lp: signal for indicating frames fr: alternating signal. display waveforms are made to alternate in sync with this signal. cl: shift clock, used to synchronize display data output with row output. ck: minimum clock used as a reference for driving the lcd. it is used to control pulse levels. fr 3 r d line lp 2 n d line cl 1 s t line 4 th line scanning period (frame period) alternating setting (1 to 160 clock pulses) ck pwm clock: 15 clock
T6K53 2001-11-07 7 functions mpu interfaces the mpu interfaces can be connected directly to the data bus of the 8-bit/16-bit mpu for data transfer. the mpu pin can be used to select either the 80 and 68 series mpu interface for the 8-bit/16-bit mpu. mpu mpu type /cs1 cs2 /rd /wr data bus h 68 series mpu l cs e r/w db0 to db15 l 80 series mpu /cs h /rd /wr db0 to db15 data identification the contents of the data bus are identified using a combination of the rs, /rd and /wr signals. 80 series rs 68 series /rd /wr function l l h l register no. set l h l h status read h h l h display data read h l h l command and display data write 16-bit access to display ram the T6K53 supports 16-bit data access. data on the 16-bit data bus (db0 to db15) can be used to access display ram. the wls bit is used to specify 16-bit access mode as the data bus mode. wls data bus width db0 to db7 db8 to db15 1 16-bit access mode db0 to db7 db8 to db15 0 8-bit access mode db0 to db7 high or low input note that even in 16-bit access mode, the internal registers are accessed in 8-bit mode (db0 to db7). therefore, 16-bit access mode is only valid for display ram access.
T6K53 2001-11-07 8 data bus mode and display ram address the mpu sets up display ram addresses using x- and y-addresses which are in pixel units. when the data bus mode is switched, address conversion is handled automatically. the following paragraphs describe display ram addresses for each data bus mode. (1) 8-bit mode in this mode, a single pixel?s data is transferred using two 8-bit data accesses. hence, 8-bit mpu data accesses are used. the transfer format is as follows: the first access sets the 8 low-order bus bits to the value of the 8 low-order dd bits, and the second access sets the 4 high-order bus bits to the value of the 4 high-order dd bits. for example, if a data transfer is interrupted after the fifth access (by an access to another command register), the access will be resumed using the 4 high-order bits of 002h (unless the y-adr has been reset). to restart data access from the point at which it was interrupted, set the y-adr to 002h. pixel first pixel second pixel y-adr 000h 001h dd bit d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bus bit d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 data access second first fourth third start y-adr: when 000h pixel first pixel second pixel third pixel fourth pixel fifth pixel y-adr 000h 001h 002h 003h 004h data access second first fourth third sixth fifth eighth seventh tenth ninth start y-adr: when 002h pixel third pixel fourth pixel fifth pixel sixth pixel seventh pixel y-adr 002h 003h 004h 005h 006h data access second first fourth third sixth fifth eighth seventh tenth ninth pixel : display pixel y- a d r : y- a d d r e s s dd bit : display data bit bus bit : data bus bit data access: number of accesses
T6K53 2001-11-07 9 (2) 16-bit mode this mode transfers one-pixel data with one 16-bit data access. so the data access of the 16-bit mpu is used. the 12 low-order bus bits (d11 to d0) correspond to the dd bits. pixel first pixel second pixel y-adr 000h 001h dd bit d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bus bit d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data access first second start y-adr: when 000h pixel first pixel second pixel third pixel fourth pixel fifth pixel y-adr 000h 001h 002h 003h 004h data access first second third fourth fifth start y-adr: when 002h pixel third pixel fourth pixel fifth pixel sixth pixel seventh pixel y-adr 002h 003h 004h 005h 006h data access first second third fourth fifth pixel : display pixel y- a d r : y- a d d r e ss dd bit : display data bit bus bit : data bus bit data access: number of accesses
T6K53 2001-11-07 10 display ram the T6K53 incorporates a bitmap display ram consisting of 160 pixels 128 rgb levels. the display ram section consists of 12 bits 128 (= 1536 bits) in the y-address direction and 160 bits in the x-address direction. the grayscale is controlled via 4-bit segment by driver outputs which correspond to the 16 grayscale levels. hence, three rgb segment driver outputs service one pixel, using four bits each for the r, g and b levels for a total of 12 bits supporting 4096 display colors (16 levels 16 levels 16 levels). the mcu sets up each ram address in pixel units by y-address/x-address pairing, as shown below: segai * i 0 to 127 grayscale control d10 d9 d8 d11 segbi grayscale control d6 d5 d4 d7 segci grayscale control d2 d1 d0 d3 x-adr 0h x-adr 1h x-adr 2h d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 12 bit 12 bit y-adr 0h 12 bit 12 bit 12 bit y-adr 1h y-adr 7fh x-adr 9fh 12 bit 12 bit 12 bit 12 bit 12 bit 12 bit
T6K53 2001-11-07 11 display ram addresses data in the ram area can be accessed continuously. if data access is performed in the address area (x-address = 00h to 9fh and y-address = 00h to 7fh) in y-address count mode, the y-address changes from 00h to 01h. if data access is performed while the y-address = 7fh, the y-address will become 00h and the x-address will be incremented to 01h. if a data access is performed when the y-address = 7fh and the x-address = 9fh, the y-address and the x-address will both be set to 00h. if a data access is performed in x-address count mode, the x-address will be incremented from 00h to 01h. every time a data access is performed when the x-address = 9fh, the x-address will wrap around to 00h and the y-address will be set to 01h. if a data access is performed when the y-address = 7fh and the x-address = 9fh, the y-address and the x-address will both be set to 00h. y-address count mode (y-adr area = 00h to 7fh and x-adr area = 00h to 9fh) x-address count mode (y-adr area = 00h to 7fh and x-adr area = 00h to 9fh) 00h 01h 02h 03h 04h 05h 06h 07h 08h 7fh 00h 01h 02h 03h y-address 9fh x-address 00h 01h 02h 03h 04h 05h 06h 07h 08h 7fh 00h 01h 02h 03h y-address 9fh x-address
T6K53 2001-11-07 12 setting up the display ram access area setting up the ram access area using the y-address control circuit and the x-address control circuit allows only part of the ram address area to be accessed. y-address control circuit in y-address count mode, setting up the addresses for the y-address area (y-start and y-end) causes the y-address to be incremented from the y-start address to the y-end address and then to wrap around back to the y-start address. when the y-address wraps around, the x-address is also incremented by one. x-address control circuit in x-address count mode, setting up the addresses for the x-address area (x-start and x-end) causes the x-address to be incremented from the x-start address to the x-end address and then to wrap around back to the x-start address. when the x-address wraps around, the y-address is also incremented by one. x-address area y-address area
T6K53 2001-11-07 13 display direction sdr the s dr pin is used to set up the direction of segment display. this is implemented by inverting the y-address when the display data is written. if sdr is low if sdr is high cdr the cdr pin is used to change the direction of com scanning. the two com scanning directions ( ) are shown below. cdr l cdr h for 1/144 duty for 1/160 duty display area com0 com8 com151 com159 display area com0 com8 com151 com159 display area com0 com160 display area com0 com160 y 0 y 1 y 2 y 127 sega0 segb0 segc0 sega1 segb1 segc1 sega2 segb2 segc2 sega127 segb127 segc127 x 0 x 159 y 127 y 126 y 125 y 0 sega0 segb0 segc0 sega1 segb1 segc1 sega2 segb2 segc2 sega127 segb127 segc127 x 0 x 159
T6K53 2001-11-07 14 swp the swp pin is used to change the rgb assignments for the seg outputs (ai, bi and ci). this function implements r-b swapping in the grayscale control circuits. swp 0 swp 1 segai segbi segci red green blue color swap 0 d11 to d8 d7 to d4 d3 to d0 corresponding bits blue green red color swap 1 d3 to d0 d7 to d4 d11 to d8 corresponding bits * i 0 to 127 ram data segai grayscale level control d10 d9 d8 d11 segbi d7 segci d6 d5 d4 grayscale level control d2 d1 d0 d3 grayscale level control msb lsb msb lsb msb lsb segai 1 grayscale level control d10 d9 d8 d11 segbi 1 d7 segci 1 d6 d5 d4 grayscale level control d2 d1 d0 d3 grayscale level control msb lsb msb lsb msb lsb * i 0 to 127 ram data segai grayscale level control segbi segci grayscale level control grayscale level control segai 1 grayscale level control segbi 1 segci 1 grayscale level control grayscale level control d10 d9 d8 d11 d7 d6 d5 d4 d2 d1 d0 d3 msb lsb msb lsb msb lsb d10 d9 d8 d11 d7 d6 d5 d4 d2 d1 d0 d3 msb lsb msb lsb msb lsb
T6K53 2001-11-07 15 relationship between sdr-/swp-based display ram and output sdr swp 0 0 seg no. seg0 seg1 seg127 output a b c a b c a b c color red green blue red green blue red green blue data bit d11 to d8 d7 to d4 d3 to d0 d11 to d8 d7 to d4 d3 to d0 d11 to d8 d7 to d4 d3 to d0 y-address 00h 01h 7fh 0 1 seg no. seg0 seg1 seg127 output a b c a b c a b c color blue green red blue green red blue green red data bit d3 to d0 d7 to d4 d11 to d8 d3 to d0 d7 to d4 d11 to d8 d3 to d0 d7 to d4 d11 to d8 y-address 00h 01h 7fh 1 0 seg no. seg0 seg1 seg127 output a b c a b c a b c color blue green red blue green red blue green red data bit d3 to d0 d7 to d4 d11 to d8 d3 to d0 d7 to d4 d11 to d8 d3 to d0 d7 to d4 d11 to d8 y-address 7fh 7eh 00h 1 1 seg no. seg0 seg1 seg127 output a b c a b c a b c color red green blue red green blue red green blue data bit d11 to d8 d7 to d4 d3 to d0 d11 to d8 d7 to d4 d3 to d0 d11 to d8 d7 to d4 d3 to d0 y-address 7fh 7eh 00h
T6K53 2001-11-07 16 display modes the following display modes are supported. ?normal mode ?partial display mode ?standby mode each mode is described below. normal mode this is the mode which is used normally. it is selected when a reset occurs. to start up a display in practice, however, requires the execution of the display on command. normal mode uses the following settings: display size : duty cycle setting display bias : bias (1) contrast setting: contrast (1) display on/off display on once a reset function is executed, the following settings must be made before display on is executed: ?stand-by mode off ?oscillator on ?op amp on executing display on sets /doff high and takes the circuit out of the display off state, thus enabling display. display off executing the display off command causes the following: ?all seg outputs : vlc2 or vlc3 (inverted by fr) ?all com outputs : vlc1 or vlc4 (inverted by fr)
T6K53 2001-11-07 17 partial display mode in this mode it is possible to specify a partial screen area for display (64 lines or 32 lines plus start block). this mode consumes little power compared with full-screen display mode and is thus suitable for use for standby modes on a mobile phone. this mode is valid when the display is on. to set up the partial display area, specify the partial area start block (scanning start position) with a block number for every four lines as shown below. the partial area size can be selected as either 64 lines and 32 lines. switching from normal mode to the partial display mode will occur at the start of the first frame after the setting has been completed. operation in partial display mode display duty cycle 1/64 duty or 1/32 duty display bias bias (2) contrast value contrast (2) oscillation circuit automatic frequency switching seg output level display data (v lc0 , v lc2, v lc3 , v lc5 ) com output (partial display section) scanning (v lc0, v lc1, v lc4, v lc5 ) common output (non-display area) v lc1 or v lc4 (inverted by fr) display section partial start line 64 lines (fixed) non-display area : not scanned (com = vlc1 or vlc4) partial display section : the section that is actually displayed com0 com152 com4 com148 com8 com156 block0 block1 block2 block37 block38 block39
T6K53 2001-11-07 18 example of use (1) 1/160 duty cdr 0 mode 1 (64 line) pds 0ch (2) 1/160 duty cdr 0 mode 0 (32 lines) pds 1fh (3) 1/160 duty cdr 0 mode 1 (64 lines) pds 1fh com12 display area com75 com127 display area com159 com127 display area com159 com0 display area com31
T6K53 2001-11-07 19 area scroll function it is possible to scroll the screen display partially by specifying the scroll area (start block, end block and the number of specific blocks). 1 block consists of 4 lines. this mode is valid after display on is executed. area scrolling supports four area modes. it is possible to scroll the screen display partially by specifying the scroll area (start block, end block and the number of specific blocks). the size of a ram block must be specified in multiples of 4 lines. the size of the display duty cycle block must also be specified in multiples of 4 lines. standby mode standby mode on/off standby mode the standby command causes the device to enter standby mode. in standby mode: ?all seg outputs : v ss ?osc : off ?display clock (fr, pm, lp and cl) : stopped ?op-amp for display power : off (vlc0 to vlc5 = fixed at v ss ) ?dc-dc conversion operation for display : off ?/doff : low output ?/stb : low output in standby mode, it is possible to access commands and display data. exiting standby mode when standby mode is exited: ?all seg outputs : doff (vlc2 or vlc3) ?all com outputs : doff (vlc1 or vlc4) ?osc : on (state before standby mode was entered) ?booster : on (state before standby mode was entered) ?op-amp : on (state before standby mode was entered) the states other than display off are the same as before the device entered standby mode. therefore, after the device has exited standby mode, the display on command must be executed before data can be displayed on-screen. full-screen upper-screen section lower-screen section middle-screen section
T6K53 2001-11-07 20 grayscale control circuit pwm grayscale two grayscale modes are available for selection on the T6K53. gs = 0: fixed-palette mode (16 predetermined grayscale levels) gs = 1: palette selection mode (any 16 grayscale levels selected from 32 available levels.) fixed-palette mode if gs = 0, fixed-palette mode is selected. in this mode, grayscale level output is performed using a predetermined 16-grayscale palette. 1 1 1 1 1 1 1 8 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 row selection period (1cl period) ck row selection period gs0 gs1 gs2 gs3 gs4 gs5 gs6 gs7 gs8 gs9 gs10 gs11 gs12 gs13 gs14 gs15 on off
T6K53 2001-11-07 21 palette selection mode if gs = 1, palette selection mode is selected. in this mode, one row selection period is divided into 31 parts so as to enable selection of 16 grayscale levels from 32 available levels (gl0 to gl31) for display grayscale output. 1 1 16 2 1 3 4 5 6 7 8 9 10 11 12 13 14 one row selection period ck gl0 on off 1 1 1 1 1 1 1 1 1 1 1 1 1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 gl1 gl2 gl3 gl4 gl5 gl6 gl7 gl8 gl9 gl10 gl11 gl12 gl13 gl14 gl15 gl16 gl17 gl18 gl19 gl20 gl21 gl22 gl23 gl24 gl25 gl26 gl27 gl28 gl29 gl30 gl31
T6K53 2001-11-07 22 individual palettes can be selected for r, g and b separately. three separate sets of 16 grayscale levels can be selected from the 32 grayscale levels shown above (for r, g and b) (gl0 to gl31) and set up in gs0 to gs15. gray scale level db4/12 db3/11 db2/10 db1/9 db0/8 gl0 0 0 0 0 0 gl1 0 0 0 0 1 gl2 0 0 0 1 0 gl30 1 1 1 1 0 gl31 1 1 1 1 1
T6K53 2001-11-07 23 normal/reverse display in this mode data output for display on the lcd is reversed without alteration to the display image data. rev = 0: turned on for data values of 1, i.e. vlc0 or vlc5 is selected as seg output when data value = 1. rev = 1: turned on for data values of 0, i.e. vlc0 or vlc5 is selected as seg output when data value = 0. switching of the pwm waveform output timing gs0 row select time n line sgm 0 n 1 line on off gs1 gs2 gs3 gs4 gs5 gs6 gs7 gs8 gs9 gs10 gs11 gs12 gs13 gs14 gs15 row select time n line sgm 1 n 1 line on off seg waveform (sgm 0) 1 row select seg waveform (sgm 0)
T6K53 2001-11-07 24 oscillation circuit the oscillation circuit incorporates both a capacitor and a resistor. when the built-in oscillator is used (ext = 0), the oscillation resistor incorporated in the oscillation circuit is switched automatically as the device is switched between normal/partial display mode (1) and duty cycle setting mode. oscillation frequencies when the built-in oscillation circuit is used display mode duty cycle setting oscillation frequency (typical) 1/160 duty 168.0 khz 1/144 duty 151.2 khz normal 1/128 duty 134.4 khz 1/64 duty 67.2 khz partial 1/32 duty 67.2 khz (divided by 2 to give internal clock) frame period = 70 hz (typical) calculation method: f osc = frame period (display line count) clock division number (15) for a partial display in 1/32 duty mode, the internal clock pulses are generated at a frequency obtained by dividing the frequency for a partial display in 1/64 duty mode by 2. if ext = 1, external clock mode is selected and an external clock signal can be input on the osc pin. in external clock mode, switching between the normal and partial display modes requires that the clock frequency be changed according to the display mode which is to be selected.
T6K53 2001-11-07 25 data bus behavior when data is accessed (example: mpu = l, i.e. device is in 80 mode) register set 8-bit mode 16-bit mode rs /cs1 /w r /rd h db7 to db0 command no. rs /cs1 /w r /rd h db7 to db0 db15 to db8 h or l command no.
T6K53 2001-11-07 26 command read (status read) 8-bit mode 16-bit mode rs /cs1 /w r /rd h db7 to db0 status read rs /cs1 /w r /rd h db7 to db0 db15 to db8 hi-z status read
T6K53 2001-11-07 27 command data write 8-bit mode 16-bit mode rs /cs1 /wr /rd h db7 to db0 8 low-order bits h db15 to db8 8 high-order bits h or l rs /cs1 /w r /rd h db15 to db0 data h
T6K53 2001-11-07 28 display data write 8-bit mode 16-bit mode rs /cs1 /wr /rd h db7 to db0 h db15 to db8 8 low-order bits 4 high-order bits h or l rs /cs1 /w r /rd h db15 to db0 data 1 h data 2
T6K53 2001-11-07 29 display data read 8-bit mode 16-bit mode rs /cs1 /wr /rd h db7 to db0 db15 to db8 hi-z 8 low-order bits 4 high-order bits data n h rs /cs1 /w r /rd h db15 to db0 data 1 data 2 data n h
T6K53 2001-11-07 30 clock-synchronous serial interface setting the p/s pin to the vss level enables data to be transferred via a clock-synchronous serial interface. when data is transferred in this way, a synchronous clock input is received on the sck pin, and transfer data is input on the si pin and output on the so pin. just as with the parallel interface, the /cs1 and cs2 pins can be used for a chip select signal. if the /cs1 pin is used, for example, data transfer begins when /cs1 changes from high to low and ends when it changes from low to high. the cs2 pin is fixed at the vdd level. the basic transfer data format uses 24 bits in total. the first eight bits are a start byte and the other 16 bits are the parameter data. the start byte consists of six start bits (000110) followed by rs and r/w bits. rs r/w function 0 0 register no. set 0 1 status read 1 0 command and display data write 1 1 display data read the 16-bit parameter data consists of db15 to db0. the bit configuration is the same as for the 16-bit parallel bus. during display data transfer, therefore, the 4 high-order bits (db15 to db12) are not valid data. with register set and status read, the 8 high-order bits are not valid data. this serial interface supports continuous transfer of parallel data when display data is read or written. the data format used for continuous transfers is made up of an 8-bit start byte, the first 16-bit parameter data item and the second 16-bit parameter data item, which are transferred in order. within the ic, parameter data is handled in units of 16 bits. the number of consecutive parameter data items is not specified. a data transfer ends when /cs1 goes high. the first parameter data item (16 bits) received during a data read (status read or display data read) is assumed to be dummy data. normal data output begins with the second parameter data item. if a transfer is terminated in the middle of the start byte or in the middle of one of the 16-bit parameter data items, the previously transferred data is nullified. in this case, the transfer should be restarted. when /cs1 is the chip select signal: when cs2 is the chip select il transfer start /cs1 sck cs2 so si 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 db 8 db 9 db 10 db 11 db 12 db 13 db 14 db 15 r/w rs 0 11 0 0 0 r/w rs start bit (000110) transfer end fixed high start byte (start bits, rs and r/w) parameter data (register number, command data and display data) db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 db 8 db 9 db 10 db 11 db 12 db 13 db 14 db 15 parameter data (status read or display data read/write) /cs1 fixed low cs2 transfer start transfer end
T6K53 2001-11-07 31 register set command setting display data write display data read status read /cs1 sc k si start byte rs 0 , r/w 0 8 high-order bits ( all ?0? ) 8 low-order bits ( db7 to db0 ) /cs1 sc k si start byte rs 1 , r/w 0 8 high-order bits ( db15 to db8 ) 8 low-order bits ( db7 to db0 ) /cs1 sc k si start byte rs 1 , r/w 0 8 high-order bits (1) ( db15 to db8 ) 8 low-order bits (1) ( db7 to db0 ) 8 high-order bits (2) ( db15 to db8 ) /cs1 sc k si dummy data (1) dummy data (2) 8 high-order bits ( db15 to db8 ) start byte rs 1 , r/w 1 so 8 low-order bits ( db7 to db0 ) /cs1 sc k si start byte rs 0 , r/w 1 8 high-order bits ( all ?0? ) 8 low-order bits ( db7 to db0 ) so
T6K53 2001-11-07 32 high-speed ram write function the T6K53 incorporates a high-speed ram write function. this function enables the T6K53 to support applications, such as animation software, which require high-speed rewriting of display data. if high-speed ram write is selected for writing display data (i.e. if hrw is set to 1), data received from the mpu is stored in registers 1 to 4 (each of which consists of one word or 12 bits) and then transferred to the display ram in 4-word units. thus, in high-speed ram write mode data access must be performed in 4-word units. the y-address area must be set up to be 000h to 0003h, 0004h to 0007h, 0008h to 000bh... or 007ch to 007fh. the y-address area cannot be set up as individual 4-address units (e.g. yas = 003h and yae = 00fd). high-speed ram write mode does not support any read functions. example: selecting a rectangular display area seg28 to seg99 and com40 to com119 when using high-speed ram write mode, observe the following precautions: precautions: conduct the access count in 4-word units. otherwise, no data transfer to ram can occur, resulting in invalid data. set the y-address area in multiples of 4 address locations. in x-address count mode, the count is incremented by one every four accesses. after this mode has been turned on or off, be sure to execute a y-adr area set (31h) before beginning to access display data. in high-speed ram write mode, display data read cannot be performed. to perform a read, first execute the high-speed ram write mode off command (hrw = 0), then start the access. 0000h 0001h 0002h 0003h 007ch 007dh 007eh 007fh y-adr display ram reg.1 reg.2 reg.3 reg.4 mpu 12 bit com40 com119 seg28 seg99 77h 28h 1ch 63h y-adr count mode 77h 28h 1c-1fh 63h x-adr count mode a ddress area setting y-adr: yas 1ch, yae 63h x-adr: xas 28h, xae 77h
T6K53 2001-11-07 33 command setting on the T6K53 both register set and status read are one-byte commands, while all other instructions consist of two bytes. in 16- bit mode both one-byte and two-byte commands are completed with a single access. in 8-bit mode, register set and status read are completed with a single access. other instructions are set up with two accesses ? first the 8 low-order bits are accessed, then the 8 high-order bits. in 8-bit mode, if a register set or status read is performed after the first-byte access, the access count will be cleared so t hat the next access starts with the first byte. thus, when performing an access in 8-bit mode, perform a status read at regular intervals so as to avoid crashes due to noise. instruction name rs /wr /rd reg. no. db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 register set l l h * * * * * * * * reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 status read l h l * * * * * * * * * * x/y rev pt rmw dp stb standby mode h l h 01h * * * * * * * * * * * * * * * stb display on/off h l h 02h * * * * * * * * * * * * * * * dp function mode (1) h l h 04h * * dc21 dc20 * * dc11 dc10 * * * * amp dcdc ext osc function mode (2) h l h 05h * * * * * hrw rmw x/y * * gs rev sgm swp cdr sdr contrast control h l h 10h * c26 c25 c24 c23 c21 c21 c20 * c16 c15 c14 c13 c12 c11 c10 display mode set h l h 11h * bs22 bs21 bs20 * bs12 bs11 bs10 * * * * * * dty1 dty0 n-line inversion h l h 12h * * * * * * * * nli7 nli6 nli5 nli4 nli3 nli2 nli1 nli0 color palette (red) h l h 18h to 1fh * * * gs1/gs3/gs5/gs7/gs9/ gs11/gs13/gs15 * * * gs0/gs2/gs4/gs6/gs8/ gs10/gs12/gs14 color palette (green) h l h 20h to 27h * * * gs1/gs3/gs5/gs7/gs9/ gs11/gs13/gs15 * * * gs0/gs2/gs4/gs6/gs8/ gs10/gs12/gs14 color palette (blue) h l h 28h to 2fh * * * gs1/gs3/gs5/gs7/gs9/ gs11/gs13/gs15 * * * gs0/gs2/gs4/gs6/gs8/ gs10/gs12/gs14 x-adr area set h l h 30h xae7 xae6 xae5 xae4 xae3 xae2 xae1 xae0 xas7 xas6 xas5 xas4 xas3 xas2 xas1 xas0 y-adr area set h l h 31h * yae6 yae5 yae4 yae3 yae2 yae1 yae0 * yas6 yas5 yas4 yas3 yas2 yas1 yas0 partial display mode h l h 40h * * pds5 pds4 pds3 pds2 pds1 pds0 * * * * * * mode pt scroll mode & area start h l h 50h * * sas5 sas4 sas3 sas2 sas1 sas0 * * * * * * sm1 sm0 scroll area set. h l h 51h * * sbn5 sbn4 sbn3 sbn2 sbn1 sbn0 * * sae5 sae4 sae3 sae2 sae1 sae0 scroll start block h l h 52h * * * * * * * * * * ssb5 ssb4 ssb3 ssb2 ssb1 ssb0 display data write h l h 70h * * * * dd11 dd10 dd9 dd8 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 display data read h h l 70h * * * * dd11 dd10 dd9 dd8 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 toshiba test mode * * * 80h to ffh * * * * * * * * * * * * * * * *
T6K53 2001-11-07 34 command descriptions register set: this command sets the register address for the command which is to be set up. 80h to ffh are test commands for use by toshiba. users should not attempt to access them. status read: this command allows the state of each setting to be checked from the 8 low-order bits. stb function 0 standby mode off 1 standby mode on dp function 0 display off 1 display on rmw function 0 read-modify-write off 1 read-modify-write on pt function 0 partial off (normal mode) 1 partial on (partial display mode) x/y function 0 y-adr count mode 1 x-adr count mode rev function 0 normal mode (0: off; 1: on.) 1 reverse mode (0: on; 1: off.) standby mode: 01h this command turns standby mode on/off. stb function 0 standby mode off 1 standby mode on
T6K53 2001-11-07 35 display on/off: 02h this command turns the display on/off. dp function 0 display off 1 display on function mode (1): 04h this command sets up the operation of each function. osc: turns the built-in oscillator on/off. osc function 0 oscillator off 1 oscillator on ext: selects either the built-in oscillator or an external oscillator. ext function 0 built-in oscillator mode 1 external oscillator mode dcdc: turns the dc-dc conversion circuit on/off. dcdc function 0 dcdc off 1 dcdc on amp: turns the operational amplifier on/off. amp function 0 amp off 1 amp on dc1x: specifies the number of dc-dc conversion steps for normal mode. dc11 dc10 function 0 0 6 booster 0 1 7 booster 1 0 8 booster 1 1 cannot be set dc2x: specifies the number of dc-dc conversion steps for partial display mode. dc21 dc20 function 0 0 3 booster 0 1 4 booster 1 0 5 booster 1 1 6 booster
T6K53 2001-11-07 36 function mode (2): 05h this command sets up the display operation mode. sdr: specifies the direction of segment output. sdr function 0 y-adr 00h seg0 1 y-adr 00h seg127 cdr: specifies the direction of com output. cdr function 0 com0 com159 1 com159 com0 swp: changes r, g and b assignments for seg (a, b and c). swp function 0 seg (a, b, c) r, g, b 1 seg (a, b, c) b, g, r sgm: specifies the switching of pwm waveform output timing. sgm function 0 off 1 on rev: specifies whether the display output data will be reversed. rev function 0 normal mode (?0?: off, ?1?: on) 1 reverse mode (?0?: on, ?1?: off) gs: switches the grayscale palette mode. gs function 0 fixed-palette mode 1 palette selection mode x/y: selects the ram address count mode. x/y function 0 y-adr count mode 1 x-adr count mode
T6K53 2001-11-07 37 rmw: read-modify-write mode on/off rmw function 0 read-modify-write off 1 read-modify-write on read-modify-write mode function when a display data read is executed, no address count is executed. the address count is executed only when display data is written. hence, for example, after the read data has been changed, new data can be written to the previous address without the need to specify the address. hrw: turns high-speed ram write mode on/off. rmw function 0 high-speed ram write mode off 1 high-speed ram write mode on
T6K53 2001-11-07 38 contrast control: 10h set normal mode contrast c16 c15 c14 c13 c12 c11 c10 00h to 3fh vlcd0 voltage (typical) for each contrast (1) setting cont (dec) cont (hex) v lc0 (v) cont (dec) cont (hex) v lc0 (v) cont (dec) cont (hex) v lc0 (v) cont (dec) cont (hex) v lc0 (v) 0 00 10.00 32 20 12.52 64 40 15.04 96 60 17.56 1 01 10.08 33 21 12.60 65 41 15.12 97 61 17.64 2 02 10.16 34 22 12.68 66 42 15.20 98 62 17.72 3 03 10.24 35 23 12.76 67 43 15.28 99 63 17.80 4 04 10.31 36 24 12.83 68 44 15.35 100 64 17.87 5 05 10.39 37 25 12.91 69 45 15.43 101 65 17.95 6 06 10.47 38 26 12.99 70 46 15.51 102 66 18.03 7 07 10.55 39 27 13.07 71 47 15.59 103 67 18.11 8 08 10.63 40 28 13.15 72 48 15.67 104 68 18.19 9 09 10.71 41 29 13.23 73 49 15.75 105 69 18.27 10 0a 10.79 42 2a 13.31 74 4a 15.83 106 6a 18.35 11 0b 10.87 43 2b 13.39 75 4b 15.91 107 6b 18.43 12 0c 10.94 44 2c 13.46 76 4c 15.98 108 6c 18.50 13 0d 11.02 45 2d 13.54 77 4d 16.06 109 6d 18.58 14 0e 11.10 46 2e 13.62 78 4e 16.14 110 6e 18.66 15 0f 11.18 47 2f 13.70 79 4f 16.22 111 6f 18.74 16 10 11.26 48 30 13.78 80 50 16.30 112 70 18.82 17 11 11.34 49 31 13.86 81 51 16.38 113 71 18.90 18 12 11.42 50 32 13.94 82 52 16.46 114 72 18.98 19 13 11.50 51 33 14.02 83 53 16.54 115 73 19.06 20 14 11.57 52 34 14.09 84 54 16.61 116 74 19.13 21 15 11.65 53 35 14.17 85 55 16.69 117 75 19.21 22 16 11.73 54 36 14.25 86 56 16.77 118 76 19.29 23 17 11.81 55 37 14.33 87 57 16.85 119 77 19.37 24 18 11.89 56 38 14.41 88 58 16.93 120 78 19.45 25 19 11.97 57 39 14.49 89 59 17.01 121 79 19.53 26 1a 12.05 58 3a 14.57 90 5a 17.09 122 7a 19.61 27 1b 12.13 59 3b 14.65 91 5b 17.17 123 7b 19.69 28 1c 12.20 60 3c 14.72 92 5c 17.24 124 7c 19.76 29 1d 12.28 61 3d 14.80 93 5d 17.32 125 7d 19.84 30 1e 12.36 62 3e 14.88 94 5e 17.40 126 7e 19.92 31 1f 12.44 63 3f 14.96 95 5f 17.48 127 7f 20.00
T6K53 2001-11-07 39 set partial display mode contrast c26 c25 c24 c23 c22 c21 c20 00h to 3fh vlc0 voltage (typical) for each contrast (2) setting cont (dec) cont (hex) v lc0 (v) cont (dec) cont (hex) v lc0 (v) cont (dec) cont (hex) v lc0 (v) cont (dec) cont (hex) v lc0 (v) 0 00 5.00 32 20 7.52 64 40 10.04 96 60 12.56 1 01 5.08 33 21 7.60 65 41 10.12 97 61 12.64 2 02 5.16 34 22 7.68 66 42 10.20 98 62 12.72 3 03 5.24 35 23 7.76 67 43 10.28 99 63 12.80 4 04 5.31 36 24 7.83 68 44 10.35 100 64 12.87 5 05 5.39 37 25 7.91 69 45 10.43 101 65 12.95 6 06 5.47 38 26 7.99 70 46 10.51 102 66 13.03 7 07 5.55 39 27 8.07 71 47 10.59 103 67 13.11 8 08 5.63 40 28 8.15 72 48 10.67 104 68 13.19 9 09 5.71 41 29 8.23 73 49 10.75 105 69 13.27 10 0a 5.79 42 2a 8.31 74 4a 10.83 106 6a 13.35 11 0b 5.87 43 2b 8.39 75 4b 10.91 107 6b 13.43 12 0c 5.94 44 2c 8.46 76 4c 10.98 108 6c 13.50 13 0d 6.02 45 2d 8.54 77 4d 11.06 109 6d 13.58 14 0e 6.10 46 2e 8.62 78 4e 11.14 110 6e 13.66 15 0f 6.18 47 2f 8.70 79 4f 11.22 111 6f 13.74 16 10 6.26 48 30 8.78 80 50 11.30 112 70 13.82 17 11 6.34 49 31 8.86 81 51 11.38 113 71 13.90 18 12 6.42 50 32 8.94 82 52 11.46 114 72 13.98 19 13 6.50 51 33 9.02 83 53 11.54 115 73 14.06 20 14 6.57 52 34 9.09 84 54 11.61 116 74 14.13 21 15 6.65 53 35 9.17 85 55 11.69 117 75 14.21 22 16 6.73 54 36 9.25 86 56 11.77 118 76 14.29 23 17 6.81 55 37 9.33 87 57 11.85 119 77 14.37 24 18 6.89 56 38 9.41 88 58 11.93 120 78 14.45 25 19 6.97 57 39 9.49 89 59 12.01 121 79 14.53 26 1a 7.05 58 3a 9.57 90 5a 12.09 122 7a 14.61 27 1b 7.13 59 3b 9.65 91 5b 12.17 123 7b 14.69 28 1c 7.20 60 3c 9.72 92 5c 12.24 124 7c 14.76 29 1d 7.28 61 3d 9.80 93 5d 12.32 125 7d 14.84 30 1e 7.36 62 3e 9.88 94 5e 12.40 126 7e 14.92 31 1f 7.44 63 3f 9.96 95 5f 12.48 127 7f 15.00
T6K53 2001-11-07 40 display mode set: 11h set duty this function sets up the display duty cycle for normal mode. dty1 dty0 function 0 0 1/160 duty com0 to com159 0 1 1/144 duty com8 to com151 1 0 1/128 duty com16 to com143 1 1 cannot be set. set bias this function specifies the display bias ratio for normal display mode and partial display mode. if the display mode is switched using the partial display command, the display bias ratio setting made using set bias will be selected automatically. normal mode bs12 bs11 bs10 function 0 0 0 1/11 bias 0 0 1 1/12 bias 0 1 0 1/13 bias 0 1 1 1/14 bias 1 0 0 1/15 bias partail mode bs22 bs21 bs20 function 0 0 0 1/6 bias 0 0 1 1/7 bias 0 1 0 1/8 bias 0 1 1 1/9 bias 1 0 0 1/10 bias n-line inversion: 12h sets the inversion period for the alternating signal (fr) to an arbitrary number of display lines. nli7 nli6 nli5 nli4 nli3 nli2 nli1 nli0 00h to 9fh 00h: frame inverted 01h: inverted every line 02h: inverted every two lines 9eh: inverted every 158 lines 9fh: inverted every 159 lines
T6K53 2001-11-07 41 color palette (red/green/blue): 18h to 2fh these are the registers which are used for setting the grayscale levels for palette selection mode. separate palettes can be selected individually for r, g and b, and 16 grayscale levels can be selected from the 32 levels available (gl0 to gl31) and specified individually for r, g and b as 5-bit values in gs0 to gs15. on a reset, the gs0 to gs15 values for r, g and b become 00h. when using this mode, be sure to set up these registers before executing display on. reg no. color db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 18h * * * gs1 * * * gs0 19h * * * gs3 * * * gs2 1ah * * * gs5 * * * gs4 1bh * * * gs7 * * * gs6 1ch * * * gs9 * * * gs8 1dh * * * gs11 * * * gs10 1eh * * * gs13 * * * gs12 1fh red * * * gs15 * * * gs14 20h * * * gs1 * * * gs0 21h * * * gs3 * * * gs2 22h * * * gs5 * * * gs4 23h * * * gs7 * * * gs6 24h * * * gs9 * * * gs8 25h * * * gs11 * * * gs10 26h * * * gs13 * * * gs12 27h green * * * gs15 * * * gs14 28h * * * gs1 * * * gs0 29h * * * gs3 * * * gs2 2ah * * * gs5 * * * gs4 2bh * * * gs7 * * * gs6 2ch * * * gs9 * * * gs8 2dh * * * gs11 * * * gs10 2eh * * * gs13 * * * gs12 2fh blue * * * gs15 * * * gs14
T6K53 2001-11-07 42 x-adr area set: 30h xasx: sets up the start address for the display ram x-adr area. xas7 xas6 xas5 xas4 xas3 xas2 xas1 xas0 00h to 9fh * : do not specify an address higher than 9fh. xaex: sets up the end address for the display ram x-adr area. xae7 xae6 xae5 xae4 xae3 xae2 xae1 xae0 00h to 9fh * : do not specify an address higher than 9fh. y-adr area set: 31h yasx: sets up the start address for the display ram y-adr area. yas6 yas5 yas4 yas3 yas2 yas1 yas0 00h to 3fh yaex: sets up the end address for the display ram y-adr area. yae6 yae5 yae4 yae3 yae2 yae1 yae0 00h to 3fh partial display mode: 40h this command turns partial display mode on/off and sets up the display duty cycle for partial display mode. pt: turns partial mode on/off. pt function 0 partial off (normal mode) 1 partial on (partial display mode) mode: selects the display duty cycle for partial display mode. mode function 0 1/32 duty 1 1/64 duty pdsx: specifies the start block for partial display mode. pds5 pds4 pds3 pds2 pds1 pds0 00h to 27h
T6K53 2001-11-07 43 scroll mode & area start: 50h sm: sets up area scroll mode. sm1 sm0 function 0 0 full-screen scroll 0 1 upper screen section scroll 1 0 lower screen section scroll 1 1 middle screen section scroll sasx: specifies the start ram block number for the scroll area. a 4-line ram block is specified. sas5 sas4 sas3 sas2 sas1 sas0 00h to 27h set scroll area: 51h saex: specifies the end block number for the scroll area. a 4-line ram block is specified. setting = total number of ram blocks ? number of lower fixed blocks ? 1 sae5 sae4 sae3 sae2 sae1 sae0 00h to 27h sbnx: specifies the number of specific blocks. 4-line display duty blocks are specified. setting = number of display duty blocks ? number of lower fixed blocks ? 1 sbn5 sbn4 sbn3 sbn2 sbn1 sbn0 00h to 27h ram block no. block start line block no. block start line block no. block start line block no. x adr 0 0 x adr 64 16 x adr 128 32 x adr 4 1 x adr 68 17 x adr 132 33 x adr 8 2 x adr 72 18 x adr 136 34 x adr 12 3 x adr 76 19 x adr 140 35 x adr 16 4 x adr 80 24 x adr 144 36 x adr 20 5 x adr 84 25 x adr 148 37 x adr 24 6 x adr 88 26 x adr 152 38 x adr 28 7 x adr 92 27 x adr 156 39 x adr 32 8 x adr 96 28 x adr 36 9 x adr 100 29 x adr 40 10 x adr 104 30 x adr 44 11 x adr 108 31 x adr 48 12 x adr 112 32 x adr 52 13 x adr 116 33 x adr 56 14 x adr 120 34 x adr 60 15 x adr 124 35
T6K53 2001-11-07 44 scroll start block: 52h this command specifies the scroll start block as a parameter. executing this command causes the specified scroll start block to be displayed as the first data item in the scroll display area. a 4-line ram block is specified. ssb5 ssb4 ssb3 ssb2 ssb1 ssb0 00h to 27h setting example if displays are scrolled up by 8 lines in middle screen section mode when the duty cycle is 1/144 and lines 1 to 7 and 137 to 144 are fixed: mode : middle screen section mode scroll area start block : 2 scroll area end block : 40 2 1 37 number of specific blocks : 36 2 1 33 scroll start block : 4 display data: 70h ddxx: accesses the display ram. dd11 dd10 dd9 dd8 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 0000h to 0fffh 16-bit mode db11 to db0 dd11 to dd0 8-bit mode first access (db7 to db0) dd11 to dd4 second access (db3 to db0) dd3 to dd0 toshiba test mode: (80h to ffh) the user cannot access commands in this area during normal use. display duty block line 1 block 0 block 1 block 2 block 34 block 35 block 33 block 32 line 5 line 9 line 13 line 129 line 133 line 137 line 141 line 144 upper fixed area scroll screen lower fixed area line 1 block 0 block 1 block 4 block 38 block 39 block 35 block 34 line 5 line 9 line 13 line 129 line 133 line 137 line 141 line 144 ram block no. display image xadr 0 block 0 block 1 block 2 block 38 block 39 block 34 block 33 xadr 4 xadr 8 xadr 12 scroll area fix xadr 135 xadr 136 block 37 background area xadr 148 xadr 152 xadr 156 xadr 159 ram block upper fixed area
T6K53 2001-11-07 45 post-reset (post-initialization) states instruction name reg. no. db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 * * * * * * * * reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 register set 0 0 0 0 0 0 0 0 * * * * * * * * * * x/y rev pt rmw dp stb status read 0 0 0 0 0 1 * * * * * * * * * * * * * * * stb standby mode 01h 1 * * * * * * * * * * * * * * * dp display on/off 02h 0 * * dc21 dc20 * * dc11 dc10 * * * * amp dcdc ext osc function mode (1) 04h 0 0 0 0 0 0 0 0 * * * * * hrw rmw x/y * * gs rev sgm swp cdr sdr function mode (2) 05h 0 0 0 0 0 0 0 0 0 * c26 c25 c24 c23 c21 c21 c20 * c16 c15 c14 c13 c12 c11 c10 contrast control 10h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * bs22 bs21 bs20 * bs12 bs11 bs10 * * * * * * dty1 dty0 display mode set 11h 0 0 0 0 0 0 0 0 * * * * * * * * nli7 nli6 nli5 nli4 nli3 nli2 nli1 nli0 n-line inversion 12h 0 0 0 0 0 0 0 0 * * * gs1/gs3/gs5/gs7/gs9/ gs11/gs13/gs15 * * * gs0/gs2/gs4/gs6/gs8/ gs10/gs12/gs14 color palette (red) 18h to 1fh 00h 00h * * * gs1/gs3/gs5/gs7/gs9/ gs11/gs13/gs15 * * * gs0/gs2/gs4/gs6/gs8/ gs10/gs12/gs14 color palette (green) 20h to 27h 00h 00h * * * gs1/gs3/gs5/gs7/gs9/ gs11/gs13/gs15 * * * gs0/gs2/gs4/gs6/gs8/ gs10/gs12/gs14 color palette (blue) 28h to 2fh 00h 00h xae7 xae6 xae5 xae4 xae3 xae2 xae1 xae0 xas7 xas6 xas5 xas4 xas3 xas2 xas1 xas0 x-adr area set 30h 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 * yae6 yae5 yae4 yae3 yae2 yae1 yae0 * yas6 yas5 yas4 yas3 yas2 yas1 yas0 y-adr area set 31h 0 0 0 0 0 0 0 1 1 1 1 1 1 1 * * pds5 pds4 pds3 pds2 pds1 pds0 * * * * * * mode pt partial display mode 40h 0 0 0 0 0 0 0 0 * * sas5 sas4 sas3 sas2 sas1 sas0 * * * * * * sm1 sm0 scroll mode & area start 50h 0 0 0 0 0 0 0 0 * * sbn5 sbn4 sbn3 sbn2 sbn1 sbn0 * * sae5 sae4 sae3 sae2 sae1 sae0 scroll area set 51h 0 0 0 0 0 0 1 0 0 1 1 1 * * * * * * * * * * ssb5 ssb4 ssb3 ssb2 ssb1 ssb0 scroll start block 52h 0 0 0 0 0 0
T6K53 2001-11-07 46 summary of display outputs and display power supply states for individual operation modes after reset (standby mode is on after a reset.) osc : off dc-dc conversion: off amp : off seg output : v ss com output : v ss v lc0 to v lc5 : v ss standby mode off (normally the display is off.) osc : on (on command is required after initialization.) dc-dc conversion: on (on command is required after initialization.) amp : on (on command is required after initialization.) seg output : v lc2 or v lc3 (display off) com output : v lc1 or v lc4 (display off) display on (display output) seg output : display data is output. com output : scanning is performed. display off (display output is stopped.) seg output : v lc2 or v lc3 (display off) com output : v lc1 or v lc4 (display off) standby mode on (sleep state) osc : off dc-dc conversion: off amp : off seg output : v ss com output : v ss v lc0 to v lc5 : v ss
T6K53 2001-11-07 47 command execution and state transition (1) reset (initialize) standby mode off display on (2) return from standby mode to display mode (3) display in progress display off (4) display off display on execute display off. display is off. seg output: v lc2 or v lc3 com output: v lc1 or v lc4 execute display on. display is on power on power supply turn-on period: 1 ms / period during which /rst is low: 1 /rst pin input ?l? /rst pin input ?h? initialization has been completed. clear internal registers. execute standby mode off command. execute osc on. execute dc-dc conversion execute amp on. wait: 200 ms execute display on. execute display on. execute standby mode off command. wait: 200 ms ? display off ? osc start ? dc-dc conversion start ? amp start
T6K53 2001-11-07 48 lcd drive waveform (normal display mode) maximum ratings characteristics symbol rating unit supply voltage (1) v dd , v in (note 1) 0.3 to 6.0 v supply voltage (2) v lc0 , v lc1 , v lc2 , v lc3 , v lc4 , v lc5 , v cc1 , v cc2 v ss 22.0 to v ss 0.3 v input voltage v inp (note 1), (note 2) 0.3 to v dd 0.3 v operating temperature t opr 30 to 85 c storage temperature t stg 55 to 125 c note 1: value with reference to v ss = 0 v note 2: does not include vcc1, vcc2, vlc0, vlc1, vlc2, vlc3, vlc4 and vlc5. this setting is suitable for inputs or a data bus. com0 v4 v5 v1 v0 v4 v5 v1 v4 v5 com1 v4 v0 v4 v1 v0 com160 v1 v5 v4 v0 v1 v3 seg (a, b, c) v0 v2 v5 v3 v0 on off on off lcd drive timing chart (1/160 duty)
T6K53 2001-11-07 49 electrical characteristics 1 (conditions: unless otherwise specified, v ss 0 v, v dd 2.7 to 3.3 v, v cc 20.0 v, ta 25c) characteristics symbol test circuit test conditions min typ. max unit applicable operating voltage (1) v dd 1.7 3.3 v v dd operating voltage (2) v in 2.7 3.3 v v in normal display v cc 5.0 v ss 20.0 v ss v operating voltage (3) partial display v cc 4.0 v ss 20.0 v ss v v cc high level v ih 0.8 v dd v dd v input voltage low level v il 0 0.2 v dd v db0 to db15, d/i, /wr, /rd, /cs1, cs2, d/i, p/s, 68/80, si, sck, /rst, /stb high level v oh i oh 400 a v dd 0.2 v dd v output voltage low level v ol i ol 400 a 0 0.2 v db0 to db15, so segment driver on-resistance normal display mode r col (note 3) 2.0 3.0 k seg common driver on-resistance normal display mode r row (note 3) 1.2 2.0 k com input leakage current i il v inp v dd to gnd 1 1 a db0 to db15,d/i, /wr, /rd, /cs1, cs2, rsi, p/s, wls, si, so, sck, /rst, /stb operating frequency f osc (note 7) 168 khz osc external clock input frequency f ex (note 7) 168 khz osc external clock duty f duty 45 50 55 % osc external clock rise/fall time t r /t f 50 ns osc current consumption (1) i ss1 (note 4) 300 tbd a v ss current consumption (2) i ss2 (note 5) 100 tbd a v ss current consumption (5) i ssstb (note 6) 1 1 a v ss note 3: v cc 10.0 v, load current 100 a, 1/11 bias note 4: v dd 3.0 v, v cc 18.0 v ( 7 booster), no data access, internal clock (osc 168 khz), no load, 1/14 bias, 1/160 duty, op-amp on, regulator on, normal display mode, display pattern: all-white note 5: v dd 3.0 v, v cc 10 v ( 4 booster), no data access, internal clock (osc 67.2 khz), no load, 1/9 bias, 1/64 duty, op-amp on, regulator on, partial display mode, display pattern: all-white note 6: v dd 3.3 v, v cc v ss 22.0 v, /stb ?l? note 7: 1/160 duty, f fr 70 hz
T6K53 2001-11-07 50 electrical characteristics 2 (conditions: unless otherwise specified, v ss 0 v, v dd 2.7 to 3.3 v, v cc 15.5 v, ta 25c) characteristics symbol test circuit test conditions min typ max unit applicable output voltage ( 3 booster) v o1 (1) (note 8) tbd 8.7 v v out output voltage ( 4 booster) v o2 (2) (note 9) tbd 11.6 v v out output voltage ( 5 booster) v o3 (3) (note 10) tbd 14.5 v v out output voltage ( 6 booster) v o4 (4) (note 11) tbd 17.4 v v out output voltage ( 7 booster) v o5 (5) (note 12) tbd 18.3 v v out output voltage ( 8 booster) v o6 (6) (note 13) tbd 20.0 v v out note 8: v in 3.0 v, v cc 8.7 v (external power supply input), cn /cn 1.0 f, v out v ss 1.0 v, osc 67.2 khz, contrast max, ta 25c, i load 200 a note 9: v in 3.0 v, v cc 11.6 v (external power supply input), cn /cn 1.0 f, v out v ss 1.0 v, osc 67.2 khz, contrast max, ta 25c, i load 200 a note 10: v in 3.0 v, v cc 14.5 v (external power supply input), cn /cn 1.0 f, v out v ss 1.0 v, osc 67.2 khz, contrast max, ta 25c, i load 200 a note 11: v in 3.0 v, v cc 17.4 v (external power supply input), cn /cn 1.0 f, v out v ss 1.0 v, osc 168 khz, contrast max, ta 25c, i load 500 a note 12: v in 2.7 v, v cc 18.3 v (external power supply input), cn /cn 1.0 f, v out v ss 1.0 v, osc 168 khz, contrast max, ta 25c, i load 500 a note 13: v in 2.7 v, v cc 20.0 v (external power supply input), cn /cn 1.0 f, v out v ss 1.0 v, osc 168 khz, contrast max, ta 25c, i load 500 a electrical characteristics 3 (conditions: unless otherwise specified, v ss 0 v, v dd v in 2.7 to 3.3 v, v cc 15.5 v, ta 25c) characteristics symbol test circuit test conditions min typ max unit applicable regulator reference high voltage (1) v hr1 (note14) 19.95 20.00 20.05 v v cc regulator reference high voltage (2) v hr2 (note 15) 14.95 15.00 15.05 v v cc regulator reference high voltage temperature gradient v hrinc (note 14) ta 20 to 60c 0.00 %/c v cc regulator reference high voltage temperature gradient variation
v hrinc (note 14) ta 20 to 60c 0.02 0.02 %/c v cc note 14: v dd v in 3.0 v, v cc 20 v (external supply), contrast max, no display load, normal display mode note 15: v dd v in 3.0 v, v cc 15 v (external supply), contrast max, no display load, normal display mode
T6K53 2001-11-07 51 electrical characteristics 4 (conditions: unless otherwise specified, v ss 0 v, v dd 2.7 to 3.3 v, ta 25c) characteristics symbol test circuit test conditions min typ max unit applicable op-amp output voltage offset (1) v opoff (note 16) tbd tbd mv v lc0 , v lc1 , v lc2 , v lc3 , v lc4 op-amp output voltage offset (2) v opoffs1 (note 17) tbd tbd mv v lc0 , v lc1 , v lc2 , v lc3 , v lc4 op-amp output voltage offset (3) v opoffs2 i ioad 300 a (note 17) tbd tbd mv v lc0 , v lc1 , v lc2 , v lc3 , v lc4 note 16: v dd 2.7 to 3.3 v, v ss 0 v, 1/15 bias, 1/160 duty, v cc 20.0 v, op-amp on, no load v lc0 : v lc0 v opoff v lc1 : (v lc0 14/15) v lc1 v opoff v lc2 : (v lc0 13/15) v lc2 v opoff v lc3 : (v lc0 2/15) v lc3 v opoff v lc4 : (v lc0 1/15) v lc4 v opoff note 17: v dd 2.7 to 3.3 v, v ss 0 v, 1/15 bias, 1/160 duty, v cc 20.0 v, op-amp on, no load v opoff1 { (v lc1 v lc2 ) (v lc0 v lc1 ) } { (v lc3 v lc4 ) (v lc4 v lc5 ) } v opoff2 { (v lc1 v lc2 ) (v lc0 v lc1 ) } { (v lc3 v lc4 ) (v lc4 v lc5 ) }
T6K53 2001-11-07 52 test circuit (1) with
3 booster (2) with 4 booster external input a v in v dd osc c1 c1 v out v cc v ss c1 i load external power supply c2 osc 67.2 khz c1 c2 1.0 f i load 200 a a ll other pins left open c2 c2 c1 c3 c3 c1 a v in v dd osc c1a c1b v out v cc v ss c1 i load external power supply c2 osc 67.2 khz c1 c2 1.0 f i load 200 a a ll other pins left open c2a c2b c1 external input
T6K53 2001-11-07 53 (3) with 5 booster (4) with 6 booster a v in v dd osc c1 c1 v out v cc v ss c1 i load external power supply c2 osc 67.2 khz c1 c2 1.0 f i load 200 a a ll other pins left open c2 c2 c1 c3 c3 c1 c4 c4 c1 external input a v in v dd osc c1 c1 v out v cc v ss c1 i load external power supply c2 osc 168 khz c1 c2 1.0 f i load 500 a a ll other pins left open c2 c2 c1 c3 c3 c1 c4 c4 c1 c5 c5 c1 external input
T6K53 2001-11-07 54 (5) with 7 booster (6) with 8 booster v in v dd osc c1 c1 a c1 v out v cc v ss i load external power supply c2 osc 168 khz c1 c2 1.0 f i load 500 a a ll other pins left open c2 c2 c1 c3 c3 c1 c4 c4 c1 c5 c5 c1 external input c6 c6 c1 v in v dd osc c1 c1 c1 a v out v cc v ss i load external power supply c2 osc 168 khz c1 c2 1.0 f i load 500 a a ll other pins left open c2 c2 c1 c3 c3 c1 c4 c4 c1 c5 c5 c1 external input c6 c6 c1 c7 c7 c1
T6K53 2001-11-07 55 switching characteristics 1 (80 series mpu parallel interface) (conditions: unless otherwise specified, v ss 0 v, v dd 2.7 to 3.3 v, ta 25c) characteristics symbol min max unit enable cycle time t cyce 100 ns enable pulse width p wel tbd ns enable rise/fall time t er , t ff tbd ns address set-up time t as tbd ns address hold time t ah tbd ns data set-up time t ds tbd ns write data hold time t dhw tbd ns data delay time t dd (note 18) tbd ns read data hold time t dhr (note 18) tdb ns note 18: when a load circuit as shown in the figure is connected v ih v il t ah v ih v il t as p wel t ef t ef t ds t dhw t er t cyce t dhr t ef t dd v il v il v il v il v ih v ih v ih v ih v il v ih v il v oh v ol v oh v ol v il v il v ih v ih v ih valid data valid data d/i /cs1 (cs2 h) data write data read /wr /rd db0 to cl 100 pf (including tool and probe capacitances) load circuit cl
T6K53 2001-11-07 56 switching characteristics 2 (68 series mpu parallel interface) (conditions: unless otherwise specified, v ss 0 v, v dd 2.7 to 3.3 v, v cc 15.5 v, ta 25c) characteristics symbol min max unit enable cycle time t cyce 100 ns enable pulse width p weh tbd ns enable rise/fall time t er , t ff tbd ns address set-up time t as tbd ns address hold time t ah tbd ns data set-up time t ds tbd ns write data hold time t dhw tbd ns data delay time t dd (note 19) tbd ns read data hold time t dhr (note 19) tdb ns note 19: when a load circuit as shown in the figure is connected v ih v il t ah v ih v il t as p weh t ef t ef t ds t dhw t cyce t dhr t dd v il v il v il v il v ih v ih v ih v il v ih v il v oh v ol v oh v ol valid data valid data d/i r/w (/wr) data write data read e (/rd) v il db0 to cl 100 pf (including tool and probe capacitances) load circuit cl
T6K53 2001-11-07 57 switching characteristics 3 (serial interface) (conditions: unless otherwise specified, v ss 0 v, v dd 2.4 to 3.3 v, ta 25c) characteristics symbol min max unit clock cycle time t cycc 100 ns clock pulse width p wcl , p wch 40 ns clock rise/fall time t cr , t cf 10 ns chip select set-up time t scu 20 ns chip select hold time t csh 50 ns data set-up time t ds 30 ns write data hold time t dh 20 ns data output delay time t dd 30 ns data output hold time t oh 10 ns v il v ih /cs1 cs2 v il v ih sck t csu v il p wl v ih v il p wh v ih v il t cycc v ih v il v ih t csh si t ds t cr t cf t dh v ih v il v ih v il so v oh v ol v oh v ol t dd t oh
T6K53 2001-11-07 58 switching characteristics 4 (conditions: unless otherwise specified, v ss 0 v, v dd 2.7 to 3.3 v, v cc 15.5 v, ta 25c) characteristics symbol min max unit v dd rise time vdst 1 ms reset hold time vrst 1 s reset pulse width rstw 1 s /rst v dd v ih v il rstw vrst v il v ih vdst
T6K53 2001-11-07 59
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