View HD66773R_4193582.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev.1.10, jun.21.2 003, page 1 of 133 HD66773R 262,144-color, 132 x 176-dot graphics controller driver for tft lcd panels rejxxxxxxx-xxxxz rev.1.20 jun.21.2003 block diagram .................................................................................................... 6 pad arrangement .............................................................................................. 7 pad coordinate.................................................................................................. 8 pin function ........................................................................................................ 10 block function.................................................................................................... 15 1. system interface ............................................................................................................. .. 15 2. bit oper ation ................................................................................................................ .... 15 3. address coun ter (ac) ...................................................................................................... 16 4. hardware-dither circuit..................................................................................................... 1 6 5. graphics ram (gram) .................................................................................................. 16 7. lcd drive power supply................................................................................................... 16 8. oscillation circ uit (osc) ................................................................................................. 16 9. lcd driver circuit........................................................................................................... 16 gram address map......................................................................................... 17 gram address and display positio n on the panel (ss = ?0?)....................................................... 17 the relationship between gram data and display data (ss =?0?)............................................. 18 gram address and display position on the panel (ss = ?1 ?, bgr = ?1?)................................... 20 the relationship between gram data and display data (ss =?1?)............................................. 21 instructions ......................................................................................................... 23 outline........................................................................................................................ ................. 23 instructions ................................................................................................................... ............... 25 index .......................................................................................................................... ................ 25 status read .................................................................................................................... .............. 25 start oscilla tion (r00h)....................................................................................................... ........ 25 driver output control (r01h) ................................................................................................... .. 26 lcd driving waveform control (r02h) .................................................................................... 28 power control 1 (r03h) po wer control 2 (r04h)....................................................................... 29 power control 3 (r0ch) power control 4 (r0dh) power control 5 (r0eh) ............................. 31 entry mode (r05h) compar e register (r06h)............................................................................ 36 display contro l 1 (r07h) ....................................................................................................... ..... 38 frame cycle c ontrol (r0bh) ..................................................................................................... .40
HD66773R rev.1.10, jun.21.2 003, page 2 of 133 gate scan po sition (r0fh) ...................................................................................................... .... 43 vertical scroll control (r11h) ................................................................................................. ... 44 1st-screen drive position (r14h) 2nd-screen drive po sition (r15h) ........................................ 44 horizontal ram address position (r16h) ve rtical ram address position (r17h).................. 45 ram write data mask (r20h) ................................................................................................... 46 ram address set (r 21h) ......................................................................................................... .. 46 write data to gram (r22h) ...................................................................................................... 47 gram data and liquid cr ystal output level ................................................................................. 49 read data from gram (r22h) .................................................................................................. 50 gram read sequence............................................................................................................. ..... 51 instruction list .................................................................................................... 53 reset function .................................................................................................... 54 initial state of output pin.................................................................................................... .......... 55 system interface.................................................................................................. 56 18-bit in terface ............................................................................................................... ............. 57 16-bit in terface ............................................................................................................... ............. 58 9-bit in terface ................................................................................................................ .............. 59 data transmission synchronization in 9-bit bus interface mode .................................................. 60 8-bit in terface ................................................................................................................ .............. 61 data transmission synchronization in 8-bit bus interface mode .................................................. 62 serial peripheral interface (spi) .............................................................................................. .... 63 high-speed burst ram write function ............................................................ 67 conditions on using high-s peed ram write mode ..................................................................... 69 high-speed ram write w ith window address ......................................................................... 70 window address function ................................................................................. 72 graphics operation function.............................................................................. 73 write-data mask function ....................................................................................................... .... 74 graphics operation processing .................................................................................................. .75 scan mode setting .............................................................................................. 83 -correction function ......................................................................................... 84 configuration of gray scale amplifier......................................................................................... 85 -correction regist er........................................................................................................... ........ 87 ladder resistors an d 8-to-1 select or........................................................................................... .. 88 variable resist or .............................................................................................................. ............ 88 relationship between ram da ta and output level ...................................................................... 94 8-color display mode ......................................................................................... 95 instruction setting flow...................................................................................... 97
HD66773R rev.1.10, jun.21.2 003, page 3 of 133 power supply setting flow ................................................................................ 99 oscillation circuit............................................................................................... 100 n-raster-row inversion ac drive ........................................................................ 101 interlaced drive .................................................................................................. 102 ac timing ......................................................................................................... 104 frame-frequency adjustment function ............................................................. 105 relationship between liquid crystal dr ive duty and frame frequency .................................... 105 screen -split drive function ............................................................................... 106 conditions on setting the 1st/2nd sc reen drive positi on register.............................................. 107 internal configuration of power generation circuit .......................................... 109 specification of external elements connected to HD66773R ........................... 111 pattern diagram for voltage setting................................................................... 112 absolute maximum ratings ............................................................................... 113 electric characteristics ....................................................................................... 114 dc charact eristics............................................................................................................. .......... 114 ac charact eristics............................................................................................................. .......... 115 68system bus interface ti ming character istics .......................................................................... 116 80-system bus interface ti ming character istics ......................................................................... 118 serial peripheral interface timing character istics ........................................................................ 120 reset timing ch aracteristics................................................................................................... .... 120 notes to electrical character istics............................................................................................ ... 121 referentia l data............................................................................................................... ............. 123 timing characteristics diagram ................................................................................................. .. 128
HD66773R rev.1.10, jun.21.2 003, page 4 of 133 description the HD66773R is a controller driver lsi compliant to 132rgb x 176-dot graphics display on tft lcd panel in 262,144 colors. the hd6 6773r?s bit-operation f unctions, 18-bit high-speed bus interface, and high-speed ram-write function enable efficient data transfer and high-speed update of graphics ram data. the HD66773R operates with low voltage up to 2.2v for power supply. the HD66773R incorporates tft gate-drive and source-drive circuits, a step-up circuit to generate lcd drive voltage, and power supply circuits such as breeder resistor and voltage follower for lcd drive, which enable a configuration of lcd module only with external elements such as capacitors and resistors. the HD66773R supports 8-color- display and standby modes, which enable precise power control by software. thes e features make this lsi the best solution for medium or small sized portable products such as digital cellular phones, bi-directional pagers, or small pda, which support www browser, where long life battery is major concern.
HD66773R rev.1.10, jun.21.2 003, page 5 of 133 features ? single chip controller/driver for 262,144-color, 132rgb x 176-dot graphics display on tft lcd ? 18-/16-/9-/8-bit high-speed bus interfaces and a serial peripheral interface (spi) ? high-speed burst-ram write function ? window address function enabling data write in a rectangu lar ram-address area ? internal bit-operation for graphics bit-unit write-data mask function pixel-unit logical operation / conditional rewrite function ? abundant color-display control function: 262,144-color display (max.) with gamma adjustment function line-unit vertical bi-directional scrolling display function ? architecture with low power consumption low-voltage operation: vcc = 2.2 ~ 3.3 v internal reference voltage power supply: vci = 2.5 ~ 3.3 v standby mode and other power-save functions: partial lcd drive: 2-screen di splay at arbitrary two positions internal power supply circuit internal equalizing function ? compliant to cst/cadd structures ? internal power supply circuits step-up circuit: 5 ~ 9-time scale, polarity inversion power supply for tft common electrode: compliant to vcom n-raster-row ac drive ac drive: vgoff n-raster-row ac drive with cadd structure vcom (vgoff) amplitude adjustment: 22-scal e internal electronic volume adjustment output power-supply voltage voltages for power supply for vcom amplitude = 6v (max.), tft common electrode: vcomh-gnd = vreg1out (max.), vcoml-gnd = 1.0v ~ -vci+0.5v (max.) ? internal ram capacity: 46,464 bytes ? lcd drive circuit with 396-output source signal and 176-output gate signal ? n-raster-row inversion drive: polarity inversion by arbitrary number of lines. ? internal oscillation and hardware reset ? changeable source and gate shift directions ? compliant to cog with single chip, incorporating gates arranged on both sides.
HD66773R rev.1.10, jun.21.2 003, page 6 of 133 block diagram control register (cr) a ddress counte r (ac) rs rw/rd* e/wr*/scl vcc 7 16 18 im3-1, im0/id cs* db0/sdi, db1/sd0, to db17 18 bit operation 16 read data latch 16 16 grayscale voltage generator index register (ir) 16 write data latch 64 gamma adjusting circuit system interface 18 bit 16 bit 9 bit 8 bit serial peripheral (spi) graphic ram (gram) 46,464 bytes timing generator vtests v0p v0n v31p vm0ni v31n s1 to s396 source driver m a/c circuit latch circuit latch circuit latch circuit gnd rvc c reset 9? test1 test2 ts7-0 mtest1 mtest2 testv1 osc2 osc1 cpg cgnd ag nd vg s gate driver circuit scan dat a generating circuit g1 to g176 lcd drive level generating circuit v0-31 18 dithering circuit vci vreg1out vci1 c11+ :* c12+ vreg2out c11- :* c12- vci2 ddvdh c21+ :* c23+ c21- :* c23- vci3 vgh c31+ c31 - vci4 vgl c41+ c41 - vgoffh vgoffl v g offout vcomr vcomh vcoml vcom1 vcom2 v g of f testa1 testa2 testa3 testa4 vcl dctest
HD66773R rev.1.10, jun.21.2 003, page 7 of 133 pad arrangement -chi p size: 20.69mm2.47mm -chi p thickness: 400 m ( t yp . ) -pad coordinate: pad center -coordinate origin: chip center -au bump size: ( 1 ) 80 :w m80 :w m corner dummy: no.1,no195,no.239,no.742 ( 2 ) 54 :w m100 :w m input side no.2 to no.194 ( 3 ) 36 :w m70 :w m laced liquid crystal output side: no.196 to no.238 no.240 to no.741 no.743 to no.786 -au bump pitch: refer to pad coordinate -au bum p hei g ht: 15 :w m ( t yp . ) :? numbers in fi g ure 2 refer to numbers in pad coordinate :? ali g nment mark (1) assignment: 2places aa coordinate ( x, y ) = ( 10135,935 ) (2-a) coordinate (x, y) = (-10119, 1100) (2-b) coordinate (x, y) = (10119, 1100) :?:? :?:? :?:? :?:? :?:? :?:? :?:? :?:? :?:?:?:w c- :?:?:?:w c- :?:?:w c- :?:?:w c- :?:? (3-b) coordinate (x, y) = (10029, 1 100) (3-a) coordinate (x, y) = (-10029, 1100) :?:? :?:? :?:? :?:? :?:? :?:? :?:? :?:? :?:? :? :? :?:?:w c- :?:?:w c- :?:?:w c- :?:?:w c- :?:? :?:? :?:? :?:? :?:? :?:? :?:? :?:? :?:?:w c- :?:?:w c- gtest 1 g b? g3 g5 g7 g79 g81 g83 g85 dummy1 @? @? @?@? @? @? @?@? @? @? @? dummy39 @?@? @? @? @?@? @? @? vcom1 @? vcom1 @? dummyr1 @? @? g87 dummyr2 @? @? g89 reset1* @? @? g91 @? g93 dummy2 @? 1.6mm dummy3 @? dummy4 @? vgh @? vgh @? vci3 @? c23+ @? c23+ @? c23- @? c23- @? c22+ @? c22+ @? c22- @? c22- @? @? g169 c21+ @? @? g171 c21+ @? @? g173 c21- @? @? g175 c21- @? @? dummy38 c41+ @? @? dummy37 c41+ @? @? dummy36 c41- @? @? dummy35 c41- @? @? dummy34 c31+ @? @? dummy33 c31+ @? @? dummy32 c31- @? @? dummy31 c31- @? @? s1 vgl @? @? s2 vgl @? @? s3 vgl @? @? s4 vgl @? cgnd @? cgnd @? cgnd @? vccdum1 @? im0/id @? gnddum1 @? im1 @? n o. 1 n o. 2 n o.786 n o. 688 n o. 689 n o. 696 n o. 697 n o.74 1 n o. 742 n o. 743 hd 667b73 typecode min 38um pich 45pin min 38um pich 44pin min 76um pich 8pin short-circuit within the chip vccdum2 @? im2 @? vccdum3 @? im3 @? gnddum2 @? dummy5 @? dummy6 @? reset2* @? gnddum3 @? test1 @? test2 @? db17 @? db16 @? db15 @? db14 @? db13 @? db12 @? db11 @? db10 @? db9 @? gnddum4 @? db8 @? db7 @? db6 @? db5 @? db4 @? db3 @? db2 @? db1/sdo @? db0/sdi @? gnddum5 @? rw/rd* @? e/wr*/scl @? rs @? cs* @? testv1 @? gnddum6 @? mtest1 @? mtest2 @? agnd @? agnd @? agnd @? agnd @? agnd @? agnd @? gnd @? gnd @? gnd @? gnd @? gnd @? hd667b73 laced top view gnd @? rvcc @? rvcc @? rvcc @? rvcc @? vcc @? vcc @? vcc @? vcc @? vcc @? vcc @? vcc @? vcc @? vci @? vci @? vci @? vci @? vci @? vci @? vci4 @? osc1 @? osc2 @? ts0 @? ts1 @? ts2 @? ts3 @? ts4 @? ts5 @? ts6 @? ts7 @? dctest @? dummy7 @? dummy8 @? dummy9 @? dummy10 @? dummy11 @? dummy12 @? vgs @? vgs @? cgnd @? cgnd @? cgnd @? v0p @? v0n @? vmoni @? vmoni @? v31p @? v31n @? vcoml @? testa4 @? y x min 80um pich 193pin min 38um pich 396pin testa1 @? vcomr @? vreg1out @? testa2 @? dummy13 @? vtests @? dummy14 @? dummy15 @? vcomh @? vcl @? vcl @? vci1 @? vci1 @? vci1 @? vci1 @? regp @? dummy16 @? vci2 @? @? s393 ddvdh @? @? s394 ddvdh @? @? s395 vci3 @? @? s396 c11- @? @? dummy30 c11- @? @? dummy29 c11- @? @? dummy28 c11- @? @? dummy27 c11+ @? @? dummy26 c11+ @? @? dummy25 c11+ @? @? dummy24 c11+ @? @? gtest2 c12- @? @? g176 c12- @? @? g174 c12- @? @? g172 c12- @? @? g170 c12+ @? c12+ @? c12+ @? c12+ @? vgoff @? vgoffout @? vgoffh @? vgoffl @? testa3 @? vreg2out @? dummy17 @? dummy18 @? 1.6mm dummy19 @? @? g94 reset3* @? @? g9 2 min 38um pich 46pin n o.28 5 n o.28 6 n o.29 2 n o.29 3 min 76um pich 7pin dummy20 @? @? g90 dummy21 @? @? g88 vcom2 @? vcom2 @? @?@? @? @? @? @? dummy22 @?@? @? @? @? @? @? @? dummy23 g2 g4 g6 g8 g80 g82 g84 g86 n o.19 4 n o.19 5 n o.19 6 n o.23 8 n o. 239 n o.24 0 min 38um pich 43pin
HD66773R rev.1.10, jun.21.2 003, page 8 of 133 pad coordinate no. p ad name x y no. p ad name x y 1 dummy1 -10209 -1099 101 vcc 109 -1089 2 vcom1 -10041 -1089 102 vcc 189 -1089 3 vcom1 -9961 -1089 103 vcc 269 -1089 4 dummyr1 -9859 -1089 104 vcc 349 -1089 5 dummyr2 -9768 -1089 105 vcc 430 -1089 6 reset1* -9650 -1089 106 vcc 510 -1089 7 dummy2 -9116 -1089 107 vci 590 -1089 8 dummy3 -8582 -1089 108 vci 670 -1089 9 dummy4 -8048 -1089 109 vci 750 -1089 10 vgh -7947 -1089 110 vci 830 -1089 11 vgh -7867 -1089 111 vci 911 -1089 12 vci3 -7765 -1089 112 vci 991 -1089 13 c23+ -7685 -1089 113 vci4 1129 -1089 14 c23+ -7605 -1089 114 osc1 1257 -1089 15 c23- -7525 -1089 115 osc2 1337 -1089 16 c23- -7445 -1089 116 ts0 1418 -1089 17 c22+ -7365 -1089 117 ts1 1498 -1089 18 c22+ -7284 -1089 118 ts2 1578 -1089 19 c22- -7204 -1089 119 ts3 1658 -1089 20 c22- -7124 -1089 120 ts4 1738 -1089 21 c21+ -7044 -1089 121 ts5 1818 -1089 22 c21+ -6964 -1089 122 ts6 1898 -1089 23 c21- -6884 -1089 123 ts7 1979 -1089 24 c21- -6803 -1089 124 dctest 2059 -1089 25 c41+ -6723 -1089 125 dummy7 2177 -1089 26 c41+ -6643 -1089 126 dummy8 2257 -1089 27 c41- -6563 -1089 127 dummy9 2337 -1089 28 c41- -6483 -1089 128 dummy10 2418 -1089 29 c31+ -6403 -1089 129 dummy11 2498 -1089 30 c31+ -6323 -1089 130 dummy12 2578 -1089 31 c31- -6242 -1089 131 vgs 2685 -1089 32 c31- -6162 -1089 132 vgs 2765 -1089 33 vgl -6029 -1089 133 cgnd 2872 -1089 34 vgl -5949 -1089 134 cgnd 2952 -1089 35 vgl -5869 -1089 135 cgnd 3032 -1089 36 vgl -5789 -1089 136 v0p 3139 -1089 37 cgnd -5687 -1089 137 v0n 3219 -1089 38 cgnd -5607 -1089 138 vmoni 3299 -1089 39 cgnd -5527 -1089 139 vmoni 3380 -1089 40 vccdum1 -5447 -1089 140 v31p 3460 -1089 41 im0/id -5356 -1089 141 v31n 3540 -1089 42 gnddum1 -5237 -1089 142 vcoml 3657 -1089 43 im1 -5146 -1089 143 testa4 3737 -1089 44 vccdum2 -5028 -1089 144 testa1 3854 -1089 45 im2 -4936 -1089 145 vcomr 3934 -1089 46 vccdum3 -4818 -1089 146 vreg1out 4014 -1089 47 im3 -4727 -1089 147 testa2 4094 -1089 48 gnddum2 -4608 -1089 148 dummy13 4201 -1089 49 dummy5 -4528 -1089 149 vtests 4308 -1089 50 dummy6 -4448 -1089 150 dummy14 4415 -1 089 51 reset2* -4357 -1089 151 dummy15 4495 -1089 52 gnddum3 -4238 -1089 152 vcomh 4602 -1089 53 test1 -4147 -1089 153 vcl 4740 -1089 54 test2 -4067 -1089 154 vcl 4820 -1089 55 db17 -3987 -1089 155 vci1 4959 -1089 56 db16 -3907 -1089 156 vci1 5039 -1089 57 db15 -3826 -1089 157 vci1 5119 -1089 58 db14 -3746 -1089 158 vci1 5199 -1089 59 db13 -3666 -1089 159 regp 5343 -1089 60 db12 -3586 -1089 160 dummy16 5450 -1089 61 db11 -3506 -1089 161 vci2 5557 -1089 62 db10 -3426 -1089 162 ddvdh 5695 -1089 63 db9 -3346 -1089 163 ddvdh 5776 -1089 64 gnddum4 -3227 -1089 164 vci3 5909 -1089 65 db8 -3136 -1089 165 c11- 6047 -1089 66 db7 -3056 -1089 166 c11- 6127 -1089 67 db6 -2976 -1089 167 c11- 6207 -1089 68 db5 -2895 -1089 168 c11- 6287 -1089 69 db4 -2815 -1089 169 c11+ 6368 -1089 70 db3 -2735 -1089 170 c11+ 6448 -1089 71 db2 -2655 -1089 171 c11+ 6528 -1089 72 db1/sdo -2575 -1089 172 c11+ 6608 -1089 73 db0/sdi -2495 -1089 173 c12- 6688 -1089 74 gnddum5 -2376 -1089 174 c12- 6768 -1089 75 rw/rd* -2285 -1089 175 c12- 6848 -1089 76 e/wr*/scl -2205 -1089 176 c12- 6929 -1089 77 rs -2125 -1089 177 c12+ 7009 -1089 78 cs* -2045 -1089 178 c12+ 7089 -1089 79 testv1 -1964 -1089 179 c12+ 7169 -1089 80 gnddum6 -1846 -1089 180 c12+ 7249 -1089 81 mtest1 -1755 -1089 181 vgoff 7388 -1089 82 mtest2 -1675 -1089 182 vgoffout 7468 -1089 83 agnd -1525 -1089 183 vgoffh 7601 -1089 84 agnd -1445 -1089 184 vgoffl 7681 -1089 85 agnd -1343 -1089 185 testa3 7814 -1089 86 agnd -1263 -1089 186 vreg2out 7947 -1089 87 agnd -1161 -1089 187 dummy17 8048 -1089 88 agnd -1081 -1089 188 dummy18 8582 -1089 89 gnd -948 -1089 189 dummy19 9116 -1089 90 gnd -868 -1089 190 reset3* 9650 -1089 91 gnd -767 -1089 191 dummy20 9768 -1089 92 gnd -687 -1089 192 dummy21 9859 -1089 93 gnd -585 -1089 193 vcom2 9961 -1089 94 gnd -505 -1089 194 vcom2 10041 -1089 95 rvcc -372 -1089 195 dummy22 10209 -1099 96 rvcc -292 -1089 196 g2 10214 -801 97 rvcc -212 -1089 197 g4 10104 -763 98 rvcc -131 -1089 198 g6 10214 -725 99 vcc -51 -1089 199 g8 10104 -687 100 vcc 29 -1089 200 g10 10214 - 649 no. p ad name x y no. p ad name x y 201 g12 10104 -610 301 s388 7249 994 202 g14 10214 -572 302 s387 7210 1104 203 g16 10104 -534 303 s386 7172 994 204 g18 10214 -496 304 s385 7134 1104 205 g20 10104 -458 305 s384 7096 994 206 g22 10214 -420 306 s383 7058 1104 207 g24 10104 -382 307 s382 7020 994 208 g26 10214 -343 308 s381 6981 1104 209 g28 10104 -305 309 s380 6943 994 210 g30 10214 -267 310 s379 6905 1104 211 g32 10104 -229 311 s378 6867 994 212 g34 10214 -191 312 s377 6829 1104 213 g36 10104 -153 313 s376 6791 994 214 g38 10214 -114 314 s375 6753 1104 215 g40 10104 -76 315 s374 6714 994 216 g42 10214 -38 316 s373 6676 1104 217 g44 10104 0 317 s372 6638 994 218 g46 10214 38 318 s371 6600 1104 219 g48 10104 76 319 s370 6562 994 220 g50 10214 114 320 s369 6524 1104 221 g52 10104 153 321 s368 6486 994 222 g54 10214 191 322 s367 6447 1104 223 g56 10104 229 323 s366 6409 994 224 g58 10214 267 324 s365 6371 1104 225 g60 10104 305 325 s364 6333 994 226 g62 10214 343 326 s363 6295 1104 227 g64 10104 382 327 s362 6257 994 228 g66 10214 420 328 s361 6218 1104 229 g68 10104 458 329 s360 6180 994 230 g70 10214 496 330 s359 6142 1104 231 g72 10104 534 331 s358 6104 994 232 g74 10214 572 332 s357 6066 1104 233 g76 10104 610 333 s356 6028 994 234 g78 10214 649 334 s355 5990 1104 235 g80 10104 687 335 s354 5951 994 236 g82 10214 725 336 s353 5913 1104 237 g84 10104 763 337 s352 5875 994 238 g86 10214 801 338 s351 5837 1104 239 dummy23 10209 1099 339 s350 5799 994 240 g88 9919 1104 340 s349 5761 1104 241 g90 9881 994 341 s348 5723 994 242 g92 9843 1104 342 s347 5684 1104 243 g94 9805 994 343 s346 5646 994 244 g96 9766 1104 344 s345 5608 1104 245 g98 9728 994 345 s344 5570 994 246 g100 9690 1104 346 s343 5532 1104 247 g102 9652 994 347 s342 5494 994 248 g104 9614 1104 348 s341 5455 1104 249 g106 9576 994 349 s340 5417 994 250 g108 9538 1104 350 s339 5379 1104 251 g110 9499 994 351 s338 5341 994 252 g112 9461 1104 352 s337 5303 1104 253 g114 9423 994 353 s336 5265 994 254 g116 9385 1104 354 s335 5227 1104 255 g118 9347 994 355 s334 5188 994 256 g120 9309 1104 356 s333 5150 1104 257 g122 9270 994 357 s332 5112 994 258 g124 9232 1104 358 s331 5074 1104 259 g126 9194 994 359 s330 5036 994 260 g128 9156 1104 360 s329 4998 1104 261 g130 9118 994 361 s328 4960 994 262 g132 9080 1104 362 s327 4921 1104 263 g134 9042 994 363 s326 4883 994 264 g136 9003 1104 364 s325 4845 1104 265 g138 8965 994 365 s324 4807 994 266 g140 8927 1104 366 s323 4769 1104 267 g142 8889 994 367 s322 4731 994 268 g144 8851 1104 368 s321 4692 1104 269 g146 8813 994 369 s320 4654 994 270 g148 8775 1104 370 s319 4616 1104 271 g150 8736 994 371 s318 4578 994 272 g152 8698 1104 372 s317 4540 1104 273 g154 8660 994 373 s316 4502 994 274 g156 8622 1104 374 s315 4464 1104 275 g158 8584 994 375 s314 4425 994 276 g160 8546 1104 376 s313 4387 1104 277 g162 8507 994 377 s312 4349 994 278 g164 8469 1104 378 s311 4311 1104 279 g166 8431 994 379 s310 4273 994 280 g168 8393 1104 380 s309 4235 1104 281 g170 8355 994 381 s308 4197 994 282 g172 8317 1104 382 s307 4158 1104 283 g174 8279 994 383 s306 4120 994 284 g176 8240 1104 384 s305 4082 1104 285 gtest2 8164 1104 385 s304 4044 994 286 dummy24 8088 1104 386 s303 4006 1104 287 dummy25 8012 1104 387 s302 3968 994 288 dummy26 7935 1104 388 s301 3929 1104 289 dummy27 7859 1104 389 s300 3891 994 290 dummy28 7783 1104 390 s299 3853 1104 291 dummy29 7706 1104 391 s298 3815 994 292 dummy30 7630 1104 392 s297 3777 1104 293s3967554994393s2963739994 294 s395 7516 1104 394 s295 3701 1104 295s3947477994395s2943662994 296 s393 7439 1104 396 s293 3624 1104 297s3927401994397s2923586994 298 s391 7363 1104 398 s291 3548 1104 299s3907325994399s2903510994 300 s389 7287 1104 400 s289 3472 1 104
HD66773R rev.1.10, jun.21.2 003, page 9 of 133 no. p ad name x y no. p ad name x y 401 s288 3434 994 501 s188 -420 1104 402 s287 3395 1104 502 s187 -458 994 403 s286 3357 994 503 s186 -496 1104 404 s285 3319 1104 504 s185 -534 994 405 s284 3281 994 505 s184 -572 1104 406 s283 3243 1104 506 s183 -610 994 407 s282 3205 994 507 s182 -649 1104 408 s281 3166 1104 508 s181 -687 994 409 s280 3128 994 509 s180 -725 1104 410 s279 3090 1104 510 s179 -763 994 411 s278 3052 994 511 s178 -801 1104 412 s277 3014 1104 512 s177 -839 994 413 s276 2976 994 513 s176 -877 1104 414 s275 2938 1104 514 s175 -916 994 415 s274 2899 994 515 s174 -954 1104 416 s273 2861 1104 516 s173 -992 994 417 s272 2823 994 517 s172 -1030 1104 418 s271 2785 1104 518 s171 -1068 994 419 s270 2747 994 519 s170 -1106 1104 420 s269 2709 1104 520 s169 -1145 994 421 s268 2671 994 521 s168 -1183 1104 422 s267 2632 1104 522 s167 -1221 994 423 s266 2594 994 523 s166 -1259 1104 424 s265 2556 1104 524 s165 -1297 994 425 s264 2518 994 525 s164 -1335 1104 426 s263 2480 1104 526 s163 -1373 994 427 s262 2442 994 527 s162 -1412 1104 428 s261 2403 1104 528 s161 -1450 994 429 s260 2365 994 529 s160 -1488 1104 430 s259 2327 1104 530 s159 -1526 994 431 s258 2289 994 531 s158 -1564 1104 432 s257 2251 1104 532 s157 -1602 994 433 s256 2213 994 533 s156 -1640 1104 434 s255 2175 1104 534 s155 -1679 994 435 s254 2136 994 535 s154 -1717 1104 436 s253 2098 1104 536 s153 -1755 994 437 s252 2060 994 537 s152 -1793 1104 438 s251 2022 1104 538 s151 -1831 994 439 s250 1984 994 539 s150 -1869 1104 440 s249 1946 1104 540 s149 -1908 994 441 s248 1908 994 541 s148 -1946 1104 442 s247 1869 1104 542 s147 -1984 994 443 s246 1831 994 543 s146 -2022 1104 444 s245 1793 1104 544 s145 -2060 994 445 s244 1755 994 545 s144 -2098 1104 446 s243 1717 1104 546 s143 -2136 994 447 s242 1679 994 547 s142 -2175 1104 448 s241 1640 1104 548 s141 -2213 994 449 s240 1602 994 549 s140 -2251 1104 450 s239 1564 1104 550 s139 -2289 994 451 s238 1526 994 551 s138 -2327 1104 452 s237 1488 1104 552 s137 -2365 994 453 s236 1450 994 553 s136 -2403 1104 454 s235 1412 1104 554 s135 -2442 994 455 s234 1373 994 555 s134 -2480 1104 456 s233 1335 1104 556 s133 -2518 994 457 s232 1297 994 557 s132 -2556 1104 458 s231 1259 1104 558 s131 -2594 994 459 s230 1221 994 559 s130 -2632 1104 460 s229 1183 1104 560 s129 -2671 994 461 s228 1145 994 561 s128 -2709 1104 462 s227 1106 1104 562 s127 -2747 994 463 s226 1068 994 563 s126 -2785 1104 464 s225 1030 1104 564 s125 -2823 994 465 s224 992 994 565 s124 -2861 1104 466 s223 954 1104 566 s123 -2899 994 467 s222 916 994 567 s122 -2938 1104 468 s221 877 1104 568 s121 -2976 994 469 s220 839 994 569 s120 -3014 1104 470 s219 801 1104 570 s119 -3052 994 471 s218 763 994 571 s118 -3090 1104 472 s217 725 1104 572 s117 -3128 994 473 s216 687 994 573 s116 -3166 1104 474 s215 649 1104 574 s115 -3205 994 475 s214 610 994 575 s114 -3243 1104 476 s213 572 1104 576 s113 -3281 994 477 s212 534 994 577 s112 -3319 1104 478 s211 496 1104 578 s111 -3357 994 479 s210 458 994 579 s110 -3395 1104 480 s209 420 1104 580 s109 -3434 994 481 s208 382 994 581 s108 -3472 1104 482 s207 343 1104 582 s107 -3510 994 483 s206 305 994 583 s106 -3548 1104 484 s205 267 1104 584 s105 -3586 994 485 s204 229 994 585 s104 -3624 1104 486 s203 191 1104 586 s103 -3662 994 487 s202 153 994 587 s102 -3701 1104 488 s201 114 1104 588 s101 -3739 994 489 s200 76 994 589 s100 -3777 1104 490 s199 38 1104 590 s99 -3815 994 491 s198 -38 1104 591 s98 -3853 1104 492 s197 -76 994 592 s97 -3891 994 493 s196 -114 1104 593 s96 -3929 1104 494 s195 -153 994 594 s95 -3968 994 495 s194 -191 1104 595 s94 -4006 1104 496 s193 -229 994 596 s93 -4044 994 497 s192 -267 1104 597 s92 -4082 1104 498 s191 -305 994 598 s91 -4120 994 499 s190 -343 1104 599 s90 -4158 1104 500 s189 -382 994 600 s89 -4197 994 no. p ad name x y no. p ad name x y 601 s88 -4235 1104 701 g167 -8393 1104 602 s87 -4273 994 702 g165 -8431 994 603 s86 -4311 1104 703 g163 -8469 1104 604 s85 -4349 994 704 g161 -8507 994 605 s84 -4387 1104 705 g159 -8546 1104 606 s83 -4425 994 706 g157 -8584 994 607 s82 -4464 1104 707 g155 -8622 1104 608 s81 -4502 994 708 g153 -8660 994 609 s80 -4540 1104 709 g151 -8698 1104 610 s79 -4578 994 710 g149 -8736 994 611 s78 -4616 1104 711 g147 -8775 1104 612 s77 -4654 994 712 g145 -8813 994 613 s76 -4692 1104 713 g143 -8851 1104 614 s75 -4731 994 714 g141 -8889 994 615 s74 -4769 1104 715 g139 -8927 1104 616 s73 -4807 994 716 g137 -8965 994 617 s72 -4845 1104 717 g135 -9003 1104 618 s71 -4883 994 718 g133 -9042 994 619 s70 -4921 1104 719 g131 -9080 1104 620 s69 -4960 994 720 g129 -9118 994 621 s68 -4998 1104 721 g127 -9156 1104 622 s67 -5036 994 722 g125 -9194 994 623 s66 -5074 1104 723 g123 -9232 1104 624 s65 -5112 994 724 g121 -9270 994 625 s64 -5150 1104 725 g119 -9309 1104 626 s63 -5188 994 726 g117 -9347 994 627 s62 -5227 1104 727 g115 -9385 1104 628 s61 -5265 994 728 g113 -9423 994 629 s60 -5303 1104 729 g111 -9461 1104 630 s59 -5341 994 730 g109 -9499 994 631 s58 -5379 1104 731 g107 -9538 1104 632 s57 -5417 994 732 g105 -9576 994 633 s56 -5455 1104 733 g103 -9614 1104 634 s55 -5494 994 734 g101 -9652 994 635 s54 -5532 1104 735 g99 -9690 1104 636 s53 -5570 994 736 g97 -9728 994 637 s52 -5608 1104 737 g95 -9766 1104 638 s51 -5646 994 738 g93 -9805 994 639 s50 -5684 1104 739 g91 -9843 1104 640 s49 -5723 994 740 g89 -9881 994 641 s48 -5761 1104 741 g87 -9919 1104 642 s47 -5799 994 742 dummy39 -10209 1099 643 s46 -5837 1104 743 g85 -10214 801 644 s45 -5875 994 744 g83 -10104 763 645 s44 -5913 1104 745 g81 -10214 725 646 s43 -5951 994 746 g79 -10104 687 647 s42 -5990 1104 747 g77 -10214 649 648 s41 -6028 994 748 g75 -10104 610 649 s40 -6066 1104 749 g73 -10214 572 650 s39 -6104 994 750 g71 -10104 534 651 s38 -6142 1104 751 g69 -10214 496 652 s37 -6180 994 752 g67 -10104 458 653 s36 -6218 1104 753 g65 -10214 420 654 s35 -6257 994 754 g63 -10104 382 655 s34 -6295 1104 755 g61 -10214 343 656 s33 -6333 994 756 g59 -10104 305 657 s32 -6371 1104 757 g57 -10214 267 658 s31 -6409 994 758 g55 -10104 229 659 s30 -6447 1104 759 g53 -10214 191 660 s29 -6486 994 760 g51 -10104 153 661 s28 -6524 1104 761 g49 -10214 114 662 s27 -6562 994 762 g47 -10104 76 663 s26 -6600 1104 763 g45 -10214 38 664 s25 -6638 994 764 g43 -10104 0 665 s24 -6676 1104 765 g41 -10214 -38 666 s23 -6714 994 766 g39 -10104 -76 667 s22 -6753 1104 767 g37 -10214 -114 668 s21 -6791 994 768 g35 -10104 -153 669 s20 -6829 1104 769 g33 -10214 -191 670 s19 -6867 994 770 g31 -10104 -229 671 s18 -6905 1104 771 g29 -10214 -267 672 s17 -6943 994 772 g27 -10104 -305 673 s16 -6981 1104 773 g25 -10214 -343 674 s15 -7020 994 774 g23 -10104 -382 675 s14 -7058 1104 775 g21 -10214 -420 676 s13 -7096 994 776 g19 -10104 -458 677 s12 -7134 1104 777 g17 -10214 -496 678 s11 -7172 994 778 g15 -10104 -534 679 s10 -7210 1104 779 g13 -10214 -572 680 s9 -7249 994 780 g11 -10104 -610 681 s8 -7287 1104 781 g9 -10214 -649 682 s7 -7325 994 782 g7 -10104 -687 683 s6 -7363 1104 783 g5 -10214 -725 684 s5 -7401 994 784 g3 -10104 -763 685 s4 -7439 1104 785 g1 -10214 -801 686 s3 -7477 994 786 gtest1 -10214 -877 687 s2 -7516 1104 688 s1 -7554 994 689 dummy31 -7630 1104 x y 690 dummy32 -7706 1104 -10135 935 691 dummy33 -7783 1104 10135 935 692 dummy34 -7859 1104 -10119 1100 693 dummy35 -7935 1104 10119 1100 694 dummy36 -8012 1104 -10029 1100 695 dummy37 -8088 1104 10029 1100 696 dummy38 -8164 1104 697 g175 -8240 1104 698 g173 -8279 994 699 g171 -8317 1104 700 g169 -8355 994 :?:?: :? :?:?:?:?:?:w:?:?::a :?::?:: :?:::o:?:?:w:::?:::?:::?:? :?:::o:?:?:w:::?:?:?:?:::?:? ::w:::?:::?:::?:? ::w : ::? :? :?:?:::? :?
HD66773R rev.1.10, jun.21.20 03, page 10 of 133 pin function signals number of pins i/o connected to functions select the mode interfacing with mpu. im3 im2 im1 im0 mpu interfacing mode db pins gnd gnd gnd gnd 68-system 16-bit interface db17-10,db8-1 gnd gnd gnd vcc 68-system 8-bit interface db17-10 gnd gnd vcc gnd 80-system 16-bit interface db17-10,db8-1 gnd gnd vcc vcc 80-system 8-bit interface db17-10 gnd vcc gnd id serial peripheral interface db17-10,db8-1 gnd vcc vcc * setting disabled vcc gnd gnd gnd 68-system 18-bit interface db17-0 vcc gnd gnd vcc 68-system 9-bit interface db17-9 vcc gnd vcc gnd 80-system 18-bit interface db17-0 vcc gnd vcc vcc 80-system 9-bit interface db17-9 vcc vcc * * setting disabled im3-1, im0/id 4 i gnd or v cc in serial peripheral interfac e mode, imo/id pin is used for id setting for the device code. cs* 1 i mpu chip selection signal. low: select HD66773R and accessible high: not select HD66773R and inaccessible must be fixed to gnd when not used. rs 1 i mpu register selection signal. low: index/status high: control must be fixed to vcc or gnd in spi mode. e/wr*/scl 1 i mpu enable signal to activate data read/write operation in 68-system bus interface. write strobe signal in 80-system bus interface, write data at low. synchronizing clock signal in spi mode. rw/rd* 1 i mpu read/write selection signal in 68-system bus interface. low: write, high: read read strobe signal in 80-system bus interface, read data at low. must be fixed to vcc or gnd in spi mode. db0/sdi 1 i/o mpu 18-bit bi-directional data bus. 8-bit bus interface: db17-10 9-bit bus interface: db17-9 16-bit bus interface: db17-10, 8-1 18-bit bus interface: db17-0 the pins not used for data transfer must be fixed to vcc or gnd. serial data input pin (sdi) to input on the rising edge of scl signal in spi mode.
HD66773R rev.1.10, jun.21.20 03, page 11 of 133 signals number of pins i/o connected to functions db1/sdo 1 i/o mpu 18-bit bi-directional data bus. 8-bit bus interface: db17-10 9-bit bus interface: db17-9 16-bit bus interface: db17-10, 8-1 18-bit bus interface: db17-0 the pins not used for data transfer must be fixed to vcc or gnd. serial data output pin (sdo) to output on the falling edge of scl signal in spi mode. db2-db17 16 i/o mpu 18-bit bi-directional data bus. 8-bit bus interface: db17-10 9-bit bus interface: db17-9 16-bit bus interface: db17-10, 8-1 18-bit bus interface: db17-0 the pins not used for data transfer must be fixed to vcc or gnd. osc1, osc2 2 i/o oscillation- resistor connect to an external resistor for r-c oscillation. when supplying clocks externally, supply with osc1, and leave osc2 open. reset1* reset2* reset3* 3impu or reset generating circuit reset pin. initialize the lsi at low. power-on reset required when turning on the power supply. supply with either one of r eset1,2,3, and leave the unused pins open. test1 1 i gnd test pin. must be fixed to gnd level. test2 1 i gnd test pin. must be fixed to gnd level. vcc, gnd 2 - power supply logic vcc: +2.2v ~ +3.3v logic-side ground, gnd: 0v rvcc 1 - power supply vcc power supply for internal ram. supply same electric potential as vcc. agnd 1 - power supply analogue-side ground, agnd: 0 v cgnd 1 o opposing gnd for external elements output gnd level. opposing gnd for external el ements (capacitors, diodes). vci 1 i vcc or power supply power supply for analogue circuits. connect to an external power supply of 2.5v ~ 3.3v. vci1 1 i/o vcc or power supply output internal reference voltage with amplitude between vci and gnd. reference voltage for step-up circuit1. connect to an external power supply of 2.75v or lower, when internal reference voltage is not used. ddvdh 1 i/o stabilizing capacitor or open output vci1 after stepped-up 2~3 times by step-up circuit 1. the step-up scale is determined with internal register setting. connect to a stabilizing capacitor. when step-up circuit 1 is not used, leave open. vci2 1 i ddvdh or power supply reference voltage for step-up circuit 2. connect to ddvdh. connect to an external power supply of 5.5v or lower, when ddvdh is not used. vgh 1 i/o stabilizing capacitor or power supply output voltage with amplit ude between vgh and gnd after stepped-up 2~4 times by step-up circuit 2. the step-up scale is determined with internal register setting. connect to a stabilizing capacitor. when step-up circuit 2 is not used, connect to an external power supply of 16.5v or lower.
HD66773R rev.1.10, jun.21.20 03, page 12 of 133 signals number of pins i/o connected to functions vci3 1 i vgh or ddvdh or power supply reference voltage for step-up circuit 3. connect to vgh or ddvdh. connect to an external power supply of 16.5v or lower, when internal power supply is not used. vgl 1 i/o stabilizing capacitor or power supply output voltage with amplit ude between vgh and gnd after multiplied by -1 by step-up circuit 3. connect to a stabilizing capacitor. when step-up circuit 3 is not used, connect to an external power supply of -16.5v or more. vci4 1 i vcc or vci1 or power supply reference voltage for a step-up circuit 4. connect to vci or an external power supply between 2.5 ~ 3.3 v. vcl 1 i/o stabilizing capacitor or power supply output voltage with amplitude between vci4 and gnd after multiplied by -1 by step-up circuit 4. connect to a stabilizing capacitor. power supply for generating vcoml. when using an external power supply, connect to an external power supply of ?3.3v or more if vcoml is negative vo ltage. when vcoml is gnd or more, halt step-up circuit 4 and connect it to gnd. vreg1out 1 i/o stabilizing capacitor or power supply generate from internally generated reference voltage with amplitude vci-gnd and output a reference voltage for vreg1 with amplitude ddvdh-gnd. the step-up scale for output voltage is determined with internal register setting. connect to a stabilizing capacitor. this is a reference voltage for generating vcom. connect to an external power supply of ddvdh or lower when step-up circuit 1 is not used. vreg2out 1 i/o stabilizing capacitor or power supply generate from internally generated reference voltage with amplitude vci-gnd and output a reference voltage for vreg2 with amplitude gnd-vgl. the step-up scale for output voltage is determined with internal register setting. connect to a stabilizing capacitor. this is a reference voltage fo r generating vgoffout. connect to an external power supply of vgl or more when step-up circuit 2 is not used. c11+ ~ c23+, c11 - ~ c23 - 10 ?\ step-up capacitor connect to a step-up capacitor if necessary depending on step-up scale. when internal step-up circuit is not used, leave open. c31+, c31- 2 ?\ step-up capacitor connect to a step-up capacitor fo r generating the vgl level from the vci3 and gnd levels. when internal step-up circuit is not used, leave open. c41+, c41- 2 ?\ step-up capacitor connect to a step-up capacitor fo r generating the vcl level from the vci4 and gnd levels. when internal step-up circuit is not used, leave open. vcom1 vcom2 2otft common electrode power supply for tft common electrode. output the same voltage level as vcoml during display off, and output the level with amplitude vcomh-vcoml during display on. the ac cycle is changeable with liquid crystal drive ac control register (r02). connect to a tft common electrode. vcomr 1 i variable resistor or open vcomh reference voltage. when vcomh is externally adjusted, halt the internal adjuster of vcomh with register setting and place a variable resistor between vr eg1out and gnd. when vcomh is not externally adjusted, leave it open and adjust vcomh with internal register setting.
HD66773R rev.1.10, jun.21.20 03, page 13 of 133 signals number of pins i/o connected to functions vcomh 1 o stabilizing capacitor vcom high level generated during vcom ac drive. connect to a stabilizing capacitor. vcoml 1 o stabilizing capacitor or open the vcom level without vcom ac drive, and vcom low level with vcom ac drive. the voltage can be adjusted with internal register setting. connect to a stabilizing capacitor. vcoml output is halted when vcomg bit is low, and in this case, stabilizing capacitor is not necessary. vgoffout 1 o vgoff or open output power supply for gate dr ive. internal register setting enables ac drive in synchronization with vcom. make an appropriate setting for the structure of hold capacitor of tft display. output the amplitude vcomh-vcoml in reference to vgoffl with ac drive. vgoff 1 i vgoffout or power supply tft gate off level. negative vo ltage. connect to vgoffout or otherwise, connect to external voltage power supply of vgl or more. vgoffh 1 o stabilizing capacitor or open vgoffout high level with vgoff ac drive. connect to a stabilizing capacitor. the vgoff output is halted when cad bit is low. in this case, no stabilizing capacitor is necessary. vgoffl 1 o stabilizing capacitor vgoffout without vgoff ac driv e, and vgoffout low level with vgoff ac drive. the voltage can be adjusted with internal register setting. connect to a stabilizing capacitor. v0p v31p 2 i/o stabilizing capacitor output from positive-polarity in ternal operational amplifier when the internal operational amplifier is turned on. connect to a stabilizing capacitor. v0n v31n 2 i/o stabilizing capacitor output from negative-polarity in ternal operational amplifier when the internal operational amplifier is turned on. connect to a stabilizing capacitor. vgs 1 i gnd or external resistor reference voltage for grayscale voltage generating circuit. place a variable resistor externally when adjusting a level for each panel. s1?s396 396 o lcd source output signal. t he shift direction of segment signal is changeable with ss bit: ss = 0, ram address 0000 is output from s1. ss = 1, it is output from s396. s1, s4, s7, ... display red (r), s2, s5, s8, ... display green (g), and s3, s6, s9, ... display blue (b) (ss = 0). g1-176 176 o lcd gate output signal. output vgh level to select a gate line, and output vgoff level not to select a gate line. gtest1-2 2 o lcd or open dummy gate output signal. output the vgh level to select a gate line, and output the vgoff level not to select a gate line when cad bit is high. output the vgoff level not to select a gate line when cad bit is low. leave open when not used. testa1 1 i/o stabilizing capacitor or open a test pin for the vcomh output. leave it open or connect to a stabilizing capacitor if necessa ry depending on the quality of display. testa2 1 i/o stabilizing capacitor or open a test pin for the vcoml output. leave it open or connect to a stabilizing capacitor if necessa ry depending on the quality of display. testa3 1 i/o stabilizing capacitor or open a test pin for the vgoff output. leave it open or connect to a stabilizing capacitor if necessa ry depending on the quality of display.
HD66773R rev.1.10, jun.21.20 03, page 14 of 133 signals number of pins i/o connected to functions testa4 1 i/o stabilizing capacitor or open a test pin for the vcoml output. leave it open or connect to a stabilizing capacitor if necessa ry depending on the quality of display. dctest 1 i gnd a test pin. must be connected to gnd. mtest1 mtest2 2 o open test pins. leave open. vtests 1 i/o open a test pin. leave open. ts0-ts7 8 o open a test pin. leave open. vmoni 1 o open a test pin. leave open. testv1 1 i gnd a test pin. must be connected to gnd. regp 1 i/o open a test pin for vreg1out. leave open. dummy1, 22, 23, 39 4 o open test outputs. leave open. dummy2-21, dummy24-38 35 ?\ dummy dummy pads. connected to nowhere.
HD66773R rev.1.10, jun.21.20 03, page 15 of 133 block function 1. system interface the HD66773R incorporates three kinds of high-speed system interfaces: 68-system and 80-system interfaces with 18-/16-/9-/8- bit bus, and serial peripheral interface ( spi). the interfacing mode is selected with im3-0 pins. the HD66773R has three 16-bit registers: index register (ir), write data regist er (wdr), and read data register (rdr). the ir stores the information of each control register and the index information of gram. the wdr temporarily stores data before written to the control register or gram. the rdr temporarily stores the data, which is read from gram. data written into gram from the mpu is first written into the wdr and then is automatically written into gram by in ternal operation. since data are read through the rdr from gram, the data read out first are inva lid and the ensuing data are read out normally. the execution time for the instructions other than oscillation start is 0-clock cycle, which enables instructions to be written consecutively. register selection (8/9/16/18 parallel interface) 80-system 68-system wr* rd* r/w rs operation 0 1 0 0 write index into ir 1 0 1 0 read internal status 0 1 0 1 write to control register and gram through wdr 1 0 1 1 read from gram through rdr register selection (serial peripheral interface) start byte r/w bits rs bits operations 0 0 write index into ir 1 0 read internal status 0 1 write to control register and gram through wdr 1 1 read from gram through rdr 2. bit operation the HD66773R supports write data mask function to write bit data selectively to gram and logical arithmetical operation to perform logical arithmetical operation and conditional rewrite on gram display data and then rewrite the data to gram. these f unctions significantly reduce the load on the graphics- processing software in the microcomputer, and enable high-speed overwrite of gram display data. for details, see ?graphics operation function?.
HD66773R rev.1.10, jun.21.20 03, page 16 of 133 3. address counter (ac) the address counter (ac) assigns addresses to gram. when an address set instruction is written into the ir, the address information is sent from the ir to the ac. after writing data into gram, the ac is automatically updated plus or minus 1. the ac is not updated when the data are read from gram. window address function enables data write only in the rectangular area of gram specified by window addresses. 4. hardware-dither circuit the hardware-dither circuit converts 18-bit one-pixel da ta to 16-bit data with hardware-dither conversion. 5. graphics ram (gram) gram is graphics ram that stores bit-pattern data of 132 x 176 bytes with 16 bits per pixel. 6. gray scale power supply voltage generating circuit the grayscale voltage generation circuit generates liquid crystal drive voltage according to the grayscale level set with the -adjustment register, enabling 262,144-color display with 18 bits per pixel. for details, see the ? -adjustment register? section. 7. lcd drive power supply the lcd drive power supply generates lcd drive voltage levels, vop, von, v31p, v31n, vgh, vgl, vgoffout, and vcom. 8. oscillation circuit (osc) the HD66773R can provide r-c oscillation simply by placing an external oscillation-resistor between osc1 and osc2 pins. an appropriate oscillation freq uency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. clock pulses can be supplied externally. since r-c oscillation is halted during standby mode, cu rrent consumption will be reduced. for details, see ?oscillation circuit?. 9. lcd driver circuit the lcd driver circuit of HD66773R consists of a 396-output source driver (s1 ~ s396) and a 176-output gate driver (g1 ~ g176). display pattern data are latched when 396-bit data arrive. the latched data controls source driver and generates drive waveforms. the gate driver, which operates display scan, selects either vgh or vgoff level to output. the shift direction of outputting 396-bit data from source driver outputs is changeable with the ss bit. the shift directio n of gate driver scan is changeable with the gs bit. the scan mode of gate driver is changeable with sm bit. select an appropri ate shift direction and scan mode for an assembly.
HD66773R rev.1.10, jun.21.20 03, page 17 of 133 gram address map gram address and display position on the panel (ss = ?0?) s385 s386 s387 s388 s389 s390 db 17 db 0 db 17 db 0 s391 s392 s393 s394 s395 s396 db 17 db 0 db 17 db 0 s7 s8 s9 s10 s11 s12 db 17 db 0 db 17 db 0 g176 s1 s2 s3 s4 s5 s6 g175 g174 g173 g172 g171 g170 g169 g168 g167 g166 g165 g164 g163 g162 g161 g160 g159 g158 g157 g7 g6 g5 g8 g4 g3 g2 g1 db 17 db 0 db 17 db 0 "0001"h "0101"h "0201"h "0301"h "0401"h "0501 h "0601"h "0701"h "0801"h "0901"h "0a01"h "0b01"h "0c01"h "0d01"h "0e01"h "0f01"h "1001"h "1101"h "1201"h "1301"h "a801"h "a901"h "aa01"h "ab01"h "ac01"h "ad01"h "ae01"h "af 01"h "0000"h "0100"h "0200"h "0300"h "0400"h "0500"h "0600"h "0700"h "0800"h "0900"h "0a00"h "0b00"h "0c00"h "0d00"h "0e00"h "0f00"h "1000"h "1100"h "1200"h "1300"h "a800"h "a900"h "aa00"h "ab00"h "ac00"h "ad00"h "ae00"h "af 00"h g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 g14 g15 g16 g17 g18 g19 g20 g170 g171 g172 g169 g173 g174 g175 g176 gs=1 gs=0 s/g p in "0002"h "0102"h "0202"h "0302"h "0402"h "0502"h "0602"h "0702"h "0802"h "090 2"h "0a02"h "0b02"h "0c02"h "0d02"h "0e02"h "0f02"h "1002"h "1102"h "1202"h "1302"h "a802"h "a902"h "aa02"h "ab02"h "ac02"h "ad02"h "ae02"h "af 02"h "0003"h "0103"h "0203"h "0303"h "0403"h "0503"h "0603"h "0703"h "0803"h "0903"h "0a03"h "0b03"h "0c03"h "0d03"h "0e03"h "0f03"h "1003"h "1103"h "1203"h "130 3"h "a803"h "a903"h "aa03"h "ab03"h "ac03"h "ad03"h "ae03"h "af 03"h "0081"h "0181"h "0281"h "0381"h "0481"h "0581 h "0681"h "0781"h "0881"h "0981"h "0a81"h "0b81"h "0c81"h "0d81"h "0e81"h "0f81"h "1081"h "1181"h "1281"h "1381"h "a881"h "a981"h "aa81"h "ab81"h "ac81"h "ad81"h "ae81"h "af 81"h "0080"h "0180"h "0280"h "0380"h "0480"h "0580"h "0680"h "0780"h "0880"h "0980"h "0a80"h "0b80"h "0c80"h "0d80"h "0e80"h "0f80"h "1080"h "1180"h "1280"h "1380"h "a880"h "a980"h "aa80"h "ab80"h "ac80"h "ad80"h "ae80"h "af 80"h "0082"h "0182"h "0282"h "0382"h "0482"h "0582"h "0682"h "0782"h "0882"h "0982"h "0a82"h "0b82"h "0c82"h "0d82"h "0e82"h "0f82"h "1082"h "1182"h "1282"h "1382"h "a882"h "a982"h "aa82"h "ab82"h "ac82"h "ad82"h "ae82"h "af 82"h "0083"h "0183"h "0283"h "0383"h "0483"h "0583"h "0683"h "0783"h "0883"h "0983"h "0a83"h "0b83"h "0c83"h "0d83"h "0e83"h "0f83"h "1083"h "1183"h "1283"h "138 3"h "a883"h "a983"h "aa83"h "ab83"h "ac83"h "ad83"h "af83"h ?ae83?h
HD66773R rev.1.10, jun.21.20 03, page 18 of 133 the relationship between gram data and display data (ss =?0?) the following figures illustrate the relationship betw een gram data and display data in each interface mode. r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b2 b1 b0 b3 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b2 b1 b0 b3 dither process circuit if dat a r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b2 b1 b0 b3 n ote: n = lower eight bit of address (0 to 132) s (3n+1) s (3n+2) s (3n+3) output pins 262,144 colors expansion circuit gram data 18-bit interface & hard dithering mod e r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b2 b1 b0 b3 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 gram data if dat a r5 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b2 b1 b0 b3 n ote: n = lower eight bit of address (0 to 132) s (3n + 1) s (3n + 2) s (3n + 3) output pins 262,144 colors expansion circui t 16-bit interface r4
HD66773R rev.1.10, jun.21.20 03, page 19 of 133 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b2 b1 b0 b3 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b2 b1 b0 b3 dither process circuit if dat a r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b2 b1 b0 b3 s (3n + 1) s (3n + 2) s (3n + 3) output pins 262,144 colors expansion circuit gram data 9-bit interface & hard dither mode first transfer second transfer n ote: n = lower eight bit of address (0 to 132) r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b2 b1 b0 b3 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 gram data if data n ote: n = lower eight bite of address (0 to 132) r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b2 b1 b0 b3 s (3n + 1) s (3n + 2) s (3n + 3) output pins 262,144 colors expansion circui t 8-bit interface / spi first transfer second transfer db 17 db 16 db 15 db 14 db 13 db 11 db 12 db 10
HD66773R rev.1.10, jun.21.20 03, page 20 of 133 gram address and display position on the panel (ss = ?1?, bgr = ?1?) s385 s386 s387 s388 s389 s390 db 0 db 17 db 0 db 17 s391 s392 s393 s394 s395 s396 db 0 db 17 db 0 db 17 s7 s8 s9 s10 s11 s12 db 0 db 17 db 0 db 17 g176 s1 s2 s3 s4 s5 s6 g175 g174 g173 g172 g171 g170 g169 g168 g167 g166 g165 g164 g163 g162 g161 g160 g159 g158 g157 g7 g6 g5 g8 g4 g3 g2 g1 db 0 db 17 db 0 db 17 g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 g14 g15 g16 g17 g18 g19 g20 g170 g171 g172 g169 g173 g174 g175 g176 gs=1 gs=0 s/g pin "0083"h "0183"h "0283"h "0383"h "0483"h "0583"h "0683"h "0783"h "0883"h "0983"h "0a83"h "0b83"h "0c83"h "0d83"h "0e83"h "0f83"h "1083"h "1183"h "1283"h "138 3"h "a883"h "a983"h "aa83"h "ab83"h "ac83"h "ad83"h "ae83"h "af83"h "0082"h "0182"h "0282"h "0382"h "0482"h "0582"h "0682"h "0782"h "0882"h "0982"h "0a82"h "0b82"h "0c82"h "0d82"h "0e82"h "0f82"h "1082"h "1182"h "1282"h "1382"h "a882"h "a982"h "aa82"h "ab82"h "ac82"h "ad82"h "ae82"h "af 82"h "0081"h "0181"h "0281"h "0381"h "0481"h "0581 h "0681"h "0781"h "0881"h "0981"h "0a81"h "0b81"h "0c81"h "0d81"h "0e81"h "0f81"h "1081"h "1181"h "1281"h "1381"h "a881"h "a981"h "aa81"h "ab81"h "ac81"h "ad81"h "ae81"h "af 81"h "0080"h "0180"h "0280"h "0380"h "0480"h "0580"h "0680"h "0780"h "0880"h "0980"h "0a80"h "0b80"h "0c80"h "0d80"h "0e80"h "0f80"h "1080"h "1180"h "1280"h "1380"h "a880"h "a980"h "aa80"h "ab80"h "ac80"h "ad80"h "ae80"h "af 80"h "0003"h "0103"h "0203"h "0303"h "0403"h "0503"h "0603"h "0703"h "0803"h "0903"h "0a03"h "0b03"h "0c03"h "0d03"h "0e03"h "0f03"h "1003"h "1103"h "1203"h "130 3"h "a803"h "a903"h "aa03"h "ab03"h "ac03"h "ad03"h "ae03"h "af03"h "0002"h "0102"h "0202"h "0302"h "0402"h "0502"h "0602"h "0702"h "0802"h "0902"h "0a02"h "0b02"h "0c02"h "0d02"h "0e02"h "0f02"h "1002"h "1102"h "1202"h "1302"h "a802"h "a902"h "aa02"h "ab02"h "ac02"h "ad02"h "ae02"h "af 02"h "0001"h "0101"h "0201"h "0301"h "0401"h "0501 h "0601"h "0701"h "0801"h "0901"h "0a01"h "0b01"h "0c01"h "0d01"h "0e01"h "0f01"h "1001"h "1101"h "1201"h "1301"h "a801"h "a901"h "aa01"h "ab01"h "ac01"h "ad01"h "ae01"h "af 01"h "0000"h "0100"h "0200"h "0300"h "0400"h "0500"h "0600"h "0700"h "0800"h "0900"h "0a00"h "0b00"h "0c00"h "0d00"h "0e00"h "0f00"h "1000"h "1100"h "1200"h "1300"h "a800"h "a900"h "aa00"h "ab00"h "ac00"h "ad00"h "ae00"h "af 00"h
HD66773R rev.1.10, jun.21.20 03, page 21 of 133 the relationship between gram data and display data (ss =?1?) the following figures illustrate the relationship betw een gram data and display data in each interface mode. r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b2 b1 b0 b3 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b2 b1 b0 b3 dither process circuit if dat a r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b2 b1 b0 b3 n ote: n = lower eight bite of address (0 to 132) s (396 ?3n) s (395 - 3n) s (394 ? 3n) output pins 262,144 colors expansion circuit gram data 18-bit interface & hard dither mode gram data if dat a r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b2 b1 b0 b3 n ote: n = lower eight bite of address (0 to 132) s (396 ?3n) s (395 - 3n) s (394 ? 3n) output pins 262,144 colors expansion circui t r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b2 b1 b0 b3 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 16-bit interface
HD66773R rev.1.10, jun.21.20 03, page 22 of 133 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b2 b1 b0 b3 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b2 b1 b0 b3 dither process circuit if dat a r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b2 b1 b0 b3 s (396 ? 3n) s (395 ? 3n) s (394 ? 3n) output pins 260,000 colors expansion circuit gram data 9-bi t interface & hardware dither mode first transfer second tran sfer r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b2 b1 b0 b3 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 gram data if data n ote: n = lower eight bite of address (0 to 131) r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b2 b1 b0 b3 s (396 ? 3n) s (395 ? 3n) s (394 ? 3n) output pins 260,000 colors expansion circui t 8-bi t interface / spi first transfer second transfer db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 n ote: n = lower eight bite of address (0 to 131)
HD66773R rev.1.10, jun.21.20 03, page 23 of 133 instructions outline the HD66773R adapts 18-bit bus arch itecture that enables high-speed in terfacing with a high-performance microcomputer. data sent from external (18/16/9/8 b its) are stored temporarily in the instruction register (ir) and the data register (dr) to store control inform ation before internal operation starts. since internal operation is decided according to the signal sent from the microcomputer, register selection signal (rs), read/write signal (r/w), and intern al 16-bit data bus signal (db15 to db0) are called instruction. gram is accessed through internal 18-bit data bus. there are eight categor ies of instructions: 1. specify index 2. read status 3. control display 4. control power management 5. process graphics data 6. set internal gram addresses 7. transfer data to and from internal gram 8. set grayscale level for internal grayscale -adjustment normally, the 7 th instruction to write data to be displayed is executed the most frequently. the address of internal gram is updated automatically after data are written to internal gram. with window address function, this reduces the amount of data transmission to minimum and thereby lightens the load on the program in the microcomputer. since instructions are executed in 0 cycle, it is possible to write instructions consecutively. as the following figure shows, th e assignment to the 16 instruction bi ts (ib15-0) varies according to the interface to be used. an instruction must adopt the data format for each interface.
HD66773R rev.1.10, jun.21.20 03, page 24 of 133 18-bit interface 16-bit interfac e db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 instruction bit (ib) ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 instruction bit (ib) ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 9-bit interface 8-bi t interface/spi db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 instruction bit (ib) ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 instruction bit (ib) ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 first transfe r second tran sfer first transfe r second transfer db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 instruction bit assignment
HD66773R rev.1.10, jun.21.20 03, page 25 of 133 instructions the following are detail explanations of instructions w ith illustrations of instruction bits (ib15-0) assigned to each interface. index the index instruction specifies a index (r00h to r3bh) of control registers and ram control, that is accessed. it sets the register num ber from 0000000 to 11111111 in binary form. do not try to access to the register to which instruction is not assigned. status read the status read instruction reads th e internal status of the HD66773R. l7?0: indicate the position of raster-row driving liquid crystal. start oscillation (r00h) the start oscillation instruction restarts the oscillator in a halt state during standby mode. after executing this instruction, wait at least 10 ms for stabilizing osc illation before issuing a next instruction. for details, see the ?standby mode? section. ?0773?h is read out, if this re gister is forced to read out. r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 ????? ? ? ? ? id5 id4 id2 id0 id1 id3 id6 r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 r 0l6l5l3l1 l2 l4 l7 l0 0 0 0 0 0 0 0 0 r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 0 ????? ? ? ? ? 1 r1 000001 11 ? ? ? ? ? ? 110111 00
HD66773R rev.1.10, jun.21.20 03, page 26 of 133 driver output control (r01h) gs: select the shift direction of outputs from the gate driver. the scan order by the gate driver is changeable in accordance to the scan mode of gate driver. select an optimum shift direction for the assembly. sm: set the scan order by the gate driver. select an optimum scan order for the assembly. for details, see ?scan mode setting?. ss: select the shift direction of outputs from the source driver. when ss = 0, the shift direction of outputs is from s1 to s396. when ss = 1, the shift direction of outputs is from s396 to s1 . in addition to the shift direction, setting for both ss and bgr bits are required to change the assignment of r, g, b dots to the source driver pins. to assign r, g, b dots to the source driver pins interchangeably from s1, set ss = 0, bgr = 0. to assign r, g, b dots to the source driver pins interchangeably from s396, set ss = 1, bgr = 1. r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 0gs sm 0 0 ss 0 0 0 nl4 nl3 nl2 nl0 nl1
HD66773R rev.1.10, jun.21.20 03, page 27 of 133 nl4-0: specify the number of lcd drive raster-rows. the number of drive raster-rows is adjusted by 8 multiple raster-rows. the mapping of addresses to gram is independent of this setting. select the number of raster-rows so that the display size covers the size of a panel. nl bits note 1) a blanking period which lasts 8h, where all gate lines output vgoff level, will be inserted after driving all gate lines. nl1 nl0 number of lcd driver lines 00 01 10 24 11 gate driver used g1 to g24 nl2 0 0 0 0 00 1 01 1 10 1 56 g1 to g56 11 1 64 g1 to g64 00 0 72 g1 to g72 nl3 0 0 0 0 0 0 0 0 1 display size 396 x 24 dots 396 x 56 dots 396 x 64 dots 396 x 72 dots 01 0 80 g1 to g80 1 396 x 80 dots 16 g1 to g16 396 x 16 dots 48 g1 to g48 396 x 48 dots 40 g1 to g40 396 x 40 dots 32 g1 to g32 396 x 32 dots setting disabled nl4 0 0 0 0 0 0 0 0 0 0 10 0 88 g1 to g88 1 396 x 88 dots 0 1 1 0 96 g1 to g96 1 396 x 96 dots 0 00 1 104 g1 to g104 1 396 x 104 dots 0 01 1 112 g1 to g112 1 396 x 112 dots 0 10 1 120 g1 to g120 1 396 x 120 dots 0 1 1 1 128 g1 to g128 1 396 x 128 dots 0 00 0 136 g1 to g136 0 396 x 136 dots 1 01 0 144 g1 to g144 0 396 x 144 dots 1 10 0 152 g1 to g152 0 396 x 152 dots 1 1 1 0 160 g1 to g160 0 396 x 160 dots 1 00 1 168 g1 to g168 0 396 x 168 dots 1 01 1 176 g1 to g176 0 396 x 176 dots 1 setting disabled setting disabled
HD66773R rev.1.10, jun.21.20 03, page 28 of 133 lcd driving waveform control (r02h) fld1-0: specify the number of fields during n-field in terlaced drive. for deta ils, see ?interlaced drive?. fld bits fld1 fld0 number of fields 0 0 setting disabled 0 1 1 field 1 0 setting disabled 1 1 3 fields b/c: when b/c =0, a field ac waveform is generated. alternation occurs every frame to drive liquid crystal. when b/c=1, alternation occurs every n raster-rows according to the settings in eor and nw5-0 bits of the lcd driving waveform control register . for details, see ?n-raster-row inversion ac drive?. eor: when eor = 1 and a c-pattern waveform is generated (b/c =1), an odd/even frame select signal and an n-raster-row inversion signal are ac-driven. this instruction is available when liquid crystal ac drive is not made depending on the combination of numbers of lcd drive raster-rows and the value of ?n? of n-raster-row inversion ac drive. for details, see ?n-raster-row inversion ac drive?. nw5-0: specify n, the number of raster-rows from 1 to 64 to alternate every n+1 raster-rows when c- pattern waveform is generated (b/c = 1). r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 100 b/c 0 0 eor 0 0 nw5 fld1 fld0 nw4 nw3 nw2 nw1 nw0
HD66773R rev.1.10, jun.21.20 03, page 29 of 133 power control 1 (r03h) power control 2 (r04h) bt2?0: change the step-up scale of the step-up circuit. adjust the scal e according to the voltage. smaller scale consumes lesser current. bt2 bt1 bt0 ddvdh output vgh outp ut note* capacitor connect pin 0 0 0 2 x vci1 3 x vci2 vgh = vci1 x 6 ddvdh, vgh, vgl, vcl, c11 , c21 , c22 , c31 , c41 0 0 1 2 x vci1 4 x vci2 vgh = vci1 x 8 ddvdh, vgh, vgl, vcl, c11 , c21 , c22 , c23 , c31 , c41 0 1 0 3 x vci1 3 x vci2 vgh = vci1 x 9 ddvdh, vgh, vgl, vcl, c11 , c12 , c21 , c22 , c31 , c41 0 1 1 3 x vci1 2 x vci2 vgh = vci1 x 6 ddvdh, vgh, vgl, vcl, c11 , c12 , c21 , c22 , c31 , c41 1 0 0 2 x vci1 vci1 + 2 x vci2 vgh = vci1 x 5 ddvdh, vgh, vgl, vcl, c11 , c21 , c22 , c31 , c41 1 0 1 2 x vci1 vci1 + 3 x vci2 vgh = vci1 x 7 ddvdh, vgh, vgl, vcl, c11 , c21 , c22 , c23 , c31 , c41 110 step-up disabled 3 x vci2 vgh = vci2 x 3 ddvdh, vgh, vgl, vcl, c21 , c22 , c31 , c41 1 1 1 setting disabled setting disabled setting disabled ? note*) the vgh is stepped-up from vci1, which is t he voltage level when ddvdh and vci2 is short-circuited. the vgh must be set to satisfy vddvdh 5.5 v and vgh 16.5 v. r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w1 w1cad0 0 0 0 0 00000 00000 0 0 0 0 0 bt2 bt1 bt0 dc2 dc1 dc0 ap2 ap1 ap0 slp stb
HD66773R rev.1.10, jun.21.20 03, page 30 of 133 dc2?0: select the operating frequency for the step-up circuit. the higher step-up frequency enhances the drive capacity of step-up circuit as well as the disp lay quality, while the current consumption will increase. adjust the frequency taking both the display qua lity and the current consumption into consideration. dc2 dc1 dc0 step-up cycle of step-up circuit 1 step-up cycle in step-up circuits 2/3/4 0 0 0 dcclk /16 dcclk / 64 0 0 1 dcclk / 32 dcclk / 64 0 1 0 dcclk / 64 dcclk / 64 0 1 1 dcclk / 32 dcclk / 256 1 0 0 dcclk / 16 dcclk / 128 1 0 1 dcclk / 32 dcclk / 128 1 1 0 dcclk / 64 dcclk / 128 1 1 1 dcclk / 64 dcclk / 256 ap2?0: adjust the amount of fixed current from the fixe d current source in the operational amplifier circuit in the liquid crystal drive power supply. when the amount of fixed current is set large, the liquid crystal drive capacity is enhanced and the display qua lity will improve, while the current consumption will increase. select an optimum amount of current taki ng both the display quality and the current consumption into account. during non-display operation, set ap2-0 = ?000? to halt the operation of operational amplifier and step-up circuit to further reduce current consumption. ap2 ap1 ap0 amount of current in operational amplifier 0 0 0 halt operational amplifier and step-up circuit 001small 0 1 0 small or medium 0 1 1 medium 1 0 0 medium or large 1 0 1 large 1 1 0 setting disabled 1 1 1 setting disabled slp: when slp = 1, the HD66773R enters into the sleep mode. in the sleep mode, internal display operation is halted except the r-c oscillator to reduce cu rrent consumption. no change is made to the gram data or instructions during the sleep mode, but it is retained. stb: when stb = 1, the HD66773R enters into the standby mode. in the standby mode, display operation is completely halted, and all inte rnal operation includin g the internal r-c oscillator and reception of external clock pulse, is halted. for details, se e ?standby mode?. only instructions to access r03h including the standby bit and to start oscillation are accepted during the standby mode. cad: make an appropriate setting for the structure of tft panel holding capacitor. set cad = ?0? for cst structure. set cad = ?1? for cadd structure.
HD66773R rev.1.10, jun.21.20 03, page 31 of 133 power control 3 (r0ch) power control 4 (r0dh) power control 5 (r0eh) vc2-0: adjust reference voltage for vreg1out, vreg 2out, and vci1 to the level of vci multiples. when vc2-0 = ?111?, internal reference voltage genera tion is halted and an arbitrary level of voltage can be applied through vci1. vc2 vc1 vc0 vreg1out (reference, vci1 output , regp output voltage) 000 vci 0 0 1 0.92 x vci 0 1 0 0.87 x vci 0 1 1 0.83 x vci 1 0 0 0.76 x vci 1 0 1 0.73 x vci 1 1 0 0.68 x vci 1 1 1 vci1: hi-z regp: gnd note) leave regp open so that the vo ltage as specified above is output. r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w1 w1 00 00 000 00 000 vrl3 vrl2 vrl1 vrl0 0 pon vrh3 vrh2 vrh1 vrh0 vc2 vc1 vc0 0 0 0 0 0 0 0 w1 00 00 vdv3 vdv2 vdv1 vdv0 0 vcm4 vcm3 vcm2 vcm1 vcm0 vco mg vdv4
HD66773R rev.1.10, jun.21.20 03, page 32 of 133 vrl3-0: set the amplifying scale of vreg2out voltage (the reference voltage for vgoff). the output from vci voltage adjustment circuit can be amplified by ?1.5 ~ ?6.5 times. vrl3 vrl2 vrl1 vrl0 vreg2out voltage 0000vci x ?1.5 0001vci x? 2.0 0 0 1 0 vci x ? 2.5 0 0 1 1 vci x ? 3.0 0100vci x? 3.5 0 1 0 1 vci x ? 4.0 0 1 1 0 vci x ? 4.5 0111halt 1 0 0 0 vci x ? 5.0 1 0 0 1 vci x ? 5.5 1 0 1 0 vci x ? 6.0 1 0 1 1 vci x ? 6.5 1 1 0 0 setting inhibited 1 1 0 1 setting inhibited 1 1 1 0 setting inhibited 1111halt note) adjust vci and vrl3-0 so that t he vreg2out voltage is ?16.0 v or more. pon: start operation of step-up circuit 3. to halt oper ation, set pon = 0. to start operation, set pon = 1.
HD66773R rev.1.10, jun.21.20 03, page 33 of 133 vrh3-0: set the amplifying scale of vlout1 voltage (the reference voltage for vcom and grayscale voltage). the output from vciout output amplifier can be amplified by 1.33 ~ 2.775 times. vrh3 vrh2 vrh1 vrh0 vreg1out voltage 0 0 0 0 regp x 1.33 0 0 0 1 regp x 1.45 0 0 1 0 regp x 1.55 0 0 1 1 regp x 1.65 0 1 0 0 regp x 1.75 0 1 0 1 regp x 1.80 0 1 1 0 regp x 1.85 0 1 1 1 halt 1 0 0 0 regp x 1.900 1 0 0 1 regp x 2.175 1 0 1 0 regp x 2.325 1 0 1 1 regp x 2.475 1 1 0 0 regp x 2.625 1 1 0 1 regp x 2.700 1 1 1 0 regp x 2.775 1 1 1 1 halt note) adjust vc2-0 and vrh3-0 so that the vreg1out voltage is 5.0 v or less. vcomg: when vcomg = 1, vcoml outputs a negative voltage up to ?5v. when vcomg = 0, the vcoml voltage is gnd and negative-polarity amplifier is halted to reduce power consumption. when vcomg = ?0?, the setting in vdv4-0 is made invalid. in this case, make adjustment for the ac amplitudes of vcom and vgoff with vcm4-0, vocomh settings.
HD66773R rev.1.10, jun.21.20 03, page 34 of 133 vdv4-0: set the ac amplitude of vcom and vgoff during vcom ac drive. the amplitude can be specified within the range of vreg1out x 0.6 ~ 1.23. when vcomg = 0, this setting is invalid. vdv4 vdv3 vdv2 vdv1 vdv0 vcom amplitude 00000vreg1out x 0.60 00001vreg1out x 0.63 00010vreg1out x 0.66 : : : : : 01100vreg1out x 0.96 01101vreg1out x 0.99 01110vreg1out x 1.02 0 1 1 1 1 setting disabled 10000vreg1out x 1.05 10001vreg1out x 1.08 10010vreg1out x 1.11 10011vreg1out x 1.14 10100vreg1out x 1.17 10101vreg1out x 1.20 10110vreg1out x 1.23 10111 11* * * setting disabled note) adjust vreg1out and vdv4-0 so that the vcom and vgoff amplitudes are 6.0 v or less.
HD66773R rev.1.10, jun.21.20 03, page 35 of 133 vcm4-0: set the vcomh voltage (the higher voltage during vcom ac drive). the amplitude can be specified within the range of vreg1out x 0.4 ~ 0.98. when vcm4-0 = ?1111?, the internal volume adjustment operation is halted, and the vcomh voltage can be adjust by placing an external resistor at vcomr. vcm4 vcm3 vcm2 vcm1 vcm0 vcomh voltage 0 0 0 0 0 vreg1out x 0.40 0 0 0 0 1 vreg1out x 0.42 0 0 0 1 0 vreg1out x 0.44 : : : : : 0 1 1 0 0 vreg1out x 0.64 0 1 1 0 1 vreg1out x 0.66 0 1 1 1 0 vreg1out x 0.68 0 1 1 1 1 halt internal vo lume. adjust by an external variable resistor vcomr. 1 0 0 0 0 vreg1out x 0.70 1 0 0 0 1 vreg1out x 0.72 1 0 0 1 0 vreg1out x 0.74 : : : : : 1 1 1 0 0 vreg1out x 0.94 1 1 1 0 1 vreg1out x 0.96 1 1 1 1 0 vreg1out x 0.98 1 1 1 1 1 halt internal vo lume. adjust by an external variable resistor vcomr. note) adjust vreg1out and vcm4-0 so that the vcomh voltage is the vdh level or less. cl1 flm gtest1,2 1 2 3 1 2 3 vgoff vgh vgh vgoff gtest1, 2 output timing chart
HD66773R rev.1.10, jun.21.20 03, page 36 of 133 entry mode (r05h) compare register (r06h) the HD66773R modifies write data sent from the microcomputer before writing to gram. this enables high-speed gram data update, and reduces the load on the microcomputer software. for details, see ?graphics operation function?. hwm: when hwm=1, data are written to gram in high speed. in high-speed write mode, 4 words are written to gram in a single operation after ex ecuting 4 ram write operations. if ram write is terminated before it is executed 4 times, the last data will not be written. make sure that ram write is executed 4 times. for this reason, the lower 2 bits mu st be set to ?0? when setting the ram address. for details, ?high-speed ram write mode?. i/d1-0: the address counter is automatically incremented by 1, after data are written to gram when i/d1- 0 = ?1?. the address counter is automatically decr emented by 1, after data are written to gram when i/d1-0 = ?0?. the setting for the increment or decrement of the address counter can be made independently for each upper and lower bits of the address. the tr ansition direction of the ad dress when data are written to gram is set with am bits. am: set the direction in which the address counter is updated automatically after data are written to gram. when am = ?0?, the address counter is updated in the horizontal directio n. when am = ?1?, the address counter is updated in the vertical direction. when window addresses are specified, data are written to the gram area specified by the window address in the manner specified with i/d1-0, am bits. dit: hardware-dither mode when dit = ?1?. use ha rdware-dither mode with 18/9-bit interface modes. 000 0h a f83h 0000h a f83h 0000h a f83h 0000h a f83h 0000h a f83h 0000h a f83h 0000h a f83h 0000h a f83h i/d1-0="00" horizontal: decrement vertical: decrement i/d1-0="01" horizontal: increment vertical: decrement i/d1-0="10" horizontal: decrement vertical: increment i/d1-0="11" horizontal: increment vertical: increment a m="0" horizontal a m="1" vertica l note: when the window address is set, data are written only in the window address area on gram. address transition direction r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w1 w1 cp15 cp14 cp7 cp6 dit 0 0 00 000 cp1 3 cp 11 cp 12 cp 10 cp 9 cp 8 cp5 cp4 cp3 cp2 cp1 cp0 lg2 lg1 lg0 bgr hwm i/d1 i/d0 am
HD66773R rev.1.10, jun.21.20 03, page 37 of 133 lg2?0: rewrite data to gram after comparing the data that are written by the microcomputer to gram with the values in the compare registers (cp17?0) and performing a logical operation. for details, see ?graphics operation function?. cp15?0: set the value for the compare register, with whic h the data read out from gram or data written to gram by the microcomputer are compared. this function is not available with 18/19-bit interface modes. in 18/19-bit interface modes, make sure lg2-0 = ?000?. bgr: reverse the order from r, g, b to b, g, r for gram data. when setting bgr = 1, cp15-0 and wm15-0 bits will be automatically changed to the same effect. logical/compare operation (lg2 - 0) write data mask* (wm15 - 0) (note 2) note 1) the logical and compare operations are effective in 8-/16-bit interace modes. otherwise, set lg2-0 = "000". the bit assignment is different for each interface mode. note 2) write data mask (wm15-0) is set with the ram write data mask register. the write data mask is available in 8-/16-bit interace modes. 0001 1 1001110 write data (note 1) 0 0 0 0 18 bit 0 0 rgb- bgr conversion (bgr) logical operatioin on gram write data lg2-0 = "000" : replace lg2-0 = "001" : or lg2-0 = "010" : and lg2-0 = "011" : eor compare (compare w/r data with compare register) lg2-0 = "100": read data correspond lg2-0 = "101": read data not correspond lg2-0 = "110": write data correspond lg2-0 = "111": write data not correspond wrte data mask (wm15-0) gram
HD66773R rev.1.10, jun.21.20 03, page 38 of 133 display control 1 (r07h) pt1-0: specify the kind of source output when non-displa y area is driven in the partial display mode. for details, see ?screen-split drive function?. vle2?1: when vle1 = 1, the first screen is scrolled in th e vertical direction. when vle2 = 1, the second screen is scrolled in the vertical direction. the fi rst and second screens cannot be scrolled simultaneously. this function is not available with external display interface mode. vle bits vle2 vle1 image on 2nd screen image on 1st screen 0 0 stationary stationary 0 1 stationary scrolled 1 0 scrolled stationary 1 1 setting disabled setting disabled cl: when cl = 1, 8-color display mode is selected. for details, see ?8-color display mode?. cl bit cl colors 0 65,536 1 8 spt: when spt = 1, liquid crystal is driven with 2 split screens. for details, see ?screen split drive function?. r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 0 0 vle1 pt1 0 spt 0 0 gon pt0 vle2 dte cl rev d1 d0
HD66773R rev.1.10, jun.21.20 03, page 39 of 133 rev: when rev = 1, a reverse display is shown. i nverting the grayscale levels allows the display of same data on both normally white and normally black panels. the source output level is as follows. combination with partial display source output level non-display area display area pt1-0 = (0.*) pt1-0= (1.0) pt1-0 = (1.1) rev gram data vcom =?l? vcom =?h? vcom=?l? vcom=?h? vc om =?l? vcom =?h? vcom =?l? vcom =?h? 0 16?h0000 16?hffff v31 v0 v0 v31 v31 v0 gnd gnd hi-z hi-z 1 16?h0000 16?hffff v0 v31 v31 v0 v31 v0 gnd gnd hi-z hi-z combination with d1-0 bits source output level d1-0 = (1.1) d1-0 = (1.0) d1-0 = (0.1) d1-0 = (0.0) rev gram data vcom =?l? vcom =?h? vcom =?l? vcom =?h? vcom =?l? vcom =?h? vcom =?l? vcom =?h? 0 16?h0000 16?hffff v31 v0 v0 v31 v31 v0 gnd gnd gnd gnd 1 16?h0000 16?hffff v0 v31 v31 v0 v31 v0 gnd gnd gnd gnd gon: when gon = 0, the gate-off level is vgh. d1?0: the graphics display is on when d1 = 1, and off when d1 = 0. when setting d1 = 0, the data are retained in gram. this means the graphics is instantly redisplayed when setting d1 to 1. when d1 is 0 (i.e., the display is off) all the source outputs are set to the gnd level. this reduces the charged/discharged current during liquid crystal ac drive. when d1-0 = 01, the HD66773R continues internal display operation, even while the external display is off. when d1-0 = 00, both internal and external display operation are halted. in combination with gon and dte bits, d1-0 bits cont rol on/off of display. for details, see ?instruction setting flow?.
HD66773R rev.1.10, jun.21.20 03, page 40 of 133 gon dte d1 d0 HD66773R internal display operation source output gate output 0 0 00halt gnd vgh 0 0 0 1 operate gnd vgh 1 0 0 1 operate gnd vgoff 1 0 1 1 operate grayscale level output vgoff 1 1 1 1 operate grayscale level output gate selective line: vgh, gate non-selective line: vgoff note 1) gram write operation from the microc omputer is irrelevant to the setting in d1?0. note 2) in the standby mode, d1?0 = ?00. the setting in the register d1?0 is retained. frame cycle control (r0bh) rtn3-0: set the 1h (1 raster-row) period. rtn bits and clock cycles rtn3 rtn2 rtn1 rtn0 clock cycles per raster-row 0 0 0 0 16 clocks 0 0 0 1 17 clocks 0 0 1 0 18 clocks :: 1 1 1 0 30 clocks 1 1 1 1 31 clocks r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 no1 0 0 0 0 rtn1 rtn0 no0 sdt1 sdt0 e q 1e q 0 div1 div0 rtn3 rtn2
HD66773R rev.1.10, jun.21.20 03, page 41 of 133 div1-0: set the division ratio of clocks for internal operations (div1-0). in ternal operations are in synchronization with the clock, the frequency of which is divided according to the div1-0 setting. when changing the number of drive rast er-rows, adjust the frame frequency too. for details, see ?frame frequency adjustment function?. div1 div0 division ratio internal operating clock frequency 0 0 1 fosc / 1 0 1 2 fosc / 2 1 0 4 fosc / 4 1 1 8 fosc / 8 fosc = r-c oscillation frequency formula for the frame frequency fosc frame frequency [hz] clock cycles per raster-row division ratio (line + 8) fosc: r-c oscillation frequency line: number of drive raster-rows (nl bit) division ratio: div bit clock cycles per raster-row: rtn bit eq1-0: set the period for equalization, where vcom output becomes hi-z. eq1 eq0 equalizing period 0 0 not equalized 0 1 1 clock 1 0 2 clocks 1 1 3 clocks note) equalizing is valid while vcoml is 0v or more. otherwise, set eq = ?00?
HD66773R rev.1.10, jun.21.20 03, page 42 of 133 sdt1-0: determine the amount of delay for the source out put from the falling edge of the gate output. sdt1 sdt0 delay time for source signal 0 0 1 clock 0 1 2 clocks 1 0 3 clocks 1 1 4 clocks 1h perio d 1h perio d delay amount of the source output gn sn equalizing per iod eq no1-0: specify the amount of non-overlap time for the gate output. no1 no0 non-overlap time 0 0 0 clock 0 1 4 clocks 1 0 6 clocks 1 1 8 clocks 1h perio d 1h perio d non-overlap per iod gn gn+1
HD66773R rev.1.10, jun.21.20 03, page 43 of 133 gate scan position (r0fh) scn4-0: specify the position where the gate scan starts. scan start position scn4 scn3 scn2 scn1 scn0 gs = 0 gs = 1 00000g1 g176 00001g9 g168 00010g17 g160 . . . . . . . . . . . . . . 10100g161 g17 10101g169 g9 g1 g176 g17 g1 g176 g57 gs=0 nl=10011 scn4-0=00010 gs=0 nl=01110 scn4-0=00111 note: set nl so that the gate scan end position does not exceed g176. r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w1 0 0 0 0 000scn0 scn4 scn3 scn2 scn1 00 00
HD66773R rev.1.10, jun.21.20 03, page 44 of 133 vertical scroll control (r11h) vl7?0: specify the number of raster-rows to be scrolled and control smooth scrolling in the vertical direction. the number of raster-rows is specified between 0 to 176, the raster-rows of the specified number are scrolled during display. when the 176th raster-row is displayed, th e scrolling display starts afresh from the 1st raster-row. the number of raster-rows to be scrolled (vl7?0) can be speci fied when the first screen vertical scroll enable bit vle1 = 1 or the second scre en vertical scroll enable bit vle2 = 1. the number of raster-rows is fixed (not changeable) when vle2-1 = 00. vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 amount of scrolling (number of raster-row) 000000000 raste r-row 000000011 raste r-row 000000102 raste r-rows . . . . . . . . . . . . . . . . . . 11101110 174 raster-rows 11101111 175 raster-rows note: when setting the number of raster-rows fo r scrolling, it must be 175 (?af?h) or less. 1st-screen drive position (r14h) 2nd-screen drive position (r15h) ss17?10: specify the start position for driving the first screen by line. the liquid crystal is driven by from the gate driver of ?the set value + 1?. se17?10: specify the end position for driving the first screen by line. the liquid crystal is driven by to the gate driver of ?the set value + 1?. for instance, when ss17?10 = ?07?h and se17?10 = ?10?h, the liquid crystal is driven from g8 to g17, and black display is driven from g1 to g7, and g18 thereafter. make sure that ss17?10 se17?10 ?af?h. for details, see ?screen-split drive function?. ss27?20: specify the start position for driving the second sc reen by line. the liqui d crystal is driven by from the gate driver of ?the set value + 1?. the second screen is driven when spt = 1. r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w1 0 0 0 0 0 vl7 00 0 vl6 vl5 vl4 vl3 vl2 vl1 vl0 r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w1 w1 se17 se16 se15 se14 se13 se12 se11 se10 s s 17 s s 16 s s 15 ss14 s s 13 s s 12 s s 11 s s 10 s s 27 s s 26 s s 25 s s 24 s s 23 s s 22 ss21 s s 20 se27 se26 se25 se24 se23 se22 se21 se20
HD66773R rev.1.10, jun.21.20 03, page 45 of 133 se27?20: specify the end position for driving the second scre en by line. the liquid crystal is driven by to the gate driver of ?the set value + 1?. for instance, when spt = 1, and ss27?20 = ?20?h, se27?20 = ?4f?h, the liquid crystal is driven from 33 to g80. make sure that ss17?10 se17?10 < ss27?20 se27?20 ?aef?h. for details, see ?screen-split drive function?. horizontal ram address position (r16h) vertical ram address position (r17h) hsa7-0/hea7-0: specify the start/end positions of the window-address range by address in the horizontal direction. data are written to gram within the area determined by the addresses specified by hea7-0 and hsa7-0. these addresses must be set before ram write. in setting these bits, make sure that ?00?h hsa7-0 hea7-0 ?83?h. vsa7-0/vea7-0: specify the start/end positions of the win dow-address range by address in the vertical direction. data are written to gram within the area determined by the addresses specified by vea7-0 and vsa7-0. these addresses must be set before ram write. in setting these bits, make sure that ?00?h vsa7-0 vea7-0 ?af?h. n ote 1) the window address area should be set within the gram address space. n ote 2) in the high speed write mode, data are written to gram every 4 word. some window address setting may require insurtion of dummy write. see "high speed burst ram write". n ote 3) the address set must be within the window address area. in the high speed write mode, set within the area including dummy write area. hsa hea "00"h ? vsa7-0 ? vea7-0 ? "af"h "00"h ? hsa7-0 ? hea7-0 ? "83"h vsa vea 0000h a f83h gram address space window address setting range window address r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w1 w1 hea7 hea6 hea5 hea4 hea3 hea2 hea1 hea0 hsa7 hsa6 hsa5 hsa4 hsa3 hsa2 hsa1 hsa0 vea7 vea6 vea5 vea4 vea3 vea2 vea1 vea0 vsa7 vsa6 vsa5 vsa4 vsa3 vsa2 vsa1 vsa0
HD66773R rev.1.10, jun.21.20 03, page 46 of 133 ram write data mask (r20h) wm15?0: write-mask the data when written to gram by bit. the write-mask function is available with 8/16-bit interface modes. for example, if wm15 = 1, the data in wd15 bit is write-masked so that it is not written to gram. the rest of wm14-0 bits also write -mask the data in the corresponding wd bits when these bits are set to ?1?. for deta ils, see ?graphics operation function?. ram address set (r21h) ad15?0: make a gram address initial setting in the addr ess counter (ac). afte r gram data are written, the address counter is auto matically updated according to the settings with am, i/d bits and the setting for a new gram address is not required in the address counter. therefore, data are written consecutively without resetting the address. the address counter is not automatically updated when data are read out from gram. gram address setting can not be made during the standby mode. an address set should be made within the area specified with the window address. gram address range ad15?ad0 gram setting ?0000?h ? ?0083?h bitmap data for g1 ?0100?h ? ?0183?h bitmap data for g2 ?0200?h ? ?0283?h bitmap data for g3 ?0300?h ? ?0383?h bitmap data for g4 : : ?ac00?h ? ?ac83?h bitmap data for g173 ?ad00?h ? ?ad83?h bitmap data for g174 ?ae00?h ? ?ae83?h bitmap data for g175 ?af00?h ? ?af83?h bitmap data for g176 r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w1 wm 15 wm 14 wm 7 wm 6 wm 13 wm 12 wm 11 wm 10 wm 9 wm 8 wm 5 wm 4 wm 3 wm 2 wm 1 wm 0 r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w 1 ad 0 ad 15 ad 14 ad 13 ad 12 ad 11 ad 10 ad 9 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 ad 1 ad 8
HD66773R rev.1.10, jun.21.20 03, page 47 of 133 write data to gram (r22h) wd17?0: all data are expanded into 18 bits internally before being wr itten to gram. each interface has its own way of expanding data to 18 bits. the grayscale level is selected according to gram data. the address is automatically updated according to the setting with the am and i/d bits after data are written to gram. during the standby mode, no access is allowed to gram. when the 9 or 18 bit inte rface mode is selected, set dit = ?1? to activate the internal hardware-dither circuit before writing to gram. n ote: write data into gam after setting dit = ?1 ?. hd 17 hd 16 hd 15 hd 14 hd 13 hd 12 hd 11 hd 10 hd 9 hd 8 hd 7 hd 6 hd 5 hd 4 hd 2 hd 1 hd 0 hd 3 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 wd 15 dither process circuit i nput pin r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b0 b4 b2 b1 b3 rgb assignment gram write data 18-bit interface wd 14 wd 13 wd 12 wd 11 wd 10 wd 9 wd 8 wd 7 wd 6 wd 5 wd 4 wd 3 wd 2 wd 1 wd 0 shrinking shri nking 1 pixel 262,144 colors available r/w rs w 1 wd 15 ram write data (wd17-0) the pin assignment for db17-0 varies for each interface (see below). when rgb-i/f wd 14 wd 13 wd 12 wd 11 wd 10 wd 9 wd 8 wd 7 wd 6 wd 5 wd 4 wd 3 wd 2 wd 1 wd 0 wd 17 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pd17 pd16 wd 16
HD66773R rev.1.10, jun.21.20 03, page 48 of 133 wd 15 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 gram write data input pin rgb assignment r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b0 b4 b2 b1 b3 1 pixel wd 14 wd 13 wd 12 wd 11 wd 10 wd 9 wd 8 wd 7 wd 6 wd 5 wd 4 wd 3 wd 2 wd 1 wd 0 hd 17 hd 16 hd 15 hd 14 hd 13 hd 12 hd 11 hd 10 hd 9 hd 8 hd 7 hd 6 hd 5 hd 4 hd 2 hd 1 hd 0 hd 3 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 wd 15 dither process circuit i nput pin r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b0 b4 b2 b1 b3 rgb assignment gram write data wd 14 wd 13 wd 12 wd 11 wd 10 wd 9 wd 8 wd 7 wd 6 wd 5 wd 4 wd 3 wd 2 wd 1 wd 0 shr inking shr i nking 1 pixel wd 15 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 10 db 17 db 16 db 15 db 14 db 13 db 12 db 11 gram write data input pin rgb assignment r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b0 b4 b2 b1 b3 1 pixel wd 14 wd 13 wd 12 wd 11 wd 10 wd 9 wd 8 wd 7 wd 6 wd 5 wd 4 wd 3 wd 2 wd 1 wd 0 9-bit interface 262,144 colors available first transfer (upper) second transfer (lower) db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 16-bit interface 65,536 colors available 8-bit interface 65,536 colors available note :write data to gram after setting dit = "1". first transfer (upper) second transfer (lower)
HD66773R rev.1.10, jun.21.20 03, page 49 of 133 gram data and liquid crystal output level 000000 00000 000001 000010 00001 000011 000100 00010 000101 000110 00011 000111 001000 00100 001001 00101 001010 001011 00110 001100 001101 00111 001110 00 1111 v0 v1 v2 v3 v4 v5 v6 v7 v31 v30 v29 v2 8 v27 v26 v25 v24 - - - - - - - - v31 - v30 v0 ? v1 v29 ? v28 v2 ? v3 v28 ? v27 v3 ? v4 v26 ? v25 v5 ? v6 v25 ? v24 v6 ? v7 v24 ? v23 v7 ? v8 v30 ? v29 v1 ?v2 v27 ? v26 v4 ? v5 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 0 11111 v8 v9 v10 v11 v12 v13 v14 v15 v23 v22 v21 v2 0 v19 v18 v17 v16 v23 ? v22 v8 ? v9 v21 ? v20 v10 ? v11 v20 ? v19 v11 ? v12 v18 ? v17 v13 ? v14 v17 ? v16 v14 ? v15 v16 ? v15 v15 ? v16 v22 ? v21 v9 ?v10 v19 ? v18 v12 ? v13 01000 01001 01010 01011 01100 01101 01110 01111 - - - - - - - - 10000 10001 10010 10011 10100 10101 10110 10111 - - - - - - - - 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 selected grayscale v16 v17 v18 v19 v20 v21 v22 v23 v15 v14 v13 v 12 v11 v10 v9 v8 v15 ? v14 v16 ? v17 v13 ? v12 v18 ? v19 v12 ? v11 v19 ? v20 v10 ? v9 v21 ? v22 v9 ? v8 v22 ? v23 v8 ? v7 v23 ? v24 v14 ? v13 v17 ?v18 v11 ? v10 v20 ? v21 11000 11001 11010 11011 11100 11101 11110 11111 - - - - - - - gram data setting 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 v24 v25 v26 v27 v28 v29 v30 v31 v7 v6 v5 v4 v3 v2 v1 v0 v7 ? v6 v24 ? v25 v5 ? v4 v26 ? v27 v4 ? v3 v27 ? v28 v2 ? v1 v29 ? v30 v1 ? v0 v30 ? v31 v0 v31 v6 ? v5 v25 ?v26 v3 ? v2 v28 ? v29 - selected grayscale gram data setting g r/b negative positive g r/b negative positive selected grayscale gram data setting selected grayscale gram data setting g r/b negative positive g r/b negative positive
HD66773R rev.1.10, jun.21.20 03, page 50 of 133 read data from gram (r22h) rd15?0: read 16-bit data from gram. the bit assignment for the data to be read out from gram is different according to the interface. when data are read out from gram to the microc omputer, the first word re ad immediately after gram address set are latched in the intern al read-data latch, and the data in the data bus (db17?0) are nullified. the second word is read as a valid data. when the HD66773R performs an internal bit processing, such as logical operation, it uses the data latched in the read-data latch, and completes it by single read out operation. the data are expanded internally into 18 bits before going through the logical operation. gram data read and logical operation are available w ith 8-/16-bit interface mode. if 9-/18-bit interface modes are selected, this function is not available. out p ut p in rd 15 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 read data gram data r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b0 b4 b2 b1 b3 rd 14 rd 13 rd 12 rd 11 rd 10 rd 9 rd 8 rd 7 rd 6 rd 5 rd 4 rd 3 rd 2 rd 1 rd 0 16-bit interface 8-bit interface / interface spi rd 15 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 read data gram data out p ut p ins r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b0 b4 b2 b1 b3 rd 14 rd 13 rd 12 rd 11 rd 10 rd 9 rd 8 rd 7 rd 6 rd 5 rd 4 rd 3 rd 2 rd 1 rd 0 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 first transfer (upper) second transfer (lower) 1 pixel r/w rs r 1 ram read data (rd17-0) the pin assignment fo r db17-0 varies for eac h interface (see below).
HD66773R rev.1.10, jun.21.20 03, page 51 of 133 gram read sequence a ddress: n set first word second word i) read data to microcomputer a ddress: n set ii) logical arithmetic operation inside HD66773R automatic address update: n+ a ddress: m set set i/d, am, hsa/hse, vsa/vea bits read (data in address "n") read data latch => db17-10 db8-1 dummy read (invalid data) gram => read data latch read (data in address "m") read data latch => db17-10 db8-1 dummy read (invalid data) gram => read data latch write (data in address "n") db17-10 => gram db8-1 dummy read (invalid data) gram => read data latch write (data in address "n") db17-10 => gram db8-1 dummy read (invalid data) gram => read data latch set i/d, am, hsa/hse, vsa/vea bits first word second word first word second word first word second word
HD66773R rev.1.10, jun.21.20 03, page 52 of 133 gamma control (r 30h to r3bh) table 29 w1 r/w rs ib7 ib0 ib6 ib5 ib4 ib3 ib2 ib1 ib8 ib9 ib10 ib11 ib12 ib13 ib14 ib15 00 00 w1 00 00 w1 00 00 w1 00 00 r30 r31 r32 r33 w1 00 00 w1 00 00 w 1 00 00 w1 00 00 r34 r35 r36 r37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pkp 00 pkp 01 pkp 02 r3a w1 000 0000 r3b w1 000 0000 vrp 14 vrp 13 vrp 12 vrp 11 vrp 10 vrp 03 vrp 02 vrp 01 vrp 00 vrn 14 vrn 13 vrn 12 vrn 11 vrn 10 vrn 03 vrn 02 vrn 01 vrn 00 pkp 10 pkp 11 pkp 12 pkp 20 pkp 21 pkp 22 pkp 40 pkp 41 pkp 42 pkp 30 pkp 31 pkp 32 pkp 50 pkp 51 pkp 52 prp 00 prp 01 prp 02 prp 10 prp 11 prp 12 pkn 10 pkn 11 pkn 12 pkn 00 pkn 01 pkn 02 pkn 20 pkn 21 pkn 22 pkn 30 pkn 31 pkn 32 pkn 50 pkn 51 pkn 52 pkn 40 pkn 41 pkn 42 prn 00 prn 01 prn 40 prn 41 prn 02 prn 42 pkp52?00: gamma fine adjustment register for the positive polarity output prp12-00: gradient adjustment register for the positive polarity output vrp14-00: amplitude adjustment register for the positive polarity output pkn52-00: gamma fine adjustment register for the negative polarity output prn12-00: gradient adjustment register for the negative polarity output vrn14-00: amplitude adjustment register for the negative polarity output. for details, see ?gamma adjustment function?.
HD66773R rev.1.10, jun.21.20 03, page 53 of 133 instruction list note1) ?*? is ?don?t care?. note2) high-speed write mode is available only with ram write. r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 rindex 00******** sr status read 1 0 l7 l6 l5 l4 l3 l2 l1 l0 oscillation start 0 1 * * * * * * * * device code read 1 1 0 0 0 0 0 1 1 1 r01h driver output control 0 1 0 0 0 0 0 sm gs ss r02h lcd drive ac control 0 1 0 0 0 0 fld1 fld0 b/c eor r03h power control (1) 0 1 0 0 0 0 0 bt2 bt1 bt0 r04h power control (2) 0 1 cad 0 0 0 0 0 0 0 r05h entry mode 0 1 dit 0 0 bgr 0 0 hwm 0 r06h compare register 0 1 cp15 cp14 cp13 cp12 cp11 cp10 cp9 cp8 r07h display control 0 1 0 0 0 pt1 pt0 vle2 vle1 spt r0bh frame cycle control 0 1 no1 no0 sdt1 sdt0 eq1 eq0 div1 div0 r0ch power control (3) 0 1 0 0 0 0 0 0 0 0 r0dh power control (4) 0 1 0 0 0 0 vrl3 vrl2 vrl1 vrl0 r0eh power control (5) 0 1 0 0 vcomg vdv4 vdv3 vdv2 vdv1 vdv0 r0fh gate scan starting position 0 1 0 0 0 0 0 0 0 0 r11h vertical scroll control 0 1 0 0 0 0 0 0 0 0 r14h first display drive position 0 1 se17 se16 se15 se14 se13 se12 se11 se10 r15h second display drive position 0 1 se27 se26 se25 se24 se23 se22 se21 se20 r16h horizontal ram address position 0 1 hea7 hea6 hea5 hea4 hea3 hea2 hea1 hea0 r17h vertical ram address position 0 1 vea7 vea6 vea5 vea4 vea3 vea2 vea1 vea0 r20h ram write data mask 0 1 wm15 wm14 wm13 wm12 wm11 wm10 wm9 wm8 r21h ram address set 0 1 ram data write 0 1 ram data read 1 1 r30h control (1) 0 1 0 0 0 0 0 pkp12 pkp11 pkp10 r31h control (2) 0 1 0 0 0 0 0 pkp32 pkp31 pkp30 r32h :w control (3) 0 1 0 0 0 0 0 pkp52 pkp51 pkp50 r33h :w control (4) 0 1 0 0 0 0 0 prp12 prp11 prp10 r34h :w control (5) 0 1 0 0 0 0 0 pkn12 pkn11 pkn10 r35h :w control (6) 0 1 0 0 0 0 0 pkn32 pkn31 pkn30 r36h :w control (7) 0 1 0 0 0 0 0 pkn52 pkn51 pkn50 r37h :w control (8) 0 1 0 0 0 0 0 prn12 prn11 prn10 r3ah :w control (9) 0 1 0 0 0 vrp14 vrp13 prp 1 2 vrp11 vrp10 r3bh :w control (10) 0 1 0 0 0 vrn14 vrn13 vrn 1 2 vrn11 vrn10 write data (upper) read data (upper) r22h r00h reg is t e r no. upper code register ad15-8 (uppe r) instructions ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 * id6 id5 id4 id3 id2 id1 id0 set index register values. 0000 0 0 0 0 read out drive line position (l7-0). **** * * * 1 start oscillation diring standby. 0111 0 0 1 1 0 0 0 nl4 nl3 nl2 nl1 nl0 0 0 nw5 nw4 nw3 nw2 nw1 nw0 dc2 dc1 dc0 ap2 ap1 ap0 slp stb 0000 0 0 0 00i/d1i/d0amlg2lg1lg0 set logical operation (lg2-0), ac counter mode (am), increment/decrement (i/d1-0), high-speed write mode (hwm), bgr mode, hard-dither mode(dit). cp7 cp6 cp5 cp4 cp3 cp2 cp1 cp0 0 0 gon dte cl rev d1 d0 set disply on (di1-0), reverse display (rev), display colors (cl), disptmg enable (dte), gate output on (gon), screen split control (spt), vertical scroll (vle2-1), and source output state (pt1-0). 0 0 0 0 rtn3 rtn2 rtn1 rtn0 0 0 0 0 0 vc2 vc1 vc0 0 0 0 pon vrh3 vrh2 vrh1 vrh0 start operation of step-up circuit 3 (pon), specify the amplifying scale of vregout1 voltage (vrh3-0), and amplifying scale of vregout2 voltage (vrl3-0). 0 0 0 vcm4 vcm3 vcm2 vcm1 vcm0 set the scan start position of gate driver (scn4-0). 0 0 0 scn4 scn3 scn2 scn1 scn0 vl7vl6vl5vl4vl3vl2vl1vl0 set the screen scroll amount (vl7-0). ss17 ss16 ss15 ss14 ss13 ss12 ss11 ss10 ss27 ss26 ss25 ss24 ss23 ss22 ss21 ss20 hsa7 hsa6 hsa5 hsa4 hsa3 hsa2 hsa1 hsa0 vsa7 vsa6 vsa5 vsa4 vsa3 vsa2 vsa1 vsa0 wm7 wm6 wm5 wm4 wm3 wm2 wm1 wm0 set write data mask (wm15-0) for ram write. initialize address counter with ram address. write data to ram. read data to ram. 0 0 0 0 0 pkp02 pkp01 pkp00 gamma control. 0 0 0 0 0 pkp22 pkp21 pkp20 gamma control. 0 0 0 0 0 pkp42 pkp41 pkp40 gamma control. 0000 0prp02prp01prp00 gamma control. 0000 0pkn02pkn01pkn00 gamma control. 0000 0pkn22pkn21pkn20 gamma control. 0000 0pkn42pkn41pkn40 gamma control. 0 0 0 0 0 prn02 prn01 prn00 gamma control. 0 0 0 0 vrp03 vrp02 vrp01 vrp00 gamma control. 0 0 0 0 vrn03 vrn02 vrn01 vrn00 gamma control. write data (lower) read data (lower) lower code ad7-0 (lower ) read out "0773h". set the gate driver shift direction (gs), source drive shift direction (ss), and the position of drive line(nl4-0). set liquid crystal drive ac waveform (b/c), the number of fields in interlaced drive (fld1-0), the eor output (eor) during c-pattern ac drive, and the number of lines for ac drive "n" (nw5-0). set tandby mode (stb), lcd power supply on (ap2-0), sleep mode (slp), step-up cycle (dc2-0), and step-up output scale (bt3-0). set the structure of holding capacity (cad). set compare registers (cp15-0). set 1h period (rtn3-0), operational clock division ratio (div1-0), equalize period (eq1-0), source output delay (sdt1-0), and gete output non-overlap (no1-0). set the vci adjustment factor (vc2-0). set the vcom h voltage (vcm4-0), the amplitude of vgoff ac (vdv4-0), and the vcom voltage (vcomg). set the start /end positions (ss17-10, se17-10) of the first screen drive. set the start /end positions (ss27-20, se27-20) of the second screen drive. ram address start/end positions (hsa7-0, hea7-0) in holizontal direction. ram address start/end positions (vsa7-0, vea7-0) in vertical direction.
HD66773R rev.1.10, jun.21.20 03, page 54 of 133 reset function the HD66773R makes internal initial settings with reset input. during the reset, the HD66773R is in a busy state, and no instructions from the mpu and access to gram are accepted. the time required for the reset input is at least 1ms. in case of power-on reset, wait at least 10ms after the power is turned on until the r-c oscillation frequency becomes stabilized. while waiting, do not make initial settings for the instruction set, nor access to gram. initial state of instructions a. start oscillation b. driver output control (nl4?0 = ?10101?, ss = ?0?, cs = ?0?) c. liquid crystal ac drive control (fld1-0 = ?01?, b/c = ?0?, eor = ?0?, nw5?0 = ?00000?) d. power control 1 (bt2-0 = ?000?, dc2?0 = ?000?, ap2?0 = ?000?: liquid crystal power supply off, slp = ?0?, stb = ?0? : standby mode off) e. power control 2 (cad = ?0?) f. entry mode set (dit = ?0?, bgr = ?0?, hw m = ?0?, i/d1-0 = ?11?: increment by 1, am = ?0?: horizontal directi on, lg2?0 = ?000?: replace mode) g. compare register (cp15?0 : ?0000 0000 0000 0000?) h. display control (pt1-0 = ?00?, vle2-1 = ?00?: no vertical scroll, spt = ?0?, gon = ?0?, dte = ?0?, cl = ?0?: 262,144 colors, rev = ?0?, d1-0 = ?00?: display off) i. power control 3 (vc2-0 = ?000?) j. power control 4 (vrl3-0 = ?0000?, pon = ?0?, vrh3-0 = ?0000?) k. power control 5 (vdv4-0 = ?00000?, vcomg = ?0?, vcm4-0 = ?00000?) l. frame cycle control (no1-0 = ?00?, sdt1-0 = ?00?, eq1-0 = ?00? : no equalization, div1-0 = ?00?: clock/1, rtn3-0 = ?0000? : 16 clocks in 1h period) m. gate scan starting position (scn4-0 = ?00000?) n. vertical scroll (vl7?0 = ?00000000?) o. 1st split-screen (se17-10 = ?1 1111111?, ss17-10 = ?00000000?) p. 2nd split-screen (se27-20 = ?11111111?, ss27-20 = ?00000000?) q. horizontal ram address position (hea7- 0 = ?10000011?, hsa7-0 = ?00000000?) r. vertical ram address position (vea 7-0 = ?10101111?, vsa7-0 = ?00000000?) s. ram write data mask (wm15?0 = ?0000?h: no mask) t. ram address set (ad15?0 = ?0000?h) u. control (pkp02-00 = ?000?, pkp12-10 = ?000?, pkp22-20 = ?000?, pkp32-30 = ?000?, pkp42-40 = ?000?, pkp52-50 = ?000?, prp02-00 = ?000?, prp12-10 = ?000?) (pkn02-00 = ?000?, pkn12-10 = ?000?, pkn22-20 = ?000?, pkn32-30 = ?000?, pkn42-40 = ?000?, pkn52-50 = ?000?, prn02-00 = ?000?, prn12-10 = ?000?) (vrp14-10 = ?00000?, vrp0 3-00 = ?0000?, vrn14-10 = ?00000?, vrn12-10 = ?000?) gram data initialization the data in gram are not initialized with the reset input. initialize through software during the display off (d1?0 = ?00?).
HD66773R rev.1.10, jun.21.20 03, page 55 of 133 initial state of output pin a. liquid crystal driver output pins (source outputs): output gnd level liquid crystal driver output pins (gate outputs): output vgh level b. oscillator output pin (osc2): output oscillation signal
HD66773R rev.1.10, jun.21.20 03, page 56 of 133 system interface a system interface is selected among the following interfaces with the im3-0 pin setting. the system interface enables instruction setting and ram access. im3 im2 im1 im0 mpu-interface mode db pin 0000 68-system 16-bit interface db17 to 10, 8-to-1 0001 68-system 8-bit interface db17 to 10 0010 80-system 16-bit interface db17 to 10, 8-to-1 0011 80-system 8-bit interface db17 to 10 010* serial peripheral inte rface (spi) db1 to 0 011* setting inhibited ? 1000 68-system 18-bit interface db17-0 1001 68-system 9-bit interface db17-9 1010 80-system 18-bit interface db17-0 1011 80-system 9-bit interface db17-9 11* * setting inhibited ?
HD66773R rev.1.10, jun.21.20 03, page 57 of 133 18-bit interface 68-system 18-bit parallel data transmission becomes operable by setting im3/2/1/0 pins to vcc/gnd/gnd/gnd levels respectively. 80-system 18-bit parallel data transmission becomes operable by setting im3/2/1/0 pins to vcc/gnd/vcc/gnd levels respectively. the data transfer through 18-bit mode is effective only for write mode , and not effective for read operation. csn* a 1 hwr* (rd*) d31 - 0 cs* rs wr* (rd*) db17 - 10 mpu hd667 73r 18 data format for 18-bit bus interface hd 15 hd 14 hd 13 hd 12 hd 11 hd 10 hd 9 hd 8 hd 7 hd 6 hd 5 hd 4 hd 2 hd 1 hd 0 hd 3 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 dither process circuit input gram write data r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b0 b4 b2 b1 b3 1 pixel instru ction code ib 15 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 instruction input ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 db 0 instruction ram data write db 9 ib 8 hd 17 hd 16 db 0 db 9 shrinking shri nking 18-bit bus interface note: 262,144 colocs available with 18-bit system interface by setting dit bit to "1".
HD66773R rev.1.10, jun.21.20 03, page 58 of 133 16-bit interface 68-system 16-bit parallel data transmission becomes operable by setting im3/2/1/0 pins to gnd/gnd/gnd/gnd levels respectively. 80-system 16-bit parallel data transmission becomes operable by setting im3/2/1/0 pins to gnd/gnd/vcc/gnd levels respectively. instruction code ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 ib 15 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 instruction input ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 note: 65,536-color real display with 16-bit system interface. do not set dit bit to "1". wd 15 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 gram write data input r,g,b assignme nt r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b0 b4 b2 b1 b3 1 pixel wd 14 wd 13 wd 12 wd 11 wd 10 wd 9 wd 8 wd 7 wd 6 wd 5 wd 4 wd 3 wd 2 wd 1 wd 0 instruction ram data write csn* a 1 hwr* (rd*) d15 - 0 cs* rs wr* (rd*) db17 ? 10, 8-1 h8/2245 hd667 73r 16 db9, 0 gnd data format for 16-bit interface 16-bit interface
HD66773R rev.1.10, jun.21.20 03, page 59 of 133 9-bit interface 68-system 9-bit parallel data transmission becomes operable by setting im3/2/1/0 pins to vcc/gnd/gnd/vcc levels respectively throughdb17-9 pi ns. 80-system 9-bit parallel data transmission becomes operable by setting im3/2/1/0 pins to vcc/gnd/vcc/vcc levels respectively throughdb17-9 pins. the 16-bit instruction is divided into 2 8-bit data and upper 8-bit data is transferred first. the lsb is not used for each upper/lower-bit data transfer. the 18-bit ram data is also divided into 2 9-bit data and upper 9-bit data is transferred first. the unused pins db8-0 must be fixed to either ?vcc? or ?gnd?. the upper-byte write is also required when writing index registers. the data transfer through 9-bit mode is effective only for write mode, and not effective for read operation. csn* a 1 hwr* (rd*) d15 - 0 cs* rs wr* (rd*) db17 ? 9 db8-0 h8/2245 hd667 73r 9 gnd instruction instru ction code ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 ib 15 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 instruction input ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 data format for 9-bit bus interface db 9 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 first transfer (upper) second transfer (lower) ram data wr ite i nput r,g,b assignme nt r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b0 b4 b2 b1 b3 1 pixel dither process circuit hd 17 hd 16 hd 15 hd 14 hd 13 hd 12 hd 11 hd 10 hd 9 hd 7 hd 6 hd 5 hd 4 hd 3 hd 2 hd 1 hd 0 hd 8 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 db 9 first transfer (upper) second transfer (l ower) wd 15 wd 14 wd 13 wd 12 wd 11 wd 10 wd 9 wd 8 wd 7 wd 6 wd 5 wd 4 wd 3 wd 2 wd 1 wd 0 shrinking shri nking 9 note: 262,144 colocs available with 9-bit system interface by setting dit bit to "1". 9-bit bus interface
HD66773R rev.1.10, jun.21.20 03, page 60 of 133 data transmission synchronization in 9-bit bus interface mode the HD66773R supports the data transmission synchronizing function, which resets the upper/lower counter that counts the nu mber of transmission of upper/lower 9-b it data in the 9-bit bus interface mode. when a discrepancy occurs in the transmission of upper/lower 9-bit data due to effects from noise and so on, the ?00? h instruction is written 4 times consecutiv ely to forcibly reset the upper/lower counter so that data transmission restarts with an upper 9-bit transmission. periodical execution of the synchronization allows the system recovery from the excursion. db17 to db9 (1) (2) (3) (4) 9-bit transfer synchr onization rs rd wr "00"h "00"h "00"h "00"h upper low er upper or low er
HD66773R rev.1.10, jun.21.20 03, page 61 of 133 8-bit interface 68-system 8-bit parallel data transmission becomes operable by setting im3/2/1/0 pins to gnd/gnd/gnd/vcc levels respectively throughdb17-10 pins. 80-system 8-bit parallel data transmission becomes operable by setting im3/2/1/0 pins to gnd/gnd/vcc/vcc levels respectively throughdb17-10 pins. the 16-bit instruction is divided into 2 8-bit data and upper 8-bit data is transferred first. the lsb is not used for each upper/lower-bit data transfer. the 16-bit ram data is also divided into 2 8-bit data and upper 9-bit data is transferred first. the unused pins db9-0 must be fixed to either ?vcc? or ?gnd?. the upper-byte write is also required when writing index registers. csn* a 1 hwr* (rd*) d15 - 0 cs* rs wr* (rd*) db17 - 10 db9 - 0 h8/2245 hd66773 r 8 10 gnd data format for 8-bit bus interface instruction instru ction code ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 ib 15 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 instruction input ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 first transfer ( u pp er ) second transfer ( lowe r ) ram data wr ite wd 15 db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 gram write data input r,g,b assignme nt r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b0 b4 b2 b1 b3 wd 14 wd 13 wd 12 wd 11 wd 10 wd 9 wd 8 wd 7 wd 6 wd 5 wd 4 wd 3 wd 2 wd 1 wd 0 first transfer ( u pp er ) second transfer ( lowe r ) db 17 db 16 db 15 db 14 db 13 db 12 db 11 db 10 1 p ixel 8-bit bus interface note: 65,536-color real display with 8-bit system interface. do not set dit bit to "1".
HD66773R rev.1.10, jun.21.20 03, page 62 of 133 data transmission synchronization in 8-bit bus interface mode the HD66773R supports the data transmission synchronizing function, which resets the upper/lower counter that counts the nu mber of transmission of upper/lower 8-b it data in the 8-bit bus interface mode. when a discrepancy occurs in the transmission of upper/lower 8-bit data due to effects from noise and so on, the ?00? h instruction is written 4 times consecutiv ely to forcibly reset the upper/lower counter so that data transmission restarts with an upper 8-bit transmission. periodical execution of the synchronization allows the system recovery from the excursion. (1) (2) (3) ( 4) rs rd wr db17 to db10 "00"h "00"h "00"h "00"h upper low er upper or low er 8-bit transfer synchronization
HD66773R rev.1.10, jun.21.20 03, page 63 of 133 serial peripheral interface (spi) the serial peripheral interface (spi) becomes opera ble by setting im3/2/1 pi ns to gnd/vcc/gnd levels respectively. the spi is available through the chip select lin e (cs*), serial transfer clock line (scl), serial data input (sdi), and serial data output (sdo). in the spi mode, the im0/id pin functions as id pin. in the spi mode, the unused db15-2 pins must be fixed at either vcc or gnd level. the HD66773R recognizes the start of data transfer at the falling edge of cs* input to initiate the transfer of a start byte. it recognizes the end of data transf er at the rising edge of cs* input. the HD66773R is selected when the 6-bit chip address in the start byte transferred from the transmission device and the 6-bit device identification code assigned to the HD66773R are compared and the both 6-bit data correspond. when selected, the HD66773R starts taking in the subsequent data string. the setting for the least significant bit of the identification code is made with the id pin. the five upper bits of the identification code must be 01110. two different chip addresses must be assigned to the hd66789 because the seventh bit of the start byte is assigned to a register select b it (rs). when rs = 0, index register write or status read is executed. when rs = 1, instruction write or ram re ad/write is executed. the eighth bit of the start byte is to specify read or write (r/w bit). the data are received when the r/w bit is 0, and are transmitted when the r/w bit is 1. in the spi mode, the data are written to gram afte r the two-byte data transmission. the data are expanded into 18 bits by adding one bit (the same data as the msb of rb) next to the lsb of rb data. after receiving the start byte, th e HD66773R starts data transmissi on/reception by byte. the data transmission adopts the format which the msb is first transmitted. all HD66773R instructions consist of 16 bits and they are executed internally after two bytes are transmitted with the msb first (db15 to 0). the data to be written to ram are expanded into 18-b it data. after the start byte is received, the upper eight bits of the instruction are always fetched as the first byte, and the lower eight bits of the instruction are always fetched as the second byte. the 4-byte data that are read from ram right after the start byte are made invalid. the HD66773R reads as valid data from the 5th-byte data. start byte format transmitted bits s 1 2 3 4 5 6 7 8 start byte format transmission start device id code rs r/w 01110id note 1) id bit is select ed with the im0/id pin. rs and r/w bit function rs r/w function 0 0 set index register 0 1 read status 1 0 write instruction or ram data 1 1 read instruction or ram data
HD66773R rev.1.10, jun.21.20 03, page 64 of 133 instruction ram data write instruction input d15 instruction code ib 15 d14 d13 d12 d11 d10 d9 d8 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 d7 d6 d5 d4 d3 d2 d0 d1 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 input r4 r3 r2 r0 g4 g3 g2 g1 g0 b4 b2 b1 b0 b3 rgb pixel assignment one pixel 66,536 colors are available in clock synchronized serial interface. do not set dit = ?1?. d15 d14 d13 d12 d11 d10 d9 d8 wd 15 gram write data d7 d6 d5 d4 d3 d2 d0 d1 wd 14 wd 13 wd 12 wd 11 wd 10 wd 9 wd 8 wd 7 wd 6 wd 5 wd 4 wd 3 wd 2 wd 1 wd 0 1 st transfer (upper) 2 nd tr ansfer(lower) 1 st transfer (upper) 2 nd transfer(lower) data format for serial peripheral interface
HD66773R rev.1.10, jun.21.20 03, page 65 of 133 a ) timin g basic data transfer throu g h clock s y nchronized serial bus interface start byte index register setting, instruction, ram data wite scl (input) transfer start transfer en d sdi (inpu t) devise id code msb "0" lsb 1 2 3 4 5 6 7 8 9 10111213141516171819202122232 4 "1" "1" "1" "0" id rs r w db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 rs r w sdo (output) status read, instruction read, ram data read db 15 db 14 db 13 db 12 db 11 db 10 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 cs* (input) b) timing of consecutive data-transfer through clock-synchronized serial bus interface start by te instruction 1: execution time scl (input) 12345678 910111213141516 171819 instruction 1: upper eight bits instruction 1: lower eight bits 20 21 22 23 24 25 26 27 28 29 30 31 32 instruction 2: upper eigh t bits start end cs* (input) sdi (input) note: the first byte after the start byte is always the upper eight bits.
HD66773R rev.1.10, jun.21.20 03, page 66 of 133 d) status read / instruction read start byte rs = 0, r/w = 1 scl (input) start cs* (input) sdi (input) end sdo (output) dummy read 1 status read: upper 8 bits status read: lower 8 bits note: the one-byte data read after the start byte is invalid. the hd6677r starts to read the second-byte data as normal data. c) ram-data read-transfer timing note: the five-byte data following the start byte are read as invalid data. the HD66773R read the 6th-byte data as normal data. 73r start byte rs=1, r/w=1 start end dummy read 1 dummy read 2 dummy read 3 dummy read 4 dummy read 5 ram read: upper eight bits ram read: lower eight bits cs* (input) scl (input) sdi (input) sdo (output)
HD66773R rev.1.10, jun.21.20 03, page 67 of 133 high-speed burst ram write function the HD66773R incorporates the high-speed burst ram- write function, which writes data to ram in one- fourth the access time required for the standard ram-write operation. this function is especially useful for applications which require the high-speed rewrite of the display data such as display of colored moving picture and so on. in high-speed ram write mode (hwm), data to be written to ram is temporarily stored to the internal register of HD66773R. the data storage in the register is executed by word. when the data storage operation is executed 4 times, all the data stored in the register is written to ram at once. while the data is being written from the register to ram, another set of data is being written to the register. this function enables high-speed and consecutive ram write, which is required in displaying moving pictures and so on. register 1 register 2 register 3 regist er 4 gram 18 72 a ddress counter 9? a c 9? 16 microcomputer "0000"h "0001"h "0002"h "00 03"h register 1 register 2 register 3 regist er 4 gram address counter (ac) microcomputer "0000"h "0001"h "0002"h "0003"h a)operational flow of high-speed consecutive ram write
HD66773R rev.1.10, jun.21.20 03, page 68 of 133 the high-speed burst ram write function wirtes data to ram every 4 words. this means in the 8-bit interface mode, ram write is executed every 8 write operations to the internal register. c) example of high-speed consecutive ram write * set the lower two bits of the address as follows in the high-speed write mode. when id0 = ?0?, the low er two bits of the address must be set to ?11?. when id1 = ?0?, the lower two bits of the address must be set to ?00? . index 9? r22 9? wr (input) cs * (input) db17-10 ram address ( ac15-0 ) "0000" h "0004" ram data (5) - (8) ram write execution time 9? (input/ output) ram write data ( 64-bit ) ram write execution time ram data (1) - (4) ram data (1) upper ram data (1) low er ram data (2) upper ram data (2) low er ram data (3) upper ram data (3) low er ram data (4) upper ram data (4) low er ram data (1) upper ram data (1) low er ram data (2) upper ram data (2) low er ram data (3) upper ram data (3) low er ram data (4) upper ram data (4) lower 1234567 8 12345678 note: index 9? r22 9? wr (input) b) example of high-speed consecutive ram write cs* (input) db17-0 (input/output) ram data 1 ram data 1 to 4 ram write data (72 bits ) ram write execution time ram data 5 to 8 ram data 2 ram data 3 ram data 4 ram data 5 ram data 6 ram data 7 ram data 8 ram wite ex ecution time ram address (ac15-0) "0000 "h ram data 9 to 12 ram write ex ecution time* ram data 9 ram data 10 ram data 11 ram data 12 index 1 2341 2341 234 "0004"h "0008"h "000a"h note: w hen terminating high-speed ram write, wait until ram write execution is completed (tcyc: bus cycle time for nomal ram write before executing a next instruction. * set the lower two bits of the address as follows in the high-speed write mode. when id0 = ?0?, the lower two bits of the address must be set to ?11?. when id1 = ?0?, the lower two bits of the address must be set to ?00?.
HD66773R rev.1.10, jun.21.20 03, page 69 of 133 conditions on using high-speed ram write mode 1. the logical/compare operations are not available. 2. ram write operation is executed ev ery four words. set the lower 2 bits of the addresses as follows when setting addresses. *when id0=0, the lower two bits in the address must be set to 11 before ram write. *when id0=1, the lower two bits in the address must be set to 00 before ram write. 3. ram write operation is executed ev ery four words. if ram write operation is terminated before all four-word data is written to ram, the last data will not be written to ram. 4. when the index register is set to r22h (ram da ta write), the first ram write operation is always executed. in this case, the ram data read is not operable simultaneously. during ram read, set the hwm to 0. 5. the high-speed ram write mode is not compatible with the normal ram write mode. when the mode must be switched to the other, make a new address setting before starting ram write. 6. when writing data in high speed ram write mode within the range specified with the window address, some window-address range may require dummy write operation. see ?high-speed ram write with window address function?. comparison between normal and high-speed ram write operations normal ram write (hwm=0) high-speed ram write (hwm=1) logical operation available in 8-/ 16-bit interface not available compare operation available in 8- /16-bit interface not available bgr function available available write mask function available in 8-/16-bit interface available ram address set specified by one word id0 bit=0: set the lower two bits to 11 id0 bit=1: set the lower two bits to 00 ram read read by one word not available ram write write by one word some window-address range may require insertion of dummy write window address set by one word horizontal range(hsa/hse): 4 word or more number of horizontal writing : 4n (n>=2) am setting am = 1/0 am = 0
HD66773R rev.1.10, jun.21.20 03, page 70 of 133 high-speed ram write with window address to rewrite the data in an arbitrar y rectangular area of ram consecutiv ely in high speed, the number of ram access should be made 4 multiple times. ac cordingly some window-address range may require dummy write operation to make the ram access 4 multiple times. the horizontal window-address range specifying bits (hsa1-0, hea1-0) specify the number of dummy write operations executed at the start and end of th e data to be written to ram. the total ram access must be 4 multiple times per line. number of dummy write operations in high-speed ram write (hsa bits) hsa1 hsa0 number of dummy write operations to be inserted at the start of a row 00 0 01 1 10 2 times 11 3 times number of dummy write operations in high-speed ram write (hea bits) hea1 hea0 number of dummy write operations to be inserted at the end of a row 00 3 times 01 2 times 10 1 time 11 0
HD66773R rev.1.10, jun.21.20 03, page 71 of 133 the number of ram access when writing data in the horizontal direction must be made 4 n times by including the dummy writes. horizontal ram write = start dummy write + write data + end dummy write = 4 n (times) an example of ram write in high speed ram write mode with the window address is as follows. the ram data in the specified window-address rang e is written over consecutively in high speed by inserting two dummy writes at the start of the lin e and three dummy writes at the end of the line. h00 00 gram address map window address-range setting hsa=h12, hea=h30 vsa=h08, vea=ha0 set high-speed ram write mode hwm = 1 a ddress set a d = h0810 * see note dummy ram write x 2 ram write x 31 dummy ram write x 3 x 15 2 window address range (write-over area) window address-range setting hsa=h12, hea=h30 vsa=h08, vea=ha0 write in the horizontal direction a m = 0, id0 = 1 h0812 ha030 hefaf *note: set the lower two bits of the address as follows in the high-speed write mode. when id0 = ?0?, the lower two bits of the address must be set to ?11?. when id1 = ?0?, the lower two bits of the address must be set to ?00?. the ram-address range to be overwritten is limited to the area specified with the window address.
HD66773R rev.1.10, jun.21.20 03, page 72 of 133 window address function the window address function enables consecutive data write within the rectangular window-address area on the on-chip gram, which is specified with horizo ntal address registers (start: hsa7-0, end: hea 7-0) and vertical address registers (start: vsa7-0, end: vea7-0). the address transition direction is determined with am bits (either increment or decrement). accordingly, the data, including picture data, are written consecu tively without taking the data wrap position into consideration. the window-address range must be sp ecified within the gram address area. an address set must be set within the window-address range. [the condition of setting window-address range] (horizontal direction) ?00?h hsa7-0 hsa7-0 ?83?h (vertical direction) ?00?h vsa7-0 vea7-0 ?af?h [the condition of making an address set within the window-address range] (ram address) hsa7-0 ad7-0 hea7-0 vsa7-0 ad15-8 vea7-0 note: in high-speed ram write mode, the lower two bits of the address must be set as follows. id0 = 0: the lower two bits of the address must be set to 11. id0 = 1: the lower two bits of the address must be set to 00. window address-range specified area hsa7-0 = "10"h ? hse7-0 = "2f"h vsa7-0 = "20"h ? vea7-0 = "5f"h i/d = ?1? (increment) am = ?0? (horizontal write) gram address map "2010" h "202f"h "5f10" h "5f2f"h "2110"h 212f" h "0000"h "0083"h "af83"h "af00"h
HD66773R rev.1.10, jun.21.20 03, page 73 of 133 graphics operation function the HD66773R significantly reduces the load on the graphics-processing software in the microcomputer. the graphics operation includes: 1. the write data mask function that selectively rewrites some of the 16-bit write data. 2. logical rewrite function to rewrite data after performing logical operation on the data from the microcomputer and graphics ram base data. 3. the conditional rewrite function that compares th e write data and the compare bit data and writes the data sent from the microcomputer only when the conditions are satisfied. the graphics bit operation is controlled by the setting of bits in the entry mode register and ram-write- data mask register, and the write operation from the microcomputer. graphics operation bit setting operation mode i/d am lg2?0 operation and usage write mode 1 0/1 0 000 horizontal data replacement, draw a horizontal line write mode 2 0/1 1 000 vertical data replacement, draw a vertical line write mode 3 0/1 0 110 111 horizontal conditional data replacement, draw a horizontal line write mode 4 0/1 1 110 111 vertical conditional data replacement draw a vertical line read/write mode 1 0/1 0 001 010 011 horizonta l logical write, draw a horizontal line read/write mode 2 0/1 1 001 010 011 vertical logical write, draw a vertical line read/write mode 3 0/1 0 100 101 horizontal conditional data replacement, draw a horizontal line read/write mode 4 0/1 1 100 101 vertical conditional data replacement draw a vertical line note ) in 18-/9-bit interface modes, only write modes 1, 2 are effective. all operations are effective in 16-/8- bit interface modes.
HD66773R rev.1.10, jun.21.20 03, page 74 of 133 write-data mask function the HD66773R supports write data mask function, which controls gram data write by bit when 16-bit data from the microcomputer is being written to gram. the write data mask function write data in the bits whose corresponding bits in the write data mask resister (wm15?0) are assigned with ?0?. it does not write data in the bits whose corresponding bits in the write data mask register (wm15?0) are assigned with ?1?, and the corresponding data in gram are not ov erwritten but retained. this function is useful when only one-pixel data are rewritten or a particular color in the display is selectively changed. note) write data mask function is available with 8/16-bit system interface. db17 db1 write-data mask wm15 wm0 1111 0000 db15 db0 gram data r02 r01 r00 r03 g 02 g 01 g 00 g03 g02 g01 g03 1 b01 b00 1 b04 0 g04 0 g05 1 r04 b00 * g05 g04 data written by the microcomputer * ** ** * g00 * db10 db8 * 110 b02 b03
HD66773R rev.1.10, jun.21.20 03, page 75 of 133 graphics operation processing 1. write mode 1: am = 0, lg2?0 = 000 this mode is used when data are horizontally written in high-speed mode. it is also used to initialize the graphics ram (gram) or to draw a line horizontally. the write-data mask function (wm15?0) is also available in these operations. afte r writing, the address coun ter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and jumps to the counter at the opposing edge of the next one-raster-row below after when the counter reaches either left or right edge of gram. wm15 operation examples: 1) i/d = "1", am = "0", lg2-0 = "000" 2) wm15-0 = "07ff"h 3) ac = "0000"h write-data mask: 0 db17 write data (1): 1 0 0 1 write data (2): 1 1 0 0 wm0 1 1 1 1 1 1 1 1 db1 1 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 * * * * ** ** 1 1 0 * * * * ** * * "0000"h "0001"h "0002"h write data (1) write data (2) gra m 0 0 0 0 1 0 1 0 1 0 1 0 1 * * 0 * * 1 1 1 *write mask and plains db10 db8 1 * 0 * note : the data in the bit with "*" are not overwritten.
HD66773R rev.1.10, jun.21.20 03, page 76 of 133 2. write mode 2: am = 1, lg2?0 = 000 this mode is used when data are vertically written in high-speed mode. it is also used to initialize the graphics ram (gram), develop font patterns or draw a line vertically. the write-data mask function (wm15?0) is also available in these operations. after writing, the address counter (ac) automatically increments by 256, and automatically jumps to the counter either at the top of the next right row (id = 1) or the next left row (i/d = 0) according to the setting in the i/d bit, when the ad dress reaches the bottom of gram. 1) i/d = "1", am = "1", lg2-0 = "000" 2) wm15-0 = "07ff"h 3) ac = "0000"h note 1) the data in the bit with "*" are not overwritten. note 2) when data are written to the address "af00"h, the address counter (ac) jumps to "0001"h. wm15 wm0 write-data mask: 0 0 0 0 db17 write data (1): 1 0 0 1 write data (2): 1 1 0 0 write data (3): 0 1 1 1 1 1 1 1 1 1 1 1 db1 1 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 "0000"h write data (1) gram "0100"h "0200"h write data (2) write data (3) 1 0 0 1 1 1 0 0 0 1 1 1 **** * ** * **** **** **** **** 0 1 0 1 1 1 0 1 1 1 0 0 1 1 0 0 1 0 1 * * * ** ** ** db10 db8
HD66773R rev.1.10, jun.21.20 03, page 77 of 133 3. write mode 3: am = 0, lg2?0 = 110/111 this mode is used when data are horizontally written with comparing the write data and the value set in the compare register (cp15?0). when the result of the comparison satisfies a condition, the write data sent from the microcomputer are written to gram. in this operation, the write-data mask function (wm15?0) is available. after writing, the address counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and jumps to the counter at the opposing edge of the next one-raster-row below after when the counter reaches either le ft or right edge of gram. operation examples: 1) i / d = "1", am = "0", lg2-0 = "110" (matched write) 2) cp15-0 = "2860"h 2) wm15-0 = "0000"h 3) ac = "0000"h wm0 write-data mask: db1 "0000"h "0001"h gram write data (1): write data (2): 0 cp0 compare register (matched ) * ********** * 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 * * * * compare operation replacement conditional replacement c c r r * ** ** ** ** ** * conditional replacement 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 * * * * compare operation matched replacement of write data ( 1 ) wm15 0 0 0 0 0 db17 0 0 0 0 cp15 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 db10 db8 1 0000 0 0
HD66773R rev.1.10, jun.21.20 03, page 78 of 133 4. write mode 4: am = 1, lg2?0 = 110/111 this mode is used when data are horizontally written with comparing the write data and the value set in the compare register (cp15?0). when the result of the comparison satisfies a condition, the write data sent from the microcomputer are written to gram. in this operation, the write-data mask function (wm15?0) is available. after writing, the address counter (a c) automatically increments by 256, and automatically jumps to the counter either at the top of the next righ t row (id = 1) or the next left row (i/d = 0) according to the setting in the i/d bit, when the address reaches the bottom of gram. operation examples: 1) i/d = "1", am = "1", lg2-0 = "111" (unmatched write) 2) cp15-0 = "2860"h 2) wm15-0 = "0000"h 3) ac = "0000"h wm15 wm0 write-data mask: db1 write data (1): write dat a (2): compare operation compare operation cp0 compare register: conditional replacement conditional replacement c c r r (unmatched) (matched) ) 1 0 0 1 1 0 0 1 * * * * * * * * * * * * "0000"h write data (1) gram "0100"h write dat a (2) "af 00"h "0000"h "0001"h 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 * * * * * * * * * * * * 1 1 1 1 0 0 0 0 0 0 0 0 db17 1 0 0 1 1 0 0 1 cp15 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 10 0 0 0 0 1 * 1 * 1 * 1 * * * * * db10 db8 note 1) the data in the bit with "*" are not overwritten. note 2) when data are written to the address "af00"h, the address counter (ac) jumps to "0001"h. 0
HD66773R rev.1.10, jun.21.20 03, page 79 of 133 5. read/write mode 1: am = 0, lg2?0 = 001/010/011 this mode is used when data are horizontally written in high-speed with performing logical operation on the gram data (base data) and data from the microcom puter. the logical operation is performed on the gram read-out data and the data sent from the micr ocomputer, and the result of the logical operation is written to gram. in the read operation, the gram da ta is not read out to the microcomputer but retained temporarily in the read-data latch of the HD66773R. accordingly, the read operation can be performed using the same pulse width with the write-access pulse (68-system: enable ?high? level width, 80- system: enable ?low? level width), but requires the sa me bus cycle time as the normal read operation. in this operation, the write-data mask function (wm15?0) is available. after writing, the address counter (ac) automatically increments by 1 (i /d = 1) or decrements by 1 (i/d = 0), and jumps to the counter at the opposing edge of the next one-raster-row below after when the counter reaches either left or right edge of gram. wm15 operation examples: 1) i/d = "1", am = "0", lg2-0 = "001"(or) 2) wm15-0 = "0000"h 3) ac = "0000"h write-data mask: 0 0 0 0 0 0 0 0 db17 write data (1): 1 0 1 1 1 1 0 0 write data (2): 1 1 0 0 0 0 1 1 "0000"h "0001"h read data (1) + write data (1) gram read data (1): 1 0 0 1 1 0 0 1 read data (2): 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 0 1 1 0 read data (2) + write data (2) wm0 0 0 0 0 db1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 1 1 0 0 0 logical operation(or ) logical operation(or) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 db10 db8 1
HD66773R rev.1.10, jun.21.20 03, page 80 of 133 6. read/write mode 2: am = 1, lg2?0 = 110/111 this mode is used when data are vertically written in high-speed with performing logical operation on the gram data (base data) and data from the microcomputer. the logical operation is performed on the gram read-out data and the data sent from the microcomputer, and the result of the logical operation is written to gram. in the read operation, the gram da ta is not read out to the microcomputer but retained temporarily in the read-data latch of the HD66773R. accordingly, the read operation can be performed using the same pulse width with the write-access pulse (68-system: enable ?high? level width, 80- system: enable ?low? level width), but requires the sa me bus cycle time as the normal read operation. in this operation, the write-data mask function (wm15?0) is available. after wr iting, the address counter (ac) automatically increments by 256, and automatically jumps to the counter either at the top of the next right row (id = 1) or the next left row (i/d = 0) accor ding to the setting in the i/d bit, when the address reaches the bottom of gram. wm15 operation examples: 1) i / d = "1", am = "1", lg2-0 = "001"(or) 2) wm15-0 = "ffe0"h 3) ac = "0000"h write-data mask: 1 1 1 1 1 1 1 1 db17 write data (1): 1 0 1 1 1 1 0 0 write data (2): 1 1 0 0 0 0 1 1 read data (1): 1 0 0 0 1 0 0 1 read data (2): 0 0 0 0 1 1 1 1 "0000"h read data (1) + write data (1) gram "0100"h read data (2) + write data (2) 0 "af 00"h "0000"h "0001"h 1 ** * ** * * * ** * *** * * wm0 1 1 1 0 db1 0 1 1 0 1 0 0 1 0 1 0 1 0 0 0 0 logical operation(or) 1 1 1 0 1 0 1 1 1 1 0 1 logical operation(or) 1 1 0 0 1 11 00 111 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 * * * * * * db10 db8 note 1) the data in the bit with "*" are not overwritten. note 2) when data are written to the address "af00"h, the address counter (ac) jumps to "0001"h.
HD66773R rev.1.10, jun.21.20 03, page 81 of 133 7. read/write mode 3: am = 0, lg2?0 = 100/101 this mode is used when data are horizontally wr itten in high-speed with performing compare operation on the gram data (base data) and the value set in the compare register (cp15-0). the compare operation is performed on the gram read-out data and the value se t in the compare register by word. when the result of the comparison satisfies a condition, the data sent from the microcomputer are written to gram. in the read operation, the gram data is not read out to th e microcomputer but retained temporarily in the read- data latch of the HD66773R. accordingly, the read operation can be performed using the same pulse width with the write-access puls e (68-system: enable ?high? level wi dth, 80-system: enable ?low? level width), but requires the same bus cycle time as the norma l read operation. in this operation, the write-data mask function (wm15?0) is available. after writing, the address counter (ac) automatically increments by 1 (i/d = 1) or decrements by 1 (i/d = 0), and jump s to the counter at the opposing edge of the next one- raster-row below after when th e counter reaches either left or right edge of gram. operation examples: 1) i/d = "1", am = "0", lg2-0 = "100" (matched write) 2) cp15-0 = "2860"h 2) wm15-0 = "0000"h 3) ac = "0000"h wm15 write-data mask: 0 0 0 0 0 0 0 0 db17 write data (1): 1 0 1 1 1 1 0 0 write data (2): 1 1 0 0 0 0 1 1 "0000"h "0001"h gram read data (1): read data (2): 0 0 0 0 1 1 1 1 cp15 compare register: 0 0 1 0 1 0 0 0 matche d 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 wm0 0 0 0 0 db1 0 1 1 0 1 0 0 0 0 0 0 0 compare operatio n compare operation cp0 conditional replacement conditional replacement c c r r 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 matched replacement write data (1) db10 db8
HD66773R rev.1.10, jun.21.20 03, page 82 of 133 8. read/write mode 4: am = 1, lg2?0 = 100/101 this mode is used when data are vertically written in high-speed with performing compare operation on the gram data (base data) and the value set in the co mpare register (cp15-0). the compare operation is performed on the gram read-out data and the value se t in the compare register by word. when the result of the comparison satisfies a condition, the data sent from the microcomputer are written to gram. in the read operation, the gram data is not read out to th e microcomputer but retained temporarily in the read- data latch of the HD66773R. accordingly, the read operation can be performed using the same pulse width with the write-access puls e (68-system: enable ?high? level wi dth, 80-system: enable ?low? level width), but requires the same bus cycle time as the norma l read operation. in this operation, the write-data mask function (wm15?0) is available. after writing, the address counter (ac) automatically increments by 256, and automatically jumps to the counter either at the top of the next right row (id = 1) or the next left row (i/d = 0) according to the setting in the i/ d bit, when the address reaches the bottom of gram. operation examples: 1 ) i / d = "1" , am = "1" , lg2-0 = "101" ( unmatched write ) 2) cp15-0 = "2860"h 2) wm15-0 = "0000"h 3) ac = "0000"h wm15 write-data mask: 0 0 0 0 0 0 0 0 db17 write data (1): 1 0 1 1 1 1 0 0 write data (2): 1 1 0 0 0 0 1 1 read data (1): 1 0 0 1 1 0 0 1 read data (2): cp15 compare register: 0 0 1 0 1 0 0 0 unmatched "0000"h write data (1) gram "0100"h write dat a (2) "af 00"h "0000"h "0001"h 0 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 wm0 0 0 0 0 db1 0 1 1 0 1 0 0 0 0 1 0 1 compare operation comp are operation cp0 conditional replacement conditional replacement c c r r 0 1 1 0 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 00 0 0 0 0 matched db10 db8 note 1) the data in the bit with "*" are not overwritten. note 2) when data are written to the address "af00"h, the address counter (ac) jumps to "0001"h. 101111000110000 0
HD66773R rev.1.10, jun.21.20 03, page 83 of 133 scan mode setting the shift direction of gate signal is changeable by th e combination of sm and gs bit settings. this allows various ways of connecting a liquid crystal panel and the HD66773R. sm gs scan direction 0 1 0 1 0 0 1 1 g1 g2 g3 g4 g173 g174 g175 g176 g176 g175 g174 173 g4 g3 g2 g1 g1 g3 g5 g173 g175 g2 g4 g6 g174 g176 g176 g174 g172 g4 g 2 g175 g173 g171 g3 g1 g1 g175 g2 g176 tft panel HD66773R g1 g175 g2 g176 odd line e ven line g1 g175 g2 g176 tft panel HD66773R g1 g175 g2 g176 odd line even line g1 g175 g2 g176 tft panel HD66773R g1 g175 g176 g2 g1 g175 g2 g176 tft panel HD66773R g1 g175 g176 g2
HD66773R rev.1.10, jun.21.20 03, page 84 of 133 -correction function the HD66773R incorporates -correction function to simultaneously display 262,144 colors, by which 8- level grayscale is determined by the gradient-adjus tment and fine-adjustment registers. select either positive or negative polarity of th e registers according to the characteristics of a liquid crystal panel. g 2 g 1 g 0 b 3 b 2 display dat a msb lsb graphics ram (gram ) g 3 b 1 b 0 b 4 g 4 g 5 r 3 r 2 r 1 r 0 r 4 32 grayscale cont rol 32 g ra y scale cont rol 32 grayscale cont rol 6 6 6 lcd driver lcd driver lcd driver rg b lcd pkp 01 pkp 00 pkp 11 pkp 10 pkp 21 pkp 20 pkp 31 pkp 30 pkp 41 pkp 40 pkp 51 pkp 50 pkp 32 pkp 42 pkp 52 pkp 12 pkp 22 pkp 0 2 nagative polarity register 8 v0 v31 32 prp 01 prp 00 prp 11 prp 10 prp 12 prp 02 pkn 01 pkn 00 pkn 11 pkn 10 pkn 21 pkn 20 pkn 31 pkn 30 pkn 41 pkn 40 pkn 51 pkn 50 pkn 32 pkn 42 pkn 52 pkn 12 pkn 22 pkn 02 prn01 prn00 prn11 prn10 prn12 prn02 grayscale amplifie r v1 frc control frc control f rc control data expansion circui t data expansion circui t r 3 r 2 r 1 r 0 r 4 r 5 b 3 b 2 b 1 b 0 b 4 b 5 positive polarity register vrp00 vrp10 vrp01 vrp11 vrp02 vrp12 vrp03 vrp13 vrp1 4 vrn00 vrn10 vrn01 vrn11 vrn02 vrn12 vrn03 vrn13 vrn1 4 note 1) 16-bit ram data is expanded into 18-bit data through data expansion circuit.
HD66773R rev.1.10, jun.21.20 03, page 85 of 133 configuration of grayscale amplifier the gradient adjustment and fine adjustment registers determine the eight levels (vin0-7) of grayscale. the 8 levels are then divided into 32 levels (v0- 31) by the ladder resistors placed between each level. 8to1 selecto r micro adjustment register (6 x 3 bits) vrp/vrn pk p/n0 3 3 3 33 333 amplitude adjustment register 5 pkp/n1 pkp/n2 pkp/n3 pkp/n4 pkp/n5 prp/n0 prp/n1 gradient adjustment regist er vg s grayscale amplifier vinp0/vinn0 vinp1/vinn1 vinp2/vinn2 vinp3/vinn3 vinp4/vinn4 vinp5/vinn5 vinp6/vinn6 vinp7/vinn7 v0 v1 v8 v16 v19 v24 v30 v31 v2 v9 v17 v20 v25 v3 v26 ladder resistor 8to1 selector 8to1 selector 8to1 selector 8to1 selector 8to1 selector vreg1o ut 4
HD66773R rev.1.10, jun.21.20 03, page 86 of 133 rp3 5 rp3 6 rp3 7 rp3 8 vrlp kvp4 1 kvp42 kvp43 kvp44 kvp45 kvp46 kvp47 kvp4 8 rp39 rp40 rp41 rp42 rp43 rp44 rp4 5 kvp49 rp46 vr p1 rp47 vinp 2 prp0[2 :0] pkp1[2:0 ] vinp 1 pkp0[2:0 ] vinp 0 vinp 3 pkp2[2:0 ] vinp 4 pkp3[2:0 ] vinp 5 pkp4[2:0 ] vinp 6 pkp5[2:0 ] vinp 7 prp1[2 :0] vrp1[4 :0] rn1 rn2 rn3 rn4 rn5 rn6 rn7 rp1 rp2 rp3 rp4 rp5 rp6 rp7 kvp0 kvp1 kvp2 kvp3 kvp4 kvp5 kvp6 kvp7 kvp8 rp0 v rhp rp9 rp10 kvp9 rp1 1 rp1 2 rp1 3 rp1 4 rp 8 kvp10 kvp11 kvp12 kvp13 kvp14 kvp15 kvp1 6 rp15 kvp1 7 kvp18 kvp19 kvp20 kvp21 kvp22 kvp23 kvp24 rp1 6 rp1 7 rp1 8 rp1 9 rp2 0 rp2 1 rp2 2 rp23 kvp2 5 kvp26 kvp27 kvp28 kvp29 kvp30 kvp31 kvp32 rp2 4 rp2 5 rp2 6 rp2 7 rp2 8 rp2 9 rp3 0 rp31 kvp3 3 kvp34 kvp35 kvp36 kvp37 kvp38 kvp39 kvp40 rp3 2 rp3 3 rp3 4 rn39 rn40 rn41 rn42 rn43 rn44 rn4 5 kvn49 rn46 v rn1 rn47 vi nn2 prn0[2:0 ] pkn1[2: 0] vi nn1 pkn0[2: 0] vi nn3 pkn2[2: 0] vi nn4 pkn3[2: 0] vi nn5 pkn4[2: 0] vi nn6 pkn5[2: 0] vi nn7 prn1[2:0 ] v rn1[4:0] kvn1 kvn2 kvn3 kvn4 kvn5 kvn6 kvn7 kvn8 rn0 v rhn rn9 rn10 kvn 9 rn1 1 rn1 2 rn1 3 rn1 4 rn8 kvn10 kvn11 kvn12 kvn13 kvn14 kvn15 kvn 16 rn15 kvn 17 kvn18 kvn19 kvn20 kvn21 kvn22 kvn23 kvn24 rn1 6 rn1 7 rn1 8 rn1 9 rn2 0 rn2 1 rn2 2 rn23 kvn 25 kvn26 kvn27 kvn28 kvn29 kvn30 kvn31 kvn32 rn2 4 rn2 5 rn2 6 rn2 7 rn2 8 rn2 9 rn3 0 rn31 kvn 33 kvn34 kvn35 kvn36 kvn37 kvn38 kvn39 kvn40 rn3 2 rn3 3 rn3 4 rn3 5 rn3 6 rn3 7 rn3 8 vrln kvn 41 kvn42 kvn43 kvn44 kvn45 kvn46 kvn47 kvn 48 4r 5r 16r 5r 5r 8r 0 to 28r 0 to 28r 0 to 31r ex vr 5r 4r 1r 1r 1r 1r 4r 5r 16r 5r 5r 8r 0 to2 8r 0 to 28r 0 to 31r 5r 4r 1r 1r 1r 1r 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel 8 to 1 sel vreg1o ut vrp0 0 to 30r vrn0 0 to 30r vrp0[3 :0] vrn0[3:0 ] vinn 0 kvn0 ladder resistors and 8-to-1 selectors
HD66773R rev.1.10, jun.21.20 03, page 87 of 133 -correction register the -adjustment register is a group of registers to set an appropriate grayscale voltage for the - characteristics of a liquid crystal panel. the register group is categorized into the ones adjusting gradient, amplitude, and fine-tuning in relation to grayscale number and voltage characteristics. each register can make an independent setting for the positive/negative polarity. the reference value and rgb are common for all registers. grayscale voltage grayscale number gradient adjustment grayscale voltage grayscale number amplitude adjustment grayscale voltage grayscale number fine adjustment -correction register 1. gradient adjustment registers the gradient adjustment registers ar e used to adjust the gradient arou nd the middle of the grayscale number and voltage characteristics without changing the dynami c range. to adjust a gradient, the values of the variable resistors (vrhp (n)/vrl (n)) in the middle of the ladder resistor block for grayscale voltage generation are controlled. the registers incorporate se parate registers for positive and negative polarities to be compatible with asymmetric drive. 2. amplitude adjustment registers the amplitude adjustment registers are used to adjust the amplitude of the grayscale voltage. to adjust the amplitude, the values of the variable resistor (vrp(n)1 /0) located at the lower side of the ladder resistor block for grayscale voltage generation are adjusted. the variable resistor located at the upper side of the ladder resistor block is adjusted by the input vdh le vel or reference resistor. same with the gradient registers, the registers also incorporate separa te registers for positive and negative polarities. 3. fine adjustment registers the fine adjustment register is to fine-adjust the grayscale voltage level. to fine-adjust the grayscale voltage level, each level of 8-level reference voltages generated from the ladder registers is controlled by 8- to-1 selector. same with the other registers, the regi sters also incorporate separa te registers for positive and negative polarities.
HD66773R rev.1.10, jun.21.20 03, page 88 of 133 -correction registers register groups positive polarity negative polarity description prp0 2 to 0 prn0 2 to 0 variable resistor vrhp (n) gradient adjustment prp1 2 to 0 prn1 2 to 0 variable resistor vrlp (n) vrp0 3 to 0 vrn0 3 to 0 v ariable resistor vrp (n)0 amplitude adjustment vrp1 4 to 0 vrn1 4 to 0 v ariable resistor vrp (n)1 pkp0 2 to 0 pkn0 2 to 0 8-to-1 select or (voltage level of grayscale 1) pkp1 2 to 0 pkn1 2 to 0 8-to-1 select or (voltage level of grayscale 8) pkp2 2 to 0 pkn2 2 to 0 8-to-1 selector (voltage level of grayscale 20) pkp3 2 to 0 pkn3 2 to 0 8-to-1 selector (voltage level of grayscale 43) pkp4 2 to 0 pkn4 2 to 0 8-to-1 selector (voltage level of grayscale 55) fine adjustment pkp5 2 to 0 pkn5 2 to 0 8-to-1 selector (voltage level of grayscale 62) ladder resistors and 8-to-1 selector block configuration the block diagram of page 86 consists of two ladder resistors including variable resistors, and 8-to-1 selectors which select the voltage generated by the ladder resistors to output a reference voltage for the grayscale voltage. the variable resistors an d the 8-to-1 selectors are controlled by the correction register. pins to be connected to a variable resistor are provided to compensate the variation among the panels. variable resistor there are two kinds of variable resistors for the gradient adjustment (vrhp(n)/vrlp(n)) and the amplitude adjustment (vrp(n)0/ vrp(n)1). the resist ance is determined by the gradient adjustment and amplitude adjustment registers as is shown below. gradient adjustment (1) gradient adjustment (2) register value prp(n)0[2:0] resistance vrhp(n) register value prp(n)1[2:0] resistance vrlp(n) 000 0r 000 0r 001 4r 001 4r 010 8r 010 8r 011 12r 011 12r 100 16r 100 16r 101 20r 101 20r 110 24r 110 24r 111 28r 111 28r
HD66773R rev.1.10, jun.21.20 03, page 89 of 133 amplitude adjustment (1) amplitude adjustment (2) register value vrp(n)0[3:0] resistance vrp(n)0 register value vrp(n)1[4:0] resistance vrp(n)1 0000 0r 00000 0r 0001 2r 00001 1r 0010 4r 00010 2r ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1101 26r 11101 29r 1111 28r 11110 30r 1111 30r 11111 31r 8-to-1 selector the 8-to-1 selectors select a voltage level generated by the ladder resistors according to the fine adjustment registers, and output six kinds of reference voltage, vin1 to vin 6. the relationship between the fine adjustment register and the selected voltage is as follows. fine adjustment registers and selected voltage the value of register selected voltage pkp(n)[2:0] vinp(n)1 vinp(n)2 vinp(n)3 vinp(n)4 vinp(n)5 vinp(n)6 000 kvp(n)1 kvp(n)9 kvp(n)17 kvp(n)25 kvp(n)33 kvp(n)41 001 kvp(n)2 kvp(n)10 kvp(n)18 kvp(n)26 kvp(n)34 kvp(n)42 010 kvp(n)3 kvp(n)11 kvp(n)19 kvp(n)27 kvp(n)35 kvp(n)43 011 kvp(n)4 kvp(n)12 kvp(n)20 kvp(n)28 kvp(n)36 kvp(n)44 100 kvp(n)5 kvp(n)13 kvp(n)21 kvp(n)29 kvp(n)37 kvp(n)45 101 kvp(n)6 kvp(n)14 kvp(n)22 kvp(n)30 kvp(n)38 kvp(n)46 110 kvp(n)7 kvp(n)15 kvp(n)23 kvp(n)31 kvp(n)39 kvp(n)47 111 kvp(n)8 kvp(n)16 kvp(n)24 kvp(n)32 kvp(n)40 kvp(n)48
HD66773R rev.1.10, jun.21.20 03, page 90 of 133 the grayscale levels (v0-v31) are calcula ted according to the following formulas. formulas for calculating volt age (positive polarity) (1) sumrp: total of the positive-polarity ladder resistors = 128 r + vrhp + vrlp + vrp0 + vrp1 sumrn: total of the negative-polarity ladder resistors = 128 r + vrhn + vrln + vrn0 + vrn1 v: voltage difference between vreg1out - vgs pins formula micro-adjsting register value reference voltage kvp0 vreg1out- @| v*vrp0/sumrp - vinp0 kvp1 vreg1out- l v*(vrp0+5r)/sumrp pkp02-00 = "000" kvp2 vreg1out- l v*(vrp0+9r)/sumrp pkp02-00 = "001" kvp3 vreg1out- l v*(vrp0+13r)/sumrp pkp02-00 = "010" kvp4 vreg1out- l v*(vrp0+17r)/sumrp pkp02-00 = "011" kvp5 vreg1out- l v*(vrp0+21r)/sumrp pkp02-00 = "100" kvp6 vreg1out- l v*(vrp0+25r)/sumrp pkp02-00 = "101" kvp7 vreg1out- l v*(vrp0+29r)/sumrp pkp02-00 = "110" kvp8 vreg1out- l v*(vrp0+33r)/sumrp pkp02-00 = "111" kvp9 vreg1out- l v*(vrp0+33r+vrhp)/sumrp pkp12-10 = "000" kvp10 vreg1out- l v*(vrp0+34r+vrhp)/sumrp pkp12-10 = "001" kvp11 vreg1out- l v*(vrp0+35r+vrhp)/sumrp pkp12-10 = "010" kvp12 vreg1out- l v*(vrp0+36r+vrhp)/sumrp pkp12-10 = "011" kvp13 vreg1out- l v*(vrp0+37r+vrhp)/sumrp pkp12-10 = "100" kvp14 vreg1out- l v*(vrp0+38r+vrhp)/sumrp pkp12-10 = "101" kvp15 vreg1out- l v*(vrp0+39r+vrhp)/sumrp pkp12-10 = "110" kvp16 vreg1out- l v*(vrp0+40r+vrhp)/sumrp pkp12-10 = "111" kvp17 vreg1out- l v*(vrp0+45r+vrhp)/sumrp pkp22-20 = "000" kvp18 vreg1out- l v*(vrp0+46r+vrhp)/sumrp pkp22-20 = "001" kvp19 vreg1out- l v*(vrp0+47r+vrhp)/sumrp pkp22-20 = "010" kvp20 vreg1out- l v*(vrp0+48r+vrhp)/sumrp pkp22-20 = "011" kvp21 vreg1out- l v*(vrp0+49r+vrhp)/sumrp pkp22-20 = "100" kvp22 vreg1out- l v*(vrp0+50r+vrhp)/sumrp pkp22-20 = "101" kvp23 vreg1out- l v*(vrp0+51r+vrhp)/sumrp pkp22-20 = "110" kvp24 vreg1out- l v*(vrp0+52r+vrhp)/sumrp pkp22-20 = "111" vinp1 vinp2 vinp3 kvp25 vreg1out- l v*(vrp0+68r+vrhp)/sumrp pkp32-30 = "000" kvp26 vreg1out- l v*(vrp0+69r+vrhp)/sumrp pkp32-30 = "001" kvp27 vreg1out- l v*(vrp0+70r+vrhp)/sumrp pkp32-30 = "010" kvp28 vreg1out- l v*(vrp0+71r+vrhp)/sumrp pkp32-30 = "011" kvp29 vreg1out- l v*(vrp0+72r+vrhp)/sumrp pkp32-30 = "100" kvp30 vreg1out- l v*(vrp0+73r+vrhp)/sumrp pkp32-30 = "101" kvp31 vreg1out- l v*(vrp0+74r+vrhp)/sumrp pkp32-30 = "110" kvp32 vreg1out- l v*(vrp0+75r+vrhp)/sumrp pkp32-30 = "111" kvp33 vreg1out- l v*(vrp0+80r+vrhp)/sumrp pkp42-00 = "000" kvp34 vreg1out- l v*(vrp0+81r+vrhp)/sumrp pkp42-40 = "001" kvp35 vreg1out- l v*(vrp0+82r+vrhp)/sumrp pkp42-40 = "010" kvp36 vreg1out- l v*(vrp0+83r+vrhp)/sumrp pkp42-40 = "011" kvp37 vreg1out- l v*(vrp0+84r+vrhp)/sumrp pkp42-40 = "100" kvp38 vreg1out- l v*(vrp0+85r+vrhp)/sumrp pkp42-40 = "101" kvp39 vreg1out- l v*(vrp0+86r+vrhp)/sumrp pkp42-40 = "110" kvp40 vreg1out- l v*(vrp0+87r+vrhp)/sumrp pkp42-40 = "111" kvp41 vreg1out- l v*(vrp0+87r+vrhp+vrlp)/sumrp pkp52-50 = "000" kvp42 vreg1out- l v*(vrp0+91r+vrhp+vrlp)/sumrp pkp52-50 = "001" kvp43 vreg1out- l v*(vrp0+95r+vrhp+vrlp)/sumrp pkp52-50 = "010" kvp44 vreg1out- l v*(vrp0+99r+vrhp+vrlp)/sumrp pkp52-50 = "011" kvp45 vreg1out- l v*(vrp0+103r+vrhp+vrlp)/sumrp pkp52-50 = "100" kvp46 vreg1out- l v*(vrp0+107r+vrhp+vrlp)/sumrp pkp52-50 = "101" kvp47 vreg1out- l v*(vrp0+111r+vrhp+vrlp)/sumrp pkp52-50 = "110" kvp48 vreg1out- l v*(vrp0+115r+vrhp+vrlp)/sumrp pkp52-50 = "111" kvp49 vreg1out- l v*(vrp0+120r+vrhp+vrlp)/sumrp - vinp7 vinp5 vinp6 vinp4
HD66773R rev.1.10, jun.21.20 03, page 91 of 133 formulas for calculating volt age (positive polarity) (2) v3d: v3d = v4+(vinp1-v4)*(540/960) grayscale voltage formula v0 vinp0 v1 v3d+(vinp1-v3d)*(8/24) v2 v4+(v3d-v4)*(16/24) v3 v4+(v3d-v4)*(8/24) v4 vinp2 v5 v10+(v4-v10)*(20/24) v6 v10+(v4-v10)*(16/24) v7 v10+(v4-v10)*(12/24) v8 v10+(v4-v10)*(8/24) v9 v10+(v4-v10)*(4/24) v10 vinp3 v11 v21+(v10-v21)*(21/24) v12 v21+(v10-v21)*(19/24) v13 v21+(v10-v21)*(17/24) v14 v21+(v10-v21)*(15/24) v15 v21+(v10-v21)*(13/24) v16 v21+(v10-v21)*(11/24) v17 v21+(v10-v21)*(9/24) v18 v21+(v10-v21)*(7/24) v19 v21+(v10-v21)*(5/24) v20 v21+(v10-v21 )*(3/24) v21 vinp4 v22 v27+(v21-v27)*(20/24) v23 v27+(v21-v27)*(16/24) v24 v27+(v21-v27)*(12/24) v25 v27+(v21-v27)*(8/24) v26 v27+(v21-v27)*(4/24) v27 vinp5 v28 vinp6+(v27-vinp6)*(780/960) v29 vinp6+(v27-vinp6)*(600/960) v30 vinp6+(v27-vinp6)*(280/960) v31 vinp7
HD66773R rev.1.10, jun.21.20 03, page 92 of 133 formulas for calculating volt age (negative polarity) (1) table 40 voltage formula: negative polarity pins formula micro-adjsting register value reference voltage kvn0 vreg1out- @| v*vrn0/sumrn - vinn0 kvn1 vreg1out- l v*(vrn0+5r)/sumrn pkn02-00 = "000" kvn2 vreg1out- l v*(vrn0+9r)/sumrn pkn02-00 = "001" kvn3 vreg1out- l v*(vrn0+13r)/sumrn pkn02-00 = "010" kvn4 vreg1out- l v*(vrn0+17r)/sumrn pkn02-00 = "011" kvn5 vreg1out- l v*(vrn0+21r)/sumrn pkn02-00 = "100" kvn6 vreg1out- l v*(vrn0+25r)/sumrn pkn02-00 = "101" kvn7 vreg1out- l v*(vrn0+29r)/sumrn pkn02-00 = "110" kvn8 vreg1out- l v*(vrn0+33r)/sumrn pkn02-00 = "111" kvn9 vreg1out- l v*(vrn0+33r+vrhn)/sumrn pkn12-10 = "000" kvn10 vreg1out- l v*(vrn0+34r+vrhn)/sumrn pkn12-10 = "001" kvn11 vreg1out- l v*(vrn0+35r+vrhn)/sumrn pkn12-10 = "010" kvn12 vreg1out- l v*(vrn0+36r+vrhn)/sumrn pkn12-10 = "011" kvn13 vreg1out- l v*(vrn0+37r+vrhn)/sumrn pkn12-10 = "100" kvn14 vreg1out- l v*(vrn0+38r+vrhn)/sumrn pkn12-10 = "101" kvn15 vreg1out- l v*(vrn0+39r+vrhn)/sumrn pkn12-10 = "110" kvn16 vreg1out- l v*(vrn0+40r+vrhn)/sumrn pkn12-10 = "111" kvn17 vreg1out- l v*(vrn0+45r+vrhn)/sumrn pkn22-20 = "000" kvn18 vreg1out- l v*(vrn0+46r+vrhn)/sumrn pkn22-20 = "001" kvn19 vreg1out- l v*(vrn0+47r+vrhn)/sumrn pkn22-20 = "010" kvn20 vreg1out- l v*(vrn0+48r+vrhn)/sumrn pkn22-20 = "011" kvn21 vreg1out- l v*(vrn0+49r+vrhn)/sumrn pkn22-20 = "100" kvn22 vreg1out- l v*(vrn0+50r+vrhn)/sumrn pkn22-20 = "101" kvn23 vreg1out- l v*(vrn0+51r+vrhn)/sumrn pkn22-20 = "110" kvn24 vreg1out- l v*(vrn0+52r+vrhn)/sumrn pkn22-20 = "111" vinn1 vinn2 vinn3 kvn25 vreg1out- l v*(vrn0+68r+vrhn)/sumrn pkn32-30 = "000" kvn26 vreg1out- l v*(vrn0+69r+vrhn)/sumrn pkn32-30 = "001" kvn27 vreg1out- l v*(vrn0+70r+vrhn)/sumrn pkn32-30 = "010" kvn28 vreg1out- l v*(vrn0+71r+vrhn)/sumrn pkn32-30 = "011" kvn29 vreg1out- l v*(vrn0+72r+vrhn)/sumrn pkn32-30 = "100" kvn30 vreg1out- l v*(vrn0+73r+vrhn)/sumrn pkn32-30 = "101" kvn31 vreg1out- l v*(vrn0+74r+vrhn)/sumrn pkn32-30 = "110" kvn32 vreg1out- l v*(vrn0+75r+vrhn)/sumrn pkn32-30 = "111" kvn33 vreg1out- l v*(vrn0+80r+vrhn)/sumrn pkn42-00 = "000" kvn34 vreg1out- l v*(vrn0+81r+vrhn)/sumrn pkn42-00 = "001" kvn35 vreg1out- l v*(vrn0+82r+vrhn)/sumrn pkn42-00 = "010" kvn36 vreg1out- l v*(vrn0+83r+vrhn)/sumrn pkn42-00 = "011" kvn37 vreg1out- l v*(vrn0+84r+vrhn)/sumrn pkn42-00 = "100" kvn38 vreg1out- l v*(vrn0+85r+vrhn)/sumrn pkn42-00 = "101" kvn39 vreg1out- l v*(vrn0+86r+vrhn)/sumrn pkn42-00 = "110" kvn40 vreg1out- l v*(vrn0+87r+vrhn)/sumrn pkn42-00 = "111" kvn41 vreg1out- l v*(vrn0+87r+vrhn+vrln)/sumrn pkn52-50 = "000" kvn42 vreg1out- l v*(vrn0+91r+vrhn+vrln)/sumrn pkn52-50 = "001" kvn43 vreg1out- l v*(vrn0+95r+vrhn+vrln)/sumrn pkn52-50 = "010" kvn44 vreg1out- l v*(vrn0+99r+vrhn+vrln)/sumrn pkn52-50 = "011" kvn45 vreg1out- l v*(vrn0+103r+vrhn+vrln)/sumrn pkn52-50 = "100" kvn46 vreg1out- l v*(vrn0+107r+vrhn+vrln)/sumrn pkn52-50 = "101" kvn47 vreg1out- l v*(vrn0+111r+vrhn+vrln)/sumrn pkn52-50 = "110" kvn48 vreg1out- l v*(vrn0+115r+vrhn+vrln)/sumrn pkn52-50 = "111" kvn49 vreg1out- l v*(vrn0+120r+vrhn+vrln)/sumrn - vinn7 vinn5 vinn6 vinn4 sumrp: total of the positive-polarity ladder resistors = 128 r + vrhp + vrlp + vrp0 + vrp1 sumrn: total of the negative-polarity ladder resistors = 128 r + vrhn + vrln + vrn0 + vrn1 v: voltage difference between vreg1out - vgs
HD66773R rev.1.10, jun.21.20 03, page 93 of 133 formulas for calculating volt age (negative polarity) (2) v3d: v3d = v4+(vinn1-v4)*(540/960) grayscale voltage formula v0 vinn0 v1 v3d+(vinn1-v3d)*(8/24) v2 v4+(v3d-v4)*(16/24) v3 v4+(v3d-v4)*(8/24) v4 vinn2 v5 v10+(v4-v10)*(20/24) v6 v10+(v4-v10)*(16/24) v7 v10+(v4-v10)*(12/24) v8 v10+(v4-v10)*(8/24) v9 v10+(v4-v10)*(4/24) v10 vinn3 v11 v21+(v10-v21)*(21/24) v12 v21+(v10-v21)*(19/24) v13 v21+(v10-v21)*(17/24) v14 v21+(v10-v21)*(15/24) v15 v21+(v10-v21)*(13/24) v16 v21+(v10-v21)*(11/24) v17 v21+(v10-v21)*(9/24) v18 v21+(v10-v21)*(7/24) v19 v21+(v10-v21)*(5/24) v20 v21+(v10-v21)*( 3/24) v21 vinn4 v22 v27+(v21-v27)*(20/24) v23 v27+(v21-v27)*(16/24) v24 v27+(v21-v27)*(12/24) v25 v27+(v21-v27)*(8/24) v26 v27+(v21-v27)*(4/24) v27 vinn5 v28 vinn6+(v27-vinn6)*(780/960) v29 vinn6+(v27-vinn6)*(600/960) v30 vinn6+(v27-vinn6)*(280/960) v31 vinn7
HD66773R rev.1.10, jun.21.20 03, page 94 of 133 relationship between ram data and output level the relationship between the ram data and the source output level is as follows. ne g ative polarity positive polarit y sn vcom relationship between ram data and source output level ram data out p ut level v0 v31 negative polarity positive polarity g pixel data 000000 r,b pixel data 00000 g pixel data 111111 r,b pixel data 11111 relationship between vcom and source output level
HD66773R rev.1.10, jun.21.20 03, page 95 of 133 8-color display mode the HD66773R incorporates 8-color display mode. the available grayscale levels are v0 and v31, and the voltages for the other levels (v1-v30) are halted to reduce power consumption. the -fine-adjustment registers, pkp0-pkp5 and pkn0-pkn5 are not available in the 8-color display mode. since the power supply for the levels v1-v30 are halted, r and b data in gram should be set to either ?00000? or ?11111? and g data in gram to either ?000000? or ?111111? before setting this mode so that v0 or v31 is selected. r 3 r 2 r 1 g 2 g 1 g 0 b 3 b 2 display dat a msb lsb graphics ram (gram ) r 0 g 3 b 1 b 0 b 4 g 4 g 5 r 4 2 grayscale cont rol 6 6 6 lcd driver lcd driver lcd driver rg b lcd 8 v0 v31 2 grayscale amplifier 2 grayscale control 2 grayscale cont rol data expansion circuit r 3 r 2 r 1 r 0 r 4 r 5 data expansion circuit b 3 b 2 b 1 b 0 b 4 b 5 nagative polarity register pkn 01 pkn 00 pkn 11 pkn 10 pkn 21 pkn 20 pkn 31 pkn 30 pkn 41 pkn 40 pkn 51 pkn 50 pkn 32 pkn 42 pkn 52 pkn 12 pkn 22 pkn 02 prn01 prn00 prn11 prn10 prn12 prn02 positive polarity register pkp 01 pkp 00 pkp 11 pkp 10 pkp 21 pkp 20 pkp 31 pkp 30 pkp 41 pkp 40 pkp 51 pkp 50 pkp 32 pkp 42 pkp 52 pkp 12 pkp 22 pkp 0 2 prp 01 prp 00 prp 11 prp 10 prp 12 prp 0 2 vrp00 vrp10 vrp01 vrp11 vrp02 vrp12 vrp03 vrp13 vrp1 4 vrn00 vrn10 vrn01 vrn11 vrn02 vrn12 vrn03 vrn13 vrn1 4
HD66773R rev.1.10, jun.21.20 03, page 96 of 133 to switch between the 262, 144-color mode and the 8-color mode, make settings according to the following sequences. 262,144 colors 8 colors wait (2 frame or more) 8 colors 262,144 colors display off gon = "1" dte = "1" d1-0 = "10", dit = "0" wait (2 frame or more) wait (2 frame or more) wait (2 frame or more) wait (2 frame or more) wait (2 frame or more) wait (2 frame or more) wait (2 frame or more) display off gon = "1" dte = "1" d1-0 = "10", dit = "1" display off gon = "1" dte = "0" d1-0 = "10", dit = "0" display off gon = "1" dte = "0" d1-0 = "10", dit = "1" display off gon = "0" dte = "0" d1-0 = "00", dit = "0" display off gon = "0" dte = "0" d1-0 = "00", dit = "1" display off gon = "0" dte = "0" d1-0 = "01", dit = "0" display off gon = "0" dte = "0" d1-0 = "01", dit = "1" display off gon = "1" dte = "0" d1-0 = "01", dit = "0" display off gon = "1" dte = "0" d1-0 = "01", dit = "1" display off gon = "1" dte = "0" d1-0 = "11", dit = "0" display off gon = "1" dte = "0" d1-0 = "11", dit = "1" display off gon = "1" dte = "1" d1-0 = "11", dit = "0" display off gon = "1" dte = "1" d1-0 = "11", dit = "1" ram setting ram setting cl = "1" cl = "0" wait (40ms or more) wait (40ms or more) 8-color mode display 262,141-color mode display
HD66773R rev.1.10, jun.21.20 03, page 97 of 133 instruction setting flow make the setting for each instructio n according to the following sequence. display on/off display off display on eq = 0 display off gon = ?1? dte = ?1? d1-0 = ?10? wait (2 frames or more) display off gon =?1? dte = ?0? d1-0 = ?10? display off gon =?0? dte = ?0? d1-0 = ?00? display on gon = ?0? dte = ?0? d1-0 = ?01? display on gon =?1? dte = ?0? d1-0 = ?11? display on gon =?1? dte = ?1? d1-0 = ?11? power on sequence see note 1 display on gon =?1? dte = ?0? d1-0 = ?01? di splay on display off power off sequence see note 2) wait (2 frames or more) wait (2 frames or more) wait (2 frames or more) to display on flow to display off flow note 1) see page 99, "power supply setting flow". execute the power on sequence. note 2) see page 99, "power supply setting flow". execute the power off sequence.
HD66773R rev.1.10, jun.21.20 03, page 98 of 133 standby and sleep standby set standby(stb = "1") oscillation start wa it 10 ms set standby release standby display off flow display on flo w sleep set sleep power on sequence note 1) display on flow release sleep set standby(stb = "0") release sleep (slp = "0") note 1) see page 99, "power supply setting flow". execute the power on sequence. note 2) see page 99, "power supply setting flow". execute the power off sequence. power supply off sequence note 2) set sleep (slp = "1") display off flow power supply off sequence note 2) power on sequence note 1)
HD66773R rev.1.10, jun.21.20 03, page 99 of 133 power supply setting flow when turning on the power supply, follow the sequence below. the stabilization time for the oscillation circuits, st ep-up circuits, and operation amplifiers may vary depending on the external resistors and capacitors. fo r no rmal display off power off (vcc off) 1ms 10ms or mor e 40ms or more 40ms or mor 100ms or mor e power on sequence power off sequence time for oscillation circuit to stabilize sequence display off display display-on bit dte = "1", d1-0 = "11" gon = "1" display-off bit dte = "0", d1-0 = "00" gon = "0" step-up2, amp halt setting bit bt2-0="000", ap2-0="000" time for step-up circuits 1,2 to stabilize power on (vcc on) time for step-up circuit 4 to stabilize time for step-up circuits & ope-amps to stabilize display-off bit dte = "0", d1-0 = "00" gon = "0", pon = "0", vcomg = "0" power-initialization setting bit set vc2-0, vrh3-0, cad, vrl3-0, vcm4-0, vdv4-0 power-operation start setting bit set bt2-0, dc2-0, ap2-0 step-up circuit 4 operation start setting bit set vcomg = "1" (not required if vcoml = gnd) step-up circuit 3 operation start setting bit set pon = "1" display-on bit dte = "1", d1-0 = "11" gon = "1" power-on reset & display off issue instruction (3) for power setting issue instruction (1) for power setting issue instruction (2) for power setting issue instruction (3) for power setting issue instruction (4) for power setting issue instruction for other mode settings display-on sequence display on step-up1 halt setting bit bt2-0 ="110" issue instruction (1) for power setting step-up3,4 halt setting bit pon="0", vcomg="0" issue instruction (2) for power setting wait 100ms or more power on sequence power off sequence
HD66773R rev.1.10, jun.21.20 03, page 100 of 133 oscillation circuit osc1 osc2 clock HD66773R damping resistor ( 2k ) osc1 osc2 rf hd66773 r osc1 osc2 rf hd 66773 r other wiring place the rf oscillation resistor as close as possible to the osc1, osc2 pins. do not arrange other wiring beneath osc1-osc2 wiring to avoid effects from coupling. place the rf resistor as close as possible to the osc1, osc2 pins 2) external resistor oscillation mode 1) external clock mode
HD66773R rev.1.10, jun.21.20 03, page 101 of 133 n-raster-row inversion ac drive the HD66773R, in addition to lcd inversion ac drive by frame, supports n-raster-row inversion ac drive where alternation occurs by n raster-rows, where n takes a number between 1 to 64. the n-raster-row inversion ac drive allows overcoming th e problems related to display quality. in determining n (the value set in the nw bit +1), the number of raster-rows by which alternation occurs, check the display quality on the actual liquid crystal pa nel. setting a small number of raster-rows will raise the ac frequency of the liquid crystal and increase th e charge/discharge current on the liquid crystal cells. 12 3 184 frame ac waveform drive 176-raster-row drive n-raster-row ac waveform drive 176-raster-row drive 3-raster-row inversion eor - "1" / 1 frame 1 frame 123 176 184 176 blank period blank period 12 44 175 175 make sure that eor = "1" in n-raster-row drive to prevent the direct bias on liquid crystal.
HD66773R rev.1.10, jun.21.20 03, page 102 of 133 interlaced drive the HD66773R supports interlaced drive, which divide one frame into n fields and then drive to prevent flickers. to determine the number of fields (n: value set in the fld bits), check the display quality on the actual liquid crystal panel. the following table shows the gate selection for each number of fields, 1 to 3. the figure illustrates the output waveforms of the 3-field interlaced drive. gate selection gs = 0 gs = 1 fld1-0 01 11 fld1-0 01 11 field gate - 1 2 3 field gate -123 g1 oo g176 oo g2 oo g175 oo g3oog174oo g4 oo g173 oo g5 oo g172 oo g6oog171oo g7 oo g170 oo g8 oo g169 oo g9oog168oo ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? g173 oo g4 oo g174oog3 oo g175 oo g2 oo g176 oo g1 oo
HD66773R rev.1.10, jun.21.20 03, page 103 of 133 a c polarit y g1 g2 g3 g4 g5 g6 1 frame field (1) (2) (3) (1) g3n+1 g3n+2 g3n+3 blank period field field field gate output timing during 3-field interlaced drive
HD66773R rev.1.10, jun.21.20 03, page 104 of 133 ac timing the ac timings of frame inversion ac drive, 3-field interlaced drive, and n-raster-row inversion drive are illustrated as follows. in case of frame inversion ac dr ive, alternation occurs at the completion of drawing one frame, followed by a blank, which lasts for 16h periods. ac timing the ac timings of frame inversion ac drive, 3-field interlaced drive, and n-raster-row inversion drive are illustrated as follows. in case of frame inversion ac dr ive, alternation occurs at the completion of drawing one frame, followed by a blank, which lasts for 8h periods. in this case, all the outputs from the gate are vgoff outputs. in case of interlaced drive, altern ation occurs at the completion of drawing one field, followed by a blank. the total period of the blanks in one frame amounts to 8 period. in case of n-raster- row, a blank lasting 8h period is inserted after drawing a full screen. n-raster-row inversion ac drive a /c timing frame inversion ac drive frame 1 blank period blank period = 8h perio d a /c 3-field interlace drive field 1 field 3 field 2 blank period 1 blank period 2 blank period 3 a /c a /c blank period = blank period 1 + blank period 2 + blank period 3 =8h period n-raster-row blank period blank period =8h period 1 frame per iod 1 frame per iod 1 frame per iod a /c a /c a /c a /c a /c a /c a /c a /c a /c a /c a /c a /c n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row
HD66773R rev.1.10, jun.21.20 03, page 105 of 133 frame-frequency adjustment function the HD66773R incorporates frame frequency adjustment function. the frame frequency during the liquid crystal drive is adjusted by the instruction setting (d iv, rtn) while keeping the oscillation frequency fixed. setting the oscillation frequency high in advance allows switching the frame frequ ency in accordance to the kind of picture to be displayed (i.e. moving/still pict ure). when displaying a still picture, set the frame frequency low to save power consum ption, while setting the frame frequency high for displaying a moving picture which requires high-speed switching of screens. relationship between liquid crysta l drive duty and frame frequency the relationship between the liquid crystal drive du ty and the frame frequency is calculated by the following formula. the frame frequency is adju sted through instruction se tting with the 1-h period adjustment bit (rtn bit) and the operation clock division bit (div bit). (formula for the frame frequency) fosc frame frequency = [hz] clock cycles per raster-row division ratio (line+8) fosc: r-c oscillation frequency line: number of drive raster-rows (nl bit) clock cycles per raster-row: rtn bit division ratio: div bit calculation example the maximum frame frequency = 60 hz number of drive raster-rows: 176 1-h period: 16 clock cycles (rtn3-0 = 0000) operation clock division ratio: 1 division fosc = 60 hz (0 + 16) clock 1 division (176 + 8) lines = 177 (khz) in this case, the r-c oscillation frequency becomes 177 khz. adjust the resistance of external resistor for the r-c oscillator to177 khz.
HD66773R rev.1.10, jun.21.20 03, page 106 of 133 screen -split drive function the HD66773R allows selectively driving two screens at arbitrary positions with the screen-drive position registers (r42 and r43). only the raster-rows requi red to display two screens at arbitrary positions are selectively driven to reduce power consumption. the first screen drive position register (r42) specifi es the start line (ss17-10) and the end line (se17-10) for displaying the first screen. the second screen drive position register (r43 ) specifies the start line (ss27-20) and the end line (se27-20) for displaying the second screen. the second screen control is effective when the spt bit is set to 1. the total num ber of raster-rows driven for displaying the first and second screens must be less than the number of liquid crystal drive raster-rows. g1 g26 g7 g42 non-display area 1st screen: 7 raster-row driving 2nd screen: 17 raster-row driving non-display are a driven raster-rows: nl4-0 = "10101" (176 raster-rows) first screen setting : ss17-10 = "00"h, se17-10 - "06"h second screen setting : ss27-20 = "19"h, se27-20 - "29"h, spt = "1"
HD66773R rev.1.10, jun.21.20 03, page 107 of 133 conditions on setting the 1st/2n d screen drive position register when making settings for the start line (ss17-10) and end line (se17-10) of the first screen drive position register (r42), and the start line (ss27-20) and end line (se27-20) of the second screen drive position register (r43) with the HD66773R, it is necessary to satisfy the following conditions to display screens correctly. one-screen drive (spt = 0) register settings display operation (se17-10) - (ss17-10) = nl full screen display the area of (se17-10) - (ss 17-10) is normally displayed. (se17-10) - (ss17-10) < nl partial screen display the area of (se17-10) - (ss 17-10) is normally displayed. the rest of the area is white disp lay irrespective of data in ram. (se17-10) - (ss17-10) > nl setting disabled note 1) ss17-10 se17-0 ?af?h note 2) setting disabled for ss27-20 and se27-20. two-screen drive (spt = 1) register settings display operation ((se17-10) - (ss17-10)) + ((se27-20) - (ss27-20)) = nl full screen display the area of (se27-20) - (ss 17-10) is normally displayed. ((se17-10) - (ss17-10)) + ((se27-20) - (s27-20)) < nl partial screen display the area of (se27-10) - (ss 17-10) is normally displayed. the rest of the area is white disp lay irrespective of data in ram. ((se17-10) - (ss17-10)) + ((se27-20) - (ss27-20)) > nl setting disabled note 1) make sure that ss17-10 se17-10 < ss27-20 se27-20 ?af?h. note 2) make sure that ((se27-20) - (ss17-10)) nl. the setting for the driver output in the non-display ar ea during the partial display is changeable according to the characteristics of the display panel. source outputs in non-display area source output for non-display area pt1 pt0 positive polarity negative polarity source output for non-display area 0 0 v31 v0 normal drive 0 1 v31 v0 vgoff 1 0 gnd gnd vgoff 1 1 high-z high-z vgoff
HD66773R rev.1.10, jun.21.20 03, page 108 of 133 to make a setting for the partial display, follow the sequence below. full screen displa y pt1 ? 0 = 0 0 set ss/se bits wait (more than 2 fram es) pt1 ? 0 = 01 or pt1 ? 0 = 10 or pt1 ? 0 = 1 1 partial disp lay on set ss/se bits full screen disp lay screen division drive set u p flow full screen drive set u p flo w set if necessary
HD66773R rev.1.10, jun.21.20 03, page 109 of 133 internal configuration of power generation circuit the internal configuration of power generation circuit of HD66773R is as follows. the step-up circuit is comprised of the step-up circuit 1 which boost 2 to 3 times the voltage supplied with vci1, the step-up circuit 2 which further boost 2 to 4 times the voltage boosted by the step-up circuit 1, the step-up circuit 3 which invert the vgh-level voltage with the gnd leve l as the axis and output the vgl-level voltage, and the step-up circuit 4 which invert the vci-level voltage with the gnd level as the axis and output the vcl- level voltage. the step-up circuit generates the vo ltage to drive a tft lcd. reference voltagea vdh, vcom and vgoff for the grayscale voltage are generated either by being adjusted in the internal voltage adjustment circuit or from the voltage at regp, which is amplified in the amplifiers 1, 2. the vcom, vgoff voltages can alternate at an arbitrary voltage level. vcom must be connected to the panel.
HD66773R rev.1.10, jun.21.20 03, page 110 of 133 amplifier 2 vgoff adjustment ampifier 1 vdh adjustment vreg2 out vreg1 out vciout output amplifier volume adjsutment circuit vci vci vcomh adjustment circuit grayscale voltage generating circuit v0p v0n v31p v31n step-up circuit 1 step-up circuit 2 step-up circuit 3 step-up circuit 4 vcomr vci1 c11- c11+ c12- c12+ ddvdh vci2 c21- c21+ c22- c22+ c23- c23+ vgh vci3 c31- c31+ vg l adjustment circuit source driver vcomh output am p lifier vcom l output amp lifier vgoff amplitude adjustment circuit vgoffh output amplifier vgoffl output am p lifier vci n ote 2 n ote 2 n ote1 regp v ci vci hd66773 r vmoni vcomh vcom vcom l vgoffh vgoffout gate driver vgoff vgoffl testa1 testa 2 testa 3 testa 4 vcc gnd vci gnd *in case of using vciout output amplifier *vcomh voltage adjustment (with external resistors) note 1) use a capacitor of 0.1 f (b characteristics). other capacitors must be 1 f (b characteristics). connect stabilizing capacitors to testa1 ~ testa4 depending on the display quality or power consumption. note 2) place a shot key barrier diode (vf = 0.4v/around 20ma, vr >= 30v vci4 c41- c41+ vc l vcom amplitude adjustment circuit internal configuration of power supply circuit
HD66773R rev.1.10, jun.21.20 03, page 111 of 133 specification of external elements connected to HD66773R the following table shows specifica tions of external elements conn ected to HD66773R power supply. capacitor capacity recommended voltage connect pins 6v vreg1out, vci1, c41-/+ note 1) ,vcl note 1) , vcomh, vcoml note 1) 10v ddvdh, c11+/-, c12+/-, c21+/-, c22+/-, c23+/- 1 f (b characteristic) 25v vreg2out, vgh, vgl, c31-/+, vgoffh note 1) , vgoffl 0.1 f (b characteristic) 25v (testa3) note 2) 0.1 f (b characteristic) 6v v0p, v0n, v31p, v31n, (testa4) note 2) note 1) these pins may not be required for some mode setting. note 2) connect to a stabilizing capacitor depend ing on the display quality or power consumption.
HD66773R rev.1.10, jun.21.20 03, page 112 of 133 pattern diagram for voltage setting the following figures are the pattern diagram of voltage setting for the hd66733r and the voltage waveforms. vgh(+9~16.5v) gnd ( 0v vcc (2.2~ 3.3v) vci (2.5~ 3.3v ) vc2-0 vrl3-0 vdv4-0 ( -1 ) vci1 bt2-0 bt2-0 ( x -1) ddvdh(+4.5 ~ 5.5v) vrh3-0 vcm4-0 vc l vg l vgh note: the relationships ddvdh-vreg1out>0.5v, vcoml-vcl>0.5v, vgoff-vgl>0.5v are changeable depeinding on the load on the panel to be driven. make an appropriate setting for the voltage. it is possible to directly imput vci to vci1. vgh vcomh vcoml vgoffh v g off l sn ddvdh vreg1out(3.0 ~ ddvdh+0.5v) vcomh(3.0 ~ vreg1out) vcoml(vcl+0.5 ~ 1.0v) vcl(- 3.6 ~ 2.5v) vgoffh(vgl+4.0 ~ 5.0v) vgoffl(vgl+0.5 ~ 5.0v) vgl(- 9 ~ -16.5v) vreg1out vreg2out gn vcom vreg1out
HD66773R rev.1.10, jun.21.20 03, page 113 of 133 absolute maximum ratings item symbol unit value notes power supply voltage (1) vcc v -0.3 ~ + 4.6 1, 2 power supply voltage (2) vci - gnd v -0.3 ~ + 4.6 1, 2 power supply voltage (3) ddvdh - gnd v -0.3 ~ + 6.0 1, 2 power supply voltage (4) gnd -vcl v -0.3 ~ + 4.6 1, 2 power supply voltage (5) ddvdh - vcl v -0.3 ~ + 9.0 1 power supply voltage (6) vgh - gnd v -0.3 ~ + 18.5 1, 2 power supply voltage (7) gnd - vgl v -0.3 ~ + 18.5 1, 2 input voltage vt v -0.3 ~ vcc + 0.3 1 operating temperature topr c -40 ~ + 85 1, 3 storage temperature tstg c -55 ~ + 110 1 note 1) the lsi may be permanently damaged if it is used under the condition exceeding the above absolute maximum ratings. it is also recommended to use the lsi within the limit of its electric characteristics during normal operation. exceedi ng the conditions may lead to malfunction of lsi and affect its credibility. note 2) the voltage from gnd. note 3) the dc and ac characteristics of chip and wafer products are guaranteed at 85 c.
HD66773R rev.1.10, jun.21.20 03, page 114 of 133 electric characteristics dc characteristics (v cc = 1.8 to 3.7 v, ta = ?40 ~ +85c note 1 ) item symbol unit test condition min typ max notes input high voltage v ih vv cc = 2.2 to 3.3 v 0.7 v cc ?v cc 2, 3 input low voltage (1) (osc1 pin) v il1 vv cc = 2.2 to 3.3 v ?0.3 ? 0.15v cc 2, 3 v cc = 2.2 to 2.4 v ?0.3 ? 0.15v cc 2, 3 input low voltage (2) (except osc1 pin) v il2 v vcc = 2.4 to 3.3v ?0.3 ? 0.2 v cc 2, 3 output high voltage (1) (db0-17 pins) v oh1 v i0h = -0.1ma -0.75vcc ? ? 2 vcc = 2.2v to 2.4v, i ol =0.1ma ? ? 0.2vcc 2 output low voltage (1) (db0-17 pins) v ol1 v vcc = 2.4v to 3.3v, i ol =0.1ma ? ? 0.15vc c 2 i/o leakage current i li a vin = 0 to vcc - 1 ? 1 4 current consumption during normal operation (vcc ? gnd) i op a ? 90 200 5 current consumption during normal operation (vci ? gnd) i ci ma ta = 25c, 260,000 colors display, vcc = 3v, cr oscillation; fosc = 176khz (176 line drive), ram data: 0000h, ap=001, cad=1, vcomg=1 vci1 = 0.92 x vci (vc2-0 = 001), ddvdh = 2 x vci1, vgh = 3 x vci2 (bt2-0 = 000), step up circuit 1 = 60 divided cycle, step up circuit 2, 3, and 4 = 240 divided cycle (dc2-0 = 000), vreg1out = regp x 1.65 = 4.55v, (vrh = 0011) vcomh = vreg1out x 0.76 = 3.46v, (vcm = 10011), vcoml = 3.46 ? (vreg1out x 1.23) = -2.13v, (vdv = 10110), vreg2out = vci x ? 5.5 = -16.5v, (vrl = 1001), vgoffl = -16.5v, vgoffh = - 16.5v + 5.59v = -10.9v ? 1.25 1.5 5 vcc = 3v, ta <=50 c?0.15 current consumption during standby mode (vcc ? gnd) i st a vcc = 3v, ta >50 c??20 5 output voltage difference ? vo m v? ? 5 ? 6 average output voltage fluctuation ? v m v? ? ? 35 7
HD66773R rev.1.10, jun.21.20 03, page 115 of 133 ac characteristics (v cc = 2.2 to 3.3 v, ta = ?40 to +85c* 1 ) clock characteristics (v cc = 2.2 to 3.3 v) item symbol unit test condition min typ max notes external clock frequency fcp khz v cc = 2.2 to 3.3 v 100 176 600 8 external clock duty ratio duty % v cc = 2.2 to 3.3 v 45 50 55 8 external clock rise time trcp s v cc = 2.2 to 3.3 v ? ? 0.2 8 external clock fall time tfcp s v cc = 2.2 to 3.3 v ? ? 0.2 8 r-c oscillation clock f osc khz rf = 240k ? , v cc = 3 v 184 229 274 9
HD66773R rev.1.10, jun.21.20 03, page 116 of 133 68system bus interface timing characteristics normal write mode (hwm=0) (vcc = 2.2 to 2.4 v) item symbol unit timing diagram min typ max enable cycle time write ns figure 1 600 ? ? read t cyce ns figure 1 800 ? ? write 90 ? ? enable ?high? level pulse width read pw eh ns figure 1 350 ? ? write 300 ? ? enable ?low? level pulse width read pw el ns figure 1 400 ? ? inable rising and falling time t er, t ef ns figure 1 ? ? 25 set up time (rs, r/w, to e, cs*) t ase ns figure 1 10 ? ? address hold time t ahe ns figure 1 5 ? ? write data set up time t dswe ns figure 1 60 ? ? write data hold time t he ns figure 1 15 ? ? read data delay time t ddre ns figure 1 ? ? 200 read data hold time t dhre ns figure 1 5 ? ? high-speed write mode (hwm=1) (vcc = 2.2 to 2.4 v) item symbol unit timing diagram min typ max enable cycle time write ns figure 1 200 ? ? read t cyce ns figure 1 800 ? ? write 90 ? ? enable ?high? level pulse width read pw eh ns figure 1 350 ? ? write 90 ? ? enable ?low? level pulse width read pw el ns figure 1 400 ? ? inable rising and falling time t er, t ef ns figure 1 ? ? 25 set up time (rs, r/w, to e, cs*) t ase ns figure 1 10 ? ? address hold time t ahe ns figure 1 5 ? ? write data set up time t dswe ns figure 1 60 ? ? write data hold time t he ns figure 1 15 ? ? read data delay time t ddre ns figure 1 ? ? 200 read data hold time t dhre ns figure 1 5 ? ?
HD66773R rev.1.10, jun.21.20 03, page 117 of 133 normal write mode (hwm=0) (vcc = 2.4 to 3.3 v) item symbol unit timing diagram min typ max note enable cycle time write ns figure 1 200 ? ? ? read t cyce ns figure 1 300 ? ? ? write 40 ? ? ? enable ?high? level pulse width read pw eh ns figure 1 150 ? ? ? write 100 ? ? ? enable ?low? level pulse width read pw el ns figure 1 100 ? ? ? inable rising and falling time t er, t ef ns figure 1 ? ? 25 10 ? ? with status read set up time (rs, r/w, to e, cs*) t ase ns figure 1 0 ? ? without status read address hold time t ahe ns figure 1 2 ? ? ? write data set up time t dswe ns figure 1 60 ? ? ? write data hold time t he ns figure 1 2 ? ? ? read data delay time t ddre ns figure 1 ? ? 100 ? read data hold time t dhre ns figure 1 5 ? ? ? high-speed write mode (hwm=1) (vcc = 2.4 to 3.3 v) item symbol unit timing diagram min typ max note enable cycle time write ns figure 1 100 ? ? read t cyce ns figure 1 300 ? ? write 40 ? ? enable ?high? level pulse width read pw eh ns figure 1 figure 1 150 ? ? write 40 ? ? enable ?low? level pulse width read pw el ns figure 1 figure 1 100 ? ? inable rising and falling time t er, t ef ns figure 1 ? ? 25 10 ? ? with status read set up time (rs, r/w, to e, cs*) t ase ns figure 1 0 without status read address hold time t ahe ns figure 1 2 ? ? write data set up time t dswe ns figure 1 60 ? ? write data hold time t he ns figure 1 2 ? ? read data delay time t ddre ns figure 1 ? ? 100 read data hold time t dhre ns figure 1 5 ? ?
HD66773R rev.1.10, jun.21.20 03, page 118 of 133 80-system bus interface timing characteristics normal write mode (hwm=0) (vcc = 2.2 to 2.4 v) item symbol unit timing diagram min typ max bus cycle time write t cycw ns figure 2 600 ? ? read t cycr ns figure 2 800 ? ? write low-level pulse width pw lw ns figure 2 90 ? ? read low-level pulse width pw lr ns figure 2 350 ? ? write high-level pulse width pw hw ns figure 2 300 ? ? read high-level pulse width pw hr ns figure 2 400 ? ? write/read rise/fall time t wrr, wrf ns figure 2 ? ? 25 setup time (rs to cs*, wr*, rd*) t as ns figure 2 10 ? ? address hold time t ah ns figure 2 5 ? ? write data set up time t dsw ns figure 2 60 ? ? write data hold time t hwr ns figure 2 15 ? ? read data delay time t ddr ns figure 2 ? ? 200 read data hold time t dhr ns figure 2 5 ? ? high-speed write mode (hwm=1) (vcc = 2.2 to 2.4 v) item symbol unit timing diagram min typ max bus cycle time write t cycw ns figure 2 200 ? ? read t cycr ns figure 2 800 ? ? write low-level pulse width pw lw ns figure 2 90 ? ? read low-level pulse width pw lr ns figure 2 350 ? ? write high-level pulse width pw hw ns figure 2 90 ? ? read high-level pulse width pw hr ns figure 2 400 ? ? write/read rise/fall time t wrr, wrf ns figure 2 ? ? 25 set up time (rs to cs*, wr*, rd*) t as ns figure 2 10 ? ? address hold time t ah ns figure 2 5 ? ? write data set up time t dsw ns figure 2 60 ? ? write data hold time t hwr ns figure 2 15 ? ? read data delay time t ddr ns figure 2 ? ? 200 read data hold time t dhr ns figure 2 5 ? ?
HD66773R rev.1.10, jun.21.20 03, page 119 of 133 normal write mode (hwm=0) (vcc = 2.4 to 3.3 v) item symbol unit timing diagram min typ max notes bus cycle time write t cycw ns figure 2 200 ? ? read t cycr ns figure 2 300 ? ? write low-level pulse width pw lw ns figure 2 40 ? ? read low-level pulse width pw lr ns figure 2 150 ? ? write high-level pulse width pw hw ns figure 2 100 ? ? read high-level pulse width pw hr ns figure 2 100 ? ? write/read rise/fall time t wrr , wrf ns figure 2 ??25 10 ? ? with status read set up time (rs to cs*, wr*, rd*) t as ns figure 2 figure 2 0?? without status read address hold time t ah ns figure 2 2?? write data setup time t dsw ns figure 2 60 ? ? write data hold time t hwr ns figure 2 2?? read data delay time t ddr ns figure 2 ? ? 100 read data hold time t dhr ns figure 2 5?? high-speed write mode (hwm=1) (vcc = 2.4 to 3.3 v) item symbol unit timing diagram min typ max notes bus cycle time write t cycw ns figure 2 100 ? ? read t cycr ns figure 2 300 ? ? write low-level pulse width pw lw ns figure 2 40 ? ? read low-level pulse width pw lr ns figure 2 150 ? ? write high -level pulse width pw hw ns figure 2 40 ? ? read high -level pulse width pw hr ns figure 2 100 ? ? write/read rise/fall time t wrr , wrf ns figure 2 ??25 10 ? ? with status read set up time (rs to cs*, wr*, rd*) t as ns figure 2 figure 2 0 without status read address hold time t ah ns figure 2 2?? write data set up time t dsw ns figure 2 60 ? ? write data hold time t hwr ns figure 2 2?? read data delay time t ddr ns figure 2 ? ? 100 read data hold time t dhr ns figure 2 5??
HD66773R rev.1.10, jun.21.20 03, page 120 of 133 serial peripheral interfa ce timing characteristics (vcc = 2.2v to 2.4v) item symbol unit timing diagram min typ max write (received) t scyc us figure 3 0.1 ? 20 serial clock cycle time read (transmitted) t scyc us figure 3 0.25 ? 20 write (received) t sch ns figure 3 40 ? ? serial clock hith-level pulse width read (transmitted) t sch ns figure 3 120 ? ? write (received) t scl ns figure 3 40 ? ? serial clock low-level pulse width read (transmitted) t scl ns figure 3 120 ? ? serial clock rise/fall time t scr, t scf ns figure 3 ? ? 20 chip select set up time t csu ns figure 3 20 ? ? chip select hold time t ch ns figure 3 60 ? ? serial input data set up time t sisu ns figure 3 30 ? ? serial input data hold time t sih ns figure 3 30 ? ? serial output data delay time t sod ns figure 3 ? ? 130 serial output data hold time t soh ns figure 3 5 ? ? (vcc = 2.4v to 3.3v) item symbol unit timing diagram min typ max write (received) t scyc us figure 3 0.076 ? 20 serial clock cycle time read (transmitted) t scyc us figure 3 0.15 ? 20 write (received) t sch ns figure 3 40 ? ? serial clock hith-level pulse width read (transmitted) t sch ns figure 3 70 ? ? write (received) t scl ns figure 3 35 ? ? serial clock low-level pulse width read (transmitted) t scl ns figure 3 70 ? ? serial clock rise/fall time t scr, t scf ns figure 3 ? ? 20 chip select set up time t csu ns figure 3 20 ? ? chip select hold time t ch ns figure 3 60 ? ? serial input data set up time t sisu ns figure 3 30 ? ? serial input data hold time t sih ns figure 3 30 ? ? serial output data delay time t sod ns figure 3 ? ? 130 serial output data hold time t soh ns figure 3 5 ? ? reset timing characteristics (v cc = 2.2 to 3.3 v) item symbol unit timing diagram min typ max reset low-level width t res ms figure 4 1 ? ? reset rise time t rres s figure 4 ? ? 10
HD66773R rev.1.10, jun.21.20 03, page 121 of 133 notes to electrical characteristics 1. the dc/ac electrical characteristics of bare die and wafer products are guaranteed at 85 c. 2. the following figures illustrate the configurations of i pin, i/o pin, and o pin. pins: reset*, cs*, e/wr/scl, rw/rd, rs, osc1, im3-1, im0/id, test1, test2, testv1, dctest v cc pmos nmos gnd pins: osc2 vcc pmos nmos gnd pins: db17 -db2, db1/sd0, db0/sdi gnd pmos output enable (input circuit ) vcc nmos (output circuit: 3 states) vcc pmos nmos output data
HD66773R rev.1.10, jun.21.20 03, page 122 of 133 3. test, im1, im0/id pins must be grounded or connected to vcc. 4. this excludes the curren t through output drive mos. 5. this excludes the current through the input/output units. the input level must be fixed to a certain level because penetrating current increases in the input circuit when cmos input level takes a middle level. the current consumption is unchanged irrespective of ?high? or ?low? of cs*pin while the HD66773R is not accessed through interface pins. 6. the output voltage difference is the difference in the voltages of neighboring source outputs for a same display (within a chip). this value is just for a referential purpose. 7. the average output voltage fluctuation is the diff erence in the average source output voltages among different chips. the average output voltage is an average source voltage within a chip for a same display. 8. this applies to the case when clocks are supplied externally. duty = th 100% th+ tl x o scillator trcp tfc p 0.7vcc 0.5vcc 0.3vcc osc1 open osc2 2k 9. this applies to the internal oscillator when external oscillation resistor rf is used. osc1 osc2 rf the oscillation frequency may change according to the capacitors of osc1 and osc2 pins. connect the osc1 and osc2 pins with the possible shortes t wiring.
HD66773R rev.1.10, jun.21.20 03, page 123 of 133 referential data oscillation resistance (k ? ) vcc = 1.8 v vcc = 2.0 v vcc = 2.4 v vcc = 3.0v vcc = 3.3v 110k ? 329.6 362.6 399.4 438.5 447.6 150k ? 260.7 285.4 313.3 337.4 343.4 180k ? 230.9 252.2 274.0 294.9 302.1 200 k ? 213.0 230.4 251.5 268.7 274.8 240 k ? 187.7 201.3 216.8 229.4 234.8 270 k ? 168.6 181.3 195.1 206.9 210.2 300 k ? 154.5 166.1 178.2 187.5 191.1 390 k ? 125.4 133.7 142.3 148.9 151.6 430 k ? 115.9 121.6 129.0 135.2 137.3
HD66773R rev.1.10, jun.21.20 03, page 124 of 133 vci adjustment circuit ? load characteristics step- up1 ? load characteristics step- up2 ? load characteristics vci1 [v] load current [ma] 3.0 2.8 2.6 2.4 2.2 2.0 1.8 0.0 0. 3 0.6 0.9 1.2 1. 5 vci1 = 1.00 x vci vci1 = 0.92 x vci vci1 = 0.87 x vci vci1 = 0.83 x vci vci1 = 0.76 x vci vci1 = 0.73 x vci vci1 = 0.68 x vci conditions typ, room temperature vcc = vci = 3.0v, fosc = 240khz ap = 011 medium current m ode 5.5 5.3 5.1 4.9 4.7 4. 5 load current [ma] 0.0 0. 3 0.6 0.9 1.2 1.5 ddvdh [v] 1/16 cycle 1/32 cycle 1/64 cycle conditions typ, room temperature vcc = vci = 3.0v, fosc = 240khz, ap = 011 medium current mode vci1 = 0.92 x vc i, load current [ma] 17 16 15 14 13 12 11 0 100 200 300 400 vgh [v ] 1/64 cycle 1/124 cycle 1/256 cycle conditions typ, room temperature vcc = vci = 3.0v, fosc = 240khz ap = 011 medium current mode vci1 = 0.92 x vci, step up1: x2 (1/32 cycle) step up 2: x3 step-up 1 : x2
HD66773R rev.1.10, jun.21.20 03, page 125 of 133 step- up3 ? load characteristics step-up 4 ? load ch aracteristics - 16 - 15 - 14 -13 - 12 - 1 1 load current [ma] 0 10 0 200 300 400 vgl [v ] 1/64 cycle conditions typ, room temperature vcc = vci = 3.0v, fosc = 240khz ap = 011 medium current mode vci1 = 0.92 x vci, step up1: x2 (1/32 cycle) st ep up 2: x3 - 3.0 - 2.8 - 2.6 -2.4 - 2. 2 load current [ma] 0 10 0 200 300 400 vgl [v ] 1/128 cycle 1/256 cycle 1/64 cycle 1/128 cycle 1/256 cycle conditions typ, room temperature vcc = vci = 3.0v, fosc = 240khz ap = 011 medium current mode vci1 = 0.92 x vci, step up1: x2 (1/32 cycle) step up 2: x3
HD66773R rev.1.10, jun.21.20 03, page 126 of 133 current consumption - frame frequency dependence current consumption ? write cycle dependency 1.6 1.4 1.2 1.0 0.8 0.6 0. 4 frame frequency [hz] 60 80 100 120 140 current consumption [m a] normal display 8-color di spla y conditions typ, room temperature vcc = vci = 3.0v, fosc = 240khz 176 duty, b waveform ac, ram = h'0000 ap = 001 small current mode vci1 = 0.92 x vci, step up1: x2 (1/64 cycle) step up2: x3 (1/256 cycle) cad mode vreg1out = regp x 1.65 vreg2out = vci x (-5.5), vcomh = vreg1out x 0.76, vcoml = vcomh - (vreg1out x 1.23) 30 25 20 15 10 5 0 normal write high-speed write write cycle [mhz] current consumption [m a] 0 2 4 6 8 1 0 conditions typ, room temperature vcc = vci = 3.0v, fosc = 240khz 176 duty, b waveform ac, ram = h'0000 ap = 001 small current mode vci1 = 0.92 x vci, step up1: x2 (1/64 cycle) step up2: x3 (1/256 cycle) cad mode vreg1out = regp x 1.65 vreg2out = vci x (-5.5), vcomh = vreg1out x 0.76, vcoml = vcomh - (vreg1out x 1.23)
HD66773R rev.1.10, jun.21.20 03, page 127 of 133 data bus: db17 ~ db0 test point 50 pf load circuit for ac characteristics test
HD66773R rev.1.10, jun.21.20 03, page 128 of 133 timing characteristics diagram 68-system bus interface operation rs r/w cs* e db0 to db 17 db0 to db 17 vih vil tase tahe pweh t ef t er t dswe t he wrire data t cyce tddre tdhre voh1 vol1 voh1 vol1 read data vih vil vil vil vih vih vil vih vil vih vil pwel vil vil note 1) note 2) note 2) note 1) pweh is determined by the overlapping period when cs* is "low" and e is "high". note 2) parallel data transfer with db17-0 pins through 18-bit bus interface. parallel data transfer with db17-10, db8-1 pins through 16-bit bus interface. fix unused db9,0 pins to "gnd". parallel data transfer with db17-9 pins through 9-bit bus interface. fix unused db8-0 pins to "gnd". parallel data transfer with db17-10 pins through 8-bit bus interface. fix unused db9-0 pins to "gnd". figure 1
HD66773R rev.1.10, jun.21.20 03, page 129 of 133 80-system bus interface operation cs* twrf twrr tdsw tdhr voh1 vil vih vil rs wr * rd* vih vil vih vil tas tah vil vih pwlw, pwlr pwhw, pwhr tcycw, tcycr vih vih vil vih vil db0 to db 17 db0 to db 17 wrire data read data voh1 vol1 vol1 tddr note 2 note : 2 thwr note1 vih note 1) pweh is determined by the overlapping period when cs* is "low" and e is "high". note 2) parallel data transfer with db17-0 pins through 18-bit bus interface. parallel data transfer with db17-10, db8-1 pins through 16-bit bus interface. fix unused db9,0 pins to "gnd". parallel data transfer with db17-9 pins through 9-bit bus interface. fix unused db8-0 pins to "gnd". parallel data transfer with db17-10 pins through 8-bit bus interface. fix unused db9-0 pins to "gnd". figure 2
HD66773R rev.1.10, jun.21.20 03, page 130 of 133 serial peripheral interface operation tsch tsisu tscr vih vil vih vil vih vil tch vih vil vih vil tscl tsih vil tscyc input data vih start: s end: p sdo voh1 vol1 voh1 vol1 output data output data tsoh tscf vih cs* scl sdi vil vil input data tcsu tsod figure 3 reset operation vil vil t rr es tres vih reset* figure 4
HD66773R rev.1.10, jun.21.20 03, page 131 of 133 insert wiring example
HD66773R rev.1.10, jun.21.20 03, page 132 of 133 keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but ther e is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation p roduct best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporat ion or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, origin ating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reas ons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest produ ct information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracie s or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas te chnology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp oration assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used un der circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor wh en considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or u ndersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com copyright ? 2003. renesas technology corporation, all rights reserved. printed in japan. colophon 0.0
HD66773R rev.1.10, jun.21.20 03, page 133 of 133 revision record rev. date contents of modification drawn by approved by page 112. delete ?db1sd0? and ?db0/sd1? in the figure. 1.01 2003.jan. page 113. change note 6. change ?r1? to ?%rf? in the figure. page 7. add ?or ddvdh?. page 8. error corrections. page 9. error corrections. add descriptions to ?dummy1, 21, 23, 39? and ?dummy 2-21, 24-38?. page 21. specify the instruction accessible during the standby mode: r03h page 73. error correction. page 77. add the power off sequence. page 78. add the power off sequence. page 79. correction to the figure: power off sequence. page 89. change the recommended voltage for test4. page 90. error correction. page 95, 96. error corrections. change figure 1 to figure 2, ?t h ? to ?t hwr ? page 97. error correction. 1.2 2003.jun. page 99. specify the application of notes 6, 7.

▲Up To Search▲

Price & Availability of HD66773R

	To Download HD66773R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .