? semiconductor components industries, llc, 2008 march, 2008 - rev. 0 1 publication order number: NLX1G97/d NLX1G97 configurable multifunction gate the NLX1G97 minigate is an advanced high-speed cmos multifunction gate. the device allows the user to choose logic functions mux, and, or, nand, nor, invert and buffer. the device has schmitt-trigger inputs, thereby enhancing noise immunity. the NLX1G97 input and output structures provide protection when voltages up to 7.0 v are applied, regardless of the supply voltage. features ? high speed: t pd = 3.3 ns (typ) @ v cc = 5.0 v ? low power dissipation: i cc = 1 a (maximum) at t a = 25 c ? power down protection provided on inputs ? balanced propagation delays ? overvoltage tolerant (ovt) input and output pins ? ultra-small packages ? these are pb-free devices http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ordering information (top view) in b gnd in a in c v cc out y pin assignments marking diagrams f = specific device code m = date code 1 2 3 6 5 4 1 1 1 ullga6 1.0 x 1.0 case 613ad ullga6 1.2 x 1.0 case 613ae ullga6 1.45 x 1.0 case 613af f m f m f m www.datasheet.in
NLX1G97 http://onsemi.com 2 figure 1. function diagram out y in a in b in c pin assignment 1 in b 2 gnd 3 in a 4 out y 5 v cc 6 in c function table* input output a b c y l l l l l l h l l h l h l h h l h l l l h l h h h h l h h h h h *to select a logic function, please refer to logic configurations section. www.datasheet.in
NLX1G97 http://onsemi.com 3 logic configurations figure 2. 2-input mux figure 3. 2-input and (when b = ?l?) figure 4. 2-input or with input c inverted (when b = ?h?) figure 5. 2-input and with input c inverted (when a = ?l?) figure 6. 2-input or (when a =?h?) figure 7. inverter (when a = ?l? and b = ?h?) figure 8. buffer (when a = c = ?l?) bc y 1 2 3 6 5 4 v cc a c y 1 2 3 6 5 4 y a c v cc a c y 1 2 3 6 5 4 y y a c a c v cc b c y 1 2 3 6 5 4 y y b c b c v cc b c y 1 2 3 6 5 4 y b c v cc y 1 2 3 6 5 4 y c v cc b y 1 2 3 6 5 4 y b v cc a b a c y c www.datasheet.in
NLX1G97 http://onsemi.com 4 maximum ratings symbol parameter value unit v cc dc supply voltage -0.5 to +7.0 v v in dc input voltage -0.5 to +7.0 v v out dc output voltage -0.5 to +7.0 v i ik dc input diode current v in < gnd -50 ma i ok dc output diode current v out < gnd -50 ma i o dc output source/sink current 50 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature range -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c msl moisture sensitivity level 1 f r flammability rating oxygen index: 28 to 34 ul 94 v-0 @ 0.125 in v esd esd withstand voltage human body model (note 2) machine model (note 3) charged device model (note 4) >2000 >200 n/a v i latchup latchup performance above v cc and below gnd at 125 c (note 5) 500 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. measured with minimum pad spacing on an fr4 board, using 10 mm-by-1 inch, 2 ounce copper trace no air flow. 2. tested to eia/jesd22-a114-a. 3. tested to eia/jesd22-a115-a. 4. tested to jesd22-c101-a. 5. tested to eia/jesd78. recommended operating conditions symbol parameter min max unit v cc positive dc supply voltage 1.65 5.5 v v in digital input voltage 0 5.5 v v out output voltage 0 5.5 v t a operating free-air temperature -55 +125 c t/ v input transition rise or fall rate v cc = 2.5 v 0.2 v v cc = 3.3 v 0.3 v v cc = 5.0 v 0.5 v 0 0 0 no limit no limit no limit ns/v www.datasheet.in
NLX1G97 http://onsemi.com 5 dc electrical characteristics symbol parameter conditions v cc (v) t a = 25 c t a +85 c t a = -55 c to +125 c unit min typ max min max min max v t+ positive threshold voltage 1.65 0.79 1.16 1.16 1.16 v 2.3 1.11 1.56 1.56 1.56 3.0 1.5 1.87 1.87 1.87 4.5 2.16 2.74 2.74 2.74 5.5 2.61 3.33 3.33 3.33 v t- negative threshold voltage 1.65 0.35 0.62 0.35 0.35 v 2.3 0.58 0.87 0.58 0.58 3.0 0.84 1.19 0.84 0.84 4.5 1.41 1.9 1.41 1.41 5.5 1.78 2.29 1.78 1.78 v h hysteresis voltage 1.65 0.30 0.62 0.30 0.62 0.30 0.62 v 2.3 0.40 0.8 0.40 0.8 0.40 0.8 3.0 0.53 0.87 0.53 0.87 0.53 0.87 4.5 0.71 1.04 0.71 1.04 0.71 1.04 5.5 0.8 1.2 0.8 1.2 0.8 1.2 v oh minimum high-level output voltage v in = v t-min or v t+max i oh = -50 a 1.65 - 5.5 v cc - 0.1 v cc - 0.1 v cc - 0.1 v v in = v t-min or v t+max i oh = -4 ma 1.65 1.2 1.2 1.2 i oh = -8 ma 2.3 1.9 1.9 1.9 i oh = -16 ma 3.0 2.4 2.4 2.4 i oh = -24 ma 3.0 2.3 2.3 2.3 i oh = -32 ma 4.5 3.8 3.8 3.8 v ol maximum low-level output voltage v in = v t-min or v t+max i ol = 50 a 1.65 - 5.5 0.1 0.1 0.1 v v in = v t-min or v t+max i ol = 4 ma 1.65 0.45 0.45 0.45 i ol = 8 ma 2.3 0.3 0.3 0.3 i ol = 16 ma 3.0 0.4 0.4 0.4 i ol = 24 ma 3.0 0.55 0.55 0.55 i ol = 32 ma 4.5 0.55 0.55 0.55 i in input leakage current 0 v in 5.5 v 0 to 5.5 0.1 1.0 1.0 a i cc quiescent supply current 0 v in v cc 5.5 1.0 10 10 a www.datasheet.in
NLX1G97 http://onsemi.com 6 ac electrical characteristics (input t r = t f = 3.0 ns) symbol parameter v cc (v) test condition t a = 25 c t a +85 c t a = -55 c to +125 c unit min typ max min max min max t plh , t phl propagation delay, any input to output y (see test circuit) 1.65 - 1.95 3.2 8.6 14.4 3.2 14.4 3.2 14.4 ns 2.3 - 2.7 2.0 5.1 8.3 2.0 8.3 2.0 8.3 3.0 - 3.6 1.5 3.9 6.3 1.5 6.3 1.5 6.3 4.5 - 5.5 1.1 3.3 5.1 1.1 5.1 1.1 5.1 c in input capacitance 3.5 pf c pd power dissipation capacitance (note 6) 5.0 f = 10 mhz 22 pf 6. c pd is defined as the value of the internal equivalent capacitance which is calculated from the dynamic operating current consumption without load. average operating current can be obtained by the equation i cc(opr) = c pd ? v cc ? f in + i cc . c pd is used to determine the no-load dynamic power consumption: p d = c pd ? v cc 2 ? f in + i cc ? v cc. test circuit and voltage waveforms figure 9. load circuit r l c l * from output under test gnd open v load r l *c l includes probes and jig capacitance. test s1 t plh /t phl open t plz /t pzl v load t phz /t pzh gnd v cc inputs v m v load c l r l v v i t r /t f 1.8 v 0.15 v v cc 2 ns v cc /2 2 x v cc 30 pf 1 k 0.15 v 2.5 v 0.2 v v cc 2 ns v cc /2 2 x v cc 30 pf 500 0.15 v 3.3 v 0.3 v 3 v 2.5 ns 1.5 v 6 v 50 pf 500 0.3 v 5.5 v 0.5 v v cc 2.5 ns v cc /2 2 x v cc 50 pf 500 0.3 v www.datasheet.in
NLX1G97 http://onsemi.com 7 figure 10. voltage waveforms pulse duration figure 11. voltage waveforms setup and hold times figure 12. voltage waveforms propagation delay times inverting and noninverting outputs figure 13. voltage waveforms enable and disable times low- and high-level enabling input input output output v m v load /2 v m t w v i 0 v v m v m v m v m v m v m v i 0 v t plh t phl t phl t plh v oh v ol v oh v ol output control v i 0 v v m v m v m v m t pzh t phz v ol v oh 0 v output output waveform 1 s1 at v load (note 7) waveform 2 s1 at gnd (note 8) v i 0 v timing input data input v i 0 v v m v m v m t su t h v ol + v v oh - v 7. waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. 8. waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control 9. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 . 10. the outputs are measured one at a time, with one transition per measurement. 11. all parameters are waveforms are not applicable to all devices. ordering information device package shipping ? NLX1G97amx1tcg ullga6 - 0.5p (pb-free) 3000 / tape & reel NLX1G97bmx1tcg ullga6 - 0.4p (pb-free) 3000 / tape & reel NLX1G97cmx1tcg ullga6 - 0.35p (pb-free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. www.datasheet.in
NLX1G97 http://onsemi.com 8 package dimensions ullga6 1.0x1.0, 0.35p case 613ad-01 issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. a maximum of 0.05 pull back of the plated terminal from the edge of the package is allowed. a b e d bottom view b e 6x 0.10 b 0.05 a c c l 5x note 3 0.10 c pin one reference top view 0.10 c 6x a a1 0.05 c 0.05 c c seating plane side view l1 1 3 4 6 dim min max millimeters a --- 0.40 a1 0.00 0.05 b 0.12 0.22 d 1.00 bsc e 1.00 bsc e 0.35 bsc l 0.25 0.35 l1 0.30 0.40 note 4 soldermask defined* dimensions: millimeters 0.22 5x 0.48 6x 1.18 0.53 pitch *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 0.35 1 mounting footprint pkg outline www.datasheet.in
NLX1G97 http://onsemi.com 9 package dimensions ullga6 1.2x1.0, 0.4p case 613ae-01 issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. a maximum of 0.05 pull back of the plated terminal from the edge of the package is allowed. a b e d bottom view b e 6x 0.10 b 0.05 a c c l 5x note 3 0.10 c pin one reference top view 0.10 c 6x a a1 0.05 c 0.05 c c seating plane side view l1 1 3 4 6 dim min max millimeters a --- 0.40 a1 0.00 0.05 b 0.15 0.25 d 1.20 bsc e 1.00 bsc e 0.40 bsc l 0.25 0.35 l1 0.35 0.45 note 4 soldermask defined* dimensions: millimeters 0.26 5x 0.49 6x 1.24 0.53 pitch *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 0.40 1 mounting footprint pkg outline www.datasheet.in
NLX1G97 http://onsemi.com 10 package dimensions ullga6 1.45x1.0, 0.5p case 613af-01 issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. a maximum of 0.05 pull back of the plated terminal from the edge of the package is allowed. a b e d bottom view b e 6x 0.10 b 0.05 a c c l 5x note 3 0.10 c pin one reference top view 0.10 c 6x a a1 0.05 c 0.05 c c seating plane side view l1 1 3 4 6 dim min max millimeters a --- 0.40 a1 0.00 0.05 b 0.15 0.25 d 1.45 bsc e 1.00 bsc e 0.50 bsc l 0.25 0.35 l1 0.30 0.40 note 4 soldermask defined* dimensions: millimeters 0.30 5x 0.49 6x 1.24 0.53 pitch *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 0.50 1 mounting footprint pkg outline on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 NLX1G97/d minigate is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative www.datasheet.in
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