? 2005 fairchild semiconductor corporation ds010932 www.fairchildsemi.com march 1993 revised march 2005 74actq541 quiet series octal buffer/line driver with 3-state outputs 74actq541 quiet series octal buffer/line driver with 3-state outputs general description the 74actq541 is an octal buffer/line driver designed to be employed as memory and address drivers, clock drivers and bus oriented transmitter/receivers. this device is similar in function to the 74actq244 while providing flow-through architecture (inputs on opposite side from outputs). this pinout arrangement makes this device especially useful as an output port for microprocessors, allowing ease of layout and greater pc board density. the 74actq541 utilizes fact quiet series technology to guarantee quiet output switching and improved dynamic threshold performance. fact quiet series features gto output control and undershoot corrector in addition to split ground bus for superior performance. features i cc and i oz reduced by 50% guaranteed simultaneous switching noise level and dynamic threshold performance guaranteed pin-to-pin skew ac performance inputs and outputs on opposite sides of package for easy board layout non-inverting 3-state outputs guaranteed 4 kv minimum esd immunity ttl compatible inputs outputs source/sink 24 ma ordering code: device also available in tape and reel. specify by appending suffix letter ?x? to the order code. note 1: ?_nl? indicates pb-free package (per jedec j-std-020b). device available in tape and reel only. fact , fact quiet series and gto are trademarks of fairchild semiconductor corporation. order number package package description number 74actq541sc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74actq541scx_nl (note 1) pb-free 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74actq541mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74actq541pc n20a 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide
www.fairchildsemi.com 2 74actq541 logic symbol ieee/iec pin descriptions connection diagram truth table h high voltage level x immaterial l low voltage level z high impedance pin name pin description oe 1 ? oe 2 3-state output enable (active-low) i 0 ? i 7 inputs o 1 ? o 7 outputs inputs outputs oe 1 oe 2 i llhh hxxz xhxz llll
3 www.fairchildsemi.com 74actq541 absolute maximum ratings (note 2) recommended operating conditions note 2: absolute maximum ratings are those values beyond which damage to the device may occur. the databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. fairchild does not recommend operation of fact circuits outside databook specifications. dc electrical characteristics note 3: all outputs loaded; thresholds on input associated with output under test. note 4: maximum test duration 2.0 ms, one output loaded at a time. note 5: plastic dip package. note 6: max number of outputs defined as (n). data inputs are driven 0v to 3v. one output @ gnd. note 7: max number of data inputs (n) switching. (n ? 1) inputs switching 0v to 5v (acq). input-under-test switching: 5v to threshold (v ild ), 0v to threshold (v ihd ), f 1 mhz. supply voltage (v cc ) 0.5v to 7.0v dc input diode current (i ik ) v i 0.5v 20 ma v i v cc 0.5v 20 ma dc input voltage (v i ) 0.5v to v cc 0.5v dc output diode current (i ok ) v o 0.5v 20 ma v o v cc 0.5v 20 ma dc output voltage (v o ) 0.5v to v cc 0.5v dc output source or sink current (i o ) r 50 ma dc v cc or ground current per output pin (i cc or i gnd ) r 50 ma storage temperature (t stg ) 65 q c to 150 q c dc latch-up source or sink current r 300 ma junction temperature (t j ) 140 q c supply voltage v cc 4.5v to 5.5v input voltage (v i )0v to v cc output voltage (v o )0v to v cc operating temperature (t a ) 40 q c to 85 q c minimum input edge rate ' v/ ' t v in from 0.8v to 2.0v v cc @ 4.5v, 5.5v 125 mv/ns symbol parameter v cc t a 25 q ct a 40 q c to 85 q c units conditions (v) typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out 0.1v input voltage 5.5 1.5 2.0 2.0 or v cc 0.1v v il maximum low level 4.5 1.5 0.8 0.8 v v out 0.1v input voltage 5.5 1.5 0.8 0.8 or v cc 0.1v v oh minimum high level 3.0 2.99 2.9 2.9 vi out 50 p a output voltage 4.5 4.49 4.4 4.4 4.5 3.86 3.76 v v in v il or v ih (note 3) i oh = 24 ma 24 ma 5.5 4.86 4.76 v ol maximum low level 3.0 0.002 0.1 0.1 vi out 50 p a output voltage 4.5 0.001 0.1 0.1 4.5 0.36 0.44 v v in v il or v ih (note 3) i oh = 24 ma 24 ma 5.5 0.36 0.44 i in maximum input leakage current 5.5 r 0.1 r 1.0 p av i v cc , gnd i oz maximum 3-state 5.5 r 0.25 r 2.5 p av i v il , v ih leakage current v o v cc , gnd i cct maximum i cc /input 5.5 0.6 1.5 ma v i v cc 2.1v i old minimum dynamic 5.5 75 ma v old 1.65v max i ohd output current (note 4) 5.5 75 ma v ohd 3.85v min i cc maximum quiescent supply current 5.5 4.0 40.0 p av in v cc or gnd v olp quiet output 5.0 1.1 1.5 v figure 1, figure 2 maximum dynamic v ol (note 5)(note 6) v olv quiet output 5.0 0.6 1.2 v figure 1, figure 2 minimum dynamic v ol (note 5)(note 6) v ihd minimum high level 5.0 1.9 2.2 v (note 5)(note 7) dynamic input voltage v ild maximum low level 5.0 1.2 0.8 v (note 5)(note 7) dynamic input voltage
www.fairchildsemi.com 4 74actq541 ac electrical characteristics note 8: voltage range 5.0 is 5.0v r 0.5v note 9: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). parameter guaranteed by design. capacitance symbol parameter v cc t a 25 q ct a 40 q c to 85 q c units (v) c l 50 pf c l 50 pf (note 8) min typ max min max t plh propagation delay 5.0 2.0 4.5 7.0 2.0 7.5 ns t phl data to output 2.0 5.5 7.0 2.0 7.5 t pzh output enable time 5.0 2.0 5.0 9.0 2.0 9.5 ns t pzl 2.0 6.5 9.0 2.0 9.5 t phz output disable time 5.0 1.5 5.5 7.5 1.5 8.0 ns t plz 1.5 5.5 7.5 1.5 8.0 t oshl output to output 0.5 1.0 1.0 ns t oslh skew data to output (note 9) 0.5 1.0 1.0 symbol parameter typ units conditions c in input capacitance 4.5 pf v cc open c pd power dissipation capacitance 70 pf v cc 5.0v
5 www.fairchildsemi.com 74actq541 fact noise characteristics the setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. the following is a brief description of the setup used to measure the noise characteristics of fact. equipment: hewlett packard model 8180a word generator pc-163a test fixture tektronics model 7854 oscilloscope procedure: 1. verify test fixture loading: standard load 50 pf, 500 : . 2. deskew the hfs generator so that no two channels have greater than 150 ps skew between them. this requires that the oscilloscope be deskewed first. it is important to deskew the hfs generator channels before testing. this will ensure that the outputs switch simultaneously. 3. terminate all inputs and outputs to ensure proper load- ing of the outputs and that the input levels are at the correct voltage. 4. set the hfs generator to toggle all but one output at a frequency of 1 mhz. greater frequencies will increase dut heating and effect the results of the measure- ment. 5. set the hfs generator input levels at 0v low and 3v high for act devices and 0v low and 5v high for ac devices. verify levels with an oscilloscope. v ohv and v olp are measured with respect to ground reference. input pulses have the following characteristics: f 1 mhz, t r 3ns, t f 3 ns, skew 150 ps. figure 1. quiet output noise voltage waveforms v olp /v olv and v ohp /v ohv : determine the quiet output pin that demonstrates the greatest noise levels. the worst case pin will usually be the furthest from the ground pin. monitor the output volt- ages using a 50 : coaxial cable plugged into a standard smb type connector on the test fixture. do not use an active fet probe. measure v olp and v olv on the quiet output during the worst case transition for active and enable. measure v ohp and v ohv on the quiet output during the worst case active and enable transition. verify that the gnd reference recorded on the oscillo- scope has not drifted to ensure the accuracy and repeat- ability of the measurements. v ild and v ihd : monitor one of the switching outputs using a 50 : coaxial cable plugged into a standard smb type connector on the test fixture. do not use an active fet probe. first increase the input low voltage level, v il , until the output begins to oscillate or steps out a min of 2 ns. oscillation is defined as noise on the output low level that exceeds v il limits, or on output high levels that exceed v ih limits. the input low voltage level at which oscillation occurs is defined as v ild . next decrease the input high voltage level, v ih , until the output begins to oscillate or steps out a min of 2 ns. oscillation is defined as noise on the output low level that exceeds v il limits, or on output high levels that exceed v ih limits. the input high voltage level at which oscillation occurs is defined as v ihd verify that the gnd reference recorded on the oscillo- scope has not drifted to ensure the accuracy and repeat- ability on the measurements. figure 2. simultaneous switching test circuit
www.fairchildsemi.com 6 74actq541 physical dimensions inches (millimeters) unless otherwise noted 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide package number m20b
7 www.fairchildsemi.com 74actq541 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc20
www.fairchildsemi.com 8 74actq541 quiet series octal buffer/line driver with 3-state outputs physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide package number n20a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
|
