differential clock buffer/drive r cy28353-2 rev 1.0, november 24, 2006 page 1 of 9 2200 laurelwood road, santa clara, ca 95054 tel:(4 08) 855-0555 fax:(408) 855-05 50 www.spectralinear.com features ? phase-locked loop (pll) clock distribution for double data rate synchronous dram applications ? distributes one differential cl ock input to si x differential outputs ? external feedback pins (fbint, fbinc) are used to synchronize the outputs to the clock input ? conforms to the ddri specification ? spread aware for electromagnetic interference (emi) reduction ? 28-pin ssop package description this pll clock buffer is designed for 2.5 v dd and 2.5 av dd operation and differential data input and output levels. this device is a zero delay buff er that distributes a differential clock input pair (clkint, clkinc) to six differential pairs of clock outputs (clkt[0:5], clkc[0:5]) and one differential pair feedback clock outputs (fbo utt, fboutc). the clock outputs are controlled by the input clocks (clkint, clkinc) and the feedback clocks (fbint, fbinc). the two-line serial bus can set each output clock pair (clkt[0:5], clkc[0:5]) to the hi-z state. when av dd is grounded, the pll is turned off and bypassed for test purposes. the pll in this device uses the input clocks (clkint, clkinc) and the feedback clocks (fbint, fbinc) to provide high-performance, low-skew, low?jitter output differential clocks. block diagram pin configuration 28 pin ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd clkt5 fbinc fboutt clkt3 clkc3 gnd fboutc fbint clkc5 clkc4 clkt4 vdd sdata clkc0 vdd clkint avdd vdd clkt2 clkc2 agnd clkinc clkt0 clkt1 clkc1 gnd sclk cy28353-2 serial interface logic sdata sclk clkt0 fboutt fboutc clkc0 clkt1 clkc1 clkt2 clkc2 clkc3 clkt3 clkc4 clkt4 clkc5 clkt5 pll fbinc fbint clkint avdd clkinc 10
cy28353-2 rev 1.0, november 24, 2006 page 2 of 9 pin description [1] pin number pin name i/o pin descri ption electrical characteristics 8clkinti complementary clock input . lv differential input 9clkinci complementary clock input . 21 fbinc i feedback clock input . connect to fboutc for accessing the pll. differential input 20 fbint i feedback clock input . connect to fboutt for accessing the pll. 2,4,13,17,24,26 clkt(0:5) o clock outputs . differential outputs 1,5,14,16,25,2 7 clkc(0:5) o clock outputs . 19 fboutt o feedback clock output . connect to fbint for normal operation. a bypass delay capacitor at this output will control input reference/output clocks phase relationships. differential output 18 fboutc o feedback clock output . connect to fbinc for normal operation. a bypass delay capacitor at this output will control input reference/output clocks phase relationships. 7sclki, pu serial clock input . clocks data at sdata into the internal register. data input for the two-line serial bus 22 sdata i/o, pu serial data input . input data is clocked to the internal register to enable/disable individual outputs. this provides flexi- bility in power management. data input and output for the two-line serial bus 3,12,23 vdd 2.5v power supply for logic . 2.5v nominal 10 avdd 2.5v power supply for pll . 2.5v nominal 6,15,28 gnd ground . 11 agnd analog ground for pll . function table inputs outputs pll vdda clkint clkinc clkt(0:5) [2] clkc(0:5) [2] fboutt fboutc gnd l h l h l h bypassed/off gnd h l h l h l bypassed/off 2.5v l h l h l h on 2.5v h l h l h l on 2.5v < 20 mhz < 20 mhz hi-z hi-z hi-z hi-z off notes: 1. a bypass capacitor (0.1 f) should be placed as close as possible to each positive power pin (< 0.2?). if these bypass capacitors are not close to the p ins their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. 2. each output pair can be three-stated via the two-line serial interface.
cy28353-2 rev 1.0, november 24, 2006 page 3 of 9 zero delay buffer when used as a zero delay buffer the cy28353-2 will likely be in a nested clock tree application. for these applications the cy28353-2 offers a differential clock input pair as a pll reference. the cy28353-2 then can lock onto the reference and translate with near zero delay to low skew outputs. for normal operation, the external feedback input, fbint, is connected to the feedback output, fboutt. by connecting the feedback output to the feedback input the propagation delay through the device is eliminated. the pll works to align the output edge with the input reference edge thus producing a near zero delay. the reference frequency affects the static phase offset of the pll and thus the relative delay between the inputs and outputs. when vdda is strapped low, the pll is turned off and bypassed for test purposes. power management the individual output enable/dis able control of the cy28353-2 allows the user to implement unique power management schemes into the design. output s are tri-stated when disabled through the two-line interface as individual bits are set low in byte0 and byte1 registers. the feedback output pair (fboutt, fboutc) cannot be disabled via two line serial bus. the enabling and disabling of individual outputs is done in such a manner as to eliminat e the possibility of partial ?runt? clocks. serial data interface to enhance the flexibility and func tion of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. the registers associated with the serial data interface initializes to their default sett ing upon power-up, and therefore use of this interface is optiona l. clock device register changes are normally made upon system initialization, if any are required. the interface ca nnot be used during system operation for power management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block r\ead operat ions from the controller. for block write/read operation, t he bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. for byte write and byte read operations, the system controller can access individually indexed bytes. the offset of the indexed byte is encoded in the command code, as described in table 1 . the block write and block read protocol is outlined in table 2 while table 3 outlines the corresponding byte write and byte read protocol. the slave rece iver address is 11010010 (d2h). table 1. command code definition bit description 7 0 = block read or block write operation, 1 = byte read or byte write operation (6:0) byte offset for byte read or byte write operation. fo r block read or block write operations, these bits should be '0000000' table 2. block read and block write protocol block write protocol block read protocol bit description bit description 1start 1start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 byte count ? 8 bits (skip this step if i 2 c_en bit set) 20 repeat start 28 acknowledge from slave 27:21 slave address ? 7 bits 36:29 data byte 1 ? 8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 45:38 data byte 2 ? 8 bits 37:30 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge .... data byte /slave acknowledges 46:39 data byte 1 from slave ? 8 bits .... data byte n ?8 bits 47 acknowledge .... acknowledge from slave 55:48 data byte 2 from slave ? 8 bits .... stop 56 acknowledge
cy28353-2 rev 1.0, november 24, 2006 page 4 of 9 .... data bytes from slave / acknowledge .... data byte n from slave ? 8 bits .... not acknowledge ... stop table 3. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1 start 1 start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 data byte ? 8 bits 20 repeated start 28 acknowledge from slave 27:21 slave address ? 7 bits 29 stop 28 read 29 acknowledge from slave 37:30 data from slave ? 8 bits 38 not acknowledge 39 stop byte0: output register (1 = enable, 0 = disable) bit @pup pin# description 7 1 2, 1 clkt0, clkc0 6 1 4, 5 clkt1, clkc1 51?reserved 41?reserved 3 1 13, 14 clkt2, clkc2 2 1 26, 27 clkt5, clkc5 11?reserved 0 1 24, 25 clkt4, clkc4 byte1: output register (1 = enable, 0 = disable) bit @pup pin# description 71?reserved 6 1 17, 16 clkt3, clkc3 50?reserved 40?reserved 30?reserved 20?reserved 10?reserved 00?reserved table 2. block read and block write protocol (continued) block write protocol block read protocol bit description bit description
cy28353-2 rev 1.0, november 24, 2006 page 5 of 9 maximum ratings [3] input voltage relative to v ss :...............................v ss ? 0.3v input voltage relative to v ddq or av dd : ............. v dd + 0.3v storage temperature: ................................. ?65c to +150c operating temperature:.................................... 0c to +85c maximum power supply: ................................................ 3.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v dd . unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). byte2: test register 3 bit @pup pin# description 7 1 ? 0 = pll leakage test, 1 = disable test 6 1 ? reserved 5 1 ? reserved 4 1 ? reserved 3 1 ? reserved 2 1 ? reserved 1 1 ? reserved 0 1 ? reserved dc parameters v dda = v ddq = 2.5v + 5%, t a = 0 c to +70 c [4] parameter description condition min. typ. max. unit vil input low voltage sdata, sclk 1.0 v vih input high voltage 2.2 v vid differential input voltage [5] clkint, fbint 0.35 v ddq + 0.6 v vix differential input crossing voltage [6] clkint, fbint (v ddq /2) ? 0.2 v ddq /2 (v ddq /2) + 0.2 v iin input current v in = 0v or v in = v ddq , clkint, fbint ?10 10 a iol output low current v ddq = 2.375v, v out = 1.2v 26 35 ma ioh output high current v ddq = 2.375v, v out =1v ?18 ?32 ma vol output low voltage v ddq = 2.375v, i ol = 12 ma 0.6 v voh output high voltage v ddq = 2.375v, i oh = ?12 ma 1.7 v vout output voltage swing [7] 1.1 v ddq ? 0.4 v voc output crossing voltage [8] (v ddq /2) ? 0.2 v ddq /2 (v ddq /2) + 0.2 v ioz high-impedance output current v o = gnd or v o = v ddq ?10 10 a iddq dynamic supply current [9] all v ddq and v ddi , f o = 170 mhz 235 300 ma idstat static supply current 1ma idd pll supply current v dda only 9 12 ma cin input pin capacitance 4 6 pf
cy28353-2 rev 1.0, november 24, 2006 page 6 of 9 ac parameters v dd = v ddq = 2.5v 5%, t a = 0c to +70c [10,11] parameter description condition min. typ. max. unit fclk operating clock frequency av dd , v dd = 2.5v 0.2v 60 170 mhz tdc input clock duty cycle 40 60 % tlock maximum pll lock time 100 s tr / tf output clocks slew rate 20% to 80% of v od 1 2.5v/ns tpzl, tpzh output enable time [12] (all outputs) 3 ns tplz, tphz output disable time [12] (all outputs) 3 ns tccj cycle to cycle jitter f > 66 mhz ?100 100 ps tjit(h-per) half-period jitter [14] f > 66 mhz ?100 100 ps tplh low-to-high propagation delay, clkint to clkt[0:5] 1.5 3.5 6 ns tphl high-to-low propagation delay, clkint to clkt[0:5] 1.5 3.5 6 ns tskew any output to any output skew [13] 100 ps tphase phase error [13] ?150 150 ps tphasej phase error jitter f > 66mhz ?50 50 ps notes: 3. multiple supplies : the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply srquencing is not required. 4. unused inputs must be held high or low to prevent them from floating. 5. differential input signal voltage specifies the differential voltage |vtr ? vcp| required for switching, where vtr is the tru e input level and vcp is the comple- mentary input level. 6. differential cross-point input voltage is expected to track vddq and is the voltage at which the differential signals must be crossing. 7. for load conditions see figure 7 . 8. the value of voc is expected to be |vtr + vcp|/2 . in case of each clock di rectly terminated by a 120 resistor. see figure 7 . 9. all outputs switching loaded with 16 pf in 60 environment. see figure 7 . 10. parameters are guaranteed by design and char acterization. not 100% tested in production. 11. pll is capable of meeting the specified parameters while supporting ssc synthesizers with modulation frequency between 30 kh z and 33.3 khz with a down spread of ?0.5%. 12. refers to transition of non-inverting output.
cy28353-2 rev 1.0, november 24, 2006 page 7 of 9 differential parameter measurement information notes: 13. all differential input and output terminals are terminated with 120 /16 pf, as shown in figure 7 . 14. period jitter and half-period jitter specifications are sepa rate specifications that must be met independently of each other . t ( ? ) n = n=n t ( ? ) n (n is large number of samples) 1 t ( ? ) n t ( ? ) n+1 clkint clkinc fbinc fbint figure 1. static phase offset t d( ? ) t d( ? ) t ( ? ) t ( ? ) t d( ? ) t d( ? ) clkint clkinc fbinc fbint figure 2. dynamic phase offset clkt[0:5], fboutt tsk(o) clkc[0:5], fboutc clkt[0:5], fboutt clkc[0:5], fboutc figure 3. output skew
cy28353-2 rev 1.0, november 24, 2006 page 8 of 9 t c(n) 1 f(o) t jit(hper) = t c(n) - 1 fo clkt[0:5], fboutt clkc[0:5], fboutc clkt[0:5], fboutt clkc[0:5], fboutc figure 4. period jitter 1 f(o) t (hper_n+1) t (hper_n) t jit(hper) = t hper(n) - 1 2x fo clkt[0:5], fboutt clkc[0:5], fboutc figure 5. hal f-period jitter t j it(cc) = t c(n) -t c(n+1) clkt[0:5], fboutt clkc[0:5], fboutc t c(n) t c(n) figure 6. cycle-to-cycle jitter clkt t pcb t pcb clkc 110 measurem ent point 16 pf measurem ent point 16 pf clkin fbint fboutt 110 110 fbinc fboutc figure 7. differential signal using direct termination resistor
rev 1.0, november 24, 2006 page 9 of 9 cy28353-2 while sli has reviewed all information herein for accuracy and re liability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it inte nded for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear in c., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package drawing and dimensions ordering information part number package type product flow cy28353oc-2 28-pin ssop commercial, 0 to 70c CY28353OC-2T 28-pin ssop?tape and reel commercial, 0 to 70c lead free cy28353oxc-2 28-pin ssop commercial, 0 to 70c cy28353oxc-2t 28-pin ssop?tape and reel commercial, 0 to 70c 28-lead (5.3 mm) shrunk small outline package o28
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