1 november 2010 dsc-3873/10 2010 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. ? features 128k x 8 advanced high-speed cmos static ram jedec revolutionary pinout (center power/gnd) for reduced noise equal access and cycle times ? commercial: 10/12/15ns ? industrial: 12/15ns one chip select plus one output enable pin inputs and outputs are lvttl-compatible single 3.3v supply low power consumption via chip deselect available in a 32-pin 300- and 400-mil plastic soj, and 32-pin type ii tsop packages. functional block diagram description the idt71v124 is a 1,048,576-bit high-speed static ram organized as 128k x 8. it is fabricated using idt?s high-performance, high-reliability cmos technology. this state-of-the-art technology, combined with inno- vative circuit design techniques, provides a cost-effective solution for high- speed memory needs. the jedec center power/gnd pinout reduces noise generation and improves system performance. the idt71v124 has an output enable pin which operates as fast as 5ns, with address access times as fast as 9ns available. all bidirec- tional inputs and outputs of the idt71v124 are lvttl-compatible and operation is from a single 3.3v supply. fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. address decoder 1,048,576-bit memory array i/o control ? ? ? a 0 a 16 3873 drw 01 8 8 i/o 0 -i/o 7 8 ? ? ? control logic we oe cs . 3.3v cmos static ram 1 meg (128k x 8-bit) center power & ground pinout idt71v124sa
2 idt71v124sa, 3.3v cmos static ram 1 meg (128k x 8-bit) center power & ground pinout commercial and industrial tempe rature ranges truth table (1) recommended dc operating conditions absolute maximum ratings (1) dc electrical characteristics (v dd = min. to max., commercial and industrial temperature ranges) pin configuration soj and tsop top view capacitance (t a = +25c, f = 1.0mhz, soj package) 5 6 7 8 9 10 11 12 a 0 a 1 a 2 1 2 3 4 32 31 30 29 28 27 26 25 24 23 22 21 a 15 a 3 cs i/o 1 v dd a 14 oe i/o 7 i/o 6 gnd i/o 5 3873 drw 02 gnd 13 20 14 19 15 18 16 a 7 17 i/o 2 i/o 3 we a 4 a 5 a 6 a 12 a 11 a 10 a 9 a 8 so32-2 so32-3 so32-4 i/o 0 a 16 a 13 v dd i/o 4 . note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliabilty. symbol rating value unit v dd supply voltage relative to gnd -0.5 to +4.6 v v in , v out terminal voltage relative to gnd -0.5 to v dd +0.5 v t a commercial operating temperature -0 to +70 o c industrial operating temperature -40 to +85 t bias temperature under bias -55 to +125 o c t stg storage temperature -55 to +125 o c p t power dissipation 1.25 w i out dc output current 50 ma 3873 tbl 02 note: 1. h = v ih , l = v il , x = don't care. cs oe we i/o function llhdata out read data lx ldata in write data l h h high-z output disabled h x x high-z deselected ? standby 3873 tbl 01 note: 1. this parameter is guaranteed by device characterization, but is not production tested. symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 6 pf c i/o i/o capacitance v out = 3dv 7 pf 3873 t bl 03 notes: 1. for 71v124sa10 only. 2. for all speed grades except 71v124sa10. 3. v ih (max.) = v dd +2v for pulse width less than 5ns, once per cycle. 4. v il (min.) = ?2v for pulse width less than 5ns, once per cycle. symbol parameter min. typ. max. unit v dd (1 ) supply voltage 3.15 3.3 3.6 v v dd (2 ) supply voltage 3.0 3.3 3.6 v v ss ground 0 0 0 v v ih input high voltage 2.0 ____ v dd +0.3 (3) v v il input low voltage ?0.5 (1 ) ____ 0.8 v 3873 tbl 04 symbol parameter test conditions min. max. unit |i li | input leakage current v dd = max., v in = gnd to v dd ___ 5a |i lo | output leakage current v dd = max., cs = v ih , v out = gnd to v dd ___ 5a v ol output low voltage i ol = 8ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = ?4ma, v dd = min. 2.4 ___ v 38 73 t b l 0 5 recommended operating tempera- ture and supply voltage grade temperature gnd v dd commercial 0c to +70c 0v see below industrial -40c to +85c 0v see below 3873 tbl 02a
6.42 idt71v124sa, 3.3v cmos static ram 1 meg (128k x 8-bit) center power & ground pinout commercial and industrial tem perature ranges 3 +1.5v 50 i/o z 0 =50 3873 drw 03 30pf . *including jig and scope capacitance. figure 2. ac test load (for t clz , t olz , t chz , t ohz , t ow, and t whz ) figure 1. ac test load ac test conditions dc electrical characteristics (1, 2) (v dd = min. to max., v lc = 0.2v, v hc = v dd ? 0.2v) 3873 drw 04 320 350 5pf* data out 3.3v notes: 1. all values are maximum guaranteed values. 2. all inputs switch between 0.2v (low) and v dd ?0.2v (high). 3. f max = 1/t rc (all address inputs are cycling at f max ) ; f = 0 means no address input lines are changing. symbol parameter 71v124sa10 71v124sa12 71v124sa15 unit commercial com'l ind com'l ind i cc dynamic operating current cs < v lc , outputs open, v dd = max., f = f max (3) 145 130 140 100 120 ma i sb dynamic standby power supply curren t cs > v hc , outputs open, v dd = max., f = f max (3) 45 40 40 35 40 ma i sb1 full standby power supply current (static) cs > v hc , outputs open, v dd = max., f = 0 (3) 10 10 10 10 10 ma 3873 tbl 06 input pulse levels input rise/fall times input timing reference levels output reference levels ac test load gnd to 3.0v 3ns 1.5v 1.5v see figure 1 and 2 3873 tbl 07
4 idt71v124sa, 3.3v cmos static ram 1 meg (128k x 8-bit) center power & ground pinout commercial and industrial tempe rature ranges ac electrical characteristics (v dd = min. to max., commercial and industrial temperature ranges) notes: 1. this parameter guaranteed with the ac load (figure 2) by device characterization, but is not production tested. symbol parameter 71v124sa10 71v124sa12 71v124sa15 unit min. max. min. max. min. max. read cycle t rc read cycle time 10 ____ 12 ____ 15 ____ ns t aa address access time ____ 10 ____ 12 ____ 15 ns t acs chip select access time ____ 10 ____ 12 ____ 15 ns t clz (1) chip select to output in low-z 4 ____ 4 ____ 4 ____ ns t chz (1) chip deselect to output in high-z 0 5 0 6 0 7 ns t oe outp ut enable to outp ut valid ____ 5 ____ 6 ____ 7ns t olz (1) outp ut enable to outp ut in low-z 0 ____ 0 ____ 0 ____ ns t ohz (1) output disable to output in high-z 0 5 0 5 0 5 ns t oh output hold from address change 4 ____ 4 ____ 4 ____ ns write cycle t wc write cycle time 10 ____ 12 ____ 15 ____ ns t aw address valid to end-of-write 7 ____ 8 ____ 10 ____ ns t cw chip select to end-of-write 7 ____ 8 ____ 10 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wp write pulse width 7 ____ 8 ____ 10 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 5 ____ 6 ____ 7 ____ ns t dh data hold time 0 ____ 0 ____ 0 ____ ns t ow (2) outp ut active fro m end-o f-write 3 ____ 3 ____ 3 ____ ns t whz (2) write enable to output in high-z 0 5 0 5 0 5 ns 3873 tbl 08
6.42 idt71v124sa, 3.3v cmos static ram 1 meg (128k x 8-bit) center power & ground pinout commercial and industrial tem perature ranges 5 notes: 1. we is high for read cycle. 2. device is continuously selected, cs is low. 3. address must be valid prior to or coincident with the later of cs transition low; otherwise t aa is the limiting parameter. 4. oe is low. 5. transition is measured 200mv from steady state. timing waveform of read cycle no. 1 (1) timing waveform of read cycle no. 2 (1, 2, 4) address 3873 drw 05 oe cs data out (5) (5) (5) (5) data out valid high impedance t aa t rc t oe t acs t olz t chz t clz (3) t ohz . data out address 3873 drw 06 t rc t aa t oh t oh data out valid previous data out valid .
6 idt71v124sa, 3.3v cmos static ram 1 meg (128k x 8-bit) center power & ground pinout commercial and industrial tempe rature ranges timing waveform of write cycle no. 1 ( we controlled timing) (1,2,4) timing waveform of write cycle no. 2 ( cs controlled timing) (1, 4) notes: 1. a write occurs during the overlap of a low cs and a low we . 2. oe is continuously high. during a we controlled write cycle with oe low, t wp must be greater than or equal to t whz + t dw to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse is the specified t wp . 3. during this period, i/o pins are in the output state, and input signals must not be applied. 4. if the cs low transition occurs simultaneously with or after the we low transition, the outputs remain in a high impedance state. cs must be active during the t cw write period. 5. transition is measured 200mv from steady state. address cs we data out data in 3873 drw 07 (5) (2) (5) (5) data in valid high impedance t wc t aw t as t whz t wp t chz t ow t dw t dh t wr (3) (3) . cs address data in 3873 drw 08 t aw t wc t cw t as t wr t dw t dh data in valid we (3) .
6.42 idt71v124sa, 3.3v cmos static ram 1 meg (128k x 8-bit) center power & ground pinout commercial and industrial tem perature ranges 7 ordering information
the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 8 idt71v124sa, 3.3v cmos static ram 1 meg (128k x 8-bit), center power & ground pinout commercial and industrial temperature ranges corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or ipchelp@idt.com san jose, ca 95138 408-284-8200 800-345-7015 fax: 408-284-2775 www.idt.com 11/22/99 updated to new format pg. 1?4, 7 added industrial temperature range offerings pg. 2 added recommended operating temperature and supply voltage table pg. 6 revised footnotes on write cycle no. 1 diagram pg. 8 added datasheet document history 08/30/00 pg. 3 tighten i cc and i sb pg. 4 tighten ac characteristics t ohz , t ow and t whz 08/22/01 pg. 7 removed footnote "400-mil soj package only offered in 10ns and 12ns speed grade" 11/30/03 pg. 1,3,7 added industrial temperature offering 10ns speed grade 01/30/04 pg. 7 added "restricted hazardous substance device" to ordering information. 2/14/07 pg. 7 added h generation die step to data sheet ordering information. 10/13/08 pg. 7 removed "idt" from the orderable part number 11/15/10 pg. 1,3,4,7 removed 20ns commercial, 10ns & 20ns industrial and also removed hsa offering.
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