? semiconductor components industries, llc, 2008 september, 2008 ? rev. 1 1 publication order number: NCV8665/d NCV8665 150 ma very low iq low dropout linear regulator with reset and delay reset the NCV8665 is a precision 5.0 v fixed output, low dropout integrated voltage regulator with an output current capability of 150 ma. careful management of light load current consumption, combined with a low leakage process, achieve a typical quiescent ground current of 30 a. NCV8665 is pin for pin compatible with the ncv8675 and the ncv4275 and it could replace this part when lower output current, and very low quiescent current is required. the output voltage is accurate within 2.0%, and maximum dropout voltage is 600 mv at full rated load current. it is internally protected against 45 v input transients, input supply reversal, output overcurrent faults, and excess die temperature. no external components are required to enable these features. features ? 5 v fixed output (3.3 v and 2.5 v versions are also available) ? 2.0% output accuracy, over full temperature range ? 40 a maximum quiescent current at i out = 100 a ? 600 mv maximum dropout voltage at 150 ma load current ? wide input voltage operating range of 5.5 v to 45 v ? internal fault protection ? ? 42 v reverse voltage ? short circuit ? thermal overload ? ncv prefix for automotive and other applications requiring site and control changes ? these are pb ? free devices + ? v in d v out gnd r o current limit and saturation sense bandgap reference thermal shutdown reset generator figure 1. block diagram error amplifier http://onsemi.com http://onsemi.com d 2 pak 5 ? pin ds suffix case 936a 1 5 pin 1. v in 2. ro tab, 3. gnd* 4. d 5. v out * tab is connected to pin 3 ordering information marking diagrams 1 a = assembly location wl, l = wafer lot y = year ww, w = work week g or = lead free indicator v665 ? 50g awlywwg see detailed ordering and shipping information in the dimensions section on page 9 of this data sheet. 1 8 soic ? 8 d suffix case 751 v6655 alywx 1 8 pin 1. v in 2. ro 3. d 4. v out 5 ? 8. gnd pin connections d 2 pak soic ? 8
NCV8665 http://onsemi.com 2 pin descriptions symbol function v in unregulated input voltage; 5.5 v to 45 v; battery input voltage. bypass to gnd with a 0.1 f ceramic capacitor. r o reset output; open collector active reset (accurate when v out > 1.0 v) gnd ground; pin 3 internally connected to tab d reset delay; timing capacitor to gnd for reset delay function v out output; 2.0%, 150 ma. 10 f, esr < 16 absolute maximum ratings pin symbol, parameter symbol min max unit v in , dc input voltage v in ? 42 +45 v v out , dc voltage v out ? 0.3 +16 v reset output voltage v ro ? 0.3 25 v reset output current i ro ? 5.0 5.0 ma reset delay voltage v d ? 0.3 7.0 v reset delay current i d ? 2.0 2.0 ma storage temperature t stg ? 55 +150 c esd capability, human body model (note 1) v esdhb 4000 v esd capability, machine model (note 1) v esdmm 200 v moisture sensitivity level msl 1 ? stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series incorporates esd protection and is tested by the following methods: esd human body model (hbm) tested per aec ? q100 ? 002 (eia/jesd22 ? a 114c) esd machine model (mm) tested per aec ? q100 ? 003 (eia/jesd22 ? a 115c) 2. latchup current maximum rating: 100 ma per jedec standard: jesd78. operating range pin symbol, parameter symbol min max unit input voltage operating range v in 5.5 45 v junction temperature t j ? 40 150 c thermal resistance parameter symbol min max unit junction to ambient (note 3) d 2 pak r ja ? 85.4 c/w junction to case (note 3) d 2 pak r jc ? 6.8 junction to ambient (note 4) soic ? 8 r ja ? 138 junction to lead 6 (note 4) soic ? 8 jl6 ? 21 3. as mounted on a 35x35x1mm fr4 pcb with a single layer of 100 mm 2 of 1 oz copper heat spreading area. 4. as mounted on a 35x35x1mm fr4 pcb with a single layer of 100 mm 2 of 1 oz copper heat spreading area including traces directly connected to the leads. pb soldering temperature and msl parameter symbol min max unit lead temperature soldering reflow (smd styles only), pb ? free (note 5) t sld ? 265 pk c msl, 8 ? lead ep, ls temperature 260 c msl 1 ? 5. this device series incorporates esd protection and exceeds the following ratings: human body model (hbm) 2.0 kv per jedec standard: jesd22?a114. machine model (mm) 200 v per jedec standard: jesd22?a115.
NCV8665 http://onsemi.com 3 electrical characteristics v in = 13.5 v, t j = ? 40 c to +150 c, unless otherwise specified parameter symbol test conditions min typ max unit output output voltage v out 0.1 ma i out 150 ma (note 6) 6 v v in 28 v 4.900 5.000 5.100 v output voltage v out 0 ma i out 150 ma 5.5 v v in 28 v ? 40 c t j 125 c 4.900 5.000 5.100 v line regulation v out versus v in i out = 5 ma 8 v v in 32 v ? 25 5 +25 mv load regulation v out vs. i out 1 ma i out 150 ma (note 6) ? 35 5 +35 mv dropout voltage v in ? v out i out = 100 ma (notes 6 and 7) i out = 150 ma (notes 6 and 7) 200 250 500 600 mv quiescent current i q i out = 100 a t j = 25 c t j = ? 40 c to +85 c 30 30 34 40 a active ground current i g(on) i out = 50 ma (note 6) i out = 150 ma (note 6) 1.8 12 3.5 19 ma power supply rejection psrr v ripple = 0.5 v pp , f = 100 hz 69 %/v output capacitor for stability c out esr i out = 0.1 ma to 150 ma 10 16 f reset timing d and output ro reset switching threshold v out,rt ? 4.50 4.65 4.80 v reset output low voltage v rol r ext > 5.0 k, v out > 1.0 v ? 0.20 0.40 v reset output leakage current i roh v roh = 5.0 v ? 0 10 a reset charging current i d,c v d = 1.0 v 2.0 4.0 6.5 a upper timing threshold v du ? 1.2 1.3 1.4 v reset delay time t rd c d = 47 nf 10 16 22 m s reset reaction time t rr c d = 47 nf 1.5 4.0 s protection current limit i out(lim) v out = 4.5 v (note 6) 150 500 ma short circuit current limit i out(sc) v out = 0 v (note 6) 100 500 ma thermal shutdown threshold t tsd (note 8) 150 200 c 6. use pulse loading to limit power dissipation. 7. dropout voltage = (v in ? v out ), measured when the output voltage has dropped 100 mv relative to the nominal value obtained with v in = 13.5 v. 8. not tested in production. limits are guaranteed by design.
NCV8665 http://onsemi.com 4 1 4 5 2 3 in d out ro gnd v in v out v ro c d 47 nf c in 100 nf i d i ro i out c out 10 f r ro 5.0 k i q figure 2. application circuit
NCV8665 http://onsemi.com 5 typical characteristic curves 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0 50 100 150 200 load current (ma) dropout voltage (v) figure 3. NCV8665 dropout voltage vs. load current 125 c 25 c ? 40 c 0 1 2 3 4 5 6 0 1020304050 input voltage (v) output voltage (v) figure 4. NCV8665 input voltage vs. output voltage (full range) 0 1 2 3 4 5 6 0246810 output voltage (v) input voltage (v) figure 5. NCV8665 input voltage vs. output voltage (low voltage) 0 2 4 6 8 10 12 14 16 18 0 50 100 150 output load (ma) esr ( ) figure 6. NCV8665 stability curve unstable region v in = 13.5 v c load 10 f stable region 0 1 2 3 4 5 6 7 8 9 10 0 50 100 150 200 quiescent current (ma) load current (ma) figure 7. NCV8665 quiescent current vs. load current (full range) 125 c 25 c ? 40 c v in = 13.5 v 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 5 10 15 20 25 125 c 25 c ? 40 c quiescent current (ma) load current (ma) figure 8. NCV8665 quiescent current vs. load current (light load) v in = 13.5 v load = 5 ma load = 5 ma
NCV8665 http://onsemi.com 6 typical characteristic curves 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 ? 50 0 50 100 150 v in = 13.5 v load = 100 a quiescent current (ma) temperature ( c) figure 9. NCV8665 quiescent current vs. temperature 0 1 2 3 4 5 6 7 8 9 10 0 1020304050 quiescent current (ma) input voltage figure 10. NCV8665 quiescent current vs. input voltage load = 50 ma
NCV8665 http://onsemi.com 7 circuit description the NCV8665 is an integrated low dropout regulator that provides 5.0 v, 150 ma protected output and a signal for power on reset. the regulation is provided by a pnp pass transistor controlled by an error amplifier with a bandgap reference, which gives it the lowest possible drop out voltage and best possible temperature stability. the output current capability is 150 ma, and the base drive quiescent current is controlled to prevent over saturation when the input voltage is low or when the output is overloaded. the regulator is protected by both current limit and thermal shutdown. thermal shutdown occurs above 150 c to protect the ic during overloads and extreme ambient temperatures. the delay time for the reset output is adjustable by selection of the timing capacitor. see figure 2, application circuit, for circuit element nomenclature illustration. regulator the error amplifier compares the reference voltage to a sample of the output voltage (v out ) and drives the base of a pnp series pass transistor by a buffer. the reference is a bandgap design to give it a temperature ? stable output. saturation control of the pnp is a function of the load current and input voltage. oversaturation of the output power device is prevented, and quiescent current in the ground pin is minimized. regulator stability considerations the input capacitor (c in ) is necessary to stabilize the input impedance to avoid voltage line influences. the output capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacit or value and type should be based on cost, availability, size and temperature constraints. tantalum, aluminum electrolytic, film, or ceramic capacitors are all acceptable solutions, however attention must be paid to esr constraints. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures ( ? 25 c to ? 40 c), both the capacitance and esr of the capacitor will vary considerably. the capacitor manufacturer?s data sheet usually provides this information. the value for the output capacitor c out shown in figure 2, application circuit, should work for most applications; however, it is not necessarily the optimized solution. reset output the reset output is used as the power on indicator to the microcontroller. this signal indicates when the output voltage is suitable for reliable operation of the controller. it pulls low when the output is not considered to be ready. ro is pulled up to v out by an external resistor , typically 5.0 k in value. the input and output conditions that control the reset output and the relative timing are illustrated in figure 11, reset t iming. output voltage regulation must be maintained for the delay time before the reset output signals a valid condition. the delay for the reset output is defined as the amount of time it takes the timing capacitor on the delay pin to charge from a residual voltage of 0 v to the upper timing threshold voltage v du of 1.8 v. the char ging current for this is i d of 5.5 a. by using typical ic parameters with a 47 nf capacitor on the d pin, the following time delay is derived: t rd = c d * v du / i d t rd = 47 nf * (1.8 v) / 5.5 a = 15.4 ms other time delays can be obtained by changing the c d capacitor value.
NCV8665 http://onsemi.com 8 v i v q v d v ro reset delay time reset reaction time power ? on ? reset thermal shutdown voltage dip at input undervoltage secondary spike overload at output < reset reaction time t t t t v q,rt upper timing threshold v du lower timing threshold v dl dv d dt reset charge current c d figure 11. reset timing calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 12) is: p d(max) [v i(max) v q(min) ]i q(max) (1) v i(max) i q where v i(max) is the maximum input voltage, v q(min) is the minimum output voltage, i q(max) is the maximum output current for the application, i q is the quiescent current the regulator consumes at i q(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p d (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation no tag will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. smart regulator ? iq control features i q i i figure 12. single output regulator with key performance parameters labeled v i v q } heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (3)
NCV8665 http://onsemi.com 9 where r jc is the junction ? to ? case thermal resistance, r cs is the case ? to ? heatsink thermal resistance, r sa is the heatsink ? to ? ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heatsink data sheets of heatsink manufacturers. thermal, mounting, and heatsinking considerations are discussed in the on semiconductor application note an1040/d. copper area (mm 2 ) figure 13. thermal resistance vs. pcb area thermal resistance junction ? to ? air ( c/w) r(t), ( c/w) pulse time (sec) figure 14. ncv8675 @ pcb cu area 100 mm 2 pcb cu thk 1 oz 20 60 100 140 160 0 100 200 300 400 500 600 700 800 900 soic ? 8 1 oz soic ? 8 2 oz 0.1 1 10 1000 0.000001 0.0001 0.01 1 100 d 2 pak single pulse 40 80 120 d 2 pak 1 oz d 2 pak 2 oz 100 soic ? 8 ordering information device package shipping ? NCV8665ds50g d2pak (pb ? free) 50 units / rail NCV8665ds50r4g d2pak (pb ? free) 800 / tape & reel NCV8665d50g soic ? 8 (pb ? free) 98 units / rail NCV8665d50r2g soic ? 8 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
NCV8665 http://onsemi.com 10 package dimensions d 2 pak, 5 lead ds suffix case 936a ? 02 issue c 5 ref a 123 k b s h d g c e m l p n r v u terminal 6 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. tab contour optional within dimensions a and k. 4. dimensions u and v establish a minimum mounting surface for terminal 6. 5. dimensions a and b do not include mold flash or gate protrusions. mold flash and gate protrusions not to exceed 0.025 (0.635) maximum. dim a min max min max millimeters 0.386 0.403 9.804 10.236 inches b 0.356 0.368 9.042 9.347 c 0.170 0.180 4.318 4.572 d 0.026 0.036 0.660 0.914 e 0.045 0.055 1.143 1.397 g 0.067 bsc 1.702 bsc h 0.539 0.579 13.691 14.707 k 0.050 ref 1.270 ref l 0.000 0.010 0.000 0.254 m 0.088 0.102 2.235 2.591 n 0.018 0.026 0.457 0.660 p 0.058 0.078 1.473 1.981 r 5 ref s 0.116 ref 2.946 ref u 0.200 min 5.080 min v 0.250 min 6.350 min 45 m 0.010 (0.254) t ? t ? optional chamfer 8.38 0.33 1.016 0.04 16.02 0.63 10.66 0.42 3.05 0.12 1.702 0.067 scale 3:1 mm inches soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
NCV8665 http://onsemi.com 11 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCV8665/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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