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description the CXA1854AR is an ic designed exclusively to drive color lcd panels lcx009ak/akb/lcx005bk/ bkb. this ic greatly reduces the number of circuits and parts required to drive lcd panels by incorporating rgb decoder functions for video signals, driver functions, and a timing generator for driving panels onto a single chip. features color lcd panels lcx009ak/akb/lcx005bk/bkb driver both ntsc/pal compatible supports composite inputs, y/c inputs and y/color difference inputs band-pass filter, trap and delay line sharpness function 2-point g compensation circuits r, b output delay time adjustment circuit (supports both right and left inversion) polarity reversed circuit / line inverted mode supports external rgb input supports line inversion supports ac drive for lcd panel during no signal applications color lcd viewfinders liquid crystal projectors industrial monitors structure bipolar cmos ic absolute maximum ratings (ta = 25?) supply voltage v cc 1 ?gnd 6 v supply voltage v cc 2 ?gnd 14 v supply voltage v dd ?v ss 6v analog input pin voltage vina ?.3 to v cc 1v digital input pin voltage vind ?.3 to v dd + 0.3 v operating temperature range topr ?5 to +70 ? storage temperature range tstg ?0 to +150 ? allowable power dissipation pd (ta 70?) 400 mw operating conditions supply voltage v cc 1 ?gnd 4.6 to 5.3 v supply voltage v cc 2 ?gnd 11.0 to 13.0 v supply voltage lcx009 mode v dd ?v ss 4.5 to 5.5 v lcx005 mode v dd ?v ss 2.7 to 5.5 v ?1 CXA1854AR e95x01a73 decoder/driver/timing generator for color lcd panels sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin lqfp (plastic)
?2 CXA1854AR block diagram decoder & h-timing pulse gen v-pos reset gen v-ctl decoder v-pos counter h-ctl decoder pll counter aux-v counter decoder h-pos counter v-ctl counter field & line ctl pal pulse elim & mode sel pol sw sub bright rgb gain gamma demod lpf matrix contrast sub contrast ext sw bright s/h int/ext clamp pal id pal sw reset apc vxo hue ps acc det killer filt cal agg det color cont bpf pic cont agc dl 2 dl 1 trap clamp acc amp sync sep h. filter half-h killer h-sync det h-skew det mode select pll phase comp pulse gen v-timing test s/r 1/7 v-sync sep buf buf buf reg. master ck sub ck bgp clp blk eqp xclr regv rgb yc/yrb/comp spal/dpal/ntsc sh1 sh2 sh3 sh4 frp 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 +5v +12v +5v gnd2 v cc 2 1 2 b-yin r-yin cout hue/rst color xvxo r-brt b-brt rgb-gain gamma2 gamma1 bright contrast cin r-gain b-gain test5 vd hd hck1 hck2 hst1 test4 clr en vck1 vck2 vst1 test3 slck test0 test1 test2 cko cki v ss rpd ext-b ext-g ext-r mode2 mode1 gnd1 pict agctc agcadj yin syncin v dd rgt test6 test7 test8 gnd2 r out fb r g out fb g b out fb b v cc 2 blklim v cc 1 reg gnd1 v ss
?3 CXA1854AR pin description (h: pull up, m: intermediate setting, l: pull down) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 i i i o i i i i i i o i o i i i i o o o o o o o o o o o o i sync input y signal input agc level adjustment agc time constant y signal frequency characteristics adjustment analog 5v gnd switches between ntsc (h), dpal * (m) and spal * (l) switches between composite (h), y/color difference (m) and yc input (l) external digital input r (input conditions noted separately) external digital input g (input conditions noted separately) external digital input b (input conditions noted separately) phase comparator output digital gnd oscillation cell input oscillation cell output test test test switches between lcx005bk (h) and lcx009ak (l) leave this pin open. v start pulse 1 output v clock pulse 2 output v clock pulse 1 output en pulse output clr pulse output leave this pin open. h start pulse 1 output h clock pulse 2 output h clock pulse 1 output hd pulse output vd pulse output leave this pin open. m m l l l l l sync in y in agcadj agctc pict gnd1 mode1 mode2 ext-r ext-g ext-b rpd v ss cki cko test2 test1 test0 slck test3 vst1 vck2 vck1 en clr test4 hst1 hck2 hck1 hd vd test5 * dpal supports demodulation methods which use an external delay line during demodulation; spal supports methods which internally process chroma demodulation. pin no. symbol i/o description input pin for open status
?4 CXA1854AR pin no. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 i i i i o i o i o i i o i i o i i i i i i i i i i i i i digital 5v power supply switches between normal scan (h) and reverse scan (l) leave this pin open. leave this pin open. leave this pin open. analog 12v gnd r output r signal dc voltage feedback input g output g signal dc voltage feedback input b output b signal dc voltage feedback input analog 12v power supply black peak limiter level adjustment analog 5v power supply constant voltage capacitor connection b-y demodulator input (or b-y/color difference signal input) r-y demodulator input (or r-y/color difference signal input) chroma signal output (for pal 1hdl) hue adjustment/system reset color adjustment vxo crystal oscillator connection r brightness adjustment b brightness adjustment rgb gain adjustment g 2 adjustment g 1 adjustment brightness adjustment contrast adjustment chroma signal input r gain adjustment b gain adjustment h h h h v dd rgt test6 test7 test8 gnd2 r out fb r g out fb g b out fb b v cc 2 blklim v cc 1 reg b-yin r-yin cout hue/rst color xvxo r-brt b-brt rgb-gain gamma2 gamma1 bright contrast cin r-gain b-gain symbol i/o description input pin for open status
?5 CXA1854AR analog block pin description 1 sync in sync input. normally inputs the y signal. the standard signal input level is 0.5vp-p (up to 100% white level from the sync chip). 1 200 50p v cc 1 gnd1 2 yin 3.2v y signal input. the standard signal input level is 0.5vp-p (up to 100% white level from the sync chip). input at low impedance (75 or less). 1k 50a v cc 1 gnd1 2 3 agcadj v cc 1/2 agc gain adjustment pin. 2k v cc 1 gnd1 3 40k 2.5v 4 agctc agc detection filter connection. 1k v cc 1 gnd1 20k 4 50a 5 pict v cc 1/2 adjusts frequency characteristics of luminance signal. increasing the voltage emphasizes contours. 1k v cc 1 gnd1 47k 2.5v 50a 5 pin no. symbol pin voltage equivalent circuit description
?6 CXA1854AR 9 ext-r 10 ext-g 11 ext-b 39 r out 41 g out 43 b out 40 fb r 42 fb g 44 fb b v cc 2 2 external digital signal input. there are two threshold values: vth1 (approximately 1.2v) and vth2 (approximately 2.2v). when one of the ext- rgb signals exceeds vth1, all of the rgb outputs go to black level (black side clip level); when an input exceeds vth2, only the corresponding output goes to white level (white side limiter level). rgb primary color signal output. smoothing capacitor connection for the feedback circuit of rgb output dc level control. use a low-leakage capacitor because of high impedance. v cc 1 gnd1 200 9 11 10 39 43 50 v cc 2 gnd2 50 41 gnd2 40 42 44 2k v cc 2 46 blklim sets the rgb output amplitude (black-black) clip level. 46 2k v cc 1 gnd1 50k 48 reg 4.2v smoothing capacitor connection for the internally generated constant voltage source circuit. connect a capacitor of 1f or more. v cc 1 gnd1 60k 40k 40k 48 pin no. symbol pin voltage equivalent circuit description
?7 CXA1854AR 49 b-yin 50 r-yin color difference demodulation circuit inputs during dpal mode. leave this pin open for ntsc. color difference signal is input respectively when y/color difference input. (standard input is 0.15vp-p.) at this time, the bias is 3.5v. 200 v cc 1 gnd1 2k 49 50 50a 51 cout 2.3v color adjusted chroma signal is output. when taking the chroma signal, connect to gnd with a load resistor (approximately 5k ). 51 v cc 1 gnd1 50a 52 hue/rst 3.2v color phase adjustment pin during ntsc. use for detective axis adjustment of the r-y/b-y axes during spal. also doubles as the reset pin. the system is reset when this pin is connected to gnd. v cc 1 gnd1 100k 6k 5p 50a 12k 3.2v 52 53 color 3.2v color adjustment. v cc 1 gnd1 100k 5p 50a 25k 3.2v 53 54 xvxo 3.5v crystal oscillator connection. v cc 1 gnd1 2k 54 500 pin no. symbol pin voltage equivalent circuit description
?8 CXA1854AR 55 rbrt 56 bbrt v cc 1/2 fine adjustment for r and b signal brightness. 55 56 v cc 1 gnd1 47k 3k 2.5v 57 rgb-gain v cc 1/2 adjusts rgb output amplitude gain. 57 v cc 1 gnd1 47k 3k 2.5v 58 gamma2 v cc 1/2 adjusts voltage gain change point g 2. 58 v cc 1 gnd1 47k 3k 2.5v 59 gamma1 v cc 1/2 adjusts voltage gain change point g 1. 59 v cc 1 gnd1 47k 3k 2.5v 60 bright v cc 1/2 rgb output brightness adjustment. it does not influence the g compensation curve. 60 v cc 1 gnd1 47k 4k 2.5v pin no. symbol pin voltage equivalent circuit description
?9 CXA1854AR pin no. symbol pin voltage equivalent circuit description 61 contrast v cc 1/2 contrast adjustment. 61 v cc 1 gnd1 47k 4k 2.5v 62 cin video signal input when using composite input. chroma signal input when using y/c input. leave this pin open when y/color difference input. v cc 1 gnd1 20k 500 15p 100a 50a 62 63 r-gain 64 b-gain v cc 1/2 fine adjustment for r and b signal contrast. 63 64 v cc 1 gnd1 47k 3k 2.5v
?10 CXA1854AR setting conditions for measuring electrical characteristics when measuring the dc characteristics, the tg block must be horizontally synchronized by performing setting 2. setting 2 must also be performed when measuring the ac characteristics. when measuring items with bands greater than 2mhz such as the y frequency response or sharpness characteristics, settings 1 and 3 must also be performed and measurements made with the sample-and-hold circuit set to through status. setting 1. system reset after turning on the power, set sw52 to on and start up v52 from gnd in order to activate the timing controller system reset. (see fig. 1-1.) setting 2. horizontal afc adjustment input sig6 (vl = 0mv) to (a) and adjust vr12 so that wl and wh of the tp12 output waveform are the same. (see fig. 1-2.) setting 3. s/h off input the signals shown in fig. 1-3 to pins 16, 17, 18 and 19 in order to set the sample-and-hold circuit to through status. v dd (v cc 1) v52 (reset) t r > 10s t r sig6 tp12 wl = wh wl wh ws fig. 1-1. system reset fig. 1-2. horizontal afc adjustment v dd gnd v dd gnd v dd gnd v dd gnd pin 19 pin 18 pin 17 pin 16 fig. 1-3. s/h off input pattern
?11 CXA1854AR electrical characteristics ?dc characteristics (1) unless otherwise specified, setting 2 and the following setting conditions are required. v cc 1 = 5.0v, v cc 2 = 12.0v, gnd1 = gnd2 = gnd, v dd = 5.0v, v ss = gnd v3, v5, v46, v55, v56, v57, v58, v59, v60, v61, v63, v64 = 2.5v v52, v53 = 3.2v sw3, sw5, sw46, sw52, sw53, sw55, sw56, sw57, sw58, sw59, sw60, sw61, sw63, sw64 = on set sw7, sw8, sw9, sw10, sw11 and sw19 are setting a. input sig5 to (a) and sig3 (0db) to (b). measure the i cc 1 current value. comp input mode input sig5 to (a) and sig3 (0db) to (b). set sw8 to c. measure the i cc 1 current value. y/c input mode input sig5 to (a) and sig5 to (f) and (g). set sw8 to b. measure the i cc 1 current value. y/color difference input mode input sig5 to (a) and sig3 (0db) to (b). measure the i cc 2 current value. input sig5 to (a) and sig3 (0db) to (b). measure the i dd current value. lcx009 mode input sig5 to (a) and sig3 (0db) to (b). set sw19 to b. measure the i dd current value. lcx005 mode input sig5 to (a) and sig3 (0db) to (b). set sw19 to b. v dd = 3.0v measure the i dd current value. lcx005 mode 35 34 32 3 7 5 2 44 42.5 40 5.5 10.5 8 3 53 51 48 8 14 10.5 4.5 ma ma ma ma ma ma ma i cc 11 i cc 12 i cc 13 i cc 2 i dd 1 i dd 2 i dd 3 power supply characteristics current consumption v cc 1 current consumption v cc 2 current consumption v dd item symbol conditions min. typ. max. unit
?12 CXA1854AR input pin with pull-up resistor * 1 vin = v ss input pin with pull-down resistor * 2 vin = v dd ioh = ?ma * 3 v dd = 5.0v v dd = 3.0v v dd = 5.0v v dd = 3.0v v dd = 5.0v v dd = 3.0v v dd = 5.0v v dd = 3.0v ?40 ?44 40 24 v dd 0.8 v dd 1.0 ?00 ?0 100 60 ?0 ?4 240 144 ? ? v ii1 ii2 voh1 digital block i/o characteristics input current 1 input current 2 high level output voltage output pins except cko and rpd ioh = ?ma iol = 3ma ioh = ?ma iol = 1.5ma high impedance status vout = v ss or vout = v dd cmos input cell cmos input cell mode m ? l level threshold sw7, sw8 = b mode m ? h level threshold sw7, sw8 = b 0.5v dd v dd ?.2 ?0 0.7v dd 0.2v dd 0.6v dd 0.3v dd 0.7v dd 0.5v dd 1.0 40 0.3v dd 0.4v dd 0.8v dd v v v v ? v v v v voh2 vol2 voh3 vol3 ioff vih vil mdthl mdthh high level output voltage cko pin low level output voltage cko pin high level output voltage rpd pin low level output voltage rpd pin output off leak current rpd pin high level input voltage slck and rgt pins low level input voltage slck and rgt pins ternary input switching threshold voltage (mode1/mode2) low level output voltage output pins except cko and rpd vol11 iol = 2ma * 3 0.5 0.6 v vol12 iol = 500a * 3 0.3 v * 1 input pins with pull-up resistors: rgt, test6, test7, test8 * 2 input pins with pull-down resistors: slck, test0, test1, test2, test5 * 3 output pins except cko and rpd: hd, vd, vst1, vck1, vck2, clr, en, hst1, hck1, hck2, test3, test4 item symbol conditions min. typ. max. unit
?13 CXA1854AR electrical characteristics ?ac characteristics (1) unless otherwise specified, setting 2 and the following setting conditions are required. vcc1 = 5.0v, vcc2 = 12.0v, gnd1 = gnd2 = gnd, (v dd = 5.0v, v ss = gnd) v5, v55, v56, v57, v60, v61, v63, v64 = 2.5v v3, v58 = 0v v46, v59 = 5.0v v52, v53 = 3.2v sw3, sw5, sw46, sw52, sw53, sw55, sw56, sw57, sw58, sw59, sw60, sw61, sw63, sw64 = on set sw7, sw8, sw9, sw10, sw11 and sw19 are setting a. unless otherwise specified, measure the non-reversed outputs for tp39, tp41 and tp43. input sig5 to (a) and measure the ratio between the output amplitude (white-black) and input amplitude at tp41. assume the output amplitude at tp41 when sig2 (0db, no burst, 100khz) is input to (a) as 0db. vary the frequency of the input signal to obtain the frequency with an output amplitude of ?db. settings 1 and 3 are required. assume the output amplitude at tp41 when sig8 (100khz) is input to (a) as 0db. obtain the output amplitude ratio for the input sig8 (2.0mhz). v5 = 4.0v settings 1 and 3 are required. composite input assume the output amplitude at tp41 when sig8 (100khz) is input to (a) as 0db. obtain the output amplitude ratio for the input sig8 (2.5mhz). v5 = 4.0v, sw8 = c settings 1 and 3 are required. y/c input assume the output amplitude at tp41 when sig8 (100khz) is input to (a) as 0db. obtain the output amplitude ratio for the input sig8 (2.0mhz). v5 = 0v settings 1 and 3 are required. composite input assume the output amplitude at tp41 when sig8 (100khz) is input to (a) as 0db. obtain the output amplitude ratio for the input sig8 (2.5mhz). v5 = 0v, sw8 = c settings 1 and 3 are required. y/c input 13.5 5.0 2.5 3.0 7 10 16.5 12 16 ? 1 19.5 2 4 db mhz mhz mhz db db db db gv fcyyc fcycmn fcycmp gshpmxc gshpmxy gshpmnc gshpmny y signal block video maximum gain y signal frequency characteristics sharpness characteristics max sharpness characteristics min y/c input, sw8 = c composite input (ntsc) composite input (pal), sw7 = c item symbol conditions min. typ. max. unit
?14 CXA1854AR adjust the output amplitude at tp41 when sig1 (apl: 50%) is input to (a) to 1.5vp-p with v61. assume this as 0 db, and obtain the tp41 output amplitude ratio when input sig1 (apl: 90%) is input. v3 = 2.5v, v60 = 3.5v adjust the output amplitude at tp41 when sig1 (apl: 50%) is input to (a) to 1.5vp-p with v61. assume this as 0db, and obtain the tp41 output amplitude ratio when input sig1 (apl: 10%) is input. v3 = 2.5v, v60 = 3.5v input sig5 to (a) and obtain the ratio between the tp41 output amplitude when v61 = 2.5v and the tp41 output amplitude when v61 = 5v. input sig5 to (a) and obtain the ratio between the tp41 output amplitude when v61 = 2.5v and the tp41 output amplitude when v61 = 1v. input sig3 (0db) to (a) and (b). adjust the chroma signal phase so that the amplitude (black ?white) at tp43 is at a maximum. using a spectrum analyzer, measure the input and the 3.58mhz or 4.43mhz component, and obtain crrlk = 150mv 10 ? d/20 using their difference ? d. sw7 = a for ntsc measurement, and c for pal measurement. input sig6 (vl = 150mv) to (a). measure the delay time from the rising edge of the input signal to the rising edge of the non-reversed output. v5 = 2v ?.5 2.5 5 ?0 400 780 760 ? 1 2 250 630 610 ? 4 ? 30 550 930 910 db db db db mvpp ns ns ns gapl90 gapl10 gcntmx gcntmn crrlk tdyyc tdycmn tdycmp apl = 90% apl = 10% contrast characteristics max contrast characteristics min carrier leak (residual carrier) y signal i/o delay time y/c input sw8 = c composite input (ntsc) composite input (pal), sw7 = c agc characteristics item symbol conditions min. typ. max. unit
?15 CXA1854AR input sig6 (vl = 0mv) to (a) and sig3 (0db/+6db/?0db, 3.58mhz burst/chroma phase = 180? or 4.43mhz burst/chroma phase = 135? to (b). measure the output amplitude at tp51, assuming the output corresponding to 0db, +6db and ?0db as v0, v1 and v2, respectively. acc1 = 20log (v1/v0) acc2 = 20log (v2/v0) input sig6 (vl = 0mv) to (a) and sig3 (0db, 3.58mhz burst/chroma phase = 180? or 4.43mhz burst/chroma phase = 135? to (b), and measure the output amplitude at tp43. changing the sig3 burst frequency, mesure the frequency fl which tp43 output changes (the killer mode is canceled). (the crystal parallel floating capacitance is 2pf or less) ntsc: fapcn = fl ?3579545hz pal: fapcp = fl ?4433619hz input sig6 (vl = 0mv) to (a) and sig3 (0db, 3.58mhz burst/chroma phase = 180? to (b). assume the chroma amplitude when v53 = 3.2v, 5v and 2.1v as v0, v1 and v2, respectively, and calculate gcolmx = 20log (v1/v0) and gcolmn = 20log (v2/v0). input sig6 (vl = 0mv) to (a) and sig3 (0 db) to (b). assume the phase at which the output amplitude at tp43 reaches a minimum when v53 = 3.2v, 5v and 1.6v as q 0, q 1 and q 2, respectively, and calculate tntmx = q 1 ? q 0 and tntmn = q 2 ? q 0. input sig6 (vl = 0mv) to (a) and sig3 (level variable, 3.58mhz burst/chroma phase = 180? or 4.43mhz burst/chroma phase = 135? to (b), and measure the output amplitude at tp43. gradually reduce the sig3 amplitude and measure the level at which the killer operation is activated. ? 0 +3 db ? 0 +3 db ? 0 +3 db ? 350 hz ?50 hz 350 hz 3 5.5 db ?0 ?5 db 30 deg ?6 ?0 db ?3 ?7 db ?0 deg ?50 hz 0+3db acc1n acc1p acc2n acc2p fapcnu fapcnd fapcpu fapcpd gcolmx gcolmn tntmx tntmn ackn ackp chroma signal block acc amplitude characteristics 1 acc amplitude characteristics 2 apc pull-in range color adjustment characteristics max color adjustment characteristics min hue adjustment range max hue adjustment range min killer operation input level ntsc pal sw7 = c ntsc pal sw7 = c ntsc upper limit cl = 20pf ntsc lower limit cl = 20pf pal upper limit sw7 = c cl = 16pf pal lower limit sw7 = c cl = 16pf ntsc pal sw7 = c electrical characteristics ?ac characteristics (2) item symbol conditions min. typ. max. unit
?16 CXA1854AR input sig6 (vl = 0mv) to (a) and sig3 (0db, 3.58mhz) to (b) and change the chroma phase. assume the maximum amplitude at tp39 as vr, the maximum amplitude at tp41 as vg, and the maximum amplitude at tp43 as vb, and calculate vrbn = vr/vb and vgbn = vg/vb. v60 = 3.5v input sig6 (vl = 0mv) to (a) and sig3 (0db, 3.58mhz) to (b) and change the chroma phase. assume the phase at which the maximum amplitude at tp39, tp41 and tp43 as q r, q g and q b, respectively, and calculate q rbn = q r ? q b and q gbn = q g ? q b. v60 = 3.5v input sig6 (vl = 0mv) to (a) and sig3 (0 db, 4.43mhz) to (b) and change the chroma phase. assume the maximum amplitude at tp39 as vr, the maximum amplitude at tp41 as vg, and the maximum amplitude at tp43 as vb, and calculate vrbp = vr/vb and vgbp = vg/vb. v60 = 3.5v, sw7 = c input sig6 (vl = 0mv) to (a) and sig3 (0 db, 4.43mhz) to (b) and change the chroma phase. assume the phase at which the maximum amplitude at tp39, tp41 and tp43 as q r, q g and q b, respectively, and calculate q rbp = q r ? q b and q gbp = q g ? q b. v60 = 3.5 v, sw7 = c 0.63 0.32 109 242 0.75 0.40 90 244 0.53 0.25 99 230 0.65 0.33 80 232 0.73 0.39 119 254 0.85 0.47 100 256 deg deg deg deg vrbn vgbn q rbn q gbn vrbp vgbp q rbp q gbp demodulation output amplitude ratio (ntsc) demodulation output phase difference (ntsc) demodulation output amplitude ratio (pal) demodulation output phase difference (pal) item symbol conditions min. typ. max. unit
?17 CXA1854AR input sig6 (vl = 0mv) to (a). adjust v60 so that the output (black-black) at tp41 is 9vp-p and measure the dc voltage at tp39, tp41 and tp43. input sig6 (vl = 0mv) to (a). adjust v60 so that the output (black-black) at tp41 is 9vp-p, measure the dc voltage at tp39, tp41 and tp43, and obtain the maximum difference between these values. input sig6 (vl = 0mv) to (a) and measure the output (black-black) at tp39, tp41 and tp43 when v60 = 0v. input sig6 (vl = 0mv) to (a) and measure the output (black-black) at tp39, tp41 and tp43 when v60 = 5v. input sig6 (vl = 0mv) to (a) and measure the difference between the outputs (black-black) at tp39 and tp43 and the output (black-black) at tp41 when v55 and v56 = 1v and when v55 and v56 = 4v. input sig5 to (a) and measure the difference between the outputs (white-black) at tp39 and tp43 and the output (white-black) at tp41 when v63 and v64 = 1v and when v63 and v64 = 4v. input sig5 to (a) and obtain the gain difference between the non-reversed output amplitudes (white-black) and the reversed output amplitudes at tp39, tp41 and tp43. input sig9 to (a) and adjust the non-reversed output amplitude (white-black) at tp41 to 4vp-p with v61. calculate the following: g g 1 = 20log (vg1/0.0357) g g 2 = 20log (vg2/0.0357) g g 3 = 20log (vg3/0.0357) (see fig. 6 for definitions of vg1, vg2 and vg3.) input sig4 to (a) and adjust the output amplitude (white- black) at tp41 to 4vp-p with v61 when v57 and v58 = 0v and v59 = 5v. measure the point where the gain of the non-reversed output at tp41 changes and the voltage difference v g 1 between this output and v cc 2/2 when v59 = 0v and when v59 = 2.7v. v g 1mn when v59 = 0v, and v g 1mx when v59 = 2.7v (see fig. 7.) input sig4 to (a) and adjust the output amplitude (white- black) at tp41 to 4vp-p with v61 when v57 and v58 = 0v. measure the point where the gain of the non-reversed output at tp41 changes and the voltage difference v g 2 between this output and v cc 2/2 when v58 = 5v and when v58 = 1.5v. v g 2mn when v58 = 5v and v g 2mx when v58 = 1.5v. (see fig. 7.) 21.5 9.5 18.5 3.5 2.0 25.5 12.5 23.5 29.5 15.5 26.5 2.0 0.9 db db db v v v v 5.85 9.0 ? ? ?.6 6.05 0 ? 0 6.25 100 3.0 0.6 v mv v v v db db vout ? vout brtmx brtmn sbbrt sbcnt ? g (nr) item rgb signal output characteristics g characteristics rgb output dc voltage rgb output dc voltage difference amount of change in brightness amount of change in sub-brightness amount of change in sub-contrast difference in rgb reversed/ non-reversed gain g gain v g 1 adjustment variable range v g 2 adjustment variable range g g 1 g g 2 g g 3 v g 1mn v g 1mx v g 2mn v g 2mx symbol conditions min. typ. max. unit electrical characteristics ?ac characteristics (3)
?18 CXA1854AR input sig6 (vl = 0mv, ws = 4.7s, vs variable) to (a) and confirm that it is synchronized with the output at tp30. gradually reduce the vs of sig6 from 143mv and obtain the vs at which input and output become non-synchronized. input sig6 (vl = 0mv, vs = 143mv, ws = 4.7s) to (a) and measure the delay time with the output at tp30. tdhdh is from the falling edge of the input sync signal to the rising edge of tp30, and tdhdl from the rising edge of the input sync signal to the falling edge of tp30. input sig6 (vl = 0mv, vs = 143mv, ws = 4.7s, horizontal frequency variable) to (a) and confirm that it is synchronized with the output at tp30. obtain the frequency fh where the input and output are synchronized by changing the horizontal frequency of sig6 from the non-synchronized condition. hplln = fh ?15734, hpllp = fh ?15625 input sig6 (vl = 0mv) to (a) and sig7 (vl variable) to (c), (d) and (e). raise the amplitude from 0 v and assume the voltage, where the outputs at tp39, tp41 and tp43 go to black level as vt1ext. then raise the amplitude further and assume the voltage where these outputs go to white level as vt2ext. sw9 = b, sw10 = b, sw11 = b input sig6 (vl = 0 mv) to (a) and sig7 (vl = 3 v) to (c), (d) and (e), and adjust the output amplitudes at tp39, tp41 and tp43 to 2.0v with v57. measure the rise delay time td1extand the fall delay time td2ext. sw9 = b, sw10 = b, sw11 = b (see fig. 2.) input sig6 (vl = 0mv) to (a) and sig7 (vl = 1.7v) to (c), (d) and (e), and measure the difference from the black level of the outputs at tp39, tp41 and tp43. sw9 = b, sw10 = b, sw11 = b input sig6 (vl = 0mv) to (a) and sig7 (vl = 2.7v) to (c), (d) and (e), and measure the difference from the black level of the outputs at tp39, tp41 and tp43. sw9 = b, sw10 = b, sw11 = b 2.9 4.4 500 500 1.0 2.0 100 100 1.8 40 3.2 4.7 1.2 2.2 200 200 2.2 60 3.5 5.0 1.4 2.4 300 300 0 mv ? ? hz hz v v ns ns v v vssep tdhdh tdhdl hplln hpllp vt1ext vt2ext td1ext td2ext extbk extwt item sync separation, tg block sync separation input voltage sensitivity hd output delay time horizontal pull-in range external rgb input threshold voltage propagation delay time between external rgb input and output black level voltage during external rgb input white level voltage during external rgb input symbol conditions min. typ. max. unit electrical characteristics ?ac characteristics (4) external i/o characteristics ntsc pal sw7 = c
?19 CXA1854AR input sig6 (vl =0 mv) to (a) and sig2 (0db, frequency variable) to (b). obtain frequencies fc1 and fc2 which reduce the output amplitude by 3db from the maximum output at tp51 by changing the frequency, and calculate f0bpf = (fc1 + fc2)/2. settings 1 and 3 are required. input sig6 (vl = 0mv) to (a) and sig2 (0db, frequency variable) to (b). assume tp51 when the center frequency is input as 0db and measure the output level at tp51 when the frequencies noted on the right are input. settings 1 and 3 are required. input sig2 (0db, 3.58mhz, 4.43mhz) to (a) and measure the output at tp41 with a spectrum analyzer. assume the output during y/c mode (sw8 = a) as 0db and measure the amount of attenuation during comp mode (sw8 = c). settings 1 and 3 are required. input sig6 (vl = 0mv) to (a) and sig2 (amplitude 100mv, frequency variable) to (f) and (g). assume the output amplitude at tp41 when 100khz is input as 0db, and measure the frequency which attenuates the output amplitude by ?db. input sig6 (vl = 0mv) to (a). load 30pf (see fig. 4.) v3, v46, v58, v59 = 2.5v input sig6 (vl = 0 mv) to (a). load 30pf (see fig. 5.) hck1/hck2 v3, v46, v58, v59 = 2.5v input sig6 (vl = 0mv) to (a). measure the hck1 and hck2 output duty. load 30pf v3, v46, v58, v59 = 2.5v 3.33 4.13 ? ? 0.6 47 3.58 4.43 ? ?3 ? ?0 0.8 50 3.83 4.73 ? ?5 ? ?5 ?5 ?5 1.2 30 25 10 53 mhz mhz db db db db db db mhz ns ns ns % f0bpfn f0bpfp atbpf atrapn atrapp demlp ttlh tthl ? t dtyhc item filter characteristics bpf center frequency amount of bpf attenuation amount of trap attenuation r-y, b-y and lpf characteristics output transition time (note 3 pins) cross-point time difference hck duty symbol conditions min. typ. max. unit electrical characteristics ?ac characteristics (5) digital block i/o characteristics ntsc pal sw7 = c 2.78mhz 1.50mhz 3.23mhz 2.00mhz ntsc pal sw7 = c ntsc pal sw7 = c
?20 CXA1854AR description of electrical characteristics measurement methods sig7 tp39, 41, 43 non-reversed output td1ext td2ext 3v gnd 2v 1v cmax cmax ?3db chroma output fc1 fc2 f bpf center frequency fobpf = 2 fc1 + fc2 fig. 2. measuring the delay between external rgb input and output fig. 3. bpf center frequency ttlh 90% tthl 10% 50% d t d t fig. 4. output transition time measurement condition fig. 5. cross-point time difference measurement condition g g 1 non-reversed output input g g 2 g g 3 1/2 v cc 2 white peak limiter white black non-reversed output input v g 2 1/2 v cc 2 white black v g 1 fig. 6. g characteristics measurement condition fig. 7. g adjustment variable range
?21 CXA1854AR input waveforms (1) sg no. waveform sig1 0.357v 0.143v 0.179v 0.357v apl10% apl50% apl90% apl variable, 5-step waveform sig2 sig3 0.15v 0.143v 0.15v sine wave video signal with burst. (amplitude and frequency are variable.) vsweep 0.15v chroma signal: burst, chroma frequency (3.579545mhz, 4.433619mhz) chroma phase and burst frequency variable 0.143v sig4 sig5 0.143v 0.357v 1h lamp waveform 0.143v 0.15v 5-step waveform
?22 CXA1854AR sg no. waveform sig6 ws vs vl vl amplitude is variable. vs variable: 143mv unless otherwise specified ws variable: 4.7s unless otherwise specified fh variable: 15.734khz (ntsc) or 15.625khz (pal) unless otherwise specified f h sig7 5s 30s vl gnd sync timing vl amplitude is variable. sig8 frequency variable 0.175v 0.143v 0.075v sig9 0.357v 0.143v 10-step waveform input waveforms (2)
?23 CXA1854AR electrical characteristics measurement circuit b-yin r-yin cout hue/rst color xvxo r-brt b-brt rgb-gain gamma2 gamma1 bright contrast cin r-gain b-gain test5 vd hd hck1 hck2 hst1 test4 clr en vck1 vck2 vst1 test3 slck test0 test1 syncin yin agcadj agctc pict gnd1 mode1 mode2 ext-r ext-g ext-b rpd v ss cki cko test2 reg v cc 1 blklim v cc 2 fb b b out fb g g out fb r r out gnd 2 test8 test7 test6 rgt v dd sw52 sw53 sw55 sw56 sw57 sw58 sw59 sw60 sw61 sw63 sw64 v52 v53 v55 v56 v57 v58 v59 v60 v61 v63 v64 cl * 1 (b) (g) tp51 (f) 1 1 4.7k 1 47 0.1 +v cc 1 +5v tp39 tp41 100p 100p 330k 1 100p 330k 1 0.1 330k tp43 47 +v cc 2 +12v sw46 v46 a 1 0.1 47 +v cc 1 +5v 0.01 +12v 47k 10k 30p * 2 220p l * 3 s16 33k 3300p 3.3 10k 1k (c) (d) (e) +5v a c b b sw8 sw7 sw5 v5 sw3 v3 1 1 s18 s17 tp31 tp30 tp29 tp28 tp27 tp26 tp25 tp24 tp23 tp22 tp21 s19 +5v 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 (a) CXA1854AR 10k a b 10k ca sw19 vr12 a a sw11 sw10 sw9 * 1 used crystal: kinseki cx-5f frequency deviation: within 30ppm, frequency temperature characteristics: within 30ppm during ntsc: 3.579545mhz, load capacity: 16pf, cl = 20pf during pal: 4.433619mhz, load capacity: 16pf, cl = 16pf measure under the condition that the crystal parallel floating capacitance is within 2pf. * 2 vari-cap diode: 1t369 (sony) * 3 l value: 10h when using the lcx005 4.7h when using the lcx009
?24 CXA1854AR description of operation the CXA1854AR incorporates the three functions of an rgb decoder block, an rgb driver block and a timing generator (tg) block onto a single chip using bicmos technology. this section describes these functions and their mutual relationship. 1) description of the overall configuration rgb decoder ext-r ext-g ext-b y sync c r-y b-y CXA1854AR enb clr vst1 vck2 vck1 hst1 hck2 hck1 frp r out g out b out r g b sync blk 3.58mhz or 4.43mhz rpd cki rgb driver tg vco corresponding lcd panels lcx009ak/akb 1.8cm 180k dots lcx005bk/bkb 1.4cm 113k dots 2) description of rgb decoder block operation input mode switching signal input: composite input, y/c input and y/color difference input switching is supported by pin 8 (mode2). during composite input: the composite signal is input to pins 1, 2 and 62. during y/c input: the y signal is input to pins 1 and 2, and the c signal to pin 62. during y/color difference input: the y signal is input to pins 1 and 2, the r-y signal to pin 50, and the b-y signal to pin 49. (chroma signal input (delay line output) is also used during pal, but is switched with the mode1 setting.) recommended input signal voltages for each mode are shown in the pin description table. the y signal enters the trap circuit in composite mode, but through operation is performed in all other modes. also, the picture center frequency is set separately for composite input and y/c input. (see the ac characteristics tables.) ntsc/pal switching ntsc and pal (dpal using an external delay line and spal) are switched by mode1. the built-in trap and bpf center frequencies are switched automatically according to the external crystal. the center frequency is stabilized by the apc operation. the r-y demodulation detective axis is set internally to 90 during spal/dpal. however, optimally adjust the demodulation phase axis with the hue adjustment pin. video agc/acc circuit different agc characteristics are obtained depending on the apl level of the luminance signal. the gain for the luminance signal is adjusted with the average value. the sync amplitude of the burst signal output is detected and used to adjust the acc amplifier gain.
?25 CXA1854AR vxo, apc detection the vxo local oscillation circuit is crystal oscillation circuit. the phases of the input burst signal and the vxo oscillator output are compared in the apc detection block, and the detective output is used to form a pll loop that controls the vxo oscillation frequency, which means that the need for adjustments is eliminated. in addition, the filter f0 is automatically adjusted, since the bpf and trap center frequency is feedback controlled by vxo. crystal oscillator for the xvxo pin connection a 3.579545mhz crystal vibrator is connected to the xvxo pin during ntsc, and a 4.433619mhz crystal vibrator during pal. (use kinseki cx-5f crystal vibrator with a load capacity of 16pf, frequency deviation within 30ppm, and frequency temperature characteristics within 30ppm.) external inputs digital input with two thresholds is optimal for multiplexed character output to screens. when one of the rgb inputs is higher than the lower threshold vth1, all rgb outputs go to black level. when the higher threshold vth2 is exceeded, the output for only the signal in question goes to white level, while the other outputs remain at black level. externally connect a pull-down resistor (10k or more). 3) description of rgb driver block operation 2-point g compensation circuit in order to support the characteristic of lcd panels, the i/o characteristics are as shown in fig. 1. the voltage at g gain change point a can be changed to that shown in fig. 2 by adjusting the gamma1 pin (pin 59). also, the voltage at the g 2 gain change point can be changed to that shown in fig. 3 by adjusting the gamma2 pin (pin 58). the drive for lcd panels can be optimized by adjusting the overall gain with these two gain change points and the rgb-gain pin (pin 57). g 2 g 1 b a output input g 2 g 1 b a output input g 2 g 1 b a output input fig. 1 fig. 3 fig. 2
?26 CXA1854AR sample-and-hold circuit as the lcd panels sample-and-hold rgb signals simultaneously, rgb signal output from cxa1854r must be synchronized to lcd panel drive pulses and sample-and-hold performed. sample-and-hold is performed by receiving the sh1 to sh4 pulses from the tg block. since lcd panels perform color coding using an rgb delta arrangement, each horizontal line must be compensated by 1.5 dots. this relationship is reversed during right/left inversion. these timing pulses are generated by the tg block. accordingly, rgb signals are each sampled-and-held at the optimal timing and output by the rgb driver block. s/h s/h s/h s/h s/h s/h r b g sh1 sh3 sh2 sh4 hck sh3 sh1 sh4 sh2 normal scan hck sh2 sh1 sh4 sh3 reverse scan example of sample-and-hold circuits and s/h timing rgb output rgb outputs (pins 39, 41, and 43) are reversed each horizontal line by the frp pulse supplied from the tg block as shown in the figure below. feedback is applied so that the center voltage of the output signal matches the reference voltage (v cc 2 + gnd1)/2. in addition, the white level output is clipped by the vsig center voltage level, and the black level output is clipped by the limiter operation point that is adjusted at the blklim pin (pin 46). video in frp rgb out waveform black level limiter (reversed side) vsig center voltage black level limiter (non-reversed side)
?27 CXA1854AR 4) description of tg block operation this section describes the main functions of the tg block. (see individual description materials for details.) pll circuit block the pll circuit block contains a phase comparator and frequency division counter circuit in order to accurately align the timing, and performs pll operation by externally connecting a vco circuit. the average voltage of the rpd pin (pin 12) is locked roughly in the center by adjusting it to v dd /2. (see the attached application circuit for the external circuit diagram. the 1t369 is recommended as the vari-cap diode used in the vco circuit.) sync detection circuit this circuit separates the input sync signal into hsync and vsync, and recognizes the even and odd fields and line numbers, etc. this circuit is necessary for the reasons (1) and (2). (1) shifts 1.5 dots each horizontal line for the rgb delta arrangement. (2) field recognition and accurate line number recognition for changing the eliminated lines for each even and odd field and smoothing the picture during pal. in addition, if the sync waveform is not detected for more than a certain interval, the unit shifts automatically to the free running state and the lcd panel is driven by self oscillation. pulse generator block the pulse generator circuit is synchronized to the previously mentioned sync detection circuit and pll circuit, and generates the pulses necessary to drive the lcd panel. (the main output pulse timings are shown for each mode in a later section.) at the same time, the pulse generator circuit also generates the bgp, blk and other waveforms for the rgb decoder. therefore, tg block pll circuit operation is necessary for rgb decoder functions. ac drive during no signal hst1, hck1, hck2, frp, vst1, vck1, vck2, hd and vd are made to run free so that the lcd panel is ac driven even when there is no composite sync from the sync pin. during this time, the hsync separation circuit stops and the pll counter is made to run free. in addition, the reference pulse for generates vd and vst, and the auxiliary v counter creates the reference pulse for generates vd and vst. the vsync separation circuit is also stopped and the period of the v counter is designed to be 269h for ntsc and 321h for pal. when there is no vsync during 269h or 321h, the free running state is assumed. in addition, rpd is kept at high impedance in order to prevent the afc circuit from producing a phase error due to phase comparison when there is no signal. afc circuit (702/1050fh generation) a fully synchronized afc circuit is built in. pll error signal is generated at the following timing. the phase comparison output of the entire bottom of sync and the internal h counter becomes rpd. rpd output is converted to dc error with the lag-lead filter, and then it changes the vari-cap diode capacitance and the oscillation frequency is stabilized at 702fh in the lcx005bk/bkb and 1050fh in the lcx009ak/akb. 4.7s v dd 0v v dd /2 sync rpd sync center
?28 CXA1854AR 5) description of tg block mode settings slck: selects the driven lcd panel. l h selects the lcx009 selects the lcx005 h l normal scan mode reverse scan mode note) the vco frequency varies depending on the used panel. vco center frequency lcx005 (702fh) lcx009 (1050fh) ntsc pal 11.06mhz 10.97mhz ntsc pal 16.52mhz 16.41mhz the external vco circuit diagram is shown in the application circuit. recommended value: l value lcx005: 10h, lcx009: 4.7h the hst1, hck1 and hck2 timing are switched by the rgt selection. the timing of the internal sample-and-hold pulse is also switched at the same time. connect the panel rgt pin directly, as it does not support output. rgt: switches the horizontal scan direction. h m l ntsc d-pal spal h m l composite input y/color difference input y/c input mode1/mode2: sets the type of video signal input. mode1 mode2 signal input connections for each mode are noted in the rgb decoder block.
?29 CXA1854AR lcx009ak/akb and lcx005bk/bkb color coding diagram the delta arrangement is used for the color coding in the lcd panels with which this ic is compatible. note that the shaded region within the diagram is not displayed. lcx009ak/akb pixel arrangement b r g b r g b r g b r g b r g b r r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g g b r g b r b r r g b r g b r g b r g b r g b r g b r g b r b r g b r g b r g b r g b r g b r b r g b r g b r g b r g b r g b r b r g b r g b r g b r g b r g b r g b r g g b r g b r b r r g b r g g b r g g b r g b r b r r g b r g g b r g g b r g b r b r r g b r g r g b r g b r g b r g b r g b r g 800 13 14 827 display area photo-shielding area dummy3 vline225 vline224 dummy2 vline3 vline2 vline1 dummy1 dummy1 to 4 hsw1 hsw2 hsw267 hsw268 dummy5 to 8 2 1 225 228 lcx005bk/bkb pixel arrangement 521 13 3 537 dummy4 vline218 vline217 dummy2 vline3 vline2 vline1 dummy1 hsw1 hsw3 hsw174 hsw175 dummy2 to 5 2 2 218 222 rgbrgbrgbrgbrgbr brgbrgbrgbrgbrgb rgbrgbrgbrgbrgbr brgbrgbrgbrgbrgb rgbrgbrgbrgbrgbr brgbrgbrgbrgbrgb rgbrgbrgbrgbrgbr brgbrgbrgbrgbrgb rgbrgbrgbrgbrgbr brgbrgbrgbrgbrgb rgbrgbrgbrgbrgbr dummy3 dummy1 hsw2 display area photo-shielding area
?30 CXA1854AR application circuit ?ntsc (comp and y/c input) 1 47 0.1 +v dd +5v red green 330k 1 330k 1 330k blue 47 +v cc 2 +12v 0.1 47 +v cc 1 +5v 0.01 +v cc 2 +12v 47k 10k 30p * 2 220p l * 3 33k 3300p 3.3 10k 1k 10k 10k 10k +v dd +5v y/c comp 1 1 to panel * 1 0.01 comp/y in c in hue color r-brt b-brt rgb gam2 gam1 brt cont r-g b-g agc pic b-lim to panel y/c comp +v dd +5v 47k 1 0.01 47k 0.1 1.7k 0.01 20pf 47k 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 005 009 b-yin r-yin cout hue/rst color xvxo r-brt b-brt rgb-gain gamma2 gamma1 bright contrast cin r-gain b-gain test5 vd hd hck1 hck2 hst1 test4 clr en vck1 vck2 vst1 test3 slck test0 test1 syncin yin agcadj agctc pict gnd1 mode1 mode2 ext-r ext-g ext-b rpd v ss cki cko test2 reg v cc 1 blklim v cc 2 fb b b out fb g g out fb r r out gnd 2 test8 test7 test6 rgt v dd 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 CXA1854AR application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. * 1 used crystal: kinseki cx-5f frequency deviation: within 30ppm, frequency temperature characteristics: within 30ppm 3.579545mhz, load capacity: 16pf * 2 vari-cap diode: 1t369 (sony) * 3 l value: 10h when using the lcx005 4.7h when using the lcx009
?31 CXA1854AR application circuit ?pal (comp and y/c input) hue color r-brt b-brt rgb gam2 gam1 brt cont r-g b-g agc pic b-lim 1 47 0.1 +v dd +5v red green 330k 1 330k 1 330k blue 47 +v cc 2 +12v 1 0.1 47 +v cc 1 +5v 0.01 +vcc2 +12v 47k 10k 30p * 2 220p l * 3 33k 3300p 3.3 10k 1k 10k 10k 10k +v dd +5v 1 1 +5v * 1 comp/y in c in to panel y/c comp +v dd 47k y/c comp to panel 0.01 0.01 47k 1.7k 0.01 47k 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 16pf 005 009 0.1 b-yin r-yin cout hue/rst color xvxo r-brt b-brt rgb-gain gamma2 gamma1 bright contrast cin r-gain b-gain test5 vd hd hck1 hck2 hst1 test4 clr en vck1 vck2 vst1 test3 slck test0 test1 syncin yin agcadj agctc pict gnd1 mode1 mode2 ext-r ext-g ext-b rpd v ss cki cko test2 reg v cc 1 blklim v cc 2 fb b b out fb g g out fb r r out gnd 2 test8 test7 test6 rgt v dd 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 CXA1854AR application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. * 1 used crystal: kinseki cx-5f frequency deviation: within 30ppm, frequency temperature characteristics: within 30ppm 4.433619mhz, load capacity: 16pf * 2 vari-cap diode: 1t369 (sony) * 3 l value: 10h when using the lcx005 4.7h when using the lcx009
?32 CXA1854AR application circuit ?y/color difference input (ntsc/pal) 1 47 0.1 +v dd +5v red green 330k 1 330k 1 330k blue 47 +v cc 2 +12v 1 0.1 47 +v cc 1 +5v 0.01 +vcc2 +12v 47k 10k 30p * 1 220p l * 2 33k 3300p 3.3 10k 1k 10k 10k 10k +v dd +5v pal ntsc 1 1 +5v y in hue color r-brt b-brt rgb gam2 gam1 brt cont r-g b-g agc pic b-lim to panel +v dd b-yin r-yin 1 1 1.7k to panel 0.01 0.01 47k 0.01 47k 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 47k 0.01 0.1 005 009 47k b-yin r-yin cout hue/rst color xvxo r-brt b-brt rgb-gain gamma2 gamma1 bright contrast cin r-gain b-gain test5 vd hd hck1 hck2 hst1 test4 clr en vck1 vck2 vst1 test3 slck test0 test1 syncin yin agcadj agctc pict gnd1 mode1 mode2 ext-r ext-g ext-b rpd v ss cki cko test2 reg v cc 1 blklim v cc 2 fb b b out fb g g out fb r r out gnd 2 test8 test7 test6 rgt v dd 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 CXA1854AR * 1 vari-cap diode: 1t369 (sony) * 2 l value: 10h when using the lcx005 4.7h when using the lcx009 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?33 CXA1854AR rgt: h (normal scan) composite in clk sync (blk) hd hst hck1 hck2 frp (internal pulse) vck1 vck2 clr en (pal) 653 663 673 683 693 1 11 21 31 41 51 61 71 81 91 4.7s (52fh) 13fh 18.5fh 4.7s (52fh) 4.5s (50fh) 2.0s (22fh) even field 3.0s (33fh) 702 0.5s (6fh) 23.5fh odd field odd line lcx005 horizontal direction timing chart (ntsc, pal) note) during y/c input, the hst timing is delayed 6fh from the above timing. the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified.
?34 CXA1854AR 653 663 673 683 693 1 11 21 31 41 51 61 71 81 91 4.7s (52fh) 13fh 18.0fh 4.7s (52fh) 4.5s (50fh) rgt: h (normal scan) composite in 2.0s (22fh) 3.0s (33fh) 22fh 0.5s (6fh) odd field even field 702 clk sync (blk) hd hst hck1 hck2 frp (internal pulse) vck1 vck2 clr en (pal) even line lcx005 horizontal direction timing chart (ntsc, pal) note) during y/c input, the hst timing is delayed 6fh from the above timing. the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified.
?35 CXA1854AR clk sync (blk) hd hst hck1 hck2 frp (internal pulse) vck1 vck2 clr en (pal) 653 663 673 683 693 1 11 21 31 41 51 61 71 81 91 4.7s (52fh) 18.0fh 4.5s (50fh) rgt: l (reverse scan) composite in 2.0s (22fh) 4.7s (52fh) even field 3.0s (34fh) 23fh 0.5s (5fh) odd field 702 13fh odd line lcx005 horizontal direction timing chart (ntsc, pal) note) during y/c input, the hst timing is delayed 6fh from the above timing. the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified.
?36 CXA1854AR clk sync (blk) hd hst hck1 hck2 frp (internal pulse) vck1 vck2 clr en (pal) 653 663 673 683 693 1 11 21 31 41 51 61 71 81 91 4.7s (52fh) 13fh 18.5fh 4.5s (50fh) rgt: l (reverse scan) composite in 2.0s (22fh) 4.7s (52fh) even field 3.0s (34fh) 24.5fh 0.5s (5fh) odd field 702 even line lcx005 horizontal direction timing chart (ntsc, pal) note) during y/c input, the hst timing is delayed 6fh from the above timing. the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified.
?37 CXA1854AR 263 20 13 3.0h 3.0h 3.0h 12h 505 20h 1 display start hd (vd) sync (blk) vst vck1 vck2 frp (internal pulse) hst en clr frp (internal pulse) fld (internal pulse) vd vrst (internal pulse) (1f inversion) 3.0h 3.0h 3.0h 243 20h 275 display start even field odd field 11.5h 12345678 12 34 12 34 56 78 1 2 3 4 lcx005 vertical direction timing chart (ntsc) note) the second and fourth rows of the timing chart "vd" and "blk" are pulses indicated as a reference and are not pulses output from pins.
?38 CXA1854AR 328 16 2.5h 2.5h 2.5h 14.5h 26 600 25h 1 hd (vd) sync (blk) vst vck1 vck2 frp (internal pulse) hst en clr frp (internal pulse) fld (internal pulse) vd vrst (internal pulse) 6 5 4 3 2 18 7 4 2 1 2.5h 2.5h 2.5h 288 25h 314 display start 3 6, 8 decimation even field odd field 14h 3 4 12 1234567812345612345678 12345678 12345678123456123 display start (1f inversion) lcx005 vertical direction timing chart (pal) note) the second and fourth rows of the timing chart "vd" and "blk" are pulses indicated as a reference and are not pulses output from pins.
?39 CXA1854AR hd sync (blk) vck1 vck2 hst frp (internal pulse) clr en (pal) 971 981 991 1001 1011 1021 1031 1041 1 11 21 31 41 51 61 71 81 91 101 111 1050 4.7s (78fh) 2.0s (33fh) 4.5s (73fh) 4.7s (78fh) 20.5fh 12fh 43.5fh 3.0s (50fh) 0.5s (8fh) even field odd field hck1 hck2 clk rgt: h (normal scan) composite in odd line lcx009 horizontal direction timing chart (ntsc, pal) note) during y/c input, the hst timing is delayed 6fh from the above timing. the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified.
?40 CXA1854AR hd sync (blk) vck1 vck2 hst frp (internal pulse) clr en (pal) 971 981 991 1001 1011 1021 1031 1041 1 11 21 31 41 51 61 71 81 91 101 111 1050 4.7s (78fh) 2.0s (33fh) 4.5s (73fh) 4.7s (78fh) 19fh 12fh 43.0fh 3.0s (50fh) 0.5s (8fh) odd field even field hck1 hck2 clk rgt: h (normal scan) composite in even line lcx009 horizontal direction timing chart (ntsc, pal) note) during y/c input, the hst timing is delayed 6fh from the above timing. the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified.
?41 CXA1854AR hd sync (blk) vck1 vck2 hst frp (internal pulse) clr en (pal) 971 981 991 1001 1011 1021 1031 1041 1 11 21 31 41 51 61 71 81 91 101 111 1050 4.7s (78fh) 2.0s (33fh) 4.5s (73fh) 4.7s (78fh) 20fh 12fh 43.0fh 3.0s (51fh) 0.5s (7fh) even field odd field hck1 hck2 clk rgt: l (reverse scan) composite in odd line lcx009 horizontal direction timing chart (ntsc, pal) note) during y/c input, the hst timing is delayed 6fh from the above timing. the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified.
?42 CXA1854AR hd sync (blk) vck1 vck2 hst frp (internal pulse) clr en (pal) 971 981 991 1001 1011 1021 1031 1041 1 11 21 31 41 51 61 71 81 91 101 111 1050 4.7s (78fh) 2.0s (33fh) 4.5s (73fh) 4.7s (78fh) 21.5fh 12fh 43.0fh 3.0s (51fh) 0.5s (7fh) even field odd field hck1 hck2 clk rgt: l (reverse scan) composite in even line lcx009 horizontal direction timing chart (ntsc, pal) note) during y/c input, the hst timing is delayed 6fh from the above timing. the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified.
?43 CXA1854AR 263 20 10 3.0h 3.0h 3.0h 9h 505 20h 1 hd (vd) sync (blk) vst vck1 vck2 frp (internal pulse) hst en clr frp (internal pulse) fld (internal pulse) vd vrst (internal pulse) 6 5 4 3 2 18 7 4 3 2 1 3.0h 3.0h 3.0h 243 20h 272 6 5 4 3 2 18 7 4 even field odd field 8.5h display start display start (1f inversion) 3 2 1 lcx009 vertical direction timing chart (ntsc) note) the second and fourth rows of the timing chart "vd" and "blk" are pulses indicated as a reference and are not pulses output from pins.
?44 CXA1854AR 2.5h 2.5h 2.5h 10.5h 5.5h 26 600 25h 112 hd (vd) sync (blk) vst vck1 vck2 frp (internal pulse) hst en clr frp (internal pulse) fld (internal pulse) vd vrst (internal pulse) 6 5 4 3 2 18 76 5 4 3 2 18 76 5 4 3 2 16 5 4 3 2 18 71 4 3 2 1 2.5h 2.5h 2.5h 288 25h 314 324 10.0h 6.0h 6 5 4 3 2 18 76 5 4 3 2 1 4 3 2 1 3 2 1 6 5 4 3 2 18 7 6, 8 decimation even field odd field display start display start (1f inversion) lcx009 vertical direction timing chart (pal) note) the second and fourth rows of the timing chart "vd" and "blk" are pulses indicated as a reference and are not pulses output from pins.
?45 CXA1854AR package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating 42 alloy package structure 64pin lqfp (plastic) 12.0 0.2 10.0 0.2 48 33 116 49 64 32 17 1.25 0.5 + 0.08 0.18 ?0.03 m 0.1 0.1 0.1 (0.5) 0.5 0.2 0?to 10 1.7 max detail a a 0.1 0.15 0.05 lqfp-64p-l061 lqfp064-p-1010-ay 0.3g

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